./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.09.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.09.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:52:35,966 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:52:36,020 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:52:36,023 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:52:36,024 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:52:36,024 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:52:36,043 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:52:36,044 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:52:36,044 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:52:36,045 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:52:36,045 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:52:36,045 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:52:36,046 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:52:36,046 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:52:36,046 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:52:36,046 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:52:36,046 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:52:36,047 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:52:36,047 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:52:36,047 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:52:36,051 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:52:36,051 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:52:36,051 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:52:36,051 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:52:36,052 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:52:36,052 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:52:36,052 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:52:36,052 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:52:36,052 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:52:36,052 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:52:36,052 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:52:36,053 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:52:36,053 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:52:36,053 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:52:36,053 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:52:36,053 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:52:36,053 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:52:36,054 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:52:36,054 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:52:36,055 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:52:36,055 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 834ccc2d6e5ce947bfece9c1e11f57131346eaac8927553a9495d7568350ac6e [2024-11-17 08:52:36,249 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:52:36,270 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:52:36,272 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:52:36,273 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:52:36,274 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:52:36,275 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2024-11-17 08:52:37,539 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:52:37,731 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:52:37,732 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.09.cil-1.c [2024-11-17 08:52:37,748 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d3798c8d5/6c2a0975deb146f786f1c55934fc624f/FLAG002970d04 [2024-11-17 08:52:37,760 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d3798c8d5/6c2a0975deb146f786f1c55934fc624f [2024-11-17 08:52:37,765 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:52:37,766 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:52:37,771 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:37,771 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:52:37,779 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:52:37,780 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:37" (1/1) ... [2024-11-17 08:52:37,780 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1741edee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:37, skipping insertion in model container [2024-11-17 08:52:37,781 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:37" (1/1) ... [2024-11-17 08:52:37,820 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:52:38,107 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:38,120 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:52:38,174 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:38,199 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:52:38,199 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38 WrapperNode [2024-11-17 08:52:38,200 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:38,201 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:38,201 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:52:38,201 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:52:38,209 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,218 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,285 INFO L138 Inliner]: procedures = 46, calls = 59, calls flagged for inlining = 54, calls inlined = 183, statements flattened = 2766 [2024-11-17 08:52:38,285 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:38,286 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:52:38,286 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:52:38,286 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:52:38,295 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,298 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,305 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,335 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:52:38,335 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,335 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,362 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,365 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,373 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,378 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,385 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:52:38,386 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:52:38,386 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:52:38,386 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:52:38,387 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (1/1) ... [2024-11-17 08:52:38,395 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:38,411 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:38,432 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:38,438 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:52:38,476 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:52:38,476 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:52:38,476 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:52:38,476 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:52:38,581 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:52:38,583 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:52:40,213 INFO L? ?]: Removed 564 outVars from TransFormulas that were not future-live. [2024-11-17 08:52:40,213 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:52:40,242 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:52:40,242 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:52:40,243 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:40 BoogieIcfgContainer [2024-11-17 08:52:40,243 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:52:40,244 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:52:40,244 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:52:40,247 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:52:40,251 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:40,251 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:52:37" (1/3) ... [2024-11-17 08:52:40,252 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@c5386e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:40, skipping insertion in model container [2024-11-17 08:52:40,252 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:40,252 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:38" (2/3) ... [2024-11-17 08:52:40,252 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@c5386e9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:40, skipping insertion in model container [2024-11-17 08:52:40,252 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:40,252 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:40" (3/3) ... [2024-11-17 08:52:40,253 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.09.cil-1.c [2024-11-17 08:52:40,311 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:52:40,311 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:52:40,312 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:52:40,312 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:52:40,312 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:52:40,312 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:52:40,312 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:52:40,313 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:52:40,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1232 states, 1231 states have (on average 1.48659626320065) internal successors, (1830), 1231 states have internal predecessors, (1830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:40,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1100 [2024-11-17 08:52:40,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:40,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:40,394 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:40,394 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:40,394 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:52:40,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1232 states, 1231 states have (on average 1.48659626320065) internal successors, (1830), 1231 states have internal predecessors, (1830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:40,406 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1100 [2024-11-17 08:52:40,406 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:40,406 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:40,413 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:40,413 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:40,420 INFO L745 eck$LassoCheckResult]: Stem: 589#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 30#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 524#L1391true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 519#L651-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 783#L658true assume !(1 == ~m_i~0);~m_st~0 := 2; 622#L663true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 968#L668true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 161#L673true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 719#L678true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 859#L683true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 98#L688true assume 1 == ~t6_i~0;~t6_st~0 := 0; 591#L693true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 556#L698true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 936#L703true assume !(1 == ~t9_i~0);~t9_st~0 := 2; 734#L709true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 306#L939-1true assume !(0 == ~M_E~0); 776#L944-1true assume !(0 == ~T1_E~0); 368#L949-1true assume !(0 == ~T2_E~0); 365#L954-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1122#L959-1true assume !(0 == ~T4_E~0); 805#L964-1true assume !(0 == ~T5_E~0); 192#L969-1true assume !(0 == ~T6_E~0); 926#L974-1true assume !(0 == ~T7_E~0); 726#L979-1true assume !(0 == ~T8_E~0); 1152#L984-1true assume !(0 == ~T9_E~0); 291#L989-1true assume !(0 == ~E_M~0); 534#L994-1true assume 0 == ~E_1~0;~E_1~0 := 1; 217#L999-1true assume !(0 == ~E_2~0); 703#L1004-1true assume !(0 == ~E_3~0); 41#L1009-1true assume !(0 == ~E_4~0); 213#L1014-1true assume !(0 == ~E_5~0); 670#L1019-1true assume !(0 == ~E_6~0); 977#L1024-1true assume !(0 == ~E_7~0); 162#L1029-1true assume !(0 == ~E_8~0); 233#L1034-1true assume 0 == ~E_9~0;~E_9~0 := 1; 259#L1040-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59#L460-12true assume 1 == ~m_pc~0; 634#L461-12true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35#L463-12true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 362#L472-12true assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 692#L1167-12true assume !(0 != activate_threads_~tmp~1#1); 613#L1173-12true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 773#L479-12true assume !(1 == ~t1_pc~0); 1078#L489-12true is_transmit1_triggered_~__retres1~1#1 := 0; 342#L482-12true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1132#L491-12true assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48#L1175-12true assume !(0 != activate_threads_~tmp___0~0#1); 507#L1181-12true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 383#L498-12true assume 1 == ~t2_pc~0; 1092#L499-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 711#L501-12true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12#L510-12true assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1008#L1183-12true assume !(0 != activate_threads_~tmp___1~0#1); 733#L1189-12true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 415#L517-12true assume 1 == ~t3_pc~0; 349#L518-12true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 664#L520-12true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 244#L529-12true assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1120#L1191-12true assume !(0 != activate_threads_~tmp___2~0#1); 960#L1197-12true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 113#L536-12true assume 1 == ~t4_pc~0; 1108#L537-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 148#L539-12true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 623#L548-12true assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 562#L1199-12true assume !(0 != activate_threads_~tmp___3~0#1); 218#L1205-12true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 531#L555-12true assume !(1 == ~t5_pc~0); 129#L565-12true is_transmit5_triggered_~__retres1~5#1 := 0; 1188#L558-12true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 846#L567-12true assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 646#L1207-12true assume !(0 != activate_threads_~tmp___4~0#1); 299#L1213-12true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36#L574-12true assume 1 == ~t6_pc~0; 611#L575-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 749#L577-12true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 335#L586-12true assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 856#L1215-12true assume !(0 != activate_threads_~tmp___5~0#1); 167#L1221-12true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 404#L593-12true assume 1 == ~t7_pc~0; 1125#L594-12true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 976#L596-12true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57#L605-12true assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 364#L1223-12true assume !(0 != activate_threads_~tmp___6~0#1); 978#L1229-12true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1207#L612-12true assume 1 == ~t8_pc~0; 1048#L613-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1210#L615-12true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1080#L624-12true assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 825#L1231-12true assume !(0 != activate_threads_~tmp___7~0#1); 206#L1237-12true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 594#L631-12true assume !(1 == ~t9_pc~0); 70#L641-12true is_transmit9_triggered_~__retres1~9#1 := 0; 1159#L634-12true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1160#L643-12true assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1026#L1239-12true assume !(0 != activate_threads_~tmp___8~0#1); 37#L1245-12true assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 707#L1047-1true assume !(1 == ~M_E~0); 452#L1052-1true assume !(1 == ~T1_E~0); 15#L1057-1true assume !(1 == ~T2_E~0); 150#L1062-1true assume !(1 == ~T3_E~0); 806#L1067-1true assume !(1 == ~T4_E~0); 360#L1072-1true assume !(1 == ~T5_E~0); 651#L1077-1true assume !(1 == ~T6_E~0); 90#L1082-1true assume !(1 == ~T7_E~0); 439#L1087-1true assume !(1 == ~T8_E~0); 4#L1092-1true assume !(1 == ~T9_E~0); 16#L1097-1true assume !(1 == ~E_M~0); 980#L1102-1true assume !(1 == ~E_1~0); 520#L1107-1true assume !(1 == ~E_2~0); 454#L1112-1true assume !(1 == ~E_3~0); 490#L1117-1true assume !(1 == ~E_4~0); 1204#L1122-1true assume !(1 == ~E_5~0); 402#L1127-1true assume !(1 == ~E_6~0); 234#L1132-1true assume !(1 == ~E_7~0); 984#L1137-1true assume !(1 == ~E_8~0); 149#L1142-1true assume !(1 == ~E_9~0); 741#L1148-1true assume true;assume { :end_inline_reset_delta_events } true; 185#L1428true [2024-11-17 08:52:40,425 INFO L747 eck$LassoCheckResult]: Loop: 185#L1428true assume true; 408#L1428-1true assume !false; 221#start_simulation_while_11_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 767#L778true assume !true; 624#L786true assume true; 390#L932true assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 910#L651true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1071#L939true assume 0 == ~M_E~0;~M_E~0 := 1; 758#L944true assume 0 == ~T1_E~0;~T1_E~0 := 1; 182#L949true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1227#L954true assume 0 == ~T3_E~0;~T3_E~0 := 1; 884#L959true assume 0 == ~T4_E~0;~T4_E~0 := 1; 693#L964true assume !(0 == ~T5_E~0); 147#L969true assume 0 == ~T6_E~0;~T6_E~0 := 1; 655#L974true assume 0 == ~T7_E~0;~T7_E~0 := 1; 736#L979true assume 0 == ~T8_E~0;~T8_E~0 := 1; 637#L984true assume 0 == ~T9_E~0;~T9_E~0 := 1; 481#L989true assume 0 == ~E_M~0;~E_M~0 := 1; 1201#L994true assume 0 == ~E_1~0;~E_1~0 := 1; 1211#L999true assume 0 == ~E_2~0;~E_2~0 := 1; 444#L1004true assume !(0 == ~E_3~0); 142#L1009true assume 0 == ~E_4~0;~E_4~0 := 1; 744#L1014true assume 0 == ~E_5~0;~E_5~0 := 1; 539#L1019true assume 0 == ~E_6~0;~E_6~0 := 1; 768#L1024true assume 0 == ~E_7~0;~E_7~0 := 1; 598#L1029true assume 0 == ~E_8~0;~E_8~0 := 1; 511#L1034true assume 0 == ~E_9~0;~E_9~0 := 1; 328#L1040true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1155#L460-1true assume !(1 == ~m_pc~0); 851#L470-1true is_master_triggered_~__retres1~0#1 := 0; 919#L463-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 411#L472-1true assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 436#L1167-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 572#L1173-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71#L479-1true assume 1 == ~t1_pc~0; 917#L480-1true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 797#L482-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 653#L491-1true assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1042#L1175-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 165#L1181-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 658#L498-1true assume 1 == ~t2_pc~0; 654#L499-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1187#L501-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1102#L510-1true assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 69#L1183-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 177#L1189-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1094#L517-1true assume 1 == ~t3_pc~0; 793#L518-1true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 457#L520-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131#L529-1true assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 251#L1191-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 260#L1197-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 864#L536-1true assume 1 == ~t4_pc~0; 1177#L537-1true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 990#L539-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 576#L548-1true assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1198#L1199-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1221#L1205-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 969#L555-1true assume 1 == ~t5_pc~0; 200#L556-1true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 424#L558-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 712#L567-1true assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 497#L1207-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 715#L1213-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 751#L574-1true assume 1 == ~t6_pc~0; 325#L575-1true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 50#L577-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1087#L586-1true assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 465#L1215-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 382#L1221-1true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87#L593-1true assume !(1 == ~t7_pc~0); 559#L603-1true is_transmit7_triggered_~__retres1~7#1 := 0; 875#L596-1true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 502#L605-1true assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25#L1223-1true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 420#L1229-1true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 577#L612-1true assume !(1 == ~t8_pc~0); 326#L622-1true is_transmit8_triggered_~__retres1~8#1 := 0; 894#L615-1true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 866#L624-1true assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 123#L1231-1true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7#L1237-1true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1001#L631-1true assume !(1 == ~t9_pc~0); 708#L641-1true is_transmit9_triggered_~__retres1~9#1 := 0; 62#L634-1true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1030#L643-1true assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 689#L1239-1true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 363#L1245-1true assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 684#L1047true assume 1 == ~M_E~0;~M_E~0 := 2; 397#L1052true assume 1 == ~T1_E~0;~T1_E~0 := 2; 42#L1057true assume 1 == ~T2_E~0;~T2_E~0 := 2; 18#L1062true assume 1 == ~T3_E~0;~T3_E~0 := 2; 276#L1067true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1156#L1072true assume 1 == ~T5_E~0;~T5_E~0 := 2; 782#L1077true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1018#L1082true assume 1 == ~T7_E~0;~T7_E~0 := 2; 753#L1087true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1097#L1092true assume 1 == ~T9_E~0;~T9_E~0 := 2; 763#L1097true assume 1 == ~E_M~0;~E_M~0 := 2; 1209#L1102true assume 1 == ~E_1~0;~E_1~0 := 2; 1084#L1107true assume 1 == ~E_2~0;~E_2~0 := 2; 1135#L1112true assume 1 == ~E_3~0;~E_3~0 := 2; 1231#L1117true assume 1 == ~E_4~0;~E_4~0 := 2; 472#L1122true assume 1 == ~E_5~0;~E_5~0 := 2; 109#L1127true assume 1 == ~E_6~0;~E_6~0 := 2; 830#L1132true assume 1 == ~E_7~0;~E_7~0 := 2; 310#L1137true assume 1 == ~E_8~0;~E_8~0 := 2; 1183#L1142true assume 1 == ~E_9~0;~E_9~0 := 2; 633#L1148true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 115#L716-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 621#L754-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 508#L769-1true assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 313#L1447true assume !(0 == start_simulation_~tmp~3#1); 85#L1458true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 657#L716true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1075#L754true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 982#L769true assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 216#L1402true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 305#L1404true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 566#L1410true assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 361#L1460true assume !(0 != start_simulation_~tmp___0~1#1); 185#L1428true [2024-11-17 08:52:40,434 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:40,434 INFO L85 PathProgramCache]: Analyzing trace with hash 2013994962, now seen corresponding path program 1 times [2024-11-17 08:52:40,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:40,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642764064] [2024-11-17 08:52:40,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:40,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:40,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:40,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:40,712 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:40,712 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642764064] [2024-11-17 08:52:40,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642764064] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:40,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:40,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:40,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635797819] [2024-11-17 08:52:40,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:40,720 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:40,721 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:40,721 INFO L85 PathProgramCache]: Analyzing trace with hash 1209300740, now seen corresponding path program 1 times [2024-11-17 08:52:40,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:40,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012106923] [2024-11-17 08:52:40,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:40,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:40,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:40,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:40,797 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:40,798 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2012106923] [2024-11-17 08:52:40,798 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2012106923] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:40,799 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:40,799 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:40,799 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051885730] [2024-11-17 08:52:40,799 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:40,800 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:40,801 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:40,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:40,826 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:40,829 INFO L87 Difference]: Start difference. First operand has 1232 states, 1231 states have (on average 1.48659626320065) internal successors, (1830), 1231 states have internal predecessors, (1830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:40,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:40,907 INFO L93 Difference]: Finished difference Result 1220 states and 1792 transitions. [2024-11-17 08:52:40,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1220 states and 1792 transitions. [2024-11-17 08:52:40,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:40,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1220 states to 1214 states and 1786 transitions. [2024-11-17 08:52:40,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1214 [2024-11-17 08:52:40,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1214 [2024-11-17 08:52:40,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1214 states and 1786 transitions. [2024-11-17 08:52:40,935 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:40,936 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1786 transitions. [2024-11-17 08:52:40,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states and 1786 transitions. [2024-11-17 08:52:40,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1214. [2024-11-17 08:52:40,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1214 states, 1214 states have (on average 1.471169686985173) internal successors, (1786), 1213 states have internal predecessors, (1786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:40,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1214 states to 1214 states and 1786 transitions. [2024-11-17 08:52:40,995 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1786 transitions. [2024-11-17 08:52:40,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:41,000 INFO L425 stractBuchiCegarLoop]: Abstraction has 1214 states and 1786 transitions. [2024-11-17 08:52:41,000 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:52:41,000 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1214 states and 1786 transitions. [2024-11-17 08:52:41,007 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:41,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:41,010 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,010 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,011 INFO L745 eck$LassoCheckResult]: Stem: 3391#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 2523#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2524#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3310#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3311#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 3425#L663 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 3426#L668 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2789#L673 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2790#L678 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3496#L683 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2667#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2668#L693 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3357#L698 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3358#L703 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 3513#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3028#L939-1 assume !(0 == ~M_E~0); 3029#L944-1 assume !(0 == ~T1_E~0); 3120#L949-1 assume !(0 == ~T2_E~0); 3114#L954-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3115#L959-1 assume !(0 == ~T4_E~0); 3552#L964-1 assume !(0 == ~T5_E~0); 2838#L969-1 assume !(0 == ~T6_E~0); 2839#L974-1 assume !(0 == ~T7_E~0); 3505#L979-1 assume !(0 == ~T8_E~0); 3506#L984-1 assume !(0 == ~T9_E~0); 3005#L989-1 assume !(0 == ~E_M~0); 3006#L994-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2878#L999-1 assume !(0 == ~E_2~0); 2879#L1004-1 assume !(0 == ~E_3~0); 2547#L1009-1 assume !(0 == ~E_4~0); 2548#L1014-1 assume !(0 == ~E_5~0); 2871#L1019-1 assume !(0 == ~E_6~0); 3463#L1024-1 assume !(0 == ~E_7~0); 2791#L1029-1 assume !(0 == ~E_8~0); 2792#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 2904#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2590#L460-12 assume 1 == ~m_pc~0; 2591#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2533#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2534#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3110#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 3416#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3417#L479-12 assume !(1 == ~t1_pc~0); 2476#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 2475#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3081#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2562#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 2563#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3141#L498-12 assume 1 == ~t2_pc~0; 3142#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3492#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2483#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2484#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 3512#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3187#L517-12 assume 1 == ~t3_pc~0; 3091#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3092#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2924#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2925#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 3628#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2702#L536-12 assume 1 == ~t4_pc~0; 2703#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2765#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2766#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3364#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 2880#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2881#L555-12 assume !(1 == ~t5_pc~0); 2731#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 2732#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3580#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3447#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 3016#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2535#L574-12 assume 1 == ~t6_pc~0; 2536#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2891#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3071#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3072#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 2799#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2800#L593-12 assume 1 == ~t7_pc~0; 3172#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3373#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2582#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2583#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 3113#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3633#L612-12 assume 1 == ~t8_pc~0; 3646#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3647#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3658#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3567#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 2864#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2865#L631-12 assume !(1 == ~t9_pc~0); 2608#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 2609#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3670#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3641#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 2538#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2539#L1047-1 assume !(1 == ~M_E~0); 3231#L1052-1 assume !(1 == ~T1_E~0); 2490#L1057-1 assume !(1 == ~T2_E~0); 2491#L1062-1 assume !(1 == ~T3_E~0); 2769#L1067-1 assume !(1 == ~T4_E~0); 3107#L1072-1 assume !(1 == ~T5_E~0); 3108#L1077-1 assume !(1 == ~T6_E~0); 2654#L1082-1 assume !(1 == ~T7_E~0); 2655#L1087-1 assume !(1 == ~T8_E~0); 2466#L1092-1 assume !(1 == ~T9_E~0); 2467#L1097-1 assume !(1 == ~E_M~0); 2492#L1102-1 assume !(1 == ~E_1~0); 3312#L1107-1 assume !(1 == ~E_2~0); 3234#L1112-1 assume !(1 == ~E_3~0); 3235#L1117-1 assume !(1 == ~E_4~0); 3286#L1122-1 assume !(1 == ~E_5~0); 3170#L1127-1 assume !(1 == ~E_6~0); 2905#L1132-1 assume !(1 == ~E_7~0); 2906#L1137-1 assume !(1 == ~E_8~0); 2767#L1142-1 assume !(1 == ~E_9~0); 2768#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 2829#L1428 [2024-11-17 08:52:41,013 INFO L747 eck$LassoCheckResult]: Loop: 2829#L1428 assume true; 2830#L1428-1 assume !false; 2887#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2888#L778 assume true; 3386#L778-1 assume !false; 3387#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3642#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2745#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3328#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3329#L783 assume !(0 != eval_~tmp~0#1); 3427#L786 assume true; 3152#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3153#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3608#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 3525#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2822#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2823#L954 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3596#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3475#L964 assume !(0 == ~T5_E~0); 2763#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2764#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3455#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3437#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3269#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 3270#L994 assume 0 == ~E_1~0;~E_1~0 := 1; 3674#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 3221#L1004 assume !(0 == ~E_3~0); 2754#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 2755#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 3335#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 3336#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 3400#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 3302#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 3058#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3059#L460-1 assume 1 == ~m_pc~0; 3555#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3556#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3179#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3180#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3211#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2610#L479-1 assume 1 == ~t1_pc~0; 2611#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3548#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3452#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3453#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2797#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2798#L498-1 assume !(1 == ~t2_pc~0); 3045#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 3046#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3663#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2606#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2607#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2815#L517-1 assume !(1 == ~t3_pc~0); 3188#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 3189#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2733#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2734#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2938#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2955#L536-1 assume 1 == ~t4_pc~0; 3589#L537-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2890#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3374#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3375#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3673#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3632#L555-1 assume !(1 == ~t5_pc~0); 2500#L565-1 is_transmit5_triggered_~__retres1~5#1 := 0; 2501#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3197#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3289#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3290#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3494#L574-1 assume !(1 == ~t6_pc~0); 2651#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 2564#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2565#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3249#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3140#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2646#L593-1 assume 1 == ~t7_pc~0; 2647#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3064#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3296#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2508#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2509#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3193#L612-1 assume 1 == ~t8_pc~0; 2712#L613-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2713#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3591#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2720#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2470#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2471#L631-1 assume 1 == ~t9_pc~0; 3033#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2593#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2594#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3473#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3111#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3112#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 3162#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2549#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2493#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2494#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2983#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3535#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3536#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3521#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3522#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3526#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 3527#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 3659#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 3660#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 3668#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 3256#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 2690#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 2691#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 3035#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 3036#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 3434#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2700#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2589#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3300#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3039#L1447 assume !(0 == start_simulation_~tmp~3#1); 2642#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2643#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2511#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3634#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 2876#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2877#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3027#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3109#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 2829#L1428 [2024-11-17 08:52:41,019 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,019 INFO L85 PathProgramCache]: Analyzing trace with hash -997061167, now seen corresponding path program 1 times [2024-11-17 08:52:41,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [102215943] [2024-11-17 08:52:41,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [102215943] [2024-11-17 08:52:41,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [102215943] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,100 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:41,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221108240] [2024-11-17 08:52:41,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,101 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:41,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,102 INFO L85 PathProgramCache]: Analyzing trace with hash -976322229, now seen corresponding path program 1 times [2024-11-17 08:52:41,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792520982] [2024-11-17 08:52:41,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,225 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792520982] [2024-11-17 08:52:41,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792520982] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,226 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:41,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1812705993] [2024-11-17 08:52:41,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,227 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:41,227 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:41,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:41,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:41,228 INFO L87 Difference]: Start difference. First operand 1214 states and 1786 transitions. cyclomatic complexity: 573 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:41,250 INFO L93 Difference]: Finished difference Result 1214 states and 1785 transitions. [2024-11-17 08:52:41,250 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1214 states and 1785 transitions. [2024-11-17 08:52:41,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1214 states to 1214 states and 1785 transitions. [2024-11-17 08:52:41,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1214 [2024-11-17 08:52:41,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1214 [2024-11-17 08:52:41,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1214 states and 1785 transitions. [2024-11-17 08:52:41,265 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:41,265 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1785 transitions. [2024-11-17 08:52:41,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states and 1785 transitions. [2024-11-17 08:52:41,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1214. [2024-11-17 08:52:41,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1214 states, 1214 states have (on average 1.470345963756178) internal successors, (1785), 1213 states have internal predecessors, (1785), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1214 states to 1214 states and 1785 transitions. [2024-11-17 08:52:41,285 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1785 transitions. [2024-11-17 08:52:41,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:41,286 INFO L425 stractBuchiCegarLoop]: Abstraction has 1214 states and 1785 transitions. [2024-11-17 08:52:41,286 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:52:41,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1214 states and 1785 transitions. [2024-11-17 08:52:41,291 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,291 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:41,291 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:41,292 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,292 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,293 INFO L745 eck$LassoCheckResult]: Stem: 5828#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 4964#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 4965#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5747#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5748#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 5862#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5863#L668 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5226#L673 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5227#L678 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5933#L683 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5104#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5105#L693 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5794#L698 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5795#L703 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 5950#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5465#L939-1 assume !(0 == ~M_E~0); 5466#L944-1 assume !(0 == ~T1_E~0); 5557#L949-1 assume !(0 == ~T2_E~0); 5551#L954-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5552#L959-1 assume !(0 == ~T4_E~0); 5989#L964-1 assume !(0 == ~T5_E~0); 5275#L969-1 assume !(0 == ~T6_E~0); 5276#L974-1 assume !(0 == ~T7_E~0); 5942#L979-1 assume !(0 == ~T8_E~0); 5943#L984-1 assume !(0 == ~T9_E~0); 5443#L989-1 assume !(0 == ~E_M~0); 5444#L994-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5315#L999-1 assume !(0 == ~E_2~0); 5316#L1004-1 assume !(0 == ~E_3~0); 4984#L1009-1 assume !(0 == ~E_4~0); 4985#L1014-1 assume !(0 == ~E_5~0); 5310#L1019-1 assume !(0 == ~E_6~0); 5901#L1024-1 assume !(0 == ~E_7~0); 5228#L1029-1 assume !(0 == ~E_8~0); 5229#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 5341#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5027#L460-12 assume 1 == ~m_pc~0; 5028#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4970#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4971#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5547#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 5853#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5854#L479-12 assume !(1 == ~t1_pc~0); 4913#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 4912#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5520#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4999#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 5000#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5578#L498-12 assume 1 == ~t2_pc~0; 5579#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5929#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4920#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4921#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 5949#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5624#L517-12 assume 1 == ~t3_pc~0; 5528#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5529#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5361#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5362#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 6065#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5142#L536-12 assume 1 == ~t4_pc~0; 5143#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5202#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5203#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5802#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 5317#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5318#L555-12 assume !(1 == ~t5_pc~0); 5168#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 5169#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6017#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5884#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 5453#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4972#L574-12 assume 1 == ~t6_pc~0; 4973#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5333#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5508#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5509#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 5236#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5237#L593-12 assume 1 == ~t7_pc~0; 5609#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5810#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5019#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5020#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 5550#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6070#L612-12 assume 1 == ~t8_pc~0; 6084#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6085#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6095#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6004#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 5301#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5302#L631-12 assume !(1 == ~t9_pc~0); 5050#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 5051#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6107#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6078#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 4975#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4976#L1047-1 assume !(1 == ~M_E~0); 5668#L1052-1 assume !(1 == ~T1_E~0); 4927#L1057-1 assume !(1 == ~T2_E~0); 4928#L1062-1 assume !(1 == ~T3_E~0); 5206#L1067-1 assume !(1 == ~T4_E~0); 5544#L1072-1 assume !(1 == ~T5_E~0); 5545#L1077-1 assume !(1 == ~T6_E~0); 5091#L1082-1 assume !(1 == ~T7_E~0); 5092#L1087-1 assume !(1 == ~T8_E~0); 4905#L1092-1 assume !(1 == ~T9_E~0); 4906#L1097-1 assume !(1 == ~E_M~0); 4929#L1102-1 assume !(1 == ~E_1~0); 5749#L1107-1 assume !(1 == ~E_2~0); 5671#L1112-1 assume !(1 == ~E_3~0); 5672#L1117-1 assume !(1 == ~E_4~0); 5724#L1122-1 assume !(1 == ~E_5~0); 5607#L1127-1 assume !(1 == ~E_6~0); 5342#L1132-1 assume !(1 == ~E_7~0); 5343#L1137-1 assume !(1 == ~E_8~0); 5204#L1142-1 assume !(1 == ~E_9~0); 5205#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 5266#L1428 [2024-11-17 08:52:41,293 INFO L747 eck$LassoCheckResult]: Loop: 5266#L1428 assume true; 5267#L1428-1 assume !false; 5324#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5325#L778 assume true; 5823#L778-1 assume !false; 5824#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 6079#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5182#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5765#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5766#L783 assume !(0 != eval_~tmp~0#1); 5864#L786 assume true; 5589#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5590#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6045#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 5962#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5259#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5260#L954 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6033#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5915#L964 assume !(0 == ~T5_E~0); 5200#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5201#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5892#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5874#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5706#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 5707#L994 assume 0 == ~E_1~0;~E_1~0 := 1; 6111#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 5658#L1004 assume !(0 == ~E_3~0); 5191#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 5192#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 5772#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 5773#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 5837#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 5739#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 5495#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5496#L460-1 assume 1 == ~m_pc~0; 5992#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5993#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5616#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5617#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5648#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5045#L479-1 assume 1 == ~t1_pc~0; 5046#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5984#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5889#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5890#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5233#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5234#L498-1 assume 1 == ~t2_pc~0; 5891#L499-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5483#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6100#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5043#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5044#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5252#L517-1 assume !(1 == ~t3_pc~0); 5625#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 5626#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5170#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5171#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5375#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5392#L536-1 assume 1 == ~t4_pc~0; 6026#L537-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5327#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5811#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5812#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6110#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6069#L555-1 assume !(1 == ~t5_pc~0); 4937#L565-1 is_transmit5_triggered_~__retres1~5#1 := 0; 4938#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5634#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5726#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5727#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5931#L574-1 assume !(1 == ~t6_pc~0); 5088#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 5002#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5003#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5686#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5577#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5083#L593-1 assume 1 == ~t7_pc~0; 5084#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5501#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5733#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4947#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4948#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5630#L612-1 assume !(1 == ~t8_pc~0); 5152#L622-1 is_transmit8_triggered_~__retres1~8#1 := 0; 5151#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6028#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5159#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4909#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4910#L631-1 assume 1 == ~t9_pc~0; 5470#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5030#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5031#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5910#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5548#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5549#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 5600#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4986#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4930#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4931#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5420#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5973#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5974#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5958#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5959#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5963#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 5964#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 6096#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 6097#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 6105#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 5693#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 5127#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 5128#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 5472#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 5473#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 5871#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5140#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5026#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5737#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 5476#L1447 assume !(0 == start_simulation_~tmp~3#1); 5079#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5080#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4950#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6071#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 5313#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5314#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5464#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5546#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 5266#L1428 [2024-11-17 08:52:41,294 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,294 INFO L85 PathProgramCache]: Analyzing trace with hash -1232739342, now seen corresponding path program 1 times [2024-11-17 08:52:41,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,294 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435482081] [2024-11-17 08:52:41,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435482081] [2024-11-17 08:52:41,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435482081] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:41,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [742142726] [2024-11-17 08:52:41,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,335 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:41,336 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,336 INFO L85 PathProgramCache]: Analyzing trace with hash -1241258293, now seen corresponding path program 1 times [2024-11-17 08:52:41,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,336 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1858210583] [2024-11-17 08:52:41,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1858210583] [2024-11-17 08:52:41,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1858210583] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,415 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,415 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:41,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1487007643] [2024-11-17 08:52:41,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,415 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:41,415 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:41,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:41,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:41,416 INFO L87 Difference]: Start difference. First operand 1214 states and 1785 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:41,461 INFO L93 Difference]: Finished difference Result 1214 states and 1784 transitions. [2024-11-17 08:52:41,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1214 states and 1784 transitions. [2024-11-17 08:52:41,466 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1214 states to 1214 states and 1784 transitions. [2024-11-17 08:52:41,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1214 [2024-11-17 08:52:41,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1214 [2024-11-17 08:52:41,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1214 states and 1784 transitions. [2024-11-17 08:52:41,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:41,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1784 transitions. [2024-11-17 08:52:41,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states and 1784 transitions. [2024-11-17 08:52:41,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1214. [2024-11-17 08:52:41,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1214 states, 1214 states have (on average 1.4695222405271828) internal successors, (1784), 1213 states have internal predecessors, (1784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1214 states to 1214 states and 1784 transitions. [2024-11-17 08:52:41,488 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1784 transitions. [2024-11-17 08:52:41,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:41,489 INFO L425 stractBuchiCegarLoop]: Abstraction has 1214 states and 1784 transitions. [2024-11-17 08:52:41,489 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:52:41,489 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1214 states and 1784 transitions. [2024-11-17 08:52:41,494 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,494 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:41,494 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:41,496 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,496 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,497 INFO L745 eck$LassoCheckResult]: Stem: 8265#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 7401#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7402#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8184#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8185#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 8300#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8301#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7663#L673 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7664#L678 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8370#L683 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7541#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7542#L693 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8231#L698 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8232#L703 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 8387#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7902#L939-1 assume !(0 == ~M_E~0); 7903#L944-1 assume !(0 == ~T1_E~0); 7994#L949-1 assume !(0 == ~T2_E~0); 7989#L954-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7990#L959-1 assume !(0 == ~T4_E~0); 8426#L964-1 assume !(0 == ~T5_E~0); 7712#L969-1 assume !(0 == ~T6_E~0); 7713#L974-1 assume !(0 == ~T7_E~0); 8379#L979-1 assume !(0 == ~T8_E~0); 8380#L984-1 assume !(0 == ~T9_E~0); 7879#L989-1 assume !(0 == ~E_M~0); 7880#L994-1 assume 0 == ~E_1~0;~E_1~0 := 1; 7752#L999-1 assume !(0 == ~E_2~0); 7753#L1004-1 assume !(0 == ~E_3~0); 7421#L1009-1 assume !(0 == ~E_4~0); 7422#L1014-1 assume !(0 == ~E_5~0); 7745#L1019-1 assume !(0 == ~E_6~0); 8337#L1024-1 assume !(0 == ~E_7~0); 7665#L1029-1 assume !(0 == ~E_8~0); 7666#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 7778#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7460#L460-12 assume 1 == ~m_pc~0; 7461#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7407#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7408#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7984#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 8290#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8291#L479-12 assume !(1 == ~t1_pc~0); 7350#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 7349#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7955#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7436#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 7437#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8015#L498-12 assume 1 == ~t2_pc~0; 8016#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8366#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7357#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7358#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 8386#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8061#L517-12 assume 1 == ~t3_pc~0; 7964#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7965#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7798#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7799#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 8502#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7574#L536-12 assume 1 == ~t4_pc~0; 7575#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7639#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7640#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8238#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 7754#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7755#L555-12 assume !(1 == ~t5_pc~0); 7605#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 7606#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8454#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8321#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 7890#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7409#L574-12 assume 1 == ~t6_pc~0; 7410#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7765#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7945#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7946#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 7673#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7674#L593-12 assume 1 == ~t7_pc~0; 8046#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8247#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7456#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7457#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 7987#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8507#L612-12 assume 1 == ~t8_pc~0; 8520#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8521#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8532#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8441#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 7736#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7737#L631-12 assume !(1 == ~t9_pc~0); 7482#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 7483#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8544#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8515#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 7412#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7413#L1047-1 assume !(1 == ~M_E~0); 8105#L1052-1 assume !(1 == ~T1_E~0); 7364#L1057-1 assume !(1 == ~T2_E~0); 7365#L1062-1 assume !(1 == ~T3_E~0); 7643#L1067-1 assume !(1 == ~T4_E~0); 7981#L1072-1 assume !(1 == ~T5_E~0); 7982#L1077-1 assume !(1 == ~T6_E~0); 7526#L1082-1 assume !(1 == ~T7_E~0); 7527#L1087-1 assume !(1 == ~T8_E~0); 7340#L1092-1 assume !(1 == ~T9_E~0); 7341#L1097-1 assume !(1 == ~E_M~0); 7366#L1102-1 assume !(1 == ~E_1~0); 8186#L1107-1 assume !(1 == ~E_2~0); 8108#L1112-1 assume !(1 == ~E_3~0); 8109#L1117-1 assume !(1 == ~E_4~0); 8157#L1122-1 assume !(1 == ~E_5~0); 8044#L1127-1 assume !(1 == ~E_6~0); 7779#L1132-1 assume !(1 == ~E_7~0); 7780#L1137-1 assume !(1 == ~E_8~0); 7641#L1142-1 assume !(1 == ~E_9~0); 7642#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 7702#L1428 [2024-11-17 08:52:41,498 INFO L747 eck$LassoCheckResult]: Loop: 7702#L1428 assume true; 7703#L1428-1 assume !false; 7761#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7762#L778 assume true; 8260#L778-1 assume !false; 8261#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 8516#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7617#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8202#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8203#L783 assume !(0 != eval_~tmp~0#1); 8299#L786 assume true; 8026#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8027#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8482#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 8399#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7696#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7697#L954 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8470#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8349#L964 assume !(0 == ~T5_E~0); 7637#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7638#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8329#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8311#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8143#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 8144#L994 assume 0 == ~E_1~0;~E_1~0 := 1; 8548#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 8095#L1004 assume !(0 == ~E_3~0); 7628#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 7629#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 8209#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 8210#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 8274#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 8176#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 7932#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7933#L460-1 assume 1 == ~m_pc~0; 8429#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 8430#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8053#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8054#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8085#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7484#L479-1 assume 1 == ~t1_pc~0; 7485#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8422#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8326#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8327#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7670#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7671#L498-1 assume 1 == ~t2_pc~0; 8328#L499-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7920#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8537#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7480#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7481#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7689#L517-1 assume 1 == ~t3_pc~0; 8418#L518-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8063#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7607#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7608#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7812#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7829#L536-1 assume !(1 == ~t4_pc~0); 7763#L546-1 is_transmit4_triggered_~__retres1~4#1 := 0; 7764#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8248#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8249#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8547#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8506#L555-1 assume 1 == ~t5_pc~0; 7729#L556-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7375#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8071#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8163#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8164#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8368#L574-1 assume !(1 == ~t6_pc~0); 7525#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 7439#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7440#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8123#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8014#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7520#L593-1 assume 1 == ~t7_pc~0; 7521#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7938#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8170#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7384#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7385#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8067#L612-1 assume 1 == ~t8_pc~0; 7587#L613-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7588#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8465#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7596#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7346#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7347#L631-1 assume 1 == ~t9_pc~0; 7907#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7467#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7468#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8347#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7985#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7986#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 8037#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7423#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7369#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7370#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7857#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8410#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8411#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8395#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8396#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8400#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 8401#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 8533#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 8534#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 8542#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 8130#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 7564#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 7565#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 7909#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 7910#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 8308#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7580#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7466#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8174#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 7913#L1447 assume !(0 == start_simulation_~tmp~3#1); 7516#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7517#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 7387#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8508#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 7750#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7751#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7901#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7983#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 7702#L1428 [2024-11-17 08:52:41,498 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,499 INFO L85 PathProgramCache]: Analyzing trace with hash -409057871, now seen corresponding path program 1 times [2024-11-17 08:52:41,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,499 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1933053009] [2024-11-17 08:52:41,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,537 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1933053009] [2024-11-17 08:52:41,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1933053009] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:41,538 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1284087262] [2024-11-17 08:52:41,538 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,538 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:41,538 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,538 INFO L85 PathProgramCache]: Analyzing trace with hash -1882017723, now seen corresponding path program 1 times [2024-11-17 08:52:41,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242802874] [2024-11-17 08:52:41,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242802874] [2024-11-17 08:52:41,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1242802874] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:41,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [763933618] [2024-11-17 08:52:41,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,601 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:41,601 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:41,601 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:41,601 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:41,601 INFO L87 Difference]: Start difference. First operand 1214 states and 1784 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:41,623 INFO L93 Difference]: Finished difference Result 1214 states and 1783 transitions. [2024-11-17 08:52:41,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1214 states and 1783 transitions. [2024-11-17 08:52:41,629 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1214 states to 1214 states and 1783 transitions. [2024-11-17 08:52:41,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1214 [2024-11-17 08:52:41,636 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1214 [2024-11-17 08:52:41,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1214 states and 1783 transitions. [2024-11-17 08:52:41,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:41,637 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1783 transitions. [2024-11-17 08:52:41,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states and 1783 transitions. [2024-11-17 08:52:41,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1214. [2024-11-17 08:52:41,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1214 states, 1214 states have (on average 1.468698517298188) internal successors, (1783), 1213 states have internal predecessors, (1783), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1214 states to 1214 states and 1783 transitions. [2024-11-17 08:52:41,655 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1783 transitions. [2024-11-17 08:52:41,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:41,657 INFO L425 stractBuchiCegarLoop]: Abstraction has 1214 states and 1783 transitions. [2024-11-17 08:52:41,657 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:52:41,657 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1214 states and 1783 transitions. [2024-11-17 08:52:41,661 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:41,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:41,662 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,662 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,662 INFO L745 eck$LassoCheckResult]: Stem: 10702#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 9834#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 9835#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10621#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10622#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 10736#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10737#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10100#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10101#L678 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10807#L683 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9978#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9979#L693 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10668#L698 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10669#L703 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 10824#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10339#L939-1 assume !(0 == ~M_E~0); 10340#L944-1 assume !(0 == ~T1_E~0); 10431#L949-1 assume !(0 == ~T2_E~0); 10425#L954-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10426#L959-1 assume !(0 == ~T4_E~0); 10863#L964-1 assume !(0 == ~T5_E~0); 10147#L969-1 assume !(0 == ~T6_E~0); 10148#L974-1 assume !(0 == ~T7_E~0); 10816#L979-1 assume !(0 == ~T8_E~0); 10817#L984-1 assume !(0 == ~T9_E~0); 10316#L989-1 assume !(0 == ~E_M~0); 10317#L994-1 assume 0 == ~E_1~0;~E_1~0 := 1; 10189#L999-1 assume !(0 == ~E_2~0); 10190#L1004-1 assume !(0 == ~E_3~0); 9858#L1009-1 assume !(0 == ~E_4~0); 9859#L1014-1 assume !(0 == ~E_5~0); 10182#L1019-1 assume !(0 == ~E_6~0); 10774#L1024-1 assume !(0 == ~E_7~0); 10102#L1029-1 assume !(0 == ~E_8~0); 10103#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 10215#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9897#L460-12 assume 1 == ~m_pc~0; 9898#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9844#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9845#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10421#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 10727#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10728#L479-12 assume !(1 == ~t1_pc~0); 9787#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 9786#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10392#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9873#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 9874#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10452#L498-12 assume 1 == ~t2_pc~0; 10453#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10803#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9794#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9795#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 10823#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10498#L517-12 assume 1 == ~t3_pc~0; 10401#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10402#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10235#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10236#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 10939#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10011#L536-12 assume 1 == ~t4_pc~0; 10012#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10076#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10077#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10675#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 10191#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10192#L555-12 assume !(1 == ~t5_pc~0); 10042#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 10043#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10891#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10758#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 10327#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9846#L574-12 assume 1 == ~t6_pc~0; 9847#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10202#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10382#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10383#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 10110#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10111#L593-12 assume 1 == ~t7_pc~0; 10483#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10684#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9893#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9894#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 10424#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10944#L612-12 assume 1 == ~t8_pc~0; 10957#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10958#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10969#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10878#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 10173#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10174#L631-12 assume !(1 == ~t9_pc~0); 9919#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 9920#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10981#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10952#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 9849#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9850#L1047-1 assume !(1 == ~M_E~0); 10542#L1052-1 assume !(1 == ~T1_E~0); 9801#L1057-1 assume !(1 == ~T2_E~0); 9802#L1062-1 assume !(1 == ~T3_E~0); 10080#L1067-1 assume !(1 == ~T4_E~0); 10418#L1072-1 assume !(1 == ~T5_E~0); 10419#L1077-1 assume !(1 == ~T6_E~0); 9963#L1082-1 assume !(1 == ~T7_E~0); 9964#L1087-1 assume !(1 == ~T8_E~0); 9777#L1092-1 assume !(1 == ~T9_E~0); 9778#L1097-1 assume !(1 == ~E_M~0); 9803#L1102-1 assume !(1 == ~E_1~0); 10623#L1107-1 assume !(1 == ~E_2~0); 10545#L1112-1 assume !(1 == ~E_3~0); 10546#L1117-1 assume !(1 == ~E_4~0); 10594#L1122-1 assume !(1 == ~E_5~0); 10481#L1127-1 assume !(1 == ~E_6~0); 10216#L1132-1 assume !(1 == ~E_7~0); 10217#L1137-1 assume !(1 == ~E_8~0); 10078#L1142-1 assume !(1 == ~E_9~0); 10079#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 10139#L1428 [2024-11-17 08:52:41,663 INFO L747 eck$LassoCheckResult]: Loop: 10139#L1428 assume true; 10140#L1428-1 assume !false; 10198#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10199#L778 assume true; 10697#L778-1 assume !false; 10698#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10953#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 10054#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10639#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10640#L783 assume !(0 != eval_~tmp~0#1); 10738#L786 assume true; 10463#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10464#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10919#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 10836#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10133#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10134#L954 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10907#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10786#L964 assume !(0 == ~T5_E~0); 10074#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10075#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10766#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10748#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10580#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 10581#L994 assume 0 == ~E_1~0;~E_1~0 := 1; 10985#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 10532#L1004 assume !(0 == ~E_3~0); 10065#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 10066#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 10646#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 10647#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 10711#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 10613#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 10369#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10370#L460-1 assume 1 == ~m_pc~0; 10866#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10867#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10490#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10491#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10522#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9921#L479-1 assume 1 == ~t1_pc~0; 9922#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10859#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10763#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10764#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10107#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10108#L498-1 assume !(1 == ~t2_pc~0); 10356#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 10357#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10974#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9917#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9918#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10126#L517-1 assume !(1 == ~t3_pc~0); 10499#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 10500#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10044#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10045#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10249#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10266#L536-1 assume 1 == ~t4_pc~0; 10900#L537-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10201#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10685#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10686#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10984#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10943#L555-1 assume !(1 == ~t5_pc~0); 9811#L565-1 is_transmit5_triggered_~__retres1~5#1 := 0; 9812#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10508#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10600#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10601#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10805#L574-1 assume !(1 == ~t6_pc~0); 9962#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 9876#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9877#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10560#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10451#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9957#L593-1 assume 1 == ~t7_pc~0; 9958#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10375#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10607#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9821#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9822#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10504#L612-1 assume 1 == ~t8_pc~0; 10024#L613-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10025#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10902#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10033#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9783#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9784#L631-1 assume 1 == ~t9_pc~0; 10344#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9904#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9905#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10784#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10422#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10423#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 10474#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9860#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9806#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9807#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10294#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10847#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10848#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10832#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10833#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10837#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 10838#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 10970#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 10971#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 10979#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 10567#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 10001#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 10002#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 10346#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 10347#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 10745#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 10017#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9903#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10611#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 10350#L1447 assume !(0 == start_simulation_~tmp~3#1); 9953#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9954#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9824#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 10945#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 10187#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10188#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10338#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10420#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 10139#L1428 [2024-11-17 08:52:41,663 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,663 INFO L85 PathProgramCache]: Analyzing trace with hash -1490866158, now seen corresponding path program 1 times [2024-11-17 08:52:41,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,664 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510138766] [2024-11-17 08:52:41,664 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,664 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,691 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,691 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510138766] [2024-11-17 08:52:41,691 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510138766] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,691 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:41,692 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [991759920] [2024-11-17 08:52:41,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,692 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:41,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,692 INFO L85 PathProgramCache]: Analyzing trace with hash -976322229, now seen corresponding path program 2 times [2024-11-17 08:52:41,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236326163] [2024-11-17 08:52:41,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,749 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,749 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236326163] [2024-11-17 08:52:41,749 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236326163] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,749 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,749 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:41,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501915021] [2024-11-17 08:52:41,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,749 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:41,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:41,750 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:41,750 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:41,750 INFO L87 Difference]: Start difference. First operand 1214 states and 1783 transitions. cyclomatic complexity: 570 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:41,767 INFO L93 Difference]: Finished difference Result 1214 states and 1782 transitions. [2024-11-17 08:52:41,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1214 states and 1782 transitions. [2024-11-17 08:52:41,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,775 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1214 states to 1214 states and 1782 transitions. [2024-11-17 08:52:41,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1214 [2024-11-17 08:52:41,776 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1214 [2024-11-17 08:52:41,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1214 states and 1782 transitions. [2024-11-17 08:52:41,778 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:41,778 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1782 transitions. [2024-11-17 08:52:41,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states and 1782 transitions. [2024-11-17 08:52:41,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1214. [2024-11-17 08:52:41,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1214 states, 1214 states have (on average 1.4678747940691927) internal successors, (1782), 1213 states have internal predecessors, (1782), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1214 states to 1214 states and 1782 transitions. [2024-11-17 08:52:41,793 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1782 transitions. [2024-11-17 08:52:41,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:41,794 INFO L425 stractBuchiCegarLoop]: Abstraction has 1214 states and 1782 transitions. [2024-11-17 08:52:41,794 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:52:41,794 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1214 states and 1782 transitions. [2024-11-17 08:52:41,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:41,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:41,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,801 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,801 INFO L745 eck$LassoCheckResult]: Stem: 13139#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 12271#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12272#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13058#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13059#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 13173#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13174#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12537#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12538#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13244#L683 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12415#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12416#L693 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13105#L698 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13106#L703 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 13261#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12776#L939-1 assume !(0 == ~M_E~0); 12777#L944-1 assume !(0 == ~T1_E~0); 12868#L949-1 assume !(0 == ~T2_E~0); 12862#L954-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12863#L959-1 assume !(0 == ~T4_E~0); 13300#L964-1 assume !(0 == ~T5_E~0); 12584#L969-1 assume !(0 == ~T6_E~0); 12585#L974-1 assume !(0 == ~T7_E~0); 13253#L979-1 assume !(0 == ~T8_E~0); 13254#L984-1 assume !(0 == ~T9_E~0); 12753#L989-1 assume !(0 == ~E_M~0); 12754#L994-1 assume 0 == ~E_1~0;~E_1~0 := 1; 12626#L999-1 assume !(0 == ~E_2~0); 12627#L1004-1 assume !(0 == ~E_3~0); 12295#L1009-1 assume !(0 == ~E_4~0); 12296#L1014-1 assume !(0 == ~E_5~0); 12619#L1019-1 assume !(0 == ~E_6~0); 13211#L1024-1 assume !(0 == ~E_7~0); 12539#L1029-1 assume !(0 == ~E_8~0); 12540#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 12652#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12334#L460-12 assume 1 == ~m_pc~0; 12335#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12281#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12282#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12858#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 13164#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13165#L479-12 assume !(1 == ~t1_pc~0); 12224#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 12223#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12829#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12310#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 12311#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12889#L498-12 assume 1 == ~t2_pc~0; 12890#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13240#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12231#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12232#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 13260#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12935#L517-12 assume 1 == ~t3_pc~0; 12838#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12839#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12672#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12673#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 13376#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12448#L536-12 assume 1 == ~t4_pc~0; 12449#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12513#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12514#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13112#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 12628#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12629#L555-12 assume !(1 == ~t5_pc~0); 12479#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 12480#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13328#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13195#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 12764#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12283#L574-12 assume 1 == ~t6_pc~0; 12284#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12639#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12819#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12820#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 12547#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12548#L593-12 assume 1 == ~t7_pc~0; 12920#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13121#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12330#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12331#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 12861#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13381#L612-12 assume 1 == ~t8_pc~0; 13394#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13395#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13406#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13315#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 12610#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12611#L631-12 assume !(1 == ~t9_pc~0); 12356#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 12357#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13418#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13389#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 12286#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12287#L1047-1 assume !(1 == ~M_E~0); 12979#L1052-1 assume !(1 == ~T1_E~0); 12238#L1057-1 assume !(1 == ~T2_E~0); 12239#L1062-1 assume !(1 == ~T3_E~0); 12517#L1067-1 assume !(1 == ~T4_E~0); 12855#L1072-1 assume !(1 == ~T5_E~0); 12856#L1077-1 assume !(1 == ~T6_E~0); 12400#L1082-1 assume !(1 == ~T7_E~0); 12401#L1087-1 assume !(1 == ~T8_E~0); 12214#L1092-1 assume !(1 == ~T9_E~0); 12215#L1097-1 assume !(1 == ~E_M~0); 12240#L1102-1 assume !(1 == ~E_1~0); 13060#L1107-1 assume !(1 == ~E_2~0); 12982#L1112-1 assume !(1 == ~E_3~0); 12983#L1117-1 assume !(1 == ~E_4~0); 13031#L1122-1 assume !(1 == ~E_5~0); 12918#L1127-1 assume !(1 == ~E_6~0); 12653#L1132-1 assume !(1 == ~E_7~0); 12654#L1137-1 assume !(1 == ~E_8~0); 12515#L1142-1 assume !(1 == ~E_9~0); 12516#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 12576#L1428 [2024-11-17 08:52:41,801 INFO L747 eck$LassoCheckResult]: Loop: 12576#L1428 assume true; 12577#L1428-1 assume !false; 12635#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12636#L778 assume true; 13134#L778-1 assume !false; 13135#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 13390#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12491#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13076#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 13077#L783 assume !(0 != eval_~tmp~0#1); 13175#L786 assume true; 12900#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12901#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13356#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 13273#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12570#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12571#L954 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13344#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13223#L964 assume !(0 == ~T5_E~0); 12511#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12512#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13203#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13185#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13017#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 13018#L994 assume 0 == ~E_1~0;~E_1~0 := 1; 13422#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 12969#L1004 assume !(0 == ~E_3~0); 12502#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 12503#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 13083#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 13084#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 13148#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 13050#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 12806#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12807#L460-1 assume 1 == ~m_pc~0; 13303#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13304#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12927#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12928#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12959#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12358#L479-1 assume 1 == ~t1_pc~0; 12359#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13296#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13200#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13201#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12544#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12545#L498-1 assume 1 == ~t2_pc~0; 13202#L499-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12794#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13411#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12354#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12355#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12563#L517-1 assume !(1 == ~t3_pc~0); 12936#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 12937#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12481#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12482#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12686#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12703#L536-1 assume 1 == ~t4_pc~0; 13337#L537-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12638#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13122#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13123#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13421#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13380#L555-1 assume !(1 == ~t5_pc~0); 12248#L565-1 is_transmit5_triggered_~__retres1~5#1 := 0; 12249#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12945#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13037#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13038#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13242#L574-1 assume 1 == ~t6_pc~0; 12803#L575-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12313#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12314#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12997#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12888#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12394#L593-1 assume 1 == ~t7_pc~0; 12395#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12812#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13044#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12258#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12259#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12941#L612-1 assume 1 == ~t8_pc~0; 12461#L613-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12462#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13339#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12470#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12220#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12221#L631-1 assume 1 == ~t9_pc~0; 12781#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12341#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12342#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13221#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12859#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12860#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 12911#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12297#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12243#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12244#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12731#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13284#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13285#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13269#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13270#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13274#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 13275#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 13407#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 13408#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 13416#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 13004#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 12438#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 12439#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 12783#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 12784#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 13182#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12454#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12340#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13048#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 12787#L1447 assume !(0 == start_simulation_~tmp~3#1); 12390#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12391#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 12261#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13382#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 12624#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12625#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12775#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12857#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 12576#L1428 [2024-11-17 08:52:41,802 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,802 INFO L85 PathProgramCache]: Analyzing trace with hash -971573871, now seen corresponding path program 1 times [2024-11-17 08:52:41,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301294334] [2024-11-17 08:52:41,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301294334] [2024-11-17 08:52:41,852 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301294334] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,852 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,852 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:41,852 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1649784649] [2024-11-17 08:52:41,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,852 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:41,852 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,853 INFO L85 PathProgramCache]: Analyzing trace with hash 2115277765, now seen corresponding path program 1 times [2024-11-17 08:52:41,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,853 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542336461] [2024-11-17 08:52:41,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,914 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542336461] [2024-11-17 08:52:41,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542336461] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,914 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,915 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:41,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1689317481] [2024-11-17 08:52:41,915 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,915 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:41,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:41,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:41,915 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:41,916 INFO L87 Difference]: Start difference. First operand 1214 states and 1782 transitions. cyclomatic complexity: 569 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:41,932 INFO L93 Difference]: Finished difference Result 1214 states and 1781 transitions. [2024-11-17 08:52:41,932 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1214 states and 1781 transitions. [2024-11-17 08:52:41,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1214 states to 1214 states and 1781 transitions. [2024-11-17 08:52:41,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1214 [2024-11-17 08:52:41,942 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1214 [2024-11-17 08:52:41,942 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1214 states and 1781 transitions. [2024-11-17 08:52:41,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:41,943 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1781 transitions. [2024-11-17 08:52:41,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states and 1781 transitions. [2024-11-17 08:52:41,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1214. [2024-11-17 08:52:41,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1214 states, 1214 states have (on average 1.4670510708401976) internal successors, (1781), 1213 states have internal predecessors, (1781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:41,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1214 states to 1214 states and 1781 transitions. [2024-11-17 08:52:41,956 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1781 transitions. [2024-11-17 08:52:41,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:41,958 INFO L425 stractBuchiCegarLoop]: Abstraction has 1214 states and 1781 transitions. [2024-11-17 08:52:41,958 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:52:41,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1214 states and 1781 transitions. [2024-11-17 08:52:41,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:41,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:41,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:41,963 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,963 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:41,964 INFO L745 eck$LassoCheckResult]: Stem: 15576#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 14708#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 14709#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15495#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15496#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 15610#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15611#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14974#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14975#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15681#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14852#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14853#L693 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15542#L698 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15543#L703 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 15698#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15213#L939-1 assume !(0 == ~M_E~0); 15214#L944-1 assume !(0 == ~T1_E~0); 15305#L949-1 assume !(0 == ~T2_E~0); 15299#L954-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15300#L959-1 assume !(0 == ~T4_E~0); 15737#L964-1 assume !(0 == ~T5_E~0); 15023#L969-1 assume !(0 == ~T6_E~0); 15024#L974-1 assume !(0 == ~T7_E~0); 15690#L979-1 assume !(0 == ~T8_E~0); 15691#L984-1 assume !(0 == ~T9_E~0); 15190#L989-1 assume !(0 == ~E_M~0); 15191#L994-1 assume 0 == ~E_1~0;~E_1~0 := 1; 15063#L999-1 assume !(0 == ~E_2~0); 15064#L1004-1 assume !(0 == ~E_3~0); 14732#L1009-1 assume !(0 == ~E_4~0); 14733#L1014-1 assume !(0 == ~E_5~0); 15056#L1019-1 assume !(0 == ~E_6~0); 15648#L1024-1 assume !(0 == ~E_7~0); 14976#L1029-1 assume !(0 == ~E_8~0); 14977#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 15089#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14775#L460-12 assume 1 == ~m_pc~0; 14776#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14718#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14719#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15295#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 15601#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15602#L479-12 assume !(1 == ~t1_pc~0); 14661#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 14660#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15266#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14747#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 14748#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15326#L498-12 assume 1 == ~t2_pc~0; 15327#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15677#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14668#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14669#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 15697#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15372#L517-12 assume 1 == ~t3_pc~0; 15276#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15277#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15109#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15110#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 15813#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14887#L536-12 assume 1 == ~t4_pc~0; 14888#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14950#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14951#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15549#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 15065#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15066#L555-12 assume !(1 == ~t5_pc~0); 14916#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 14917#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15765#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15632#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 15201#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14720#L574-12 assume 1 == ~t6_pc~0; 14721#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15076#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15256#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15257#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 14984#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14985#L593-12 assume 1 == ~t7_pc~0; 15357#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15558#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14767#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14768#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 15298#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15818#L612-12 assume 1 == ~t8_pc~0; 15831#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15832#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15843#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15752#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 15049#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15050#L631-12 assume !(1 == ~t9_pc~0); 14793#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 14794#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15855#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15826#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 14723#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14724#L1047-1 assume !(1 == ~M_E~0); 15416#L1052-1 assume !(1 == ~T1_E~0); 14675#L1057-1 assume !(1 == ~T2_E~0); 14676#L1062-1 assume !(1 == ~T3_E~0); 14954#L1067-1 assume !(1 == ~T4_E~0); 15292#L1072-1 assume !(1 == ~T5_E~0); 15293#L1077-1 assume !(1 == ~T6_E~0); 14839#L1082-1 assume !(1 == ~T7_E~0); 14840#L1087-1 assume !(1 == ~T8_E~0); 14651#L1092-1 assume !(1 == ~T9_E~0); 14652#L1097-1 assume !(1 == ~E_M~0); 14677#L1102-1 assume !(1 == ~E_1~0); 15497#L1107-1 assume !(1 == ~E_2~0); 15419#L1112-1 assume !(1 == ~E_3~0); 15420#L1117-1 assume !(1 == ~E_4~0); 15470#L1122-1 assume !(1 == ~E_5~0); 15355#L1127-1 assume !(1 == ~E_6~0); 15090#L1132-1 assume !(1 == ~E_7~0); 15091#L1137-1 assume !(1 == ~E_8~0); 14952#L1142-1 assume !(1 == ~E_9~0); 14953#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 15013#L1428 [2024-11-17 08:52:41,965 INFO L747 eck$LassoCheckResult]: Loop: 15013#L1428 assume true; 15014#L1428-1 assume !false; 15072#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15073#L778 assume true; 15571#L778-1 assume !false; 15572#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 15827#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14928#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15513#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15514#L783 assume !(0 != eval_~tmp~0#1); 15612#L786 assume true; 15337#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15338#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15793#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 15710#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15007#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15008#L954 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15781#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15660#L964 assume !(0 == ~T5_E~0); 14948#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14949#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15640#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15622#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15454#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 15455#L994 assume 0 == ~E_1~0;~E_1~0 := 1; 15859#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 15406#L1004 assume !(0 == ~E_3~0); 14939#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 14940#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 15520#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 15521#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 15585#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 15487#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 15243#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15244#L460-1 assume 1 == ~m_pc~0; 15740#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15741#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15364#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15365#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15396#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14795#L479-1 assume 1 == ~t1_pc~0; 14796#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15733#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15637#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15638#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14982#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14983#L498-1 assume 1 == ~t2_pc~0; 15639#L499-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15231#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15848#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14791#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14792#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15000#L517-1 assume 1 == ~t3_pc~0; 15729#L518-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15374#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14918#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14919#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15123#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15140#L536-1 assume !(1 == ~t4_pc~0); 15074#L546-1 is_transmit4_triggered_~__retres1~4#1 := 0; 15075#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15559#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15560#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15858#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15817#L555-1 assume 1 == ~t5_pc~0; 15041#L556-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14686#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15382#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15474#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15475#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15679#L574-1 assume !(1 == ~t6_pc~0); 14834#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 14749#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14750#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15434#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15325#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14831#L593-1 assume 1 == ~t7_pc~0; 14832#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15249#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15481#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14693#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14694#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15378#L612-1 assume 1 == ~t8_pc~0; 14897#L613-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14898#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15776#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14905#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14655#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14656#L631-1 assume 1 == ~t9_pc~0; 15218#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14778#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14779#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15658#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15296#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15297#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 15347#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14734#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14678#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14679#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15168#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15718#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15719#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15706#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15707#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15711#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 15712#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 15844#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 15845#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 15853#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 15441#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 14875#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 14876#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 15220#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 15221#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 15619#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14885#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14774#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15485#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 15224#L1447 assume !(0 == start_simulation_~tmp~3#1); 14827#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14828#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 14696#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15819#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 15061#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15062#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15212#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 15294#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 15013#L1428 [2024-11-17 08:52:41,965 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,965 INFO L85 PathProgramCache]: Analyzing trace with hash 15008818, now seen corresponding path program 1 times [2024-11-17 08:52:41,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,965 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1663920508] [2024-11-17 08:52:41,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:41,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:41,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:41,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:41,998 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:41,998 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1663920508] [2024-11-17 08:52:41,998 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1663920508] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:41,998 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:41,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:41,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1718463489] [2024-11-17 08:52:41,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:41,999 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:41,999 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:41,999 INFO L85 PathProgramCache]: Analyzing trace with hash -1882017723, now seen corresponding path program 2 times [2024-11-17 08:52:41,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:41,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321198362] [2024-11-17 08:52:42,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:42,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:42,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:42,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:42,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:42,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1321198362] [2024-11-17 08:52:42,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1321198362] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:42,056 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:42,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:42,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072199588] [2024-11-17 08:52:42,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:42,056 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:42,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:42,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:42,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:42,057 INFO L87 Difference]: Start difference. First operand 1214 states and 1781 transitions. cyclomatic complexity: 568 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:42,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:42,073 INFO L93 Difference]: Finished difference Result 1214 states and 1780 transitions. [2024-11-17 08:52:42,073 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1214 states and 1780 transitions. [2024-11-17 08:52:42,078 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:42,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1214 states to 1214 states and 1780 transitions. [2024-11-17 08:52:42,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1214 [2024-11-17 08:52:42,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1214 [2024-11-17 08:52:42,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1214 states and 1780 transitions. [2024-11-17 08:52:42,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:42,084 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1780 transitions. [2024-11-17 08:52:42,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states and 1780 transitions. [2024-11-17 08:52:42,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1214. [2024-11-17 08:52:42,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1214 states, 1214 states have (on average 1.4662273476112027) internal successors, (1780), 1213 states have internal predecessors, (1780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:42,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1214 states to 1214 states and 1780 transitions. [2024-11-17 08:52:42,099 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1780 transitions. [2024-11-17 08:52:42,100 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:42,101 INFO L425 stractBuchiCegarLoop]: Abstraction has 1214 states and 1780 transitions. [2024-11-17 08:52:42,101 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:52:42,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1214 states and 1780 transitions. [2024-11-17 08:52:42,106 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:42,106 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:42,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:42,107 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:42,107 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:42,107 INFO L745 eck$LassoCheckResult]: Stem: 18013#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 17149#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 17150#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17932#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17933#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 18047#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18048#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17411#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17412#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18118#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17289#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17290#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17979#L698 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17980#L703 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 18135#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17650#L939-1 assume !(0 == ~M_E~0); 17651#L944-1 assume !(0 == ~T1_E~0); 17742#L949-1 assume !(0 == ~T2_E~0); 17736#L954-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17737#L959-1 assume !(0 == ~T4_E~0); 18174#L964-1 assume !(0 == ~T5_E~0); 17460#L969-1 assume !(0 == ~T6_E~0); 17461#L974-1 assume !(0 == ~T7_E~0); 18127#L979-1 assume !(0 == ~T8_E~0); 18128#L984-1 assume !(0 == ~T9_E~0); 17628#L989-1 assume !(0 == ~E_M~0); 17629#L994-1 assume 0 == ~E_1~0;~E_1~0 := 1; 17500#L999-1 assume !(0 == ~E_2~0); 17501#L1004-1 assume !(0 == ~E_3~0); 17169#L1009-1 assume !(0 == ~E_4~0); 17170#L1014-1 assume !(0 == ~E_5~0); 17495#L1019-1 assume !(0 == ~E_6~0); 18086#L1024-1 assume !(0 == ~E_7~0); 17413#L1029-1 assume !(0 == ~E_8~0); 17414#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 17526#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17212#L460-12 assume 1 == ~m_pc~0; 17213#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17155#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17156#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17732#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 18038#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18039#L479-12 assume !(1 == ~t1_pc~0); 17098#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 17097#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17705#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17184#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 17185#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17763#L498-12 assume 1 == ~t2_pc~0; 17764#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18114#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17105#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17106#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 18134#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17809#L517-12 assume 1 == ~t3_pc~0; 17713#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17714#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17546#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17547#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 18250#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17327#L536-12 assume 1 == ~t4_pc~0; 17328#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17387#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17388#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17986#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 17502#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17503#L555-12 assume !(1 == ~t5_pc~0); 17353#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 17354#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18202#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18069#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 17638#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17157#L574-12 assume 1 == ~t6_pc~0; 17158#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17515#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17693#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17694#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 17421#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17422#L593-12 assume 1 == ~t7_pc~0; 17794#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17995#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17204#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17205#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 17735#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18255#L612-12 assume 1 == ~t8_pc~0; 18269#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18270#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18280#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18189#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 17486#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17487#L631-12 assume !(1 == ~t9_pc~0); 17235#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 17236#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18292#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18263#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 17160#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17161#L1047-1 assume !(1 == ~M_E~0); 17853#L1052-1 assume !(1 == ~T1_E~0); 17112#L1057-1 assume !(1 == ~T2_E~0); 17113#L1062-1 assume !(1 == ~T3_E~0); 17391#L1067-1 assume !(1 == ~T4_E~0); 17729#L1072-1 assume !(1 == ~T5_E~0); 17730#L1077-1 assume !(1 == ~T6_E~0); 17276#L1082-1 assume !(1 == ~T7_E~0); 17277#L1087-1 assume !(1 == ~T8_E~0); 17090#L1092-1 assume !(1 == ~T9_E~0); 17091#L1097-1 assume !(1 == ~E_M~0); 17114#L1102-1 assume !(1 == ~E_1~0); 17934#L1107-1 assume !(1 == ~E_2~0); 17856#L1112-1 assume !(1 == ~E_3~0); 17857#L1117-1 assume !(1 == ~E_4~0); 17909#L1122-1 assume !(1 == ~E_5~0); 17792#L1127-1 assume !(1 == ~E_6~0); 17527#L1132-1 assume !(1 == ~E_7~0); 17528#L1137-1 assume !(1 == ~E_8~0); 17389#L1142-1 assume !(1 == ~E_9~0); 17390#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 17451#L1428 [2024-11-17 08:52:42,109 INFO L747 eck$LassoCheckResult]: Loop: 17451#L1428 assume true; 17452#L1428-1 assume !false; 17509#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17510#L778 assume true; 18008#L778-1 assume !false; 18009#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18264#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17367#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17950#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17951#L783 assume !(0 != eval_~tmp~0#1); 18049#L786 assume true; 17774#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17775#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18230#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 18147#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17444#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17445#L954 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18218#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18098#L964 assume !(0 == ~T5_E~0); 17385#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17386#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18077#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18059#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17891#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 17892#L994 assume 0 == ~E_1~0;~E_1~0 := 1; 18296#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 17843#L1004 assume !(0 == ~E_3~0); 17376#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 17377#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 17957#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 17958#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 18022#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 17924#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 17680#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17681#L460-1 assume 1 == ~m_pc~0; 18177#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18178#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17801#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17802#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17833#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17230#L479-1 assume !(1 == ~t1_pc~0); 17232#L489-1 is_transmit1_triggered_~__retres1~1#1 := 0; 18169#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18074#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18075#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17418#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17419#L498-1 assume !(1 == ~t2_pc~0); 17667#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 17668#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18285#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17228#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17229#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17437#L517-1 assume !(1 == ~t3_pc~0); 17810#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 17811#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17355#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17356#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17560#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17577#L536-1 assume 1 == ~t4_pc~0; 18211#L537-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17512#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17996#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17997#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18295#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18254#L555-1 assume !(1 == ~t5_pc~0); 17122#L565-1 is_transmit5_triggered_~__retres1~5#1 := 0; 17123#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17819#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17911#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17912#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18116#L574-1 assume !(1 == ~t6_pc~0); 17273#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 17187#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17188#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17871#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17762#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17268#L593-1 assume 1 == ~t7_pc~0; 17269#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17686#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17918#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17132#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17133#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17815#L612-1 assume 1 == ~t8_pc~0; 17335#L613-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17336#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18213#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17344#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17094#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17095#L631-1 assume 1 == ~t9_pc~0; 17655#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17215#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17216#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18095#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17733#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17734#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 17785#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17171#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17115#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17116#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17605#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18158#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18159#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18143#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18144#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18148#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 18149#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 18281#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 18282#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 18290#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 17878#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 17312#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 17313#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 17657#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 17658#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 18056#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17325#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17211#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17922#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 17661#L1447 assume !(0 == start_simulation_~tmp~3#1); 17264#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 17265#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17135#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 18256#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 17498#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17499#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17649#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 17731#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 17451#L1428 [2024-11-17 08:52:42,110 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:42,110 INFO L85 PathProgramCache]: Analyzing trace with hash -1820834029, now seen corresponding path program 1 times [2024-11-17 08:52:42,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:42,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260087858] [2024-11-17 08:52:42,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:42,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:42,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:42,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:42,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:42,142 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1260087858] [2024-11-17 08:52:42,142 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1260087858] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:42,142 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:42,142 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:42,143 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015654700] [2024-11-17 08:52:42,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:42,144 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:42,144 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:42,144 INFO L85 PathProgramCache]: Analyzing trace with hash -1458369202, now seen corresponding path program 1 times [2024-11-17 08:52:42,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:42,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007371767] [2024-11-17 08:52:42,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:42,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:42,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:42,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:42,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:42,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007371767] [2024-11-17 08:52:42,200 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1007371767] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:42,200 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:42,200 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:42,200 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1123353168] [2024-11-17 08:52:42,200 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:42,200 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:42,200 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:42,201 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:42,201 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:42,201 INFO L87 Difference]: Start difference. First operand 1214 states and 1780 transitions. cyclomatic complexity: 567 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:42,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:42,244 INFO L93 Difference]: Finished difference Result 1214 states and 1779 transitions. [2024-11-17 08:52:42,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1214 states and 1779 transitions. [2024-11-17 08:52:42,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:42,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1214 states to 1214 states and 1779 transitions. [2024-11-17 08:52:42,253 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1214 [2024-11-17 08:52:42,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1214 [2024-11-17 08:52:42,253 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1214 states and 1779 transitions. [2024-11-17 08:52:42,254 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:42,254 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1779 transitions. [2024-11-17 08:52:42,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states and 1779 transitions. [2024-11-17 08:52:42,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1214. [2024-11-17 08:52:42,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1214 states, 1214 states have (on average 1.4654036243822075) internal successors, (1779), 1213 states have internal predecessors, (1779), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:42,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1214 states to 1214 states and 1779 transitions. [2024-11-17 08:52:42,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1779 transitions. [2024-11-17 08:52:42,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:42,271 INFO L425 stractBuchiCegarLoop]: Abstraction has 1214 states and 1779 transitions. [2024-11-17 08:52:42,272 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:52:42,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1214 states and 1779 transitions. [2024-11-17 08:52:42,276 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:42,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:42,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:42,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:42,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:42,278 INFO L745 eck$LassoCheckResult]: Stem: 20450#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 19586#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 19587#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20369#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20370#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 20485#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20486#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19848#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19849#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20555#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19726#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19727#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20416#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 20417#L703 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 20572#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20087#L939-1 assume !(0 == ~M_E~0); 20088#L944-1 assume !(0 == ~T1_E~0); 20179#L949-1 assume !(0 == ~T2_E~0); 20174#L954-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20175#L959-1 assume !(0 == ~T4_E~0); 20611#L964-1 assume !(0 == ~T5_E~0); 19897#L969-1 assume !(0 == ~T6_E~0); 19898#L974-1 assume !(0 == ~T7_E~0); 20564#L979-1 assume !(0 == ~T8_E~0); 20565#L984-1 assume !(0 == ~T9_E~0); 20065#L989-1 assume !(0 == ~E_M~0); 20066#L994-1 assume 0 == ~E_1~0;~E_1~0 := 1; 19937#L999-1 assume !(0 == ~E_2~0); 19938#L1004-1 assume !(0 == ~E_3~0); 19606#L1009-1 assume !(0 == ~E_4~0); 19607#L1014-1 assume !(0 == ~E_5~0); 19932#L1019-1 assume !(0 == ~E_6~0); 20523#L1024-1 assume !(0 == ~E_7~0); 19850#L1029-1 assume !(0 == ~E_8~0); 19851#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 19963#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19649#L460-12 assume 1 == ~m_pc~0; 19650#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19592#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19593#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20169#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 20475#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20476#L479-12 assume !(1 == ~t1_pc~0); 19537#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 19536#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20142#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19621#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 19622#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20201#L498-12 assume 1 == ~t2_pc~0; 20202#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20551#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19542#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19543#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 20571#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20246#L517-12 assume 1 == ~t3_pc~0; 20153#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20154#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19983#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19984#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 20687#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19764#L536-12 assume 1 == ~t4_pc~0; 19765#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19824#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19825#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20424#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 19939#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19940#L555-12 assume !(1 == ~t5_pc~0); 19790#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 19791#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20639#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20506#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 20075#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19594#L574-12 assume 1 == ~t6_pc~0; 19595#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19955#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20130#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20131#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 19858#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19859#L593-12 assume 1 == ~t7_pc~0; 20232#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20432#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19641#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19642#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 20172#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20692#L612-12 assume 1 == ~t8_pc~0; 20706#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20707#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20717#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20626#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 19923#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19924#L631-12 assume !(1 == ~t9_pc~0); 19672#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 19673#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20729#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20700#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 19597#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19598#L1047-1 assume !(1 == ~M_E~0); 20290#L1052-1 assume !(1 == ~T1_E~0); 19549#L1057-1 assume !(1 == ~T2_E~0); 19550#L1062-1 assume !(1 == ~T3_E~0); 19828#L1067-1 assume !(1 == ~T4_E~0); 20166#L1072-1 assume !(1 == ~T5_E~0); 20167#L1077-1 assume !(1 == ~T6_E~0); 19713#L1082-1 assume !(1 == ~T7_E~0); 19714#L1087-1 assume !(1 == ~T8_E~0); 19527#L1092-1 assume !(1 == ~T9_E~0); 19528#L1097-1 assume !(1 == ~E_M~0); 19551#L1102-1 assume !(1 == ~E_1~0); 20371#L1107-1 assume !(1 == ~E_2~0); 20293#L1112-1 assume !(1 == ~E_3~0); 20294#L1117-1 assume !(1 == ~E_4~0); 20346#L1122-1 assume !(1 == ~E_5~0); 20229#L1127-1 assume !(1 == ~E_6~0); 19964#L1132-1 assume !(1 == ~E_7~0); 19965#L1137-1 assume !(1 == ~E_8~0); 19826#L1142-1 assume !(1 == ~E_9~0); 19827#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 19887#L1428 [2024-11-17 08:52:42,278 INFO L747 eck$LassoCheckResult]: Loop: 19887#L1428 assume true; 19888#L1428-1 assume !false; 19946#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19947#L778 assume true; 20445#L778-1 assume !false; 20446#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 20701#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19802#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 20387#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20388#L783 assume !(0 != eval_~tmp~0#1); 20484#L786 assume true; 20211#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20212#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20667#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 20584#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19881#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19882#L954 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20655#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20534#L964 assume !(0 == ~T5_E~0); 19822#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19823#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20514#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20496#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 20328#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 20329#L994 assume 0 == ~E_1~0;~E_1~0 := 1; 20733#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 20280#L1004 assume !(0 == ~E_3~0); 19813#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 19814#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 20394#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 20395#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 20459#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 20361#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 20117#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20118#L460-1 assume 1 == ~m_pc~0; 20614#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20615#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20238#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20239#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20270#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19667#L479-1 assume 1 == ~t1_pc~0; 19668#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20607#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20511#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20512#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19855#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19856#L498-1 assume 1 == ~t2_pc~0; 20513#L499-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20105#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20722#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19665#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19666#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19874#L517-1 assume !(1 == ~t3_pc~0); 20247#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 20248#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19792#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19793#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19997#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20014#L536-1 assume 1 == ~t4_pc~0; 20648#L537-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19949#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20433#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20434#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20732#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20691#L555-1 assume !(1 == ~t5_pc~0); 19559#L565-1 is_transmit5_triggered_~__retres1~5#1 := 0; 19560#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20256#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20348#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20349#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20553#L574-1 assume 1 == ~t6_pc~0; 20114#L575-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19624#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19625#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20308#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20199#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19705#L593-1 assume 1 == ~t7_pc~0; 19706#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20123#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20355#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19569#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19570#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20252#L612-1 assume 1 == ~t8_pc~0; 19772#L613-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19773#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20650#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19781#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19531#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19532#L631-1 assume 1 == ~t9_pc~0; 20092#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19652#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19653#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20532#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20170#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20171#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 20222#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19608#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19554#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19555#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20042#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20595#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20596#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20580#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20581#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 20585#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 20586#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 20718#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 20719#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 20727#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 20315#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 19749#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 19750#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 20094#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 20095#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 20493#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19762#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19648#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 20359#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 20098#L1447 assume !(0 == start_simulation_~tmp~3#1); 19701#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 19702#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 19572#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 20693#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 19935#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19936#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20086#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 20168#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 19887#L1428 [2024-11-17 08:52:42,278 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:42,278 INFO L85 PathProgramCache]: Analyzing trace with hash -1880054766, now seen corresponding path program 1 times [2024-11-17 08:52:42,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:42,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172942787] [2024-11-17 08:52:42,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:42,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:42,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:42,307 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:42,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:42,307 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172942787] [2024-11-17 08:52:42,307 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [172942787] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:42,307 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:42,308 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:42,308 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1655479916] [2024-11-17 08:52:42,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:42,308 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:42,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:42,308 INFO L85 PathProgramCache]: Analyzing trace with hash 2115277765, now seen corresponding path program 2 times [2024-11-17 08:52:42,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:42,309 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882757755] [2024-11-17 08:52:42,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:42,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:42,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:42,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:42,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:42,356 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882757755] [2024-11-17 08:52:42,356 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882757755] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:42,356 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:42,356 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:42,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1239788145] [2024-11-17 08:52:42,356 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:42,357 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:42,357 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:42,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:42,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:42,357 INFO L87 Difference]: Start difference. First operand 1214 states and 1779 transitions. cyclomatic complexity: 566 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:42,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:42,373 INFO L93 Difference]: Finished difference Result 1214 states and 1778 transitions. [2024-11-17 08:52:42,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1214 states and 1778 transitions. [2024-11-17 08:52:42,377 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:42,381 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1214 states to 1214 states and 1778 transitions. [2024-11-17 08:52:42,381 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1214 [2024-11-17 08:52:42,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1214 [2024-11-17 08:52:42,382 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1214 states and 1778 transitions. [2024-11-17 08:52:42,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:42,383 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1778 transitions. [2024-11-17 08:52:42,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1214 states and 1778 transitions. [2024-11-17 08:52:42,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1214 to 1214. [2024-11-17 08:52:42,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1214 states, 1214 states have (on average 1.4645799011532126) internal successors, (1778), 1213 states have internal predecessors, (1778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:42,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1214 states to 1214 states and 1778 transitions. [2024-11-17 08:52:42,398 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1214 states and 1778 transitions. [2024-11-17 08:52:42,399 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:42,399 INFO L425 stractBuchiCegarLoop]: Abstraction has 1214 states and 1778 transitions. [2024-11-17 08:52:42,399 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:52:42,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1214 states and 1778 transitions. [2024-11-17 08:52:42,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1087 [2024-11-17 08:52:42,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:42,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:42,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:42,404 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:42,404 INFO L745 eck$LassoCheckResult]: Stem: 22887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 22019#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 22020#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22806#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22807#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 22921#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22922#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22285#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22286#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22992#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22163#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22164#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22853#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22854#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23009#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22524#L939-1 assume !(0 == ~M_E~0); 22525#L944-1 assume !(0 == ~T1_E~0); 22616#L949-1 assume !(0 == ~T2_E~0); 22610#L954-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22611#L959-1 assume !(0 == ~T4_E~0); 23048#L964-1 assume !(0 == ~T5_E~0); 22332#L969-1 assume !(0 == ~T6_E~0); 22333#L974-1 assume !(0 == ~T7_E~0); 23001#L979-1 assume !(0 == ~T8_E~0); 23002#L984-1 assume !(0 == ~T9_E~0); 22501#L989-1 assume !(0 == ~E_M~0); 22502#L994-1 assume 0 == ~E_1~0;~E_1~0 := 1; 22374#L999-1 assume !(0 == ~E_2~0); 22375#L1004-1 assume !(0 == ~E_3~0); 22043#L1009-1 assume !(0 == ~E_4~0); 22044#L1014-1 assume !(0 == ~E_5~0); 22367#L1019-1 assume !(0 == ~E_6~0); 22959#L1024-1 assume !(0 == ~E_7~0); 22287#L1029-1 assume !(0 == ~E_8~0); 22288#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 22400#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22082#L460-12 assume 1 == ~m_pc~0; 22083#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22029#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22030#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22606#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 22912#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22913#L479-12 assume !(1 == ~t1_pc~0); 21972#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 21971#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22577#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22058#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 22059#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22637#L498-12 assume 1 == ~t2_pc~0; 22638#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22988#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21979#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21980#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 23008#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22683#L517-12 assume 1 == ~t3_pc~0; 22586#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22587#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22420#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22421#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 23124#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22196#L536-12 assume 1 == ~t4_pc~0; 22197#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22261#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22262#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22860#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 22376#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22377#L555-12 assume !(1 == ~t5_pc~0); 22227#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 22228#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23076#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22943#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 22512#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22031#L574-12 assume 1 == ~t6_pc~0; 22032#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22387#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22567#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22568#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 22295#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22296#L593-12 assume 1 == ~t7_pc~0; 22668#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22869#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22078#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22079#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 22609#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23129#L612-12 assume 1 == ~t8_pc~0; 23142#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 23143#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23154#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23063#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 22358#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22359#L631-12 assume !(1 == ~t9_pc~0); 22104#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 22105#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23166#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23137#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 22034#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22035#L1047-1 assume !(1 == ~M_E~0); 22727#L1052-1 assume !(1 == ~T1_E~0); 21986#L1057-1 assume !(1 == ~T2_E~0); 21987#L1062-1 assume !(1 == ~T3_E~0); 22265#L1067-1 assume !(1 == ~T4_E~0); 22603#L1072-1 assume !(1 == ~T5_E~0); 22604#L1077-1 assume !(1 == ~T6_E~0); 22148#L1082-1 assume !(1 == ~T7_E~0); 22149#L1087-1 assume !(1 == ~T8_E~0); 21962#L1092-1 assume !(1 == ~T9_E~0); 21963#L1097-1 assume !(1 == ~E_M~0); 21988#L1102-1 assume !(1 == ~E_1~0); 22808#L1107-1 assume !(1 == ~E_2~0); 22730#L1112-1 assume !(1 == ~E_3~0); 22731#L1117-1 assume !(1 == ~E_4~0); 22779#L1122-1 assume !(1 == ~E_5~0); 22666#L1127-1 assume !(1 == ~E_6~0); 22401#L1132-1 assume !(1 == ~E_7~0); 22402#L1137-1 assume !(1 == ~E_8~0); 22263#L1142-1 assume !(1 == ~E_9~0); 22264#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 22324#L1428 [2024-11-17 08:52:42,404 INFO L747 eck$LassoCheckResult]: Loop: 22324#L1428 assume true; 22325#L1428-1 assume !false; 22383#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22384#L778 assume true; 22882#L778-1 assume !false; 22883#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 23138#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22239#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22824#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22825#L783 assume !(0 != eval_~tmp~0#1); 22923#L786 assume true; 22648#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22649#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23104#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 23021#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22318#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22319#L954 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23092#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22971#L964 assume !(0 == ~T5_E~0); 22259#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22260#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22951#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22933#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22765#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 22766#L994 assume 0 == ~E_1~0;~E_1~0 := 1; 23170#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 22717#L1004 assume !(0 == ~E_3~0); 22250#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 22251#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 22831#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 22832#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 22896#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 22798#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 22554#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22555#L460-1 assume 1 == ~m_pc~0; 23051#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23052#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22675#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22676#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22707#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22106#L479-1 assume 1 == ~t1_pc~0; 22107#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23044#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22948#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22949#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22292#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22293#L498-1 assume 1 == ~t2_pc~0; 22950#L499-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22542#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23159#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22102#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22103#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22311#L517-1 assume 1 == ~t3_pc~0; 23040#L518-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22685#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22229#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22230#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22434#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22451#L536-1 assume !(1 == ~t4_pc~0); 22385#L546-1 is_transmit4_triggered_~__retres1~4#1 := 0; 22386#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22870#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22871#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23169#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23128#L555-1 assume !(1 == ~t5_pc~0); 21996#L565-1 is_transmit5_triggered_~__retres1~5#1 := 0; 21997#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22693#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22785#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22786#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22990#L574-1 assume !(1 == ~t6_pc~0); 22147#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 22061#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22062#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22745#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22636#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22142#L593-1 assume !(1 == ~t7_pc~0); 22144#L603-1 is_transmit7_triggered_~__retres1~7#1 := 0; 22560#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22792#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22006#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22007#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22689#L612-1 assume 1 == ~t8_pc~0; 22209#L613-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22210#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23087#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22218#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21968#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21969#L631-1 assume 1 == ~t9_pc~0; 22529#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22089#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22090#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22969#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22607#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22608#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 22659#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22045#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21991#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21992#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22479#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23032#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23033#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23017#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23018#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23022#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 23023#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 23155#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 23156#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 23164#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 22752#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 22186#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 22187#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 22531#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 22532#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 22930#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22202#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22088#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22796#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 22535#L1447 assume !(0 == start_simulation_~tmp~3#1); 22138#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22139#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22009#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 23130#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 22372#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22373#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22523#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 22605#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 22324#L1428 [2024-11-17 08:52:42,405 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:42,405 INFO L85 PathProgramCache]: Analyzing trace with hash 1720265523, now seen corresponding path program 1 times [2024-11-17 08:52:42,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:42,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771442300] [2024-11-17 08:52:42,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:42,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:42,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:42,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:42,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:42,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771442300] [2024-11-17 08:52:42,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771442300] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:42,457 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:42,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:42,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1934507057] [2024-11-17 08:52:42,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:42,458 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:42,458 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:42,458 INFO L85 PathProgramCache]: Analyzing trace with hash -1155717429, now seen corresponding path program 1 times [2024-11-17 08:52:42,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:42,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760330150] [2024-11-17 08:52:42,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:42,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:42,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:42,504 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:42,504 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:42,505 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1760330150] [2024-11-17 08:52:42,505 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1760330150] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:42,505 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:42,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:42,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715812956] [2024-11-17 08:52:42,505 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:42,505 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:42,505 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:42,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:42,506 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:42,506 INFO L87 Difference]: Start difference. First operand 1214 states and 1778 transitions. cyclomatic complexity: 565 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:42,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:42,638 INFO L93 Difference]: Finished difference Result 2229 states and 3250 transitions. [2024-11-17 08:52:42,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2229 states and 3250 transitions. [2024-11-17 08:52:42,648 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2082 [2024-11-17 08:52:42,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2229 states to 2229 states and 3250 transitions. [2024-11-17 08:52:42,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2229 [2024-11-17 08:52:42,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2229 [2024-11-17 08:52:42,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2229 states and 3250 transitions. [2024-11-17 08:52:42,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:42,661 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2229 states and 3250 transitions. [2024-11-17 08:52:42,663 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2229 states and 3250 transitions. [2024-11-17 08:52:42,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2229 to 2229. [2024-11-17 08:52:42,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2229 states, 2229 states have (on average 1.4580529385374608) internal successors, (3250), 2228 states have internal predecessors, (3250), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:42,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2229 states to 2229 states and 3250 transitions. [2024-11-17 08:52:42,700 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2229 states and 3250 transitions. [2024-11-17 08:52:42,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:42,701 INFO L425 stractBuchiCegarLoop]: Abstraction has 2229 states and 3250 transitions. [2024-11-17 08:52:42,701 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:52:42,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2229 states and 3250 transitions. [2024-11-17 08:52:42,709 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2082 [2024-11-17 08:52:42,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:42,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:42,710 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:42,711 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:42,711 INFO L745 eck$LassoCheckResult]: Stem: 26361#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 25475#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 25476#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26276#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26277#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 26399#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26400#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25742#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25743#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26480#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25619#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25620#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26325#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26326#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26497#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25984#L939-1 assume !(0 == ~M_E~0); 25985#L944-1 assume !(0 == ~T1_E~0); 26077#L949-1 assume !(0 == ~T2_E~0); 26071#L954-1 assume !(0 == ~T3_E~0); 26072#L959-1 assume !(0 == ~T4_E~0); 26542#L964-1 assume !(0 == ~T5_E~0); 25793#L969-1 assume !(0 == ~T6_E~0); 25794#L974-1 assume !(0 == ~T7_E~0); 26489#L979-1 assume !(0 == ~T8_E~0); 26490#L984-1 assume !(0 == ~T9_E~0); 25961#L989-1 assume !(0 == ~E_M~0); 25962#L994-1 assume 0 == ~E_1~0;~E_1~0 := 1; 25833#L999-1 assume !(0 == ~E_2~0); 25834#L1004-1 assume !(0 == ~E_3~0); 25499#L1009-1 assume !(0 == ~E_4~0); 25500#L1014-1 assume !(0 == ~E_5~0); 25828#L1019-1 assume !(0 == ~E_6~0); 26439#L1024-1 assume !(0 == ~E_7~0); 25744#L1029-1 assume !(0 == ~E_8~0); 25745#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 25859#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25542#L460-12 assume 1 == ~m_pc~0; 25543#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25485#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25486#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26067#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 26389#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26390#L479-12 assume !(1 == ~t1_pc~0); 25427#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 25426#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26037#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25514#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 25515#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26099#L498-12 assume 1 == ~t2_pc~0; 26100#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26475#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25434#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25435#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 26496#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26147#L517-12 assume 1 == ~t3_pc~0; 26047#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26048#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25879#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25880#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 26641#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25654#L536-12 assume 1 == ~t4_pc~0; 25655#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25717#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25718#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26332#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 25835#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25836#L555-12 assume !(1 == ~t5_pc~0); 25683#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 25684#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26576#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26421#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 25972#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25487#L574-12 assume 1 == ~t6_pc~0; 25488#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25846#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26027#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26028#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 25752#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25753#L593-12 assume 1 == ~t7_pc~0; 26132#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26342#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25534#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25535#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 26070#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26647#L612-12 assume 1 == ~t8_pc~0; 26671#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26672#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26685#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26559#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 25819#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25820#L631-12 assume !(1 == ~t9_pc~0); 25562#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 25563#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26700#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26664#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 25490#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25491#L1047-1 assume 1 == ~M_E~0;~M_E~0 := 2; 26473#L1052-1 assume !(1 == ~T1_E~0); 26774#L1057-1 assume !(1 == ~T2_E~0); 26764#L1062-1 assume !(1 == ~T3_E~0); 25721#L1067-1 assume !(1 == ~T4_E~0); 26543#L1072-1 assume !(1 == ~T5_E~0); 26759#L1077-1 assume !(1 == ~T6_E~0); 26757#L1082-1 assume !(1 == ~T7_E~0); 26755#L1087-1 assume !(1 == ~T8_E~0); 26754#L1092-1 assume !(1 == ~T9_E~0); 26752#L1097-1 assume !(1 == ~E_M~0); 26749#L1102-1 assume !(1 == ~E_1~0); 26747#L1107-1 assume !(1 == ~E_2~0); 26196#L1112-1 assume !(1 == ~E_3~0); 26197#L1117-1 assume !(1 == ~E_4~0); 26248#L1122-1 assume !(1 == ~E_5~0); 26709#L1127-1 assume !(1 == ~E_6~0); 26738#L1132-1 assume !(1 == ~E_7~0); 26649#L1137-1 assume !(1 == ~E_8~0); 25719#L1142-1 assume !(1 == ~E_9~0); 25720#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 25784#L1428 [2024-11-17 08:52:42,712 INFO L747 eck$LassoCheckResult]: Loop: 25784#L1428 assume true; 25785#L1428-1 assume !false; 25842#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25843#L778 assume true; 26356#L778-1 assume !false; 26357#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 26667#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 25697#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26295#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26296#L783 assume !(0 != eval_~tmp~0#1); 26401#L786 assume true; 26110#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26111#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26711#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 26511#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25775#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25776#L954 assume !(0 == ~T3_E~0); 26596#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26456#L964 assume !(0 == ~T5_E~0); 25715#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25716#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26430#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26411#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26231#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 26232#L994 assume 0 == ~E_1~0;~E_1~0 := 1; 26708#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 26183#L1004 assume !(0 == ~E_3~0); 25706#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 25707#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 26302#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 26303#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 26370#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 26268#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 26014#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26015#L460-1 assume 1 == ~m_pc~0; 26547#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26548#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26139#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26140#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26173#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25564#L479-1 assume 1 == ~t1_pc~0; 25565#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26538#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26427#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 26428#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25750#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25751#L498-1 assume !(1 == ~t2_pc~0); 26001#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 26002#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26693#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25558#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25559#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25768#L517-1 assume !(1 == ~t3_pc~0); 26148#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 26149#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25685#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25686#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25893#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25910#L536-1 assume !(1 == ~t4_pc~0); 25844#L546-1 is_transmit4_triggered_~__retres1~4#1 := 0; 25845#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26343#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26344#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26707#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26645#L555-1 assume 1 == ~t5_pc~0; 25810#L556-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25453#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26157#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26251#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26252#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26477#L574-1 assume !(1 == ~t6_pc~0); 25603#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 25516#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25517#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26211#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26097#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26098#L593-1 assume !(1 == ~t7_pc~0); 27078#L603-1 is_transmit7_triggered_~__retres1~7#1 := 0; 27076#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27075#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27074#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27073#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27070#L612-1 assume !(1 == ~t8_pc~0); 27067#L622-1 is_transmit8_triggered_~__retres1~8#1 := 0; 26602#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26590#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25672#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25421#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25422#L631-1 assume 1 == ~t9_pc~0; 27052#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27050#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27047#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27045#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27043#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27041#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 26449#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27038#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27035#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25445#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27032#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27030#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27028#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27026#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27023#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26512#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 26513#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 26686#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 26687#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 26698#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 26218#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 25642#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 25643#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 25991#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 25992#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 26408#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 25652#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 25541#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26266#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 25995#L1447 assume !(0 == start_simulation_~tmp~3#1); 25594#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 25595#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 26762#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 26648#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 25831#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25832#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25983#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 26066#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 25784#L1428 [2024-11-17 08:52:42,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:42,712 INFO L85 PathProgramCache]: Analyzing trace with hash 2024435059, now seen corresponding path program 1 times [2024-11-17 08:52:42,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:42,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862657618] [2024-11-17 08:52:42,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:42,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:42,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:42,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:42,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:42,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862657618] [2024-11-17 08:52:42,769 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1862657618] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:42,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:42,769 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:42,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122133552] [2024-11-17 08:52:42,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:42,770 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:42,770 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:42,770 INFO L85 PathProgramCache]: Analyzing trace with hash -149368174, now seen corresponding path program 1 times [2024-11-17 08:52:42,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:42,770 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62646767] [2024-11-17 08:52:42,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:42,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:42,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:42,818 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:42,818 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:42,818 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62646767] [2024-11-17 08:52:42,818 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [62646767] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:42,818 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:42,818 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:42,818 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275990975] [2024-11-17 08:52:42,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:42,819 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:42,819 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:42,819 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:42,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:42,819 INFO L87 Difference]: Start difference. First operand 2229 states and 3250 transitions. cyclomatic complexity: 1023 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:42,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:42,946 INFO L93 Difference]: Finished difference Result 4099 states and 5961 transitions. [2024-11-17 08:52:42,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4099 states and 5961 transitions. [2024-11-17 08:52:42,962 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3910 [2024-11-17 08:52:42,977 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4099 states to 4099 states and 5961 transitions. [2024-11-17 08:52:42,978 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4099 [2024-11-17 08:52:42,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4099 [2024-11-17 08:52:42,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4099 states and 5961 transitions. [2024-11-17 08:52:42,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:42,985 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4099 states and 5961 transitions. [2024-11-17 08:52:42,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4099 states and 5961 transitions. [2024-11-17 08:52:43,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4099 to 4083. [2024-11-17 08:52:43,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4083 states, 4083 states have (on average 1.455057555718834) internal successors, (5941), 4082 states have internal predecessors, (5941), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:43,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4083 states to 4083 states and 5941 transitions. [2024-11-17 08:52:43,042 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4083 states and 5941 transitions. [2024-11-17 08:52:43,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:43,043 INFO L425 stractBuchiCegarLoop]: Abstraction has 4083 states and 5941 transitions. [2024-11-17 08:52:43,043 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:52:43,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4083 states and 5941 transitions. [2024-11-17 08:52:43,055 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3910 [2024-11-17 08:52:43,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:43,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:43,057 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:43,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:43,057 INFO L745 eck$LassoCheckResult]: Stem: 32699#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 31815#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 31816#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32615#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32616#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 32735#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32736#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32083#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32084#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32811#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31961#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31962#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32662#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32663#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32829#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32324#L939-1 assume !(0 == ~M_E~0); 32325#L944-1 assume !(0 == ~T1_E~0); 32417#L949-1 assume !(0 == ~T2_E~0); 32411#L954-1 assume !(0 == ~T3_E~0); 32412#L959-1 assume !(0 == ~T4_E~0); 32876#L964-1 assume !(0 == ~T5_E~0); 32130#L969-1 assume !(0 == ~T6_E~0); 32131#L974-1 assume !(0 == ~T7_E~0); 32820#L979-1 assume !(0 == ~T8_E~0); 32821#L984-1 assume !(0 == ~T9_E~0); 32301#L989-1 assume !(0 == ~E_M~0); 32302#L994-1 assume !(0 == ~E_1~0); 32172#L999-1 assume !(0 == ~E_2~0); 32173#L1004-1 assume !(0 == ~E_3~0); 31839#L1009-1 assume !(0 == ~E_4~0); 31840#L1014-1 assume !(0 == ~E_5~0); 32165#L1019-1 assume !(0 == ~E_6~0); 32775#L1024-1 assume !(0 == ~E_7~0); 32085#L1029-1 assume !(0 == ~E_8~0); 32086#L1034-1 assume 0 == ~E_9~0;~E_9~0 := 1; 32198#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31878#L460-12 assume 1 == ~m_pc~0; 31879#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31825#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31826#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32407#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 32725#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32726#L479-12 assume !(1 == ~t1_pc~0); 31767#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 31766#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32378#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31854#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 31855#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32438#L498-12 assume 1 == ~t2_pc~0; 32439#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32807#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31774#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31775#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 32828#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32484#L517-12 assume 1 == ~t3_pc~0; 32387#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32388#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32218#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32219#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 32965#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31994#L536-12 assume 1 == ~t4_pc~0; 31995#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32059#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32060#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32669#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 32174#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32175#L555-12 assume !(1 == ~t5_pc~0); 32025#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 32026#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32907#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32758#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 32312#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31827#L574-12 assume 1 == ~t6_pc~0; 31828#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32185#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32368#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32369#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 32093#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32094#L593-12 assume 1 == ~t7_pc~0; 32469#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32678#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31874#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31875#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 32410#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32970#L612-12 assume 1 == ~t8_pc~0; 32991#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32992#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33008#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32893#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 32156#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32157#L631-12 assume !(1 == ~t9_pc~0); 31901#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 31902#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33027#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32984#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 31830#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31831#L1047-1 assume 1 == ~M_E~0;~M_E~0 := 2; 32805#L1052-1 assume !(1 == ~T1_E~0); 31781#L1057-1 assume !(1 == ~T2_E~0); 31782#L1062-1 assume !(1 == ~T3_E~0); 32063#L1067-1 assume !(1 == ~T4_E~0); 32404#L1072-1 assume !(1 == ~T5_E~0); 32405#L1077-1 assume !(1 == ~T6_E~0); 31946#L1082-1 assume !(1 == ~T7_E~0); 31947#L1087-1 assume !(1 == ~T8_E~0); 33225#L1092-1 assume !(1 == ~T9_E~0); 33223#L1097-1 assume !(1 == ~E_M~0); 33220#L1102-1 assume !(1 == ~E_1~0); 33217#L1107-1 assume !(1 == ~E_2~0); 33215#L1112-1 assume !(1 == ~E_3~0); 33214#L1117-1 assume !(1 == ~E_4~0); 33213#L1122-1 assume !(1 == ~E_5~0); 33145#L1127-1 assume !(1 == ~E_6~0); 33134#L1132-1 assume !(1 == ~E_7~0); 33113#L1137-1 assume !(1 == ~E_8~0); 33094#L1142-1 assume !(1 == ~E_9~0); 33084#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 33075#L1428 [2024-11-17 08:52:43,058 INFO L747 eck$LassoCheckResult]: Loop: 33075#L1428 assume true; 33068#L1428-1 assume !false; 33062#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33058#L778 assume true; 33057#L778-1 assume !false; 33056#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33048#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 33045#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33044#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 33042#L783 assume !(0 != eval_~tmp~0#1); 33041#L786 assume true; 33040#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33039#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33038#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 32845#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32116#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32117#L954 assume !(0 == ~T3_E~0); 32925#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32788#L964 assume !(0 == ~T5_E~0); 32789#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32766#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32767#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35830#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35829#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 33033#L994 assume !(0 == ~E_1~0); 33034#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 32522#L1004 assume !(0 == ~E_3~0); 32523#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 32834#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 32835#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 35828#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 35827#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 32605#L1034 assume 0 == ~E_9~0;~E_9~0 := 1; 32606#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33022#L460-1 assume 1 == ~m_pc~0; 33024#L461-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32945#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32946#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32509#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32510#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31903#L479-1 assume 1 == ~t1_pc~0; 31904#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32872#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32763#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32764#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32090#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32091#L498-1 assume !(1 == ~t2_pc~0); 32341#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 32342#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33014#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31899#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31900#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32109#L517-1 assume 1 == ~t3_pc~0; 32866#L518-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32486#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32027#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32028#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32233#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32250#L536-1 assume 1 == ~t4_pc~0; 32916#L537-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32184#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32679#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32680#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33032#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32969#L555-1 assume !(1 == ~t5_pc~0); 31792#L565-1 is_transmit5_triggered_~__retres1~5#1 := 0; 31793#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32495#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32592#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32593#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32809#L574-1 assume 1 == ~t6_pc~0; 32352#L575-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31857#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31858#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33011#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33670#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33668#L593-1 assume 1 == ~t7_pc~0; 33664#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33495#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33492#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33490#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33488#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33486#L612-1 assume !(1 == ~t8_pc~0); 33482#L622-1 is_transmit8_triggered_~__retres1~8#1 := 0; 33479#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33477#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33475#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33473#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33471#L631-1 assume 1 == ~t9_pc~0; 33468#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33466#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33464#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33463#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 33462#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33461#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 32782#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33458#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33455#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33451#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33449#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33447#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33445#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33443#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33440#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33438#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 33436#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 33432#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 33304#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 33301#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 33299#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 33297#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 33295#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 33293#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 33291#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 33290#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33203#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 33202#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33201#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 33199#L1447 assume !(0 == start_simulation_~tmp~3#1); 32905#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 33139#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 33133#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 33112#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 33108#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 33104#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 33093#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 33083#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 33075#L1428 [2024-11-17 08:52:43,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:43,058 INFO L85 PathProgramCache]: Analyzing trace with hash 1054144052, now seen corresponding path program 1 times [2024-11-17 08:52:43,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:43,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797798087] [2024-11-17 08:52:43,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:43,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:43,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:43,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:43,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:43,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [797798087] [2024-11-17 08:52:43,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [797798087] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:43,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:43,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:43,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1446602222] [2024-11-17 08:52:43,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:43,102 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:43,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:43,102 INFO L85 PathProgramCache]: Analyzing trace with hash -890182966, now seen corresponding path program 1 times [2024-11-17 08:52:43,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:43,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999897429] [2024-11-17 08:52:43,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:43,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:43,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:43,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:43,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:43,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999897429] [2024-11-17 08:52:43,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999897429] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:43,185 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:43,185 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:43,185 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1847074353] [2024-11-17 08:52:43,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:43,185 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:43,186 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:43,186 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:43,186 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:43,186 INFO L87 Difference]: Start difference. First operand 4083 states and 5941 transitions. cyclomatic complexity: 1862 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:43,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:43,318 INFO L93 Difference]: Finished difference Result 7629 states and 11062 transitions. [2024-11-17 08:52:43,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7629 states and 11062 transitions. [2024-11-17 08:52:43,351 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7440 [2024-11-17 08:52:43,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7629 states to 7629 states and 11062 transitions. [2024-11-17 08:52:43,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7629 [2024-11-17 08:52:43,401 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7629 [2024-11-17 08:52:43,401 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7629 states and 11062 transitions. [2024-11-17 08:52:43,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:43,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7629 states and 11062 transitions. [2024-11-17 08:52:43,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7629 states and 11062 transitions. [2024-11-17 08:52:43,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7629 to 7625. [2024-11-17 08:52:43,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7625 states, 7625 states have (on average 1.4502295081967214) internal successors, (11058), 7624 states have internal predecessors, (11058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:43,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7625 states to 7625 states and 11058 transitions. [2024-11-17 08:52:43,523 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7625 states and 11058 transitions. [2024-11-17 08:52:43,523 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:43,524 INFO L425 stractBuchiCegarLoop]: Abstraction has 7625 states and 11058 transitions. [2024-11-17 08:52:43,524 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:52:43,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7625 states and 11058 transitions. [2024-11-17 08:52:43,548 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7440 [2024-11-17 08:52:43,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:43,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:43,549 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:43,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:43,550 INFO L745 eck$LassoCheckResult]: Stem: 44420#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 43539#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 43540#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44338#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44339#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 44454#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44455#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43808#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43809#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44529#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43683#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43684#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44385#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44386#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44547#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44049#L939-1 assume !(0 == ~M_E~0); 44050#L944-1 assume !(0 == ~T1_E~0); 44141#L949-1 assume !(0 == ~T2_E~0); 44135#L954-1 assume !(0 == ~T3_E~0); 44136#L959-1 assume !(0 == ~T4_E~0); 44587#L964-1 assume !(0 == ~T5_E~0); 43855#L969-1 assume !(0 == ~T6_E~0); 43856#L974-1 assume !(0 == ~T7_E~0); 44538#L979-1 assume !(0 == ~T8_E~0); 44539#L984-1 assume !(0 == ~T9_E~0); 44026#L989-1 assume !(0 == ~E_M~0); 44027#L994-1 assume !(0 == ~E_1~0); 43897#L999-1 assume !(0 == ~E_2~0); 43898#L1004-1 assume !(0 == ~E_3~0); 43563#L1009-1 assume !(0 == ~E_4~0); 43564#L1014-1 assume !(0 == ~E_5~0); 43890#L1019-1 assume !(0 == ~E_6~0); 44493#L1024-1 assume !(0 == ~E_7~0); 43810#L1029-1 assume !(0 == ~E_8~0); 43811#L1034-1 assume !(0 == ~E_9~0); 43923#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43602#L460-12 assume 1 == ~m_pc~0; 43603#L461-12 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43549#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43550#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44131#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 44445#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44446#L479-12 assume !(1 == ~t1_pc~0); 43491#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 43490#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44102#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 43578#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 43579#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44165#L498-12 assume 1 == ~t2_pc~0; 44166#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44525#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43498#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 43499#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 44546#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44212#L517-12 assume 1 == ~t3_pc~0; 44111#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44112#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43944#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43945#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 44665#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43716#L536-12 assume 1 == ~t4_pc~0; 43717#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43783#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43784#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44392#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 43899#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43900#L555-12 assume !(1 == ~t5_pc~0); 43749#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 43750#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44616#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44477#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 44037#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43551#L574-12 assume 1 == ~t6_pc~0; 43552#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43910#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44092#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44093#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 43818#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43819#L593-12 assume 1 == ~t7_pc~0; 44197#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 44401#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43598#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43599#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 44134#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44670#L612-12 assume 1 == ~t8_pc~0; 44688#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44689#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44700#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44602#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 43881#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43882#L631-12 assume !(1 == ~t9_pc~0); 43624#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 43625#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44714#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44682#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 43554#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43555#L1047-1 assume 1 == ~M_E~0;~M_E~0 := 2; 44523#L1052-1 assume !(1 == ~T1_E~0); 43505#L1057-1 assume !(1 == ~T2_E~0); 43506#L1062-1 assume !(1 == ~T3_E~0); 43788#L1067-1 assume !(1 == ~T4_E~0); 44128#L1072-1 assume !(1 == ~T5_E~0); 44129#L1077-1 assume !(1 == ~T6_E~0); 43668#L1082-1 assume !(1 == ~T7_E~0); 43669#L1087-1 assume !(1 == ~T8_E~0); 45074#L1092-1 assume !(1 == ~T9_E~0); 44953#L1097-1 assume !(1 == ~E_M~0); 44951#L1102-1 assume !(1 == ~E_1~0); 44949#L1107-1 assume !(1 == ~E_2~0); 44886#L1112-1 assume !(1 == ~E_3~0); 44884#L1117-1 assume !(1 == ~E_4~0); 44882#L1122-1 assume !(1 == ~E_5~0); 44881#L1127-1 assume !(1 == ~E_6~0); 44812#L1132-1 assume !(1 == ~E_7~0); 44810#L1137-1 assume !(1 == ~E_8~0); 44782#L1142-1 assume !(1 == ~E_9~0); 44771#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 44762#L1428 [2024-11-17 08:52:43,550 INFO L747 eck$LassoCheckResult]: Loop: 44762#L1428 assume true; 44755#L1428-1 assume !false; 44749#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44745#L778 assume true; 44744#L778-1 assume !false; 44743#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 44735#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 44732#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 44731#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 44729#L783 assume !(0 != eval_~tmp~0#1); 44728#L786 assume true; 44727#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44726#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44724#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 44725#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45990#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45988#L954 assume !(0 == ~T3_E~0); 45986#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45984#L964 assume !(0 == ~T5_E~0); 45982#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45980#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45978#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45976#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45974#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 45972#L994 assume !(0 == ~E_1~0); 45970#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 45968#L1004 assume !(0 == ~E_3~0); 45966#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 45950#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 45944#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 45938#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 45930#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 45923#L1034 assume !(0 == ~E_9~0); 45917#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45909#L460-1 assume !(1 == ~m_pc~0); 45902#L470-1 is_master_triggered_~__retres1~0#1 := 0; 45899#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45640#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 45638#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45636#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45634#L479-1 assume 1 == ~t1_pc~0; 45630#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45628#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45625#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 45623#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45621#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45619#L498-1 assume !(1 == ~t2_pc~0); 45616#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 45614#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45611#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 45609#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45607#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45605#L517-1 assume !(1 == ~t3_pc~0); 45602#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 45600#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45597#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45595#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45593#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45591#L536-1 assume !(1 == ~t4_pc~0); 45588#L546-1 is_transmit4_triggered_~__retres1~4#1 := 0; 45586#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45585#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45584#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45583#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45582#L555-1 assume 1 == ~t5_pc~0; 45417#L556-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45415#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45413#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45411#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45409#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45406#L574-1 assume !(1 == ~t6_pc~0); 45403#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 45401#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45399#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45397#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45395#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45394#L593-1 assume !(1 == ~t7_pc~0); 45392#L603-1 is_transmit7_triggered_~__retres1~7#1 := 0; 45389#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45387#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45385#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45219#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45217#L612-1 assume !(1 == ~t8_pc~0); 45214#L622-1 is_transmit8_triggered_~__retres1~8#1 := 0; 45211#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45209#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45207#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45205#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45203#L631-1 assume 1 == ~t9_pc~0; 45200#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45197#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45195#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45193#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 45191#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45189#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 44501#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45186#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45184#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45178#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45176#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45174#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45172#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45170#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45168#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45051#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 45049#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 45046#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 45045#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 45042#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 45040#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 45038#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 45036#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 45034#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 45032#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 45030#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 44936#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 44934#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 44932#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 44931#L1447 assume !(0 == start_simulation_~tmp~3#1); 44614#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 44873#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 44867#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 44865#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 44863#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 44808#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44780#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 44770#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 44762#L1428 [2024-11-17 08:52:43,550 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:43,551 INFO L85 PathProgramCache]: Analyzing trace with hash -430911499, now seen corresponding path program 1 times [2024-11-17 08:52:43,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:43,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1908305014] [2024-11-17 08:52:43,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:43,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:43,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:43,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:43,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:43,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1908305014] [2024-11-17 08:52:43,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1908305014] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:43,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:43,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:43,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108901118] [2024-11-17 08:52:43,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:43,596 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:43,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:43,596 INFO L85 PathProgramCache]: Analyzing trace with hash 1243856855, now seen corresponding path program 1 times [2024-11-17 08:52:43,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:43,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021199950] [2024-11-17 08:52:43,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:43,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:43,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:43,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:43,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:43,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021199950] [2024-11-17 08:52:43,680 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021199950] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:43,681 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:43,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:43,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2097690445] [2024-11-17 08:52:43,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:43,681 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:43,681 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:43,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:43,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:43,682 INFO L87 Difference]: Start difference. First operand 7625 states and 11058 transitions. cyclomatic complexity: 3441 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:43,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:43,782 INFO L93 Difference]: Finished difference Result 11455 states and 16467 transitions. [2024-11-17 08:52:43,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11455 states and 16467 transitions. [2024-11-17 08:52:43,824 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 11263 [2024-11-17 08:52:43,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11455 states to 11455 states and 16467 transitions. [2024-11-17 08:52:43,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11455 [2024-11-17 08:52:43,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11455 [2024-11-17 08:52:43,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11455 states and 16467 transitions. [2024-11-17 08:52:43,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:43,875 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11455 states and 16467 transitions. [2024-11-17 08:52:43,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11455 states and 16467 transitions. [2024-11-17 08:52:44,005 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11455 to 11179. [2024-11-17 08:52:44,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11179 states, 11179 states have (on average 1.4383218534752662) internal successors, (16079), 11178 states have internal predecessors, (16079), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:44,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11179 states to 11179 states and 16079 transitions. [2024-11-17 08:52:44,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11179 states and 16079 transitions. [2024-11-17 08:52:44,045 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:44,046 INFO L425 stractBuchiCegarLoop]: Abstraction has 11179 states and 16079 transitions. [2024-11-17 08:52:44,046 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:52:44,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11179 states and 16079 transitions. [2024-11-17 08:52:44,077 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10987 [2024-11-17 08:52:44,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:44,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:44,079 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:44,079 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:44,079 INFO L745 eck$LassoCheckResult]: Stem: 63531#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 62627#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 62628#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63440#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63441#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 63567#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63568#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62896#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62897#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63653#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62769#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62770#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63495#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 63496#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 63672#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63138#L939-1 assume !(0 == ~M_E~0); 63139#L944-1 assume !(0 == ~T1_E~0); 63230#L949-1 assume !(0 == ~T2_E~0); 63224#L954-1 assume !(0 == ~T3_E~0); 63225#L959-1 assume !(0 == ~T4_E~0); 63718#L964-1 assume !(0 == ~T5_E~0); 62944#L969-1 assume !(0 == ~T6_E~0); 62945#L974-1 assume !(0 == ~T7_E~0); 63662#L979-1 assume !(0 == ~T8_E~0); 63663#L984-1 assume !(0 == ~T9_E~0); 63115#L989-1 assume !(0 == ~E_M~0); 63116#L994-1 assume !(0 == ~E_1~0); 62987#L999-1 assume !(0 == ~E_2~0); 62988#L1004-1 assume !(0 == ~E_3~0); 62650#L1009-1 assume !(0 == ~E_4~0); 62651#L1014-1 assume !(0 == ~E_5~0); 62980#L1019-1 assume !(0 == ~E_6~0); 63612#L1024-1 assume !(0 == ~E_7~0); 62898#L1029-1 assume !(0 == ~E_8~0); 62899#L1034-1 assume !(0 == ~E_9~0); 63013#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62689#L460-12 assume !(1 == ~m_pc~0); 62690#L470-12 is_master_triggered_~__retres1~0#1 := 0; 62637#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 62638#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63220#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 63558#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63559#L479-12 assume !(1 == ~t1_pc~0); 62580#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 62579#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 63190#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62665#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 62666#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63253#L498-12 assume 1 == ~t2_pc~0; 63254#L499-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 63648#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62587#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 62588#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 63671#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63304#L517-12 assume 1 == ~t3_pc~0; 63199#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 63200#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63033#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 63034#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 63824#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 62802#L536-12 assume 1 == ~t4_pc~0; 62803#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 62869#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62870#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63502#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 62989#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 62990#L555-12 assume !(1 == ~t5_pc~0); 62834#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 62835#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63753#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 63593#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 63126#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 62639#L574-12 assume 1 == ~t6_pc~0; 62640#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63000#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 63179#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63180#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 62907#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 62908#L593-12 assume 1 == ~t7_pc~0; 63287#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63512#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 62685#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 62686#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 63223#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 63833#L612-12 assume 1 == ~t8_pc~0; 63866#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 63867#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63880#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63735#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 62970#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 62971#L631-12 assume !(1 == ~t9_pc~0); 62710#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 62711#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 63903#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63858#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 62642#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62643#L1047-1 assume 1 == ~M_E~0;~M_E~0 := 2; 63352#L1052-1 assume !(1 == ~T1_E~0); 63353#L1057-1 assume !(1 == ~T2_E~0); 62874#L1062-1 assume !(1 == ~T3_E~0); 62875#L1067-1 assume !(1 == ~T4_E~0); 71352#L1072-1 assume !(1 == ~T5_E~0); 71351#L1077-1 assume !(1 == ~T6_E~0); 71350#L1082-1 assume !(1 == ~T7_E~0); 71349#L1087-1 assume !(1 == ~T8_E~0); 62570#L1092-1 assume !(1 == ~T9_E~0); 62571#L1097-1 assume !(1 == ~E_M~0); 62596#L1102-1 assume !(1 == ~E_1~0); 63834#L1107-1 assume !(1 == ~E_2~0); 63357#L1112-1 assume !(1 == ~E_3~0); 63358#L1117-1 assume !(1 == ~E_4~0); 63409#L1122-1 assume !(1 == ~E_5~0); 63285#L1127-1 assume !(1 == ~E_6~0); 63014#L1132-1 assume !(1 == ~E_7~0); 63015#L1137-1 assume !(1 == ~E_8~0); 63836#L1142-1 assume !(1 == ~E_9~0); 69297#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 69294#L1428 [2024-11-17 08:52:44,082 INFO L747 eck$LassoCheckResult]: Loop: 69294#L1428 assume true; 69291#L1428-1 assume !false; 69292#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 69759#L778 assume true; 69758#L778-1 assume !false; 69757#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 67739#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 67737#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 67727#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 67728#L783 assume !(0 != eval_~tmp~0#1); 69747#L786 assume true; 69745#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 69743#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 69740#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 69741#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 70879#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70878#L954 assume !(0 == ~T3_E~0); 70877#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 70876#L964 assume !(0 == ~T5_E~0); 70875#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 70874#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 70873#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 70872#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 70871#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 70870#L994 assume !(0 == ~E_1~0); 70869#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 70868#L1004 assume !(0 == ~E_3~0); 70867#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 70866#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 70865#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 70864#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 70863#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 70862#L1034 assume !(0 == ~E_9~0); 70861#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70860#L460-1 assume !(1 == ~m_pc~0); 70859#L470-1 is_master_triggered_~__retres1~0#1 := 0; 70858#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70857#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 70856#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 70855#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70854#L479-1 assume !(1 == ~t1_pc~0); 70853#L489-1 is_transmit1_triggered_~__retres1~1#1 := 0; 70851#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70850#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70849#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70848#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70847#L498-1 assume !(1 == ~t2_pc~0); 70845#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 70844#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70843#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 70842#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 70841#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70840#L517-1 assume 1 == ~t3_pc~0; 70839#L518-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 70837#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70836#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 70835#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 70834#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70833#L536-1 assume 1 == ~t4_pc~0; 70832#L537-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 70830#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70829#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70828#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70827#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70826#L555-1 assume !(1 == ~t5_pc~0); 70825#L565-1 is_transmit5_triggered_~__retres1~5#1 := 0; 70823#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70822#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 70821#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 70820#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70819#L574-1 assume !(1 == ~t6_pc~0); 70817#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 70816#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70815#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70814#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 70813#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 70812#L593-1 assume 1 == ~t7_pc~0; 70811#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 70809#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 70808#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 70807#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 70806#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 70805#L612-1 assume !(1 == ~t8_pc~0); 70803#L622-1 is_transmit8_triggered_~__retres1~8#1 := 0; 70802#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 70801#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 70800#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 70799#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 70798#L631-1 assume !(1 == ~t9_pc~0); 70797#L641-1 is_transmit9_triggered_~__retres1~9#1 := 0; 70795#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 70794#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 70793#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70792#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70791#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 63620#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70790#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 70789#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 70786#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 70785#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70784#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70783#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70782#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70781#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70780#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 70779#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 69496#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 70778#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 70777#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 70776#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 70775#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 70774#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 70773#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 70772#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 70769#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 70624#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 70623#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 70622#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 70621#L1447 assume !(0 == start_simulation_~tmp~3#1); 63751#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 69356#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 69350#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 69348#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 69346#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69344#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69342#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 69296#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 69294#L1428 [2024-11-17 08:52:44,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:44,083 INFO L85 PathProgramCache]: Analyzing trace with hash 182671928, now seen corresponding path program 1 times [2024-11-17 08:52:44,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:44,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013509795] [2024-11-17 08:52:44,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:44,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:44,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:44,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:44,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:44,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013509795] [2024-11-17 08:52:44,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013509795] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:44,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:44,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:44,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1975187233] [2024-11-17 08:52:44,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:44,151 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:44,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:44,152 INFO L85 PathProgramCache]: Analyzing trace with hash -413331945, now seen corresponding path program 1 times [2024-11-17 08:52:44,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:44,153 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845916158] [2024-11-17 08:52:44,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:44,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:44,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:44,203 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:44,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:44,203 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1845916158] [2024-11-17 08:52:44,203 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1845916158] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:44,203 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:44,203 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:44,204 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099589545] [2024-11-17 08:52:44,204 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:44,204 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:44,204 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:44,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:44,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:44,205 INFO L87 Difference]: Start difference. First operand 11179 states and 16079 transitions. cyclomatic complexity: 4912 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:44,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:44,328 INFO L93 Difference]: Finished difference Result 21185 states and 30295 transitions. [2024-11-17 08:52:44,328 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21185 states and 30295 transitions. [2024-11-17 08:52:44,405 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 20962 [2024-11-17 08:52:44,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21185 states to 21185 states and 30295 transitions. [2024-11-17 08:52:44,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21185 [2024-11-17 08:52:44,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21185 [2024-11-17 08:52:44,482 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21185 states and 30295 transitions. [2024-11-17 08:52:44,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:44,502 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21185 states and 30295 transitions. [2024-11-17 08:52:44,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21185 states and 30295 transitions. [2024-11-17 08:52:44,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21185 to 21137. [2024-11-17 08:52:44,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21137 states, 21137 states have (on average 1.4309977764110329) internal successors, (30247), 21136 states have internal predecessors, (30247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:45,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21137 states to 21137 states and 30247 transitions. [2024-11-17 08:52:45,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21137 states and 30247 transitions. [2024-11-17 08:52:45,013 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:45,013 INFO L425 stractBuchiCegarLoop]: Abstraction has 21137 states and 30247 transitions. [2024-11-17 08:52:45,014 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:52:45,014 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21137 states and 30247 transitions. [2024-11-17 08:52:45,076 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 20914 [2024-11-17 08:52:45,076 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:45,076 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:45,077 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:45,077 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:45,078 INFO L745 eck$LassoCheckResult]: Stem: 95938#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 95001#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 95002#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95835#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95836#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 95983#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95984#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95267#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95268#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96089#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 95144#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 95145#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95892#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95893#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 96109#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95523#L939-1 assume !(0 == ~M_E~0); 95524#L944-1 assume !(0 == ~T1_E~0); 95621#L949-1 assume !(0 == ~T2_E~0); 95614#L954-1 assume !(0 == ~T3_E~0); 95615#L959-1 assume !(0 == ~T4_E~0); 96178#L964-1 assume !(0 == ~T5_E~0); 95317#L969-1 assume !(0 == ~T6_E~0); 95318#L974-1 assume !(0 == ~T7_E~0); 96098#L979-1 assume !(0 == ~T8_E~0); 96099#L984-1 assume !(0 == ~T9_E~0); 95499#L989-1 assume !(0 == ~E_M~0); 95500#L994-1 assume !(0 == ~E_1~0); 95361#L999-1 assume !(0 == ~E_2~0); 95362#L1004-1 assume !(0 == ~E_3~0); 95024#L1009-1 assume !(0 == ~E_4~0); 95025#L1014-1 assume !(0 == ~E_5~0); 95354#L1019-1 assume !(0 == ~E_6~0); 96041#L1024-1 assume !(0 == ~E_7~0); 95269#L1029-1 assume !(0 == ~E_8~0); 95270#L1034-1 assume !(0 == ~E_9~0); 95387#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95063#L460-12 assume !(1 == ~m_pc~0); 95064#L470-12 is_master_triggered_~__retres1~0#1 := 0; 95011#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95012#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95610#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 95969#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95970#L479-12 assume !(1 == ~t1_pc~0); 94953#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 94952#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95579#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 95039#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 95040#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95642#L498-12 assume !(1 == ~t2_pc~0); 95643#L508-12 is_transmit2_triggered_~__retres1~2#1 := 0; 96081#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94960#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 94961#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 96108#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95692#L517-12 assume 1 == ~t3_pc~0; 95588#L518-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 95589#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95407#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 95408#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 96324#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95177#L536-12 assume 1 == ~t4_pc~0; 95178#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95242#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95243#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95903#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 95363#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95364#L555-12 assume !(1 == ~t5_pc~0); 95208#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 95209#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96223#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96011#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 95511#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 95013#L574-12 assume 1 == ~t6_pc~0; 95014#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 95374#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 95567#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95568#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 95278#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 95279#L593-12 assume 1 == ~t7_pc~0; 95677#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 95915#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95059#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95060#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 95613#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96336#L612-12 assume 1 == ~t8_pc~0; 96381#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 96382#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96405#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96196#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 95344#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 95345#L631-12 assume !(1 == ~t9_pc~0); 95084#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 95085#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96458#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96368#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 95016#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95017#L1047-1 assume 1 == ~M_E~0;~M_E~0 := 2; 95742#L1052-1 assume !(1 == ~T1_E~0); 95743#L1057-1 assume !(1 == ~T2_E~0); 95246#L1062-1 assume !(1 == ~T3_E~0); 95247#L1067-1 assume !(1 == ~T4_E~0); 96179#L1072-1 assume !(1 == ~T5_E~0); 96017#L1077-1 assume !(1 == ~T6_E~0); 96018#L1082-1 assume !(1 == ~T7_E~0); 95722#L1087-1 assume !(1 == ~T8_E~0); 95723#L1092-1 assume !(1 == ~T9_E~0); 94969#L1097-1 assume !(1 == ~E_M~0); 94970#L1102-1 assume !(1 == ~E_1~0); 102570#L1107-1 assume !(1 == ~E_2~0); 102569#L1112-1 assume !(1 == ~E_3~0); 102568#L1117-1 assume !(1 == ~E_4~0); 102567#L1122-1 assume !(1 == ~E_5~0); 102566#L1127-1 assume !(1 == ~E_6~0); 102565#L1132-1 assume !(1 == ~E_7~0); 96340#L1137-1 assume !(1 == ~E_8~0); 95244#L1142-1 assume !(1 == ~E_9~0); 95245#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 96115#L1428 [2024-11-17 08:52:45,078 INFO L747 eck$LassoCheckResult]: Loop: 96115#L1428 assume true; 103038#L1428-1 assume !false; 103001#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 102988#L778 assume true; 102977#L778-1 assume !false; 102978#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 102456#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 102454#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 99111#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 99112#L783 assume !(0 != eval_~tmp~0#1); 104611#L786 assume true; 104609#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 104607#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 104604#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 104602#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 104603#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 104598#L954 assume !(0 == ~T3_E~0); 104599#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 104594#L964 assume !(0 == ~T5_E~0); 104595#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 104590#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 104591#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 104586#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 104587#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 104582#L994 assume !(0 == ~E_1~0); 104583#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 104578#L1004 assume !(0 == ~E_3~0); 104579#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 104574#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 104575#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 104570#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 104571#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 104566#L1034 assume !(0 == ~E_9~0); 104567#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104562#L460-1 assume !(1 == ~m_pc~0); 104563#L470-1 is_master_triggered_~__retres1~0#1 := 0; 104558#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104559#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104554#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 104555#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104549#L479-1 assume !(1 == ~t1_pc~0); 104551#L489-1 is_transmit1_triggered_~__retres1~1#1 := 0; 104544#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104545#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 104540#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 104541#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 104536#L498-1 assume !(1 == ~t2_pc~0); 104537#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 104532#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104533#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 104528#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 104529#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104523#L517-1 assume !(1 == ~t3_pc~0); 104525#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 105054#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105053#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 105052#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 105051#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105050#L536-1 assume 1 == ~t4_pc~0; 105049#L537-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 105047#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105046#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 105045#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 105044#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 105043#L555-1 assume 1 == ~t5_pc~0; 105041#L556-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 105040#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105039#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 105038#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 105037#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 105036#L574-1 assume 1 == ~t6_pc~0; 105035#L575-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 105033#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 105032#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 105031#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 105030#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 105029#L593-1 assume !(1 == ~t7_pc~0); 105027#L603-1 is_transmit7_triggered_~__retres1~7#1 := 0; 105026#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 105025#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 105024#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 105023#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 105022#L612-1 assume 1 == ~t8_pc~0; 105021#L613-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 105019#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 105018#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 105017#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 105016#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 105015#L631-1 assume 1 == ~t9_pc~0; 105013#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 105012#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 105011#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 105010#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 105009#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105008#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 101545#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 105007#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 105006#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 105003#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 105002#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 105001#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 105000#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 104999#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 104998#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 104997#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 104996#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 104464#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 104995#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 104994#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 104993#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 104992#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 104991#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 104454#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 104455#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 104742#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 104732#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 104731#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 104730#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 104729#L1447 assume !(0 == start_simulation_~tmp~3#1); 103319#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 103064#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 103058#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 103056#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 103054#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103052#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103047#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 103046#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 96115#L1428 [2024-11-17 08:52:45,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:45,078 INFO L85 PathProgramCache]: Analyzing trace with hash -1017581317, now seen corresponding path program 1 times [2024-11-17 08:52:45,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:45,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1391920898] [2024-11-17 08:52:45,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:45,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:45,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:45,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:45,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:45,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1391920898] [2024-11-17 08:52:45,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1391920898] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:45,185 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:45,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:45,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1872221796] [2024-11-17 08:52:45,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:45,186 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:45,186 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:45,186 INFO L85 PathProgramCache]: Analyzing trace with hash 1023631889, now seen corresponding path program 1 times [2024-11-17 08:52:45,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:45,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154304729] [2024-11-17 08:52:45,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:45,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:45,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:45,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:45,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:45,233 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1154304729] [2024-11-17 08:52:45,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1154304729] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:45,233 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:45,233 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:45,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1801343181] [2024-11-17 08:52:45,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:45,234 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:45,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:45,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:45,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:45,234 INFO L87 Difference]: Start difference. First operand 21137 states and 30247 transitions. cyclomatic complexity: 9134 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:45,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:45,513 INFO L93 Difference]: Finished difference Result 40138 states and 57146 transitions. [2024-11-17 08:52:45,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40138 states and 57146 transitions. [2024-11-17 08:52:45,640 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 39828 [2024-11-17 08:52:45,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40138 states to 40138 states and 57146 transitions. [2024-11-17 08:52:45,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40138 [2024-11-17 08:52:45,864 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40138 [2024-11-17 08:52:45,865 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40138 states and 57146 transitions. [2024-11-17 08:52:45,903 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:45,903 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40138 states and 57146 transitions. [2024-11-17 08:52:45,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40138 states and 57146 transitions. [2024-11-17 08:52:46,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40138 to 40042. [2024-11-17 08:52:46,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40042 states, 40042 states have (on average 1.4247540082912942) internal successors, (57050), 40041 states have internal predecessors, (57050), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:46,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40042 states to 40042 states and 57050 transitions. [2024-11-17 08:52:46,461 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40042 states and 57050 transitions. [2024-11-17 08:52:46,462 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:46,462 INFO L425 stractBuchiCegarLoop]: Abstraction has 40042 states and 57050 transitions. [2024-11-17 08:52:46,462 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:52:46,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40042 states and 57050 transitions. [2024-11-17 08:52:46,564 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 39732 [2024-11-17 08:52:46,565 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:46,565 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:46,566 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:46,566 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:46,566 INFO L745 eck$LassoCheckResult]: Stem: 157162#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 156289#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 156290#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 157081#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 157082#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 157201#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 157202#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 156549#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 156550#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157280#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 156427#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 156428#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 157128#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 157129#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 157300#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 156793#L939-1 assume !(0 == ~M_E~0); 156794#L944-1 assume !(0 == ~T1_E~0); 156885#L949-1 assume !(0 == ~T2_E~0); 156879#L954-1 assume !(0 == ~T3_E~0); 156880#L959-1 assume !(0 == ~T4_E~0); 157348#L964-1 assume !(0 == ~T5_E~0); 156601#L969-1 assume !(0 == ~T6_E~0); 156602#L974-1 assume !(0 == ~T7_E~0); 157291#L979-1 assume !(0 == ~T8_E~0); 157292#L984-1 assume !(0 == ~T9_E~0); 156771#L989-1 assume !(0 == ~E_M~0); 156772#L994-1 assume !(0 == ~E_1~0); 156641#L999-1 assume !(0 == ~E_2~0); 156642#L1004-1 assume !(0 == ~E_3~0); 156309#L1009-1 assume !(0 == ~E_4~0); 156310#L1014-1 assume !(0 == ~E_5~0); 156636#L1019-1 assume !(0 == ~E_6~0); 157244#L1024-1 assume !(0 == ~E_7~0); 156551#L1029-1 assume !(0 == ~E_8~0); 156552#L1034-1 assume !(0 == ~E_9~0); 156667#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 156352#L460-12 assume !(1 == ~m_pc~0); 156353#L470-12 is_master_triggered_~__retres1~0#1 := 0; 156295#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 156296#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 156875#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 157190#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 157191#L479-12 assume !(1 == ~t1_pc~0); 156239#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 156238#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 156849#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 156324#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 156325#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 156910#L498-12 assume !(1 == ~t2_pc~0); 156911#L508-12 is_transmit2_triggered_~__retres1~2#1 := 0; 157275#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 156244#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 156245#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 157299#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 156954#L517-12 assume !(1 == ~t3_pc~0); 156955#L527-12 is_transmit3_triggered_~__retres1~3#1 := 0; 157240#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 156686#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 156687#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 157443#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 156465#L536-12 assume 1 == ~t4_pc~0; 156466#L537-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 156524#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 156525#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 157136#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 156643#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 156644#L555-12 assume !(1 == ~t5_pc~0); 156491#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 156492#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 157379#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 157223#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 156781#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 156297#L574-12 assume 1 == ~t6_pc~0; 156298#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 156659#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 156837#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 156838#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 156559#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 156560#L593-12 assume 1 == ~t7_pc~0; 156940#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 157144#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 156344#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 156345#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 156878#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 157451#L612-12 assume 1 == ~t8_pc~0; 157475#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 157476#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 157489#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 157366#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 156627#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 156628#L631-12 assume !(1 == ~t9_pc~0); 156374#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 156375#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 157516#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 157467#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 156300#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 156301#L1047-1 assume 1 == ~M_E~0;~M_E~0 := 2; 156999#L1052-1 assume !(1 == ~T1_E~0); 156251#L1057-1 assume !(1 == ~T2_E~0); 156252#L1062-1 assume !(1 == ~T3_E~0); 156529#L1067-1 assume !(1 == ~T4_E~0); 156872#L1072-1 assume !(1 == ~T5_E~0); 156873#L1077-1 assume !(1 == ~T6_E~0); 166934#L1082-1 assume !(1 == ~T7_E~0); 161275#L1087-1 assume !(1 == ~T8_E~0); 161276#L1092-1 assume !(1 == ~T9_E~0); 161269#L1097-1 assume !(1 == ~E_M~0); 161270#L1102-1 assume !(1 == ~E_1~0); 166933#L1107-1 assume !(1 == ~E_2~0); 166932#L1112-1 assume !(1 == ~E_3~0); 166931#L1117-1 assume !(1 == ~E_4~0); 166930#L1122-1 assume !(1 == ~E_5~0); 166929#L1127-1 assume !(1 == ~E_6~0); 166928#L1132-1 assume !(1 == ~E_7~0); 166927#L1137-1 assume !(1 == ~E_8~0); 166925#L1142-1 assume !(1 == ~E_9~0); 166926#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 170003#L1428 [2024-11-17 08:52:46,567 INFO L747 eck$LassoCheckResult]: Loop: 170003#L1428 assume true; 170002#L1428-1 assume !false; 170001#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 169997#L778 assume true; 169996#L778-1 assume !false; 166875#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 166876#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 167469#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 167467#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 167464#L783 assume !(0 != eval_~tmp~0#1); 167465#L786 assume true; 175100#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 175098#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 175096#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 175094#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 175092#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 175090#L954 assume !(0 == ~T3_E~0); 175088#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 175086#L964 assume !(0 == ~T5_E~0); 175083#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 175081#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 175079#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 175077#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 175075#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 175073#L994 assume !(0 == ~E_1~0); 175071#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 175069#L1004 assume !(0 == ~E_3~0); 175067#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 175065#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 175063#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 175061#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 175059#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 175057#L1034 assume !(0 == ~E_9~0); 175055#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 175053#L460-1 assume !(1 == ~m_pc~0); 175051#L470-1 is_master_triggered_~__retres1~0#1 := 0; 175049#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 175046#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 175044#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 175042#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 175040#L479-1 assume !(1 == ~t1_pc~0); 175038#L489-1 is_transmit1_triggered_~__retres1~1#1 := 0; 175035#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 175034#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 175033#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 175032#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175031#L498-1 assume !(1 == ~t2_pc~0); 175030#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 175029#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 175028#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 175027#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 175026#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 175024#L517-1 assume !(1 == ~t3_pc~0); 175022#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 175020#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 175018#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 175016#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 175014#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 175012#L536-1 assume !(1 == ~t4_pc~0); 175008#L546-1 is_transmit4_triggered_~__retres1~4#1 := 0; 175006#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 175004#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 175002#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 175000#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174998#L555-1 assume 1 == ~t5_pc~0; 174995#L556-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 174993#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174991#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 174989#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 174987#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 174985#L574-1 assume !(1 == ~t6_pc~0); 174772#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 174770#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 174768#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 174766#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 174667#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 174666#L593-1 assume !(1 == ~t7_pc~0); 174664#L603-1 is_transmit7_triggered_~__retres1~7#1 := 0; 174660#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 174643#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 174642#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 174641#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 174640#L612-1 assume !(1 == ~t8_pc~0); 174638#L622-1 is_transmit8_triggered_~__retres1~8#1 := 0; 174507#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 174502#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 174042#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 174039#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 174037#L631-1 assume 1 == ~t9_pc~0; 174034#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 174032#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 174030#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 174028#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 174026#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 174024#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 170185#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 174019#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 174017#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 174013#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 174010#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 174008#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 174006#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 174004#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 174002#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 174000#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 173999#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 170157#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 173995#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 173993#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 173991#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 173989#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 173987#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 173984#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 173982#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 172300#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 173929#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 173921#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 173912#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 168201#L1447 assume !(0 == start_simulation_~tmp~3#1); 168173#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 168174#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 170016#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 170014#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 170012#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 170010#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 170008#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 170004#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 170003#L1428 [2024-11-17 08:52:46,567 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:46,567 INFO L85 PathProgramCache]: Analyzing trace with hash -1905551874, now seen corresponding path program 1 times [2024-11-17 08:52:46,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:46,567 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184009680] [2024-11-17 08:52:46,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:46,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:46,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:46,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:46,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:46,614 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184009680] [2024-11-17 08:52:46,614 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184009680] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:46,614 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:46,614 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:46,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1729465592] [2024-11-17 08:52:46,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:46,615 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:46,615 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:46,615 INFO L85 PathProgramCache]: Analyzing trace with hash 761809882, now seen corresponding path program 1 times [2024-11-17 08:52:46,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:46,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059339527] [2024-11-17 08:52:46,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:46,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:46,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:46,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:46,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:46,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1059339527] [2024-11-17 08:52:46,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1059339527] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:46,792 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:46,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:46,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [843068808] [2024-11-17 08:52:46,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:46,793 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:46,793 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:46,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:46,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:46,793 INFO L87 Difference]: Start difference. First operand 40042 states and 57050 transitions. cyclomatic complexity: 17056 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:47,105 INFO L93 Difference]: Finished difference Result 75997 states and 107755 transitions. [2024-11-17 08:52:47,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75997 states and 107755 transitions. [2024-11-17 08:52:47,588 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 75512 [2024-11-17 08:52:47,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75997 states to 75997 states and 107755 transitions. [2024-11-17 08:52:47,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75997 [2024-11-17 08:52:47,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75997 [2024-11-17 08:52:47,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75997 states and 107755 transitions. [2024-11-17 08:52:48,050 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:48,050 INFO L218 hiAutomatonCegarLoop]: Abstraction has 75997 states and 107755 transitions. [2024-11-17 08:52:48,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75997 states and 107755 transitions. [2024-11-17 08:52:48,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75997 to 75805. [2024-11-17 08:52:49,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75805 states, 75805 states have (on average 1.4189433414682409) internal successors, (107563), 75804 states have internal predecessors, (107563), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:49,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75805 states to 75805 states and 107563 transitions. [2024-11-17 08:52:49,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75805 states and 107563 transitions. [2024-11-17 08:52:49,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:49,251 INFO L425 stractBuchiCegarLoop]: Abstraction has 75805 states and 107563 transitions. [2024-11-17 08:52:49,251 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:52:49,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75805 states and 107563 transitions. [2024-11-17 08:52:49,458 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 75320 [2024-11-17 08:52:49,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:49,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:49,460 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:49,460 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:49,461 INFO L745 eck$LassoCheckResult]: Stem: 273226#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 272332#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 272333#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 273140#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 273141#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 273261#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 273262#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 272597#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 272598#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 273341#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 272475#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 272476#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 273190#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 273191#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 273360#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 272849#L939-1 assume !(0 == ~M_E~0); 272850#L944-1 assume !(0 == ~T1_E~0); 272938#L949-1 assume !(0 == ~T2_E~0); 272932#L954-1 assume !(0 == ~T3_E~0); 272933#L959-1 assume !(0 == ~T4_E~0); 273405#L964-1 assume !(0 == ~T5_E~0); 272650#L969-1 assume !(0 == ~T6_E~0); 272651#L974-1 assume !(0 == ~T7_E~0); 273350#L979-1 assume !(0 == ~T8_E~0); 273351#L984-1 assume !(0 == ~T9_E~0); 272825#L989-1 assume !(0 == ~E_M~0); 272826#L994-1 assume !(0 == ~E_1~0); 272691#L999-1 assume !(0 == ~E_2~0); 272692#L1004-1 assume !(0 == ~E_3~0); 272355#L1009-1 assume !(0 == ~E_4~0); 272356#L1014-1 assume !(0 == ~E_5~0); 272686#L1019-1 assume !(0 == ~E_6~0); 273305#L1024-1 assume !(0 == ~E_7~0); 272599#L1029-1 assume !(0 == ~E_8~0); 272600#L1034-1 assume !(0 == ~E_9~0); 272721#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272396#L460-12 assume !(1 == ~m_pc~0); 272397#L470-12 is_master_triggered_~__retres1~0#1 := 0; 272342#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 272343#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 272928#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 273252#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 273253#L479-12 assume !(1 == ~t1_pc~0); 272285#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 272284#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 272904#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 272370#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 272371#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 272959#L498-12 assume !(1 == ~t2_pc~0); 272960#L508-12 is_transmit2_triggered_~__retres1~2#1 := 0; 273337#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 272292#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 272293#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 273359#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 273008#L517-12 assume !(1 == ~t3_pc~0); 273009#L527-12 is_transmit3_triggered_~__retres1~3#1 := 0; 273302#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 272741#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 272742#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 273508#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272513#L536-12 assume !(1 == ~t4_pc~0); 272514#L546-12 is_transmit4_triggered_~__retres1~4#1 := 0; 272572#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 272573#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 273197#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 272693#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 272694#L555-12 assume !(1 == ~t5_pc~0); 272538#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 272539#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 273439#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 273287#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 272837#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 272344#L574-12 assume 1 == ~t6_pc~0; 272345#L575-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 272704#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 272892#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 272893#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 272609#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 272610#L593-12 assume 1 == ~t7_pc~0; 272992#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 273207#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 272390#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 272391#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 272931#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 273517#L612-12 assume 1 == ~t8_pc~0; 273545#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 273546#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 273563#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 273424#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 272676#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 272677#L631-12 assume !(1 == ~t9_pc~0); 272421#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 272422#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 273596#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 273538#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 272347#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 272348#L1047-1 assume 1 == ~M_E~0;~M_E~0 := 2; 273335#L1052-1 assume !(1 == ~T1_E~0); 277573#L1057-1 assume !(1 == ~T2_E~0); 277571#L1062-1 assume !(1 == ~T3_E~0); 277572#L1067-1 assume !(1 == ~T4_E~0); 277568#L1072-1 assume !(1 == ~T5_E~0); 277569#L1077-1 assume !(1 == ~T6_E~0); 277564#L1082-1 assume !(1 == ~T7_E~0); 277565#L1087-1 assume !(1 == ~T8_E~0); 277560#L1092-1 assume !(1 == ~T9_E~0); 277561#L1097-1 assume !(1 == ~E_M~0); 273518#L1102-1 assume !(1 == ~E_1~0); 273142#L1107-1 assume !(1 == ~E_2~0); 273057#L1112-1 assume !(1 == ~E_3~0); 273058#L1117-1 assume !(1 == ~E_4~0); 273113#L1122-1 assume !(1 == ~E_5~0); 272990#L1127-1 assume !(1 == ~E_6~0); 272722#L1132-1 assume !(1 == ~E_7~0); 272723#L1137-1 assume !(1 == ~E_8~0); 272574#L1142-1 assume !(1 == ~E_9~0); 272575#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 286276#L1428 [2024-11-17 08:52:49,461 INFO L747 eck$LassoCheckResult]: Loop: 286276#L1428 assume true; 279307#L1428-1 assume !false; 279308#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 285844#L778 assume true; 285843#L778-1 assume !false; 285842#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 279271#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 279269#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 279261#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 279262#L783 assume !(0 != eval_~tmp~0#1); 285831#L786 assume true; 285829#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 285827#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 285824#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 285821#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 285817#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 285814#L954 assume !(0 == ~T3_E~0); 285812#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 285810#L964 assume !(0 == ~T5_E~0); 285808#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 285806#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 285802#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 285799#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 285796#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 285793#L994 assume !(0 == ~E_1~0); 285790#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 285787#L1004 assume !(0 == ~E_3~0); 285783#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 285780#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 285777#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 285774#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 285771#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 285768#L1034 assume !(0 == ~E_9~0); 285764#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 285761#L460-1 assume !(1 == ~m_pc~0); 285758#L470-1 is_master_triggered_~__retres1~0#1 := 0; 285755#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 285752#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 285749#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 285745#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 285742#L479-1 assume 1 == ~t1_pc~0; 285738#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 285735#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 285732#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 285730#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 285728#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 285724#L498-1 assume !(1 == ~t2_pc~0); 285720#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 285716#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 285712#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 285708#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 285703#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 285699#L517-1 assume !(1 == ~t3_pc~0); 285694#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 285689#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 285684#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 285679#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 285674#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 285669#L536-1 assume !(1 == ~t4_pc~0); 285664#L546-1 is_transmit4_triggered_~__retres1~4#1 := 0; 285659#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 285654#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 285648#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 285643#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 285638#L555-1 assume 1 == ~t5_pc~0; 285632#L556-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 285627#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 285622#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 285617#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 285612#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 285607#L574-1 assume !(1 == ~t6_pc~0); 285601#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 285596#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 285591#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 285586#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 285580#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 285575#L593-1 assume !(1 == ~t7_pc~0); 285568#L603-1 is_transmit7_triggered_~__retres1~7#1 := 0; 285562#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 285557#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 285552#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 285546#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 285541#L612-1 assume !(1 == ~t8_pc~0); 285534#L622-1 is_transmit8_triggered_~__retres1~8#1 := 0; 285527#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 285521#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 285513#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 285505#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 285498#L631-1 assume 1 == ~t9_pc~0; 285489#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 285481#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 285473#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 285465#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 285456#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 285449#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 277743#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 285435#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 285188#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 285184#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 285182#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 285180#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 285178#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 285176#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 285173#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 285171#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 285169#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 285166#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 285167#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 287357#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 287355#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 285156#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 285154#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 285151#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 285152#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 286691#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 285046#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 285047#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 285022#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 285023#L1447 assume !(0 == start_simulation_~tmp~3#1); 287330#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 286294#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 286289#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 286288#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 286287#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 286286#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 286285#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 286277#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 286276#L1428 [2024-11-17 08:52:49,462 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:49,462 INFO L85 PathProgramCache]: Analyzing trace with hash -1315767999, now seen corresponding path program 1 times [2024-11-17 08:52:49,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:49,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1177485112] [2024-11-17 08:52:49,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:49,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:49,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:49,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:49,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:49,526 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1177485112] [2024-11-17 08:52:49,526 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1177485112] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:49,526 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:49,526 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:49,526 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392336129] [2024-11-17 08:52:49,526 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:49,527 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:49,527 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:49,527 INFO L85 PathProgramCache]: Analyzing trace with hash 1243856855, now seen corresponding path program 2 times [2024-11-17 08:52:49,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:49,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251439142] [2024-11-17 08:52:49,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:49,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:49,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:49,582 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:49,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:49,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251439142] [2024-11-17 08:52:49,583 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1251439142] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:49,583 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:49,583 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:49,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1743706870] [2024-11-17 08:52:49,583 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:49,583 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:49,583 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:49,584 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:49,584 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:49,584 INFO L87 Difference]: Start difference. First operand 75805 states and 107563 transitions. cyclomatic complexity: 31854 Second operand has 4 states, 4 states have (on average 29.25) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:50,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:50,549 INFO L93 Difference]: Finished difference Result 178504 states and 251716 transitions. [2024-11-17 08:52:50,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178504 states and 251716 transitions. [2024-11-17 08:52:51,464 INFO L131 ngComponentsAnalysis]: Automaton has 144 accepting balls. 177060 [2024-11-17 08:52:51,808 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178504 states to 178504 states and 251716 transitions. [2024-11-17 08:52:51,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178504 [2024-11-17 08:52:51,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178504 [2024-11-17 08:52:51,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178504 states and 251716 transitions. [2024-11-17 08:52:52,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:52,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178504 states and 251716 transitions. [2024-11-17 08:52:52,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178504 states and 251716 transitions. [2024-11-17 08:52:53,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178504 to 143428. [2024-11-17 08:52:53,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 143428 states, 143428 states have (on average 1.4141729648325292) internal successors, (202832), 143427 states have internal predecessors, (202832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:54,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143428 states to 143428 states and 202832 transitions. [2024-11-17 08:52:54,415 INFO L240 hiAutomatonCegarLoop]: Abstraction has 143428 states and 202832 transitions. [2024-11-17 08:52:54,415 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:52:54,416 INFO L425 stractBuchiCegarLoop]: Abstraction has 143428 states and 202832 transitions. [2024-11-17 08:52:54,416 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:52:54,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 143428 states and 202832 transitions. [2024-11-17 08:52:54,745 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 142640 [2024-11-17 08:52:54,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:54,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:54,746 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:54,746 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:54,747 INFO L745 eck$LassoCheckResult]: Stem: 527553#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 526654#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 526655#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 527464#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 527465#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 527593#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 527594#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 526918#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 526919#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 527679#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 526794#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 526795#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 527514#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 527515#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 527697#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 527166#L939-1 assume !(0 == ~M_E~0); 527167#L944-1 assume !(0 == ~T1_E~0); 527257#L949-1 assume !(0 == ~T2_E~0); 527251#L954-1 assume !(0 == ~T3_E~0); 527252#L959-1 assume !(0 == ~T4_E~0); 527748#L964-1 assume !(0 == ~T5_E~0); 526965#L969-1 assume !(0 == ~T6_E~0); 526966#L974-1 assume !(0 == ~T7_E~0); 527688#L979-1 assume !(0 == ~T8_E~0); 527689#L984-1 assume !(0 == ~T9_E~0); 527139#L989-1 assume !(0 == ~E_M~0); 527140#L994-1 assume !(0 == ~E_1~0); 527008#L999-1 assume !(0 == ~E_2~0); 527009#L1004-1 assume !(0 == ~E_3~0); 526676#L1009-1 assume !(0 == ~E_4~0); 526677#L1014-1 assume !(0 == ~E_5~0); 527001#L1019-1 assume !(0 == ~E_6~0); 527638#L1024-1 assume !(0 == ~E_7~0); 526920#L1029-1 assume !(0 == ~E_8~0); 526921#L1034-1 assume !(0 == ~E_9~0); 527036#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 526716#L460-12 assume !(1 == ~m_pc~0); 526717#L470-12 is_master_triggered_~__retres1~0#1 := 0; 526664#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 526665#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 527247#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 527583#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 527584#L479-12 assume !(1 == ~t1_pc~0); 526606#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 526605#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 527221#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 526691#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 526692#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 527280#L498-12 assume !(1 == ~t2_pc~0); 527281#L508-12 is_transmit2_triggered_~__retres1~2#1 := 0; 527674#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 526613#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 526614#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 527696#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 527330#L517-12 assume !(1 == ~t3_pc~0); 527331#L527-12 is_transmit3_triggered_~__retres1~3#1 := 0; 527635#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 527055#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 527056#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 527852#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 526829#L536-12 assume !(1 == ~t4_pc~0); 526830#L546-12 is_transmit4_triggered_~__retres1~4#1 := 0; 526893#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 526894#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 527522#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 527010#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 527011#L555-12 assume !(1 == ~t5_pc~0); 526857#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 526858#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 527779#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 527619#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 527154#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 526666#L574-12 assume !(1 == ~t6_pc~0); 526667#L584-12 is_transmit6_triggered_~__retres1~6#1 := 0; 527021#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 527209#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 527210#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 526928#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 526929#L593-12 assume 1 == ~t7_pc~0; 527315#L594-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 527533#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 526710#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 526711#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 527250#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 527862#L612-12 assume 1 == ~t8_pc~0; 527891#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 527892#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 527919#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 527764#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 526994#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 526995#L631-12 assume !(1 == ~t9_pc~0); 526735#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 526736#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 527948#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 527886#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 526668#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 526669#L1047-1 assume 1 == ~M_E~0;~M_E~0 := 2; 527376#L1052-1 assume !(1 == ~T1_E~0); 526620#L1057-1 assume !(1 == ~T2_E~0); 526621#L1062-1 assume !(1 == ~T3_E~0); 526898#L1067-1 assume !(1 == ~T4_E~0); 527244#L1072-1 assume !(1 == ~T5_E~0); 527245#L1077-1 assume !(1 == ~T6_E~0); 526779#L1082-1 assume !(1 == ~T7_E~0); 526780#L1087-1 assume !(1 == ~T8_E~0); 526596#L1092-1 assume !(1 == ~T9_E~0); 526597#L1097-1 assume !(1 == ~E_M~0); 526622#L1102-1 assume !(1 == ~E_1~0); 645744#L1107-1 assume !(1 == ~E_2~0); 645743#L1112-1 assume !(1 == ~E_3~0); 645742#L1117-1 assume !(1 == ~E_4~0); 645741#L1122-1 assume !(1 == ~E_5~0); 645740#L1127-1 assume !(1 == ~E_6~0); 645739#L1132-1 assume !(1 == ~E_7~0); 645738#L1137-1 assume !(1 == ~E_8~0); 645737#L1142-1 assume !(1 == ~E_9~0); 645734#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 645730#L1428 [2024-11-17 08:52:54,747 INFO L747 eck$LassoCheckResult]: Loop: 645730#L1428 assume true; 645728#L1428-1 assume !false; 645726#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 645721#L778 assume true; 645719#L778-1 assume !false; 645718#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 645710#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 645705#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 645704#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 645702#L783 assume !(0 != eval_~tmp~0#1); 645703#L786 assume true; 646029#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 646027#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 646025#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 646023#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 646021#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 646019#L954 assume !(0 == ~T3_E~0); 646017#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 646015#L964 assume !(0 == ~T5_E~0); 646013#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 646011#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 646009#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 646007#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 646005#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 646003#L994 assume !(0 == ~E_1~0); 646001#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 645999#L1004 assume !(0 == ~E_3~0); 645997#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 645995#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 645993#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 645991#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 645989#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 645987#L1034 assume !(0 == ~E_9~0); 645985#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 645983#L460-1 assume !(1 == ~m_pc~0); 645980#L470-1 is_master_triggered_~__retres1~0#1 := 0; 645978#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 645976#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 645974#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 645972#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 645970#L479-1 assume !(1 == ~t1_pc~0); 645969#L489-1 is_transmit1_triggered_~__retres1~1#1 := 0; 645966#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 645964#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 645962#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 645960#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 645958#L498-1 assume !(1 == ~t2_pc~0); 645955#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 645953#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 645951#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 645949#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 645947#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 645945#L517-1 assume !(1 == ~t3_pc~0); 645942#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 645940#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 645938#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 645936#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 645934#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 645932#L536-1 assume !(1 == ~t4_pc~0); 645929#L546-1 is_transmit4_triggered_~__retres1~4#1 := 0; 645927#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 645925#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 645923#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 645921#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 645919#L555-1 assume !(1 == ~t5_pc~0); 645917#L565-1 is_transmit5_triggered_~__retres1~5#1 := 0; 645914#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 645912#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 645911#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 645909#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 645907#L574-1 assume !(1 == ~t6_pc~0); 578941#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 645904#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 645902#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 645900#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 645899#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 645898#L593-1 assume 1 == ~t7_pc~0; 645897#L594-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 645895#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 645894#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 645893#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 645892#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 645890#L612-1 assume !(1 == ~t8_pc~0); 645887#L622-1 is_transmit8_triggered_~__retres1~8#1 := 0; 645885#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 645883#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 645881#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 645879#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 645877#L631-1 assume 1 == ~t9_pc~0; 645873#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 645871#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 645869#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 645867#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 645865#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 645863#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 645034#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 645858#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 645856#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 645027#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 645853#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 645851#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 645849#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 645847#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 645845#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 645843#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 645841#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 645837#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 645835#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 645833#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 645831#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 645829#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 645827#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 645825#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 645822#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 645818#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 645799#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 645796#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 645794#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 645792#L1447 assume !(0 == start_simulation_~tmp~3#1); 645789#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 645774#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 645767#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 645765#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 645763#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 645761#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 645759#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 645733#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 645730#L1428 [2024-11-17 08:52:54,748 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:54,748 INFO L85 PathProgramCache]: Analyzing trace with hash -967120636, now seen corresponding path program 1 times [2024-11-17 08:52:54,748 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:54,748 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040029099] [2024-11-17 08:52:54,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:54,748 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:54,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:54,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:54,778 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:54,778 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040029099] [2024-11-17 08:52:54,779 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040029099] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:54,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:54,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:54,779 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091812718] [2024-11-17 08:52:54,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:54,779 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:54,779 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:54,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1740431526, now seen corresponding path program 1 times [2024-11-17 08:52:54,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:54,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600355973] [2024-11-17 08:52:54,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:54,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:54,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:54,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:54,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:54,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600355973] [2024-11-17 08:52:54,819 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600355973] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:54,819 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:54,819 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:54,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741803950] [2024-11-17 08:52:54,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:54,820 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:54,820 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:54,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:54,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:54,821 INFO L87 Difference]: Start difference. First operand 143428 states and 202832 transitions. cyclomatic complexity: 59500 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:55,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:55,983 INFO L93 Difference]: Finished difference Result 271635 states and 382717 transitions. [2024-11-17 08:52:55,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271635 states and 382717 transitions. [2024-11-17 08:52:57,235 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 269856 [2024-11-17 08:52:57,819 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271635 states to 271635 states and 382717 transitions. [2024-11-17 08:52:57,819 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 271635 [2024-11-17 08:52:57,975 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 271635 [2024-11-17 08:52:57,975 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271635 states and 382717 transitions. [2024-11-17 08:52:58,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:58,103 INFO L218 hiAutomatonCegarLoop]: Abstraction has 271635 states and 382717 transitions. [2024-11-17 08:52:58,271 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271635 states and 382717 transitions. [2024-11-17 08:53:00,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271635 to 270867. [2024-11-17 08:53:00,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 270867 states, 270867 states have (on average 1.4100979447477913) internal successors, (381949), 270866 states have internal predecessors, (381949), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:02,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270867 states to 270867 states and 381949 transitions. [2024-11-17 08:53:02,175 INFO L240 hiAutomatonCegarLoop]: Abstraction has 270867 states and 381949 transitions. [2024-11-17 08:53:02,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:02,175 INFO L425 stractBuchiCegarLoop]: Abstraction has 270867 states and 381949 transitions. [2024-11-17 08:53:02,175 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:53:02,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270867 states and 381949 transitions. [2024-11-17 08:53:02,770 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 269088 [2024-11-17 08:53:02,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:02,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:02,772 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:02,772 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:02,772 INFO L745 eck$LassoCheckResult]: Stem: 942649#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 941725#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 941726#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 942552#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 942553#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 942689#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 942690#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 941990#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 941991#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 942794#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 941865#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 941866#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 942606#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 942607#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 942813#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 942242#L939-1 assume !(0 == ~M_E~0); 942243#L944-1 assume !(0 == ~T1_E~0); 942339#L949-1 assume !(0 == ~T2_E~0); 942333#L954-1 assume !(0 == ~T3_E~0); 942334#L959-1 assume !(0 == ~T4_E~0); 942872#L964-1 assume !(0 == ~T5_E~0); 942040#L969-1 assume !(0 == ~T6_E~0); 942041#L974-1 assume !(0 == ~T7_E~0); 942804#L979-1 assume !(0 == ~T8_E~0); 942805#L984-1 assume !(0 == ~T9_E~0); 942217#L989-1 assume !(0 == ~E_M~0); 942218#L994-1 assume !(0 == ~E_1~0); 942083#L999-1 assume !(0 == ~E_2~0); 942084#L1004-1 assume !(0 == ~E_3~0); 941747#L1009-1 assume !(0 == ~E_4~0); 941748#L1014-1 assume !(0 == ~E_5~0); 942076#L1019-1 assume !(0 == ~E_6~0); 942740#L1024-1 assume !(0 == ~E_7~0); 941992#L1029-1 assume !(0 == ~E_8~0); 941993#L1034-1 assume !(0 == ~E_9~0); 942110#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 941785#L460-12 assume !(1 == ~m_pc~0); 941786#L470-12 is_master_triggered_~__retres1~0#1 := 0; 941735#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 941736#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 942329#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 942676#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 942677#L479-12 assume !(1 == ~t1_pc~0); 941678#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 941677#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 942300#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 941762#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 941763#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 942361#L498-12 assume !(1 == ~t2_pc~0); 942362#L508-12 is_transmit2_triggered_~__retres1~2#1 := 0; 942784#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 941685#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 941686#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 942812#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 942410#L517-12 assume !(1 == ~t3_pc~0); 942411#L527-12 is_transmit3_triggered_~__retres1~3#1 := 0; 942735#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 942129#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 942130#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 942996#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 941898#L536-12 assume !(1 == ~t4_pc~0); 941899#L546-12 is_transmit4_triggered_~__retres1~4#1 := 0; 941963#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 941964#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 942614#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 942085#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 942086#L555-12 assume !(1 == ~t5_pc~0); 941929#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 941930#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 942912#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 942715#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 942231#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 941737#L574-12 assume !(1 == ~t6_pc~0); 941738#L584-12 is_transmit6_triggered_~__retres1~6#1 := 0; 942096#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 942289#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 942290#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 942000#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 942001#L593-12 assume !(1 == ~t7_pc~0); 942393#L603-12 is_transmit7_triggered_~__retres1~7#1 := 0; 942627#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 941781#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 941782#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 942332#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 943010#L612-12 assume 1 == ~t8_pc~0; 943044#L613-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 943045#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 943070#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 942894#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 942067#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 942068#L631-12 assume !(1 == ~t9_pc~0); 941807#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 941808#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 943108#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 943033#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 941739#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 941740#L1047-1 assume 1 == ~M_E~0;~M_E~0 := 2; 942781#L1052-1 assume !(1 == ~T1_E~0); 1012402#L1057-1 assume !(1 == ~T2_E~0); 1012400#L1062-1 assume !(1 == ~T3_E~0); 1012398#L1067-1 assume !(1 == ~T4_E~0); 1012396#L1072-1 assume !(1 == ~T5_E~0); 1012394#L1077-1 assume !(1 == ~T6_E~0); 1012392#L1082-1 assume !(1 == ~T7_E~0); 1012390#L1087-1 assume !(1 == ~T8_E~0); 1012388#L1092-1 assume !(1 == ~T9_E~0); 1012386#L1097-1 assume !(1 == ~E_M~0); 1012383#L1102-1 assume !(1 == ~E_1~0); 1012381#L1107-1 assume !(1 == ~E_2~0); 1012379#L1112-1 assume !(1 == ~E_3~0); 1012377#L1117-1 assume !(1 == ~E_4~0); 1012375#L1122-1 assume !(1 == ~E_5~0); 1012373#L1127-1 assume !(1 == ~E_6~0); 1012370#L1132-1 assume !(1 == ~E_7~0); 1012368#L1137-1 assume !(1 == ~E_8~0); 1007079#L1142-1 assume !(1 == ~E_9~0); 1007075#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 1007071#L1428 [2024-11-17 08:53:02,773 INFO L747 eck$LassoCheckResult]: Loop: 1007071#L1428 assume true; 1007069#L1428-1 assume !false; 1007067#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1007062#L778 assume true; 1007060#L778-1 assume !false; 1007058#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1007021#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1007017#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1007015#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1007012#L783 assume !(0 != eval_~tmp~0#1); 1007013#L786 assume true; 1065778#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1065777#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1065776#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 1065775#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1065774#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1065773#L954 assume !(0 == ~T3_E~0); 1065772#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1065771#L964 assume !(0 == ~T5_E~0); 1065770#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1065769#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1065768#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1065767#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1065766#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 1065765#L994 assume !(0 == ~E_1~0); 1065764#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 1065763#L1004 assume !(0 == ~E_3~0); 1065762#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 1065761#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 1065760#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 1065759#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 1065758#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 1065757#L1034 assume !(0 == ~E_9~0); 1065756#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1065755#L460-1 assume !(1 == ~m_pc~0); 1065754#L470-1 is_master_triggered_~__retres1~0#1 := 0; 1065753#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1065752#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1065751#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1065750#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1065749#L479-1 assume 1 == ~t1_pc~0; 1065747#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1065746#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1065745#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1065744#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1065743#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1065742#L498-1 assume !(1 == ~t2_pc~0); 1065741#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1065740#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1065739#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1065738#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1065737#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1065736#L517-1 assume !(1 == ~t3_pc~0); 1065735#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1065734#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1065733#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1065732#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1065731#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1065730#L536-1 assume !(1 == ~t4_pc~0); 1065729#L546-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1065728#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1065727#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1065726#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1065725#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1065724#L555-1 assume 1 == ~t5_pc~0; 1065722#L556-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1065721#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1065720#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1065719#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1065718#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1065717#L574-1 assume !(1 == ~t6_pc~0); 1045797#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1065716#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1065715#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1065714#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1065713#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1065712#L593-1 assume !(1 == ~t7_pc~0); 1065711#L603-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1065710#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1065709#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1065708#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1065707#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1065706#L612-1 assume !(1 == ~t8_pc~0); 1065704#L622-1 is_transmit8_triggered_~__retres1~8#1 := 0; 1065703#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1065702#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1065701#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1065700#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1065699#L631-1 assume 1 == ~t9_pc~0; 1065697#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1065696#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1065695#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1065694#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1065693#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1065692#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 1017545#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1065691#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1065690#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1030401#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1065689#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1065688#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1065687#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1065686#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1065685#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1065684#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 1065683#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 1047594#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 1065682#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 1065681#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 1065680#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 1065679#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 1065678#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 1065677#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 1065676#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 1020838#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1065666#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1065665#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1065664#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1065662#L1447 assume !(0 == start_simulation_~tmp~3#1); 1065663#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1067480#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1067474#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1067472#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1067470#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1067468#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1067466#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1007074#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1007071#L1428 [2024-11-17 08:53:02,773 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:02,773 INFO L85 PathProgramCache]: Analyzing trace with hash -860444921, now seen corresponding path program 1 times [2024-11-17 08:53:02,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:02,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421287405] [2024-11-17 08:53:02,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:02,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:02,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:02,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:02,808 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:02,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421287405] [2024-11-17 08:53:02,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421287405] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:02,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:02,809 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:02,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022542000] [2024-11-17 08:53:02,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:02,809 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:02,809 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:02,809 INFO L85 PathProgramCache]: Analyzing trace with hash 1243856855, now seen corresponding path program 3 times [2024-11-17 08:53:02,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:02,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [513824031] [2024-11-17 08:53:02,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:02,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:02,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:02,845 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:02,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:02,845 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [513824031] [2024-11-17 08:53:02,845 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [513824031] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:02,845 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:02,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:02,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887172642] [2024-11-17 08:53:02,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:02,846 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:02,846 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:02,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:02,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:02,846 INFO L87 Difference]: Start difference. First operand 270867 states and 381949 transitions. cyclomatic complexity: 111274 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:05,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:05,493 INFO L93 Difference]: Finished difference Result 524882 states and 736634 transitions. [2024-11-17 08:53:05,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 524882 states and 736634 transitions. [2024-11-17 08:53:08,333 INFO L131 ngComponentsAnalysis]: Automaton has 384 accepting balls. 520736 [2024-11-17 08:53:10,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 524882 states to 524882 states and 736634 transitions. [2024-11-17 08:53:10,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 524882 [2024-11-17 08:53:10,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 524882 [2024-11-17 08:53:10,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 524882 states and 736634 transitions. [2024-11-17 08:53:10,387 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:10,387 INFO L218 hiAutomatonCegarLoop]: Abstraction has 524882 states and 736634 transitions. [2024-11-17 08:53:10,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 524882 states and 736634 transitions. [2024-11-17 08:53:15,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 524882 to 523346. [2024-11-17 08:53:15,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 523346 states, 523346 states have (on average 1.4046118628975859) internal successors, (735098), 523345 states have internal predecessors, (735098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:17,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 523346 states to 523346 states and 735098 transitions. [2024-11-17 08:53:17,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 523346 states and 735098 transitions. [2024-11-17 08:53:17,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:17,764 INFO L425 stractBuchiCegarLoop]: Abstraction has 523346 states and 735098 transitions. [2024-11-17 08:53:17,764 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:53:17,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 523346 states and 735098 transitions. [2024-11-17 08:53:19,517 INFO L131 ngComponentsAnalysis]: Automaton has 384 accepting balls. 519200 [2024-11-17 08:53:19,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:19,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:19,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:19,519 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:19,519 INFO L745 eck$LassoCheckResult]: Stem: 1738390#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~token~0 := 0;~local~0 := 0; 1737483#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1737484#L1391 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret27#1, start_simulation_#t~ret28#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1738299#L651-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1738300#L658 assume 1 == ~m_i~0;~m_st~0 := 0; 1738432#L663 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1738433#L668 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1737745#L673 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1737746#L678 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1738531#L683 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1737623#L688 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1737624#L693 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1738350#L698 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1738351#L703 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1738549#L709 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1737994#L939-1 assume !(0 == ~M_E~0); 1737995#L944-1 assume !(0 == ~T1_E~0); 1738093#L949-1 assume !(0 == ~T2_E~0); 1738087#L954-1 assume !(0 == ~T3_E~0); 1738088#L959-1 assume !(0 == ~T4_E~0); 1738615#L964-1 assume !(0 == ~T5_E~0); 1737796#L969-1 assume !(0 == ~T6_E~0); 1737797#L974-1 assume !(0 == ~T7_E~0); 1738540#L979-1 assume !(0 == ~T8_E~0); 1738541#L984-1 assume !(0 == ~T9_E~0); 1737969#L989-1 assume !(0 == ~E_M~0); 1737970#L994-1 assume !(0 == ~E_1~0); 1737839#L999-1 assume !(0 == ~E_2~0); 1737840#L1004-1 assume !(0 == ~E_3~0); 1737505#L1009-1 assume !(0 == ~E_4~0); 1737506#L1014-1 assume !(0 == ~E_5~0); 1737832#L1019-1 assume !(0 == ~E_6~0); 1738479#L1024-1 assume !(0 == ~E_7~0); 1737747#L1029-1 assume !(0 == ~E_8~0); 1737748#L1034-1 assume !(0 == ~E_9~0); 1737866#L1040-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1737544#L460-12 assume !(1 == ~m_pc~0); 1737545#L470-12 is_master_triggered_~__retres1~0#1 := 0; 1737493#L463-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1737494#L472-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1738083#L1167-12 assume !(0 != activate_threads_~tmp~1#1); 1738419#L1173-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1738420#L479-12 assume !(1 == ~t1_pc~0); 1737436#L489-12 is_transmit1_triggered_~__retres1~1#1 := 0; 1737435#L482-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1738052#L491-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1737521#L1175-12 assume !(0 != activate_threads_~tmp___0~0#1); 1737522#L1181-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1738118#L498-12 assume !(1 == ~t2_pc~0); 1738119#L508-12 is_transmit2_triggered_~__retres1~2#1 := 0; 1738523#L501-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1737443#L510-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1737444#L1183-12 assume !(0 != activate_threads_~tmp___1~0#1); 1738548#L1189-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1738164#L517-12 assume !(1 == ~t3_pc~0); 1738165#L527-12 is_transmit3_triggered_~__retres1~3#1 := 0; 1738475#L520-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1737884#L529-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1737885#L1191-12 assume !(0 != activate_threads_~tmp___2~0#1); 1738746#L1197-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1737656#L536-12 assume !(1 == ~t4_pc~0); 1737657#L546-12 is_transmit4_triggered_~__retres1~4#1 := 0; 1737720#L539-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1737721#L548-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1738360#L1199-12 assume !(0 != activate_threads_~tmp___3~0#1); 1737841#L1205-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1737842#L555-12 assume !(1 == ~t5_pc~0); 1737685#L565-12 is_transmit5_triggered_~__retres1~5#1 := 0; 1737686#L558-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1738657#L567-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1738457#L1207-12 assume !(0 != activate_threads_~tmp___4~0#1); 1737983#L1213-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1737495#L574-12 assume !(1 == ~t6_pc~0); 1737496#L584-12 is_transmit6_triggered_~__retres1~6#1 := 0; 1737852#L577-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1738039#L586-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1738040#L1215-12 assume !(0 != activate_threads_~tmp___5~0#1); 1737755#L1221-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1737756#L593-12 assume !(1 == ~t7_pc~0); 1738149#L603-12 is_transmit7_triggered_~__retres1~7#1 := 0; 1738371#L596-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1737540#L605-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1737541#L1223-12 assume !(0 != activate_threads_~tmp___6~0#1); 1738086#L1229-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1738761#L612-12 assume !(1 == ~t8_pc~0); 1738849#L622-12 is_transmit8_triggered_~__retres1~8#1 := 0; 1738850#L615-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1738825#L624-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1738634#L1231-12 assume !(0 != activate_threads_~tmp___7~0#1); 1737823#L1237-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1737824#L631-12 assume !(1 == ~t9_pc~0); 1737565#L641-12 is_transmit9_triggered_~__retres1~9#1 := 0; 1737566#L634-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1738862#L643-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1738790#L1239-12 assume !(0 != activate_threads_~tmp___8~0#1); 1737497#L1245-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1737498#L1047-1 assume 1 == ~M_E~0;~M_E~0 := 2; 1738521#L1052-1 assume !(1 == ~T1_E~0); 1822902#L1057-1 assume !(1 == ~T2_E~0); 1822900#L1062-1 assume !(1 == ~T3_E~0); 1822898#L1067-1 assume !(1 == ~T4_E~0); 1822896#L1072-1 assume !(1 == ~T5_E~0); 1822894#L1077-1 assume !(1 == ~T6_E~0); 1822891#L1082-1 assume !(1 == ~T7_E~0); 1822889#L1087-1 assume !(1 == ~T8_E~0); 1822887#L1092-1 assume !(1 == ~T9_E~0); 1822885#L1097-1 assume !(1 == ~E_M~0); 1738762#L1102-1 assume !(1 == ~E_1~0); 1738301#L1107-1 assume !(1 == ~E_2~0); 1738213#L1112-1 assume !(1 == ~E_3~0); 1738214#L1117-1 assume !(1 == ~E_4~0); 1738267#L1122-1 assume !(1 == ~E_5~0); 1738147#L1127-1 assume !(1 == ~E_6~0); 1737867#L1132-1 assume !(1 == ~E_7~0); 1737868#L1137-1 assume !(1 == ~E_8~0); 1737722#L1142-1 assume !(1 == ~E_9~0); 1737723#L1148-1 assume true;assume { :end_inline_reset_delta_events } true; 1877213#L1428 [2024-11-17 08:53:19,520 INFO L747 eck$LassoCheckResult]: Loop: 1877213#L1428 assume true; 1877209#L1428-1 assume !false; 1877208#start_simulation_while_11_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1877204#L778 assume true; 1877189#L778-1 assume !false; 1877185#eval_while_10_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1877029#L716-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1877019#L754-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1877012#L769-2 assume true;eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1877003#L783 assume !(0 != eval_~tmp~0#1); 1877004#L786 assume true; 1877487#L932 assume true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1877485#L651 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1877483#L939 assume 0 == ~M_E~0;~M_E~0 := 1; 1877481#L944 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1877479#L949 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1877477#L954 assume !(0 == ~T3_E~0); 1877475#L959 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1877473#L964 assume !(0 == ~T5_E~0); 1877471#L969 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1877469#L974 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1877467#L979 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1877465#L984 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1877463#L989 assume 0 == ~E_M~0;~E_M~0 := 1; 1877460#L994 assume !(0 == ~E_1~0); 1877458#L999 assume 0 == ~E_2~0;~E_2~0 := 1; 1877456#L1004 assume !(0 == ~E_3~0); 1877454#L1009 assume 0 == ~E_4~0;~E_4~0 := 1; 1877452#L1014 assume 0 == ~E_5~0;~E_5~0 := 1; 1877450#L1019 assume 0 == ~E_6~0;~E_6~0 := 1; 1877448#L1024 assume 0 == ~E_7~0;~E_7~0 := 1; 1877446#L1029 assume 0 == ~E_8~0;~E_8~0 := 1; 1877444#L1034 assume !(0 == ~E_9~0); 1877442#L1040 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1877440#L460-1 assume !(1 == ~m_pc~0); 1877438#L470-1 is_master_triggered_~__retres1~0#1 := 0; 1877436#L463-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1877434#L472-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1877432#L1167-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1877430#L1173-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1877428#L479-1 assume 1 == ~t1_pc~0; 1877425#L480-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1877423#L482-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1877421#L491-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1877419#L1175-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1877417#L1181-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1877415#L498-1 assume !(1 == ~t2_pc~0); 1877413#L508-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1877410#L501-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1877408#L510-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1877406#L1183-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1877404#L1189-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1877402#L517-1 assume !(1 == ~t3_pc~0); 1877400#L527-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1877399#L520-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1877397#L529-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1877395#L1191-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1877393#L1197-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1877391#L536-1 assume !(1 == ~t4_pc~0); 1877389#L546-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1877387#L539-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1877385#L548-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1877383#L1199-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1877381#L1205-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1877379#L555-1 assume 1 == ~t5_pc~0; 1877376#L556-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1877374#L558-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1877372#L567-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1877370#L1207-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1877368#L1213-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1877366#L574-1 assume !(1 == ~t6_pc~0); 1832668#L584-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1877362#L577-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1877360#L586-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1877358#L1215-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1877356#L1221-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1877354#L593-1 assume !(1 == ~t7_pc~0); 1877352#L603-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1877350#L596-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1877348#L605-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1877347#L1223-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1877346#L1229-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1877345#L612-1 assume !(1 == ~t8_pc~0); 1877343#L622-1 is_transmit8_triggered_~__retres1~8#1 := 0; 1877341#L615-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1877339#L624-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1877337#L1231-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1877335#L1237-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1877333#L631-1 assume 1 == ~t9_pc~0; 1877330#L632-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1877328#L634-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1877326#L643-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1877324#L1239-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1877322#L1245-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1877320#L1047 assume 1 == ~M_E~0;~M_E~0 := 2; 1822292#L1052 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1877315#L1057 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1877313#L1062 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1877309#L1067 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1877307#L1072 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1877305#L1077 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1877303#L1082 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1877300#L1087 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1877298#L1092 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1877296#L1097 assume 1 == ~E_M~0;~E_M~0 := 2; 1877294#L1102 assume 1 == ~E_1~0;~E_1~0 := 2; 1877290#L1107 assume 1 == ~E_2~0;~E_2~0 := 2; 1877288#L1112 assume 1 == ~E_3~0;~E_3~0 := 2; 1877286#L1117 assume 1 == ~E_4~0;~E_4~0 := 2; 1877284#L1122 assume 1 == ~E_5~0;~E_5~0 := 2; 1877282#L1127 assume 1 == ~E_6~0;~E_6~0 := 2; 1877280#L1132 assume 1 == ~E_7~0;~E_7~0 := 2; 1877278#L1137 assume 1 == ~E_8~0;~E_8~0 := 2; 1877276#L1142 assume 1 == ~E_9~0;~E_9~0 := 2; 1822242#L1148 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1877255#L716-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1877253#L754-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1877251#L769-1 assume true;start_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1877250#L1447 assume !(0 == start_simulation_~tmp~3#1); 1877248#L1458 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1877240#L716 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1877233#L754 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1877231#L769 assume true;stop_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret26#1;havoc stop_simulation_#t~ret26#1; 1877229#L1402 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1877227#L1404 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1877225#L1410 assume true;start_simulation_#t~ret28#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret26#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1877217#L1460 assume !(0 != start_simulation_~tmp___0~1#1); 1877213#L1428 [2024-11-17 08:53:19,520 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:19,520 INFO L85 PathProgramCache]: Analyzing trace with hash 976085834, now seen corresponding path program 1 times [2024-11-17 08:53:19,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:19,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1944890861] [2024-11-17 08:53:19,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:19,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:19,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:19,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:19,555 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:19,555 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1944890861] [2024-11-17 08:53:19,555 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1944890861] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:19,555 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:19,555 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:19,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747353919] [2024-11-17 08:53:19,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:19,556 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:19,556 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:19,556 INFO L85 PathProgramCache]: Analyzing trace with hash 1243856855, now seen corresponding path program 4 times [2024-11-17 08:53:19,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:19,556 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435360473] [2024-11-17 08:53:19,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:19,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:19,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:19,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:19,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:19,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [435360473] [2024-11-17 08:53:19,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [435360473] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:19,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:19,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:19,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [21919374] [2024-11-17 08:53:19,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:19,595 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:19,595 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:19,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:19,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:19,596 INFO L87 Difference]: Start difference. First operand 523346 states and 735098 transitions. cyclomatic complexity: 212136 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 2 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)