./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.10.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.10.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:52:40,683 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:52:40,724 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:52:40,727 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:52:40,728 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:52:40,728 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:52:40,753 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:52:40,753 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:52:40,754 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:52:40,755 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:52:40,756 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:52:40,756 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:52:40,756 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:52:40,757 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:52:40,758 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:52:40,758 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:52:40,758 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:52:40,758 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:52:40,759 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:52:40,759 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:52:40,759 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:52:40,761 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:52:40,761 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:52:40,763 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:52:40,763 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:52:40,763 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:52:40,764 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:52:40,764 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:52:40,764 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:52:40,764 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:52:40,764 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:52:40,764 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:52:40,764 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:52:40,765 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:52:40,765 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:52:40,765 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:52:40,765 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:52:40,765 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:52:40,766 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:52:40,768 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:52:40,769 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 9102a3dc168a1a089cfcbe45042daf88c4c5eebedf113fc0c98e676c1fbaab5b [2024-11-17 08:52:40,954 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:52:40,986 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:52:40,988 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:52:40,989 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:52:40,991 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:52:40,992 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2024-11-17 08:52:42,353 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:52:42,579 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:52:42,580 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.10.cil-1.c [2024-11-17 08:52:42,597 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/27975e6b1/4fbe5ef8ebd24ac0b6ea64daebffb594/FLAG37d5168ba [2024-11-17 08:52:42,930 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/27975e6b1/4fbe5ef8ebd24ac0b6ea64daebffb594 [2024-11-17 08:52:42,932 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:52:42,933 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:52:42,934 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:42,934 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:52:42,938 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:52:42,938 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:42" (1/1) ... [2024-11-17 08:52:42,939 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@f15ca2c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:42, skipping insertion in model container [2024-11-17 08:52:42,939 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:42" (1/1) ... [2024-11-17 08:52:42,976 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:52:43,301 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:43,314 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:52:43,402 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:43,434 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:52:43,434 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43 WrapperNode [2024-11-17 08:52:43,434 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:43,435 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:43,435 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:52:43,436 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:52:43,440 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,457 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,576 INFO L138 Inliner]: procedures = 48, calls = 63, calls flagged for inlining = 58, calls inlined = 212, statements flattened = 3210 [2024-11-17 08:52:43,580 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:43,581 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:52:43,581 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:52:43,581 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:52:43,597 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,597 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,609 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,666 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:52:43,670 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,670 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,715 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,724 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,726 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,737 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,757 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:52:43,758 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:52:43,759 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:52:43,759 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:52:43,760 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (1/1) ... [2024-11-17 08:52:43,771 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:43,788 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:43,810 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:43,817 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:52:43,879 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:52:43,883 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:52:43,883 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:52:43,883 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:52:44,008 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:52:44,010 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:52:45,767 INFO L? ?]: Removed 666 outVars from TransFormulas that were not future-live. [2024-11-17 08:52:45,768 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:52:45,804 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:52:45,807 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:52:45,807 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:45 BoogieIcfgContainer [2024-11-17 08:52:45,808 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:52:45,809 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:52:45,809 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:52:45,812 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:52:45,813 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:45,814 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:52:42" (1/3) ... [2024-11-17 08:52:45,814 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@59518234 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:45, skipping insertion in model container [2024-11-17 08:52:45,814 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:45,815 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:43" (2/3) ... [2024-11-17 08:52:45,815 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@59518234 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:45, skipping insertion in model container [2024-11-17 08:52:45,815 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:45,815 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:45" (3/3) ... [2024-11-17 08:52:45,816 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.10.cil-1.c [2024-11-17 08:52:45,889 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:52:45,889 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:52:45,889 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:52:45,890 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:52:45,890 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:52:45,890 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:52:45,890 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:52:45,890 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:52:45,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1436 states, 1435 states have (on average 1.4850174216027874) internal successors, (2131), 1435 states have internal predecessors, (2131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:45,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1292 [2024-11-17 08:52:45,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:45,962 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:45,979 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:45,980 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:45,980 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:52:45,982 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1436 states, 1435 states have (on average 1.4850174216027874) internal successors, (2131), 1435 states have internal predecessors, (2131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:45,997 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1292 [2024-11-17 08:52:45,997 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:45,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:45,999 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:45,999 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:46,014 INFO L745 eck$LassoCheckResult]: Stem: 691#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 29#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1030#L1528true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 593#L724-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1209#L731true assume !(1 == ~m_i~0);~m_st~0 := 2; 225#L736true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 158#L741true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 476#L746true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 22#L751true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 461#L756true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 487#L761true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1089#L766true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1390#L771true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1126#L776true assume !(1 == ~t9_i~0);~t9_st~0 := 2; 848#L781true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 337#L787true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 624#L1036-1true assume !(0 == ~M_E~0); 615#L1041-1true assume !(0 == ~T1_E~0); 1031#L1046-1true assume !(0 == ~T2_E~0); 202#L1051-1true assume !(0 == ~T3_E~0); 778#L1056-1true assume !(0 == ~T4_E~0); 835#L1061-1true assume !(0 == ~T5_E~0); 153#L1066-1true assume !(0 == ~T6_E~0); 1205#L1071-1true assume !(0 == ~T7_E~0); 762#L1076-1true assume !(0 == ~T8_E~0); 93#L1081-1true assume !(0 == ~T9_E~0); 316#L1086-1true assume !(0 == ~T10_E~0); 1220#L1091-1true assume !(0 == ~E_M~0); 1097#L1096-1true assume !(0 == ~E_1~0); 1321#L1101-1true assume !(0 == ~E_2~0); 358#L1106-1true assume !(0 == ~E_3~0); 550#L1111-1true assume !(0 == ~E_4~0); 465#L1116-1true assume !(0 == ~E_5~0); 1147#L1121-1true assume !(0 == ~E_6~0); 354#L1126-1true assume !(0 == ~E_7~0); 540#L1131-1true assume !(0 == ~E_8~0); 629#L1136-1true assume !(0 == ~E_9~0); 952#L1141-1true assume !(0 == ~E_10~0); 825#L1147-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 641#L514-13true assume 1 == ~m_pc~0; 496#L515-13true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1418#L517-13true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5#L526-13true assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 167#L1285-13true assume !(0 != activate_threads_~tmp~1#1); 1049#L1291-13true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 940#L533-13true assume 1 == ~t1_pc~0; 87#L534-13true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 658#L536-13true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 361#L545-13true assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 223#L1293-13true assume !(0 != activate_threads_~tmp___0~0#1); 1345#L1299-13true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180#L552-13true assume 1 == ~t2_pc~0; 1092#L553-13true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1305#L555-13true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76#L564-13true assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1303#L1301-13true assume !(0 != activate_threads_~tmp___1~0#1); 755#L1307-13true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 526#L571-13true assume 1 == ~t3_pc~0; 839#L572-13true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1375#L574-13true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 419#L583-13true assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 514#L1309-13true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 572#L1315-13true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 728#L590-13true assume 1 == ~t4_pc~0; 590#L591-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1346#L593-13true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 843#L602-13true assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 515#L1317-13true assume !(0 != activate_threads_~tmp___3~0#1); 1020#L1323-13true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 903#L609-13true assume 1 == ~t5_pc~0; 201#L610-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3#L612-13true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1226#L621-13true assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1151#L1325-13true assume !(0 != activate_threads_~tmp___4~0#1); 444#L1331-13true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56#L628-13true assume 1 == ~t6_pc~0; 997#L629-13true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 219#L631-13true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 296#L640-13true assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 705#L1333-13true assume !(0 != activate_threads_~tmp___5~0#1); 200#L1339-13true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 945#L647-13true assume 1 == ~t7_pc~0; 998#L648-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 618#L650-13true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 965#L659-13true assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 551#L1341-13true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 738#L1347-13true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 614#L666-13true assume 1 == ~t8_pc~0; 16#L667-13true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 460#L669-13true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1166#L678-13true assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1306#L1349-13true assume !(0 != activate_threads_~tmp___7~0#1); 51#L1355-13true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1100#L685-13true assume 1 == ~t9_pc~0; 1335#L686-13true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 176#L688-13true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 797#L697-13true assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 578#L1357-13true assume !(0 != activate_threads_~tmp___8~0#1); 530#L1363-13true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 806#L704-13true assume 1 == ~t10_pc~0; 707#L705-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 643#L707-13true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26#L716-13true assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1224#L1365-13true assume !(0 != activate_threads_~tmp___9~0#1); 129#L1371-13true assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132#L1154-1true assume !(1 == ~M_E~0); 191#L1159-1true assume !(1 == ~T1_E~0); 1360#L1164-1true assume !(1 == ~T2_E~0); 480#L1169-1true assume !(1 == ~T3_E~0); 393#L1174-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 264#L1179-1true assume !(1 == ~T5_E~0); 182#L1184-1true assume !(1 == ~T6_E~0); 229#L1189-1true assume !(1 == ~T7_E~0); 304#L1194-1true assume !(1 == ~T8_E~0); 1407#L1199-1true assume !(1 == ~T9_E~0); 275#L1204-1true assume !(1 == ~T10_E~0); 1274#L1209-1true assume !(1 == ~E_M~0); 686#L1214-1true assume 1 == ~E_1~0;~E_1~0 := 2; 1358#L1219-1true assume !(1 == ~E_2~0); 1242#L1224-1true assume !(1 == ~E_3~0); 503#L1229-1true assume !(1 == ~E_4~0); 124#L1234-1true assume !(1 == ~E_5~0); 812#L1239-1true assume !(1 == ~E_6~0); 157#L1244-1true assume !(1 == ~E_7~0); 862#L1249-1true assume !(1 == ~E_8~0); 769#L1254-1true assume 1 == ~E_9~0;~E_9~0 := 2; 74#L1259-1true assume !(1 == ~E_10~0); 682#L1265-1true assume true;assume { :end_inline_reset_delta_events } true; 232#L1565true [2024-11-17 08:52:46,016 INFO L747 eck$LassoCheckResult]: Loop: 232#L1565true assume true; 977#L1565-1true assume !false; 1140#start_simulation_while_12_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 563#L861true assume !true; 785#L869true assume true; 709#L1029true assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19#L724true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60#L1036true assume 0 == ~M_E~0;~M_E~0 := 1; 676#L1041true assume 0 == ~T1_E~0;~T1_E~0 := 1; 81#L1046true assume !(0 == ~T2_E~0); 1292#L1051true assume 0 == ~T3_E~0;~T3_E~0 := 1; 256#L1056true assume 0 == ~T4_E~0;~T4_E~0 := 1; 875#L1061true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1080#L1066true assume 0 == ~T6_E~0;~T6_E~0 := 1; 816#L1071true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1258#L1076true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1286#L1081true assume 0 == ~T9_E~0;~T9_E~0 := 1; 850#L1086true assume !(0 == ~T10_E~0); 802#L1091true assume 0 == ~E_M~0;~E_M~0 := 1; 162#L1096true assume 0 == ~E_1~0;~E_1~0 := 1; 98#L1101true assume 0 == ~E_2~0;~E_2~0 := 1; 1366#L1106true assume 0 == ~E_3~0;~E_3~0 := 1; 1327#L1111true assume 0 == ~E_4~0;~E_4~0 := 1; 313#L1116true assume 0 == ~E_5~0;~E_5~0 := 1; 42#L1121true assume 0 == ~E_6~0;~E_6~0 := 1; 297#L1126true assume !(0 == ~E_7~0); 985#L1131true assume 0 == ~E_8~0;~E_8~0 := 1; 543#L1136true assume 0 == ~E_9~0;~E_9~0 := 1; 537#L1141true assume 0 == ~E_10~0;~E_10~0 := 1; 1109#L1147true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 407#L514-1true assume !(1 == ~m_pc~0); 775#L524-1true is_master_triggered_~__retres1~0#1 := 0; 1293#L517-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1188#L526-1true assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1266#L1285-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 381#L1291-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1382#L533-1true assume 1 == ~t1_pc~0; 536#L534-1true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1017#L536-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1073#L545-1true assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 921#L1293-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 847#L1299-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1005#L552-1true assume 1 == ~t2_pc~0; 653#L553-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1130#L555-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 273#L564-1true assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1027#L1301-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 410#L1307-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 600#L571-1true assume 1 == ~t3_pc~0; 827#L572-1true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 894#L574-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 238#L583-1true assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1263#L1309-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 110#L1315-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44#L590-1true assume !(1 == ~t4_pc~0); 610#L600-1true is_transmit4_triggered_~__retres1~4#1 := 0; 107#L593-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1402#L602-1true assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 786#L1317-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 254#L1323-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8#L609-1true assume !(1 == ~t5_pc~0); 186#L619-1true is_transmit5_triggered_~__retres1~5#1 := 0; 674#L612-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 495#L621-1true assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 882#L1325-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 213#L1331-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1379#L628-1true assume !(1 == ~t6_pc~0); 1146#L638-1true is_transmit6_triggered_~__retres1~6#1 := 0; 1163#L631-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1265#L640-1true assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1264#L1333-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1138#L1339-1true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 212#L647-1true assume !(1 == ~t7_pc~0); 113#L657-1true is_transmit7_triggered_~__retres1~7#1 := 0; 193#L650-1true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1117#L659-1true assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 95#L1341-1true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 830#L1347-1true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1223#L666-1true assume !(1 == ~t8_pc~0); 902#L676-1true is_transmit8_triggered_~__retres1~8#1 := 0; 48#L669-1true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 993#L678-1true assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1341#L1349-1true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 470#L1355-1true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1237#L685-1true assume 1 == ~t9_pc~0; 310#L686-1true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1273#L688-1true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1107#L697-1true assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84#L1357-1true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 70#L1363-1true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1171#L704-1true assume 1 == ~t10_pc~0; 436#L705-1true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1173#L707-1true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 148#L716-1true assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 185#L1365-1true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 327#L1371-1true assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 718#L1154true assume 1 == ~M_E~0;~M_E~0 := 2; 925#L1159true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1037#L1164true assume 1 == ~T2_E~0;~T2_E~0 := 2; 523#L1169true assume 1 == ~T3_E~0;~T3_E~0 := 2; 390#L1174true assume 1 == ~T4_E~0;~T4_E~0 := 2; 683#L1179true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1010#L1184true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1053#L1189true assume 1 == ~T7_E~0;~T7_E~0 := 2; 482#L1194true assume 1 == ~T8_E~0;~T8_E~0 := 2; 472#L1199true assume 1 == ~T9_E~0;~T9_E~0 := 2; 652#L1204true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1326#L1209true assume 1 == ~E_M~0;~E_M~0 := 2; 865#L1214true assume 1 == ~E_1~0;~E_1~0 := 2; 1234#L1219true assume 1 == ~E_2~0;~E_2~0 := 2; 712#L1224true assume 1 == ~E_3~0;~E_3~0 := 2; 502#L1229true assume 1 == ~E_4~0;~E_4~0 := 2; 169#L1234true assume 1 == ~E_5~0;~E_5~0 := 2; 422#L1239true assume 1 == ~E_6~0;~E_6~0 := 2; 1429#L1244true assume 1 == ~E_7~0;~E_7~0 := 2; 581#L1249true assume 1 == ~E_8~0;~E_8~0 := 2; 727#L1254true assume 1 == ~E_9~0;~E_9~0 := 2; 1370#L1259true assume 1 == ~E_10~0;~E_10~0 := 2; 975#L1265true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 782#L794-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 374#L836-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 511#L852-1true assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 612#L1584true assume !(0 == start_simulation_~tmp~3#1); 1284#L1595true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 319#L794true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1103#L836true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 920#L852true assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 356#L1539true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 772#L1541true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 335#L1547true assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1212#L1597true assume !(0 != start_simulation_~tmp___0~1#1); 232#L1565true [2024-11-17 08:52:46,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:46,024 INFO L85 PathProgramCache]: Analyzing trace with hash 470382460, now seen corresponding path program 1 times [2024-11-17 08:52:46,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:46,037 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1050616763] [2024-11-17 08:52:46,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:46,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:46,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:46,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:46,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:46,368 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1050616763] [2024-11-17 08:52:46,368 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1050616763] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:46,368 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:46,368 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:46,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389236457] [2024-11-17 08:52:46,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:46,375 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:46,375 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:46,376 INFO L85 PathProgramCache]: Analyzing trace with hash 694365441, now seen corresponding path program 1 times [2024-11-17 08:52:46,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:46,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575301909] [2024-11-17 08:52:46,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:46,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:46,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:46,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:46,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:46,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1575301909] [2024-11-17 08:52:46,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1575301909] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:46,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:46,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:46,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754836794] [2024-11-17 08:52:46,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:46,424 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:46,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:46,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:46,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:46,453 INFO L87 Difference]: Start difference. First operand has 1436 states, 1435 states have (on average 1.4850174216027874) internal successors, (2131), 1435 states have internal predecessors, (2131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:46,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:46,514 INFO L93 Difference]: Finished difference Result 1421 states and 2087 transitions. [2024-11-17 08:52:46,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1421 states and 2087 transitions. [2024-11-17 08:52:46,525 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:46,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1421 states to 1414 states and 2080 transitions. [2024-11-17 08:52:46,534 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:46,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:46,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2080 transitions. [2024-11-17 08:52:46,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:46,541 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2080 transitions. [2024-11-17 08:52:46,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2080 transitions. [2024-11-17 08:52:46,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:46,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.471004243281471) internal successors, (2080), 1413 states have internal predecessors, (2080), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:46,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2080 transitions. [2024-11-17 08:52:46,603 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2080 transitions. [2024-11-17 08:52:46,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:46,610 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2080 transitions. [2024-11-17 08:52:46,610 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:52:46,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2080 transitions. [2024-11-17 08:52:46,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:46,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:46,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:46,617 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:46,617 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:46,618 INFO L745 eck$LassoCheckResult]: Stem: 3956#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 2923#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2924#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3866#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3867#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 3310#L736 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 3182#L741 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3183#L746 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2912#L751 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2913#L756 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3696#L761 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3729#L766 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4202#L771 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4220#L776 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 4084#L781 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3512#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3513#L1036-1 assume !(0 == ~M_E~0); 3881#L1041-1 assume !(0 == ~T1_E~0); 3882#L1046-1 assume !(0 == ~T2_E~0); 3268#L1051-1 assume !(0 == ~T3_E~0); 3269#L1056-1 assume !(0 == ~T4_E~0); 4025#L1061-1 assume !(0 == ~T5_E~0); 3173#L1066-1 assume !(0 == ~T6_E~0); 3174#L1071-1 assume !(0 == ~T7_E~0); 4009#L1076-1 assume !(0 == ~T8_E~0); 3059#L1081-1 assume !(0 == ~T9_E~0); 3060#L1086-1 assume !(0 == ~T10_E~0); 3469#L1091-1 assume !(0 == ~E_M~0); 4206#L1096-1 assume !(0 == ~E_1~0); 4207#L1101-1 assume !(0 == ~E_2~0); 3544#L1106-1 assume !(0 == ~E_3~0); 3545#L1111-1 assume !(0 == ~E_4~0); 3699#L1116-1 assume !(0 == ~E_5~0); 3700#L1121-1 assume !(0 == ~E_6~0); 3537#L1126-1 assume !(0 == ~E_7~0); 3538#L1131-1 assume !(0 == ~E_8~0); 3805#L1136-1 assume !(0 == ~E_9~0); 3902#L1141-1 assume !(0 == ~E_10~0); 4066#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3912#L514-13 assume 1 == ~m_pc~0; 3741#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3742#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2873#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2874#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 3202#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4142#L533-13 assume 1 == ~t1_pc~0; 3046#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3047#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3554#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3304#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 3305#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3226#L552-13 assume 1 == ~t2_pc~0; 3227#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4158#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3025#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3026#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 4004#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3781#L571-13 assume 1 == ~t3_pc~0; 3782#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3862#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3638#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3639#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3763#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3836#L590-13 assume 1 == ~t4_pc~0; 3861#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3014#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4081#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3764#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 3765#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4119#L609-13 assume 1 == ~t5_pc~0; 3264#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2871#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2872#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4226#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 3673#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2983#L628-13 assume 1 == ~t6_pc~0; 2984#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3299#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3300#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3434#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 3262#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3263#L647-13 assume 1 == ~t7_pc~0; 4144#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3885#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3886#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3812#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3813#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3880#L666-13 assume 1 == ~t8_pc~0; 2901#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2902#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3693#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4232#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 2972#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2973#L685-13 assume 1 == ~t9_pc~0; 4209#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3224#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3225#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3842#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 3785#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3786#L704-13 assume 1 == ~t10_pc~0; 3968#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2898#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2920#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2921#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 3123#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3124#L1154-1 assume !(1 == ~M_E~0); 3127#L1159-1 assume !(1 == ~T1_E~0); 3251#L1164-1 assume !(1 == ~T2_E~0); 3722#L1169-1 assume !(1 == ~T3_E~0); 3599#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3385#L1179-1 assume !(1 == ~T5_E~0); 3232#L1184-1 assume !(1 == ~T6_E~0); 3233#L1189-1 assume !(1 == ~T7_E~0); 3314#L1194-1 assume !(1 == ~T8_E~0); 3448#L1199-1 assume !(1 == ~T9_E~0); 3398#L1204-1 assume !(1 == ~T10_E~0); 3399#L1209-1 assume !(1 == ~E_M~0); 3947#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3948#L1219-1 assume !(1 == ~E_2~0); 4257#L1224-1 assume !(1 == ~E_3~0); 3751#L1229-1 assume !(1 == ~E_4~0); 3116#L1234-1 assume !(1 == ~E_5~0); 3117#L1239-1 assume !(1 == ~E_6~0); 3180#L1244-1 assume !(1 == ~E_7~0); 3181#L1249-1 assume !(1 == ~E_8~0); 4014#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 3019#L1259-1 assume !(1 == ~E_10~0); 3020#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 3323#L1565 [2024-11-17 08:52:46,618 INFO L747 eck$LassoCheckResult]: Loop: 3323#L1565 assume true; 3324#L1565-1 assume !false; 4159#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3419#L861 assume true; 3828#L861-1 assume !false; 3565#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3191#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2878#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3344#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3245#L866 assume !(0 != eval_~tmp~0#1); 3247#L869 assume true; 3971#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2909#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2910#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 2994#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3034#L1046 assume !(0 == ~T2_E~0); 3035#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3370#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3371#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4106#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4060#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4061#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4263#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4086#L1086 assume !(0 == ~T10_E~0); 4049#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 3190#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 3067#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 3068#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 4271#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 3464#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 2952#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 2953#L1126 assume !(0 == ~E_7~0); 3437#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 3806#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 3795#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 3796#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3616#L514-1 assume 1 == ~m_pc~0; 3617#L515-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4020#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4242#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4243#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3581#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3582#L533-1 assume 1 == ~t1_pc~0; 3792#L534-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3793#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4180#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4130#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4082#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4083#L552-1 assume !(1 == ~t2_pc~0); 3539#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 3540#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3394#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3395#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3623#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3624#L571-1 assume !(1 == ~t3_pc~0); 3321#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 3322#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3330#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3331#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3088#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2954#L590-1 assume 1 == ~t4_pc~0; 2955#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3084#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3085#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4035#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3364#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2880#L609-1 assume 1 == ~t5_pc~0; 2881#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3239#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3737#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3738#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3287#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3288#L628-1 assume 1 == ~t6_pc~0; 4274#L629-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4223#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4230#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4264#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4221#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3285#L647-1 assume !(1 == ~t7_pc~0); 3093#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 3094#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3250#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3062#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3063#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4069#L666-1 assume 1 == ~t8_pc~0; 3477#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 2964#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2965#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4167#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3707#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3708#L685-1 assume 1 == ~t9_pc~0; 3457#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3458#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4215#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3041#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3011#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3012#L704-1 assume !(1 == ~t10_pc~0); 3281#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 3282#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3156#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3157#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3238#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3486#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 3977#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4132#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3776#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3595#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3596#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3945#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4175#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3723#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3710#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3711#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3924#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 4098#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 4099#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 3973#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 3750#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 3200#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 3201#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 3642#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 3845#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 3846#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 3985#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 4156#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4031#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2992#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3569#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 3759#L1584 assume !(0 == start_simulation_~tmp~3#1); 3649#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3473#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3216#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4128#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 3541#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3542#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3501#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 3502#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 3323#L1565 [2024-11-17 08:52:46,619 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:46,619 INFO L85 PathProgramCache]: Analyzing trace with hash -3136483, now seen corresponding path program 1 times [2024-11-17 08:52:46,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:46,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [174711904] [2024-11-17 08:52:46,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:46,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:46,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:46,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:46,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:46,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [174711904] [2024-11-17 08:52:46,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [174711904] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:46,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:46,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:46,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1066643327] [2024-11-17 08:52:46,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:46,677 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:46,677 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:46,678 INFO L85 PathProgramCache]: Analyzing trace with hash -1306209438, now seen corresponding path program 1 times [2024-11-17 08:52:46,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:46,678 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1411297201] [2024-11-17 08:52:46,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:46,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:46,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:46,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:46,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:46,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1411297201] [2024-11-17 08:52:46,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1411297201] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:46,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:46,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:46,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1900953167] [2024-11-17 08:52:46,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:46,771 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:46,771 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:46,771 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:46,771 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:46,772 INFO L87 Difference]: Start difference. First operand 1414 states and 2080 transitions. cyclomatic complexity: 667 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:46,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:46,790 INFO L93 Difference]: Finished difference Result 1414 states and 2079 transitions. [2024-11-17 08:52:46,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1414 states and 2079 transitions. [2024-11-17 08:52:46,795 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:46,800 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1414 states to 1414 states and 2079 transitions. [2024-11-17 08:52:46,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:46,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:46,806 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2079 transitions. [2024-11-17 08:52:46,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:46,807 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2079 transitions. [2024-11-17 08:52:46,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2079 transitions. [2024-11-17 08:52:46,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:46,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.4702970297029703) internal successors, (2079), 1413 states have internal predecessors, (2079), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:46,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2079 transitions. [2024-11-17 08:52:46,840 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2079 transitions. [2024-11-17 08:52:46,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:46,842 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2079 transitions. [2024-11-17 08:52:46,842 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:52:46,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2079 transitions. [2024-11-17 08:52:46,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:46,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:46,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:46,850 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:46,851 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:46,851 INFO L745 eck$LassoCheckResult]: Stem: 6788#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 5760#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5761#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6701#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6702#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 6145#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6019#L741 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6020#L746 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5749#L751 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5750#L756 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6531#L761 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6566#L766 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7039#L771 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7056#L776 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 6921#L781 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6343#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6344#L1036-1 assume !(0 == ~M_E~0); 6718#L1041-1 assume !(0 == ~T1_E~0); 6719#L1046-1 assume !(0 == ~T2_E~0); 6103#L1051-1 assume !(0 == ~T3_E~0); 6104#L1056-1 assume !(0 == ~T4_E~0); 6860#L1061-1 assume !(0 == ~T5_E~0); 6010#L1066-1 assume !(0 == ~T6_E~0); 6011#L1071-1 assume !(0 == ~T7_E~0); 6845#L1076-1 assume !(0 == ~T8_E~0); 5896#L1081-1 assume !(0 == ~T9_E~0); 5897#L1086-1 assume !(0 == ~T10_E~0); 6306#L1091-1 assume !(0 == ~E_M~0); 7043#L1096-1 assume !(0 == ~E_1~0); 7044#L1101-1 assume !(0 == ~E_2~0); 6381#L1106-1 assume !(0 == ~E_3~0); 6382#L1111-1 assume !(0 == ~E_4~0); 6536#L1116-1 assume !(0 == ~E_5~0); 6537#L1121-1 assume !(0 == ~E_6~0); 6374#L1126-1 assume !(0 == ~E_7~0); 6375#L1131-1 assume !(0 == ~E_8~0); 6639#L1136-1 assume !(0 == ~E_9~0); 6737#L1141-1 assume !(0 == ~E_10~0); 6903#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6749#L514-13 assume 1 == ~m_pc~0; 6578#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6579#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5710#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5711#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 6037#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6978#L533-13 assume 1 == ~t1_pc~0; 5883#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5884#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6387#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6141#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 6142#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6063#L552-13 assume 1 == ~t2_pc~0; 6064#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6995#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5860#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5861#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 6841#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6618#L571-13 assume 1 == ~t3_pc~0; 6619#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6699#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6475#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6476#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6599#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6673#L590-13 assume 1 == ~t4_pc~0; 6698#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5851#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6917#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6600#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 6601#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6956#L609-13 assume 1 == ~t5_pc~0; 6101#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5705#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5706#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7063#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 6510#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5820#L628-13 assume 1 == ~t6_pc~0; 5821#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6136#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6137#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6271#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 6099#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6100#L647-13 assume 1 == ~t7_pc~0; 6981#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6722#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6723#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6649#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6650#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6717#L666-13 assume 1 == ~t8_pc~0; 5736#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5737#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6530#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7069#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 5809#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5810#L685-13 assume 1 == ~t9_pc~0; 7046#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6054#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6055#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6679#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 6622#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6623#L704-13 assume 1 == ~t10_pc~0; 6805#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5735#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5755#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5756#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 5959#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5960#L1154-1 assume !(1 == ~M_E~0); 5964#L1159-1 assume !(1 == ~T1_E~0); 6085#L1164-1 assume !(1 == ~T2_E~0); 6559#L1169-1 assume !(1 == ~T3_E~0); 6436#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6222#L1179-1 assume !(1 == ~T5_E~0); 6069#L1184-1 assume !(1 == ~T6_E~0); 6070#L1189-1 assume !(1 == ~T7_E~0); 6151#L1194-1 assume !(1 == ~T8_E~0); 6284#L1199-1 assume !(1 == ~T9_E~0); 6235#L1204-1 assume !(1 == ~T10_E~0); 6236#L1209-1 assume !(1 == ~E_M~0); 6784#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6785#L1219-1 assume !(1 == ~E_2~0); 7094#L1224-1 assume !(1 == ~E_3~0); 6588#L1229-1 assume !(1 == ~E_4~0); 5951#L1234-1 assume !(1 == ~E_5~0); 5952#L1239-1 assume !(1 == ~E_6~0); 6017#L1244-1 assume !(1 == ~E_7~0); 6018#L1249-1 assume !(1 == ~E_8~0); 6851#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 5856#L1259-1 assume !(1 == ~E_10~0); 5857#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 6158#L1565 [2024-11-17 08:52:46,853 INFO L747 eck$LassoCheckResult]: Loop: 6158#L1565 assume true; 6159#L1565-1 assume !false; 6996#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6256#L861 assume true; 6665#L861-1 assume !false; 6401#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6028#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5715#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6181#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6081#L866 assume !(0 != eval_~tmp~0#1); 6083#L869 assume true; 6806#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5744#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5745#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 5831#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5871#L1046 assume !(0 == ~T2_E~0); 5872#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6205#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6206#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6943#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6897#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6898#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7100#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6923#L1086 assume !(0 == ~T10_E~0); 6885#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 6027#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 5904#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 5905#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 7108#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 6301#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 5786#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 5787#L1126 assume !(0 == ~E_7~0); 6272#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 6643#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 6632#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 6633#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6453#L514-1 assume 1 == ~m_pc~0; 6454#L515-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6857#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7079#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7080#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6418#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6419#L533-1 assume 1 == ~t1_pc~0; 6629#L534-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6630#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7017#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6967#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6919#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6920#L552-1 assume !(1 == ~t2_pc~0); 6376#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 6377#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6231#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6232#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6460#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6461#L571-1 assume !(1 == ~t3_pc~0); 6160#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 6161#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6167#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6168#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5925#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5791#L590-1 assume 1 == ~t4_pc~0; 5792#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5921#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5922#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6872#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6203#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5717#L609-1 assume 1 == ~t5_pc~0; 5718#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6076#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6576#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6577#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6124#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6125#L628-1 assume !(1 == ~t6_pc~0); 7059#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 7060#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7067#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7101#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7058#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6122#L647-1 assume !(1 == ~t7_pc~0); 5930#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 5931#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6088#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5899#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5900#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6906#L666-1 assume 1 == ~t8_pc~0; 6314#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5801#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5802#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7006#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6544#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6545#L685-1 assume 1 == ~t9_pc~0; 6294#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6295#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7052#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5878#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5848#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5849#L704-1 assume !(1 == ~t10_pc~0); 6118#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 6119#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6000#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6001#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6075#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6323#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 6814#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6969#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6613#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6432#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6433#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6782#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7014#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6560#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6547#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6548#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6761#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 6936#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 6937#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 6810#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 6587#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 6038#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 6039#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 6479#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 6684#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 6685#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 6822#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 6994#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6868#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5829#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6406#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 6597#L1584 assume !(0 == start_simulation_~tmp~3#1); 6486#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6310#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6053#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6966#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 6378#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6379#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6338#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 6339#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 6158#L1565 [2024-11-17 08:52:46,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:46,853 INFO L85 PathProgramCache]: Analyzing trace with hash -434053284, now seen corresponding path program 1 times [2024-11-17 08:52:46,854 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:46,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [839350965] [2024-11-17 08:52:46,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:46,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:46,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:46,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:46,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:46,918 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [839350965] [2024-11-17 08:52:46,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [839350965] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:46,918 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:46,918 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:46,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [715440807] [2024-11-17 08:52:46,919 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:46,919 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:46,919 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:46,919 INFO L85 PathProgramCache]: Analyzing trace with hash 52577189, now seen corresponding path program 1 times [2024-11-17 08:52:46,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:46,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [859605169] [2024-11-17 08:52:46,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:46,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:46,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [859605169] [2024-11-17 08:52:47,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [859605169] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:47,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780870480] [2024-11-17 08:52:47,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,020 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:47,020 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:47,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:47,020 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:47,021 INFO L87 Difference]: Start difference. First operand 1414 states and 2079 transitions. cyclomatic complexity: 666 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:47,040 INFO L93 Difference]: Finished difference Result 1414 states and 2078 transitions. [2024-11-17 08:52:47,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1414 states and 2078 transitions. [2024-11-17 08:52:47,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,049 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1414 states to 1414 states and 2078 transitions. [2024-11-17 08:52:47,049 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:47,050 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:47,050 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2078 transitions. [2024-11-17 08:52:47,051 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:47,051 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2078 transitions. [2024-11-17 08:52:47,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2078 transitions. [2024-11-17 08:52:47,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:47,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.4695898161244696) internal successors, (2078), 1413 states have internal predecessors, (2078), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2078 transitions. [2024-11-17 08:52:47,066 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2078 transitions. [2024-11-17 08:52:47,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:47,067 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2078 transitions. [2024-11-17 08:52:47,068 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:52:47,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2078 transitions. [2024-11-17 08:52:47,072 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:47,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:47,074 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,074 INFO L745 eck$LassoCheckResult]: Stem: 9625#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 8597#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8598#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9540#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9541#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 8982#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8856#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8857#L746 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8586#L751 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8587#L756 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9369#L761 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9403#L766 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9876#L771 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9894#L776 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 9758#L781 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9180#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9181#L1036-1 assume !(0 == ~M_E~0); 9555#L1041-1 assume !(0 == ~T1_E~0); 9556#L1046-1 assume !(0 == ~T2_E~0); 8940#L1051-1 assume !(0 == ~T3_E~0); 8941#L1056-1 assume !(0 == ~T4_E~0); 9697#L1061-1 assume !(0 == ~T5_E~0); 8847#L1066-1 assume !(0 == ~T6_E~0); 8848#L1071-1 assume !(0 == ~T7_E~0); 9682#L1076-1 assume !(0 == ~T8_E~0); 8733#L1081-1 assume !(0 == ~T9_E~0); 8734#L1086-1 assume !(0 == ~T10_E~0); 9143#L1091-1 assume !(0 == ~E_M~0); 9880#L1096-1 assume !(0 == ~E_1~0); 9881#L1101-1 assume !(0 == ~E_2~0); 9218#L1106-1 assume !(0 == ~E_3~0); 9219#L1111-1 assume !(0 == ~E_4~0); 9373#L1116-1 assume !(0 == ~E_5~0); 9374#L1121-1 assume !(0 == ~E_6~0); 9211#L1126-1 assume !(0 == ~E_7~0); 9212#L1131-1 assume !(0 == ~E_8~0); 9476#L1136-1 assume !(0 == ~E_9~0); 9574#L1141-1 assume !(0 == ~E_10~0); 9740#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9586#L514-13 assume 1 == ~m_pc~0; 9415#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9416#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8547#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8548#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 8876#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9815#L533-13 assume 1 == ~t1_pc~0; 8720#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8721#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9226#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8978#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 8979#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8900#L552-13 assume 1 == ~t2_pc~0; 8901#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9832#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8699#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8700#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 9678#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9455#L571-13 assume 1 == ~t3_pc~0; 9456#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9536#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9312#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9313#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9436#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9510#L590-13 assume 1 == ~t4_pc~0; 9535#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8688#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9754#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9437#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 9438#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9793#L609-13 assume 1 == ~t5_pc~0; 8938#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8542#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8543#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9900#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 9347#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8657#L628-13 assume 1 == ~t6_pc~0; 8658#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8973#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8974#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9108#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 8936#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8937#L647-13 assume 1 == ~t7_pc~0; 9818#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9559#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9560#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9486#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9487#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9554#L666-13 assume 1 == ~t8_pc~0; 8573#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8574#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9367#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9906#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 8646#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8647#L685-13 assume 1 == ~t9_pc~0; 9883#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8893#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8894#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9516#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 9459#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9460#L704-13 assume 1 == ~t10_pc~0; 9642#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8572#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8594#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8595#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 8797#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8798#L1154-1 assume !(1 == ~M_E~0); 8801#L1159-1 assume !(1 == ~T1_E~0); 8923#L1164-1 assume !(1 == ~T2_E~0); 9396#L1169-1 assume !(1 == ~T3_E~0); 9273#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9059#L1179-1 assume !(1 == ~T5_E~0); 8906#L1184-1 assume !(1 == ~T6_E~0); 8907#L1189-1 assume !(1 == ~T7_E~0); 8988#L1194-1 assume !(1 == ~T8_E~0); 9121#L1199-1 assume !(1 == ~T9_E~0); 9072#L1204-1 assume !(1 == ~T10_E~0); 9073#L1209-1 assume !(1 == ~E_M~0); 9621#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9622#L1219-1 assume !(1 == ~E_2~0); 9931#L1224-1 assume !(1 == ~E_3~0); 9425#L1229-1 assume !(1 == ~E_4~0); 8788#L1234-1 assume !(1 == ~E_5~0); 8789#L1239-1 assume !(1 == ~E_6~0); 8854#L1244-1 assume !(1 == ~E_7~0); 8855#L1249-1 assume !(1 == ~E_8~0); 9688#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 8693#L1259-1 assume !(1 == ~E_10~0); 8694#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 8995#L1565 [2024-11-17 08:52:47,074 INFO L747 eck$LassoCheckResult]: Loop: 8995#L1565 assume true; 8996#L1565-1 assume !false; 9833#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9093#L861 assume true; 9502#L861-1 assume !false; 9239#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8865#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8552#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9018#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8918#L866 assume !(0 != eval_~tmp~0#1); 8920#L869 assume true; 9643#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8581#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8582#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 8668#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8708#L1046 assume !(0 == ~T2_E~0); 8709#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9042#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9043#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9780#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9734#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9735#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9937#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9760#L1086 assume !(0 == ~T10_E~0); 9722#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 8864#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 8741#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 8742#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 9945#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 9138#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 8623#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 8624#L1126 assume !(0 == ~E_7~0); 9109#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 9480#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 9469#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 9470#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9290#L514-1 assume 1 == ~m_pc~0; 9291#L515-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9694#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9916#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9917#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9255#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9256#L533-1 assume 1 == ~t1_pc~0; 9466#L534-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9467#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9854#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9804#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9756#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9757#L552-1 assume !(1 == ~t2_pc~0); 9213#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 9214#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9068#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9069#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9297#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9298#L571-1 assume !(1 == ~t3_pc~0); 8997#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 8998#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9006#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9007#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8762#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8628#L590-1 assume 1 == ~t4_pc~0; 8629#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8758#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8759#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9709#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9041#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8556#L609-1 assume 1 == ~t5_pc~0; 8557#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8913#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9413#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9414#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8964#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8965#L628-1 assume !(1 == ~t6_pc~0); 9896#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 9897#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9904#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9938#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9895#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8959#L647-1 assume 1 == ~t7_pc~0; 8960#L648-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8766#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8922#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8736#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8737#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9743#L666-1 assume !(1 == ~t8_pc~0); 9152#L676-1 is_transmit8_triggered_~__retres1~8#1 := 0; 8638#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8639#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9841#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9380#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9381#L685-1 assume 1 == ~t9_pc~0; 9129#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9130#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9889#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8715#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8683#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8684#L704-1 assume 1 == ~t10_pc~0; 9329#L705-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8956#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8830#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8831#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8910#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9160#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 9651#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9806#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9450#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9269#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9270#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9619#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9849#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9397#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9384#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9385#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9598#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 9772#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 9773#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 9647#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 9422#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 8874#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 8875#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 9316#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 9519#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 9520#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 9656#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 9830#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9703#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8666#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9243#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 9432#L1584 assume !(0 == start_simulation_~tmp~3#1); 9323#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9144#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8890#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9802#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 9215#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9216#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9175#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 9176#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 8995#L1565 [2024-11-17 08:52:47,075 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,076 INFO L85 PathProgramCache]: Analyzing trace with hash -1556332483, now seen corresponding path program 1 times [2024-11-17 08:52:47,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862253965] [2024-11-17 08:52:47,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,114 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862253965] [2024-11-17 08:52:47,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862253965] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:47,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502009180] [2024-11-17 08:52:47,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,118 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:47,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,118 INFO L85 PathProgramCache]: Analyzing trace with hash 1600903330, now seen corresponding path program 1 times [2024-11-17 08:52:47,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197096474] [2024-11-17 08:52:47,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,181 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197096474] [2024-11-17 08:52:47,181 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197096474] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,181 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,181 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:47,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560327295] [2024-11-17 08:52:47,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,182 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:47,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:47,182 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:47,183 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:47,183 INFO L87 Difference]: Start difference. First operand 1414 states and 2078 transitions. cyclomatic complexity: 665 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:47,200 INFO L93 Difference]: Finished difference Result 1414 states and 2077 transitions. [2024-11-17 08:52:47,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1414 states and 2077 transitions. [2024-11-17 08:52:47,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,210 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1414 states to 1414 states and 2077 transitions. [2024-11-17 08:52:47,210 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:47,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:47,211 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2077 transitions. [2024-11-17 08:52:47,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:47,212 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2077 transitions. [2024-11-17 08:52:47,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2077 transitions. [2024-11-17 08:52:47,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:47,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.468882602545969) internal successors, (2077), 1413 states have internal predecessors, (2077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2077 transitions. [2024-11-17 08:52:47,229 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2077 transitions. [2024-11-17 08:52:47,230 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:47,231 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2077 transitions. [2024-11-17 08:52:47,231 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:52:47,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2077 transitions. [2024-11-17 08:52:47,235 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:47,236 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:47,237 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,238 INFO L745 eck$LassoCheckResult]: Stem: 12467#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 11434#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 11435#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12377#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12378#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 11821#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11693#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11694#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11423#L751 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 11424#L756 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12207#L761 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12240#L766 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12713#L771 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12731#L776 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 12595#L781 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12023#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12024#L1036-1 assume !(0 == ~M_E~0); 12392#L1041-1 assume !(0 == ~T1_E~0); 12393#L1046-1 assume !(0 == ~T2_E~0); 11779#L1051-1 assume !(0 == ~T3_E~0); 11780#L1056-1 assume !(0 == ~T4_E~0); 12536#L1061-1 assume !(0 == ~T5_E~0); 11684#L1066-1 assume !(0 == ~T6_E~0); 11685#L1071-1 assume !(0 == ~T7_E~0); 12520#L1076-1 assume !(0 == ~T8_E~0); 11570#L1081-1 assume !(0 == ~T9_E~0); 11571#L1086-1 assume !(0 == ~T10_E~0); 11980#L1091-1 assume !(0 == ~E_M~0); 12717#L1096-1 assume !(0 == ~E_1~0); 12718#L1101-1 assume !(0 == ~E_2~0); 12055#L1106-1 assume !(0 == ~E_3~0); 12056#L1111-1 assume !(0 == ~E_4~0); 12210#L1116-1 assume !(0 == ~E_5~0); 12211#L1121-1 assume !(0 == ~E_6~0); 12048#L1126-1 assume !(0 == ~E_7~0); 12049#L1131-1 assume !(0 == ~E_8~0); 12316#L1136-1 assume !(0 == ~E_9~0); 12413#L1141-1 assume !(0 == ~E_10~0); 12577#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12423#L514-13 assume 1 == ~m_pc~0; 12252#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12253#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11384#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11385#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 11713#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12653#L533-13 assume 1 == ~t1_pc~0; 11557#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11558#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12065#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11817#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 11818#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11737#L552-13 assume 1 == ~t2_pc~0; 11738#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12669#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11539#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11540#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 12515#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12292#L571-13 assume 1 == ~t3_pc~0; 12293#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12373#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12149#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12150#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12274#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12347#L590-13 assume 1 == ~t4_pc~0; 12372#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11525#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12592#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12275#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 12276#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12630#L609-13 assume 1 == ~t5_pc~0; 11775#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11382#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11383#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12737#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 12184#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11494#L628-13 assume 1 == ~t6_pc~0; 11495#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11810#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11811#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11945#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 11773#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11774#L647-13 assume 1 == ~t7_pc~0; 12655#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12399#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12400#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12323#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12324#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12391#L666-13 assume 1 == ~t8_pc~0; 11412#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11413#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12204#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12743#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 11483#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11484#L685-13 assume 1 == ~t9_pc~0; 12720#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11735#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11736#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12355#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 12296#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12297#L704-13 assume 1 == ~t10_pc~0; 12479#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11409#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11431#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11432#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 11634#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11635#L1154-1 assume !(1 == ~M_E~0); 11638#L1159-1 assume !(1 == ~T1_E~0); 11762#L1164-1 assume !(1 == ~T2_E~0); 12233#L1169-1 assume !(1 == ~T3_E~0); 12111#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11896#L1179-1 assume !(1 == ~T5_E~0); 11743#L1184-1 assume !(1 == ~T6_E~0); 11744#L1189-1 assume !(1 == ~T7_E~0); 11825#L1194-1 assume !(1 == ~T8_E~0); 11959#L1199-1 assume !(1 == ~T9_E~0); 11909#L1204-1 assume !(1 == ~T10_E~0); 11910#L1209-1 assume !(1 == ~E_M~0); 12458#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12459#L1219-1 assume !(1 == ~E_2~0); 12768#L1224-1 assume !(1 == ~E_3~0); 12262#L1229-1 assume !(1 == ~E_4~0); 11627#L1234-1 assume !(1 == ~E_5~0); 11628#L1239-1 assume !(1 == ~E_6~0); 11691#L1244-1 assume !(1 == ~E_7~0); 11692#L1249-1 assume !(1 == ~E_8~0); 12525#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 11532#L1259-1 assume !(1 == ~E_10~0); 11533#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 11834#L1565 [2024-11-17 08:52:47,239 INFO L747 eck$LassoCheckResult]: Loop: 11834#L1565 assume true; 11835#L1565-1 assume !false; 12670#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11930#L861 assume true; 12339#L861-1 assume !false; 12076#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11702#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11389#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11855#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11756#L866 assume !(0 != eval_~tmp~0#1); 11758#L869 assume true; 12482#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11420#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11421#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 11505#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11545#L1046 assume !(0 == ~T2_E~0); 11546#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11881#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11882#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12617#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12571#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12572#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12774#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12597#L1086 assume !(0 == ~T10_E~0); 12559#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 11701#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 11578#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 11579#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 12782#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 11975#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 11460#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 11461#L1126 assume !(0 == ~E_7~0); 11946#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 12317#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 12306#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 12307#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12127#L514-1 assume 1 == ~m_pc~0; 12128#L515-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12531#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12753#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12754#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12092#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12093#L533-1 assume !(1 == ~t1_pc~0); 12305#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 12304#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12691#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12641#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12593#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12594#L552-1 assume !(1 == ~t2_pc~0); 12050#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 12051#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11905#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11906#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12134#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12135#L571-1 assume !(1 == ~t3_pc~0); 11832#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 11833#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11841#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11842#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11599#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11465#L590-1 assume 1 == ~t4_pc~0; 11466#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11595#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11596#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12546#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11877#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11391#L609-1 assume 1 == ~t5_pc~0; 11392#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11750#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12250#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12251#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11798#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11799#L628-1 assume 1 == ~t6_pc~0; 12785#L629-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12734#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12741#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12775#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12732#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11796#L647-1 assume !(1 == ~t7_pc~0); 11604#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 11605#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11761#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11573#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11574#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12580#L666-1 assume 1 == ~t8_pc~0; 11988#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11475#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11476#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12680#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12218#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12219#L685-1 assume 1 == ~t9_pc~0; 11968#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11969#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12726#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11552#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11522#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11523#L704-1 assume !(1 == ~t10_pc~0); 11792#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 11793#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11674#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11675#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11749#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11997#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 12488#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12643#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12287#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12106#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12107#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12456#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12688#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12234#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12221#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12222#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12435#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 12609#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 12610#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 12484#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 12261#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 11711#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 11712#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 12153#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 12356#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 12357#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 12496#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 12667#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12542#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11503#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 12080#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 12271#L1584 assume !(0 == start_simulation_~tmp~3#1); 12160#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11984#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11727#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 12640#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 12052#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12053#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12012#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 12013#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 11834#L1565 [2024-11-17 08:52:47,240 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,240 INFO L85 PathProgramCache]: Analyzing trace with hash 347127612, now seen corresponding path program 1 times [2024-11-17 08:52:47,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1158430671] [2024-11-17 08:52:47,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1158430671] [2024-11-17 08:52:47,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1158430671] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,275 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,275 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:47,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1876653857] [2024-11-17 08:52:47,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,276 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:47,276 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,276 INFO L85 PathProgramCache]: Analyzing trace with hash 988458085, now seen corresponding path program 1 times [2024-11-17 08:52:47,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1692699787] [2024-11-17 08:52:47,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1692699787] [2024-11-17 08:52:47,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1692699787] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,337 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:47,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1622366767] [2024-11-17 08:52:47,337 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,337 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:47,337 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:47,338 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:47,338 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:47,338 INFO L87 Difference]: Start difference. First operand 1414 states and 2077 transitions. cyclomatic complexity: 664 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:47,390 INFO L93 Difference]: Finished difference Result 1414 states and 2076 transitions. [2024-11-17 08:52:47,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1414 states and 2076 transitions. [2024-11-17 08:52:47,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1414 states to 1414 states and 2076 transitions. [2024-11-17 08:52:47,400 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:47,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:47,401 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2076 transitions. [2024-11-17 08:52:47,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:47,402 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2076 transitions. [2024-11-17 08:52:47,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2076 transitions. [2024-11-17 08:52:47,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:47,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.4681753889674682) internal successors, (2076), 1413 states have internal predecessors, (2076), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2076 transitions. [2024-11-17 08:52:47,417 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2076 transitions. [2024-11-17 08:52:47,417 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:47,419 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2076 transitions. [2024-11-17 08:52:47,419 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:52:47,419 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2076 transitions. [2024-11-17 08:52:47,423 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:47,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:47,424 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,424 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,425 INFO L745 eck$LassoCheckResult]: Stem: 15299#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 14271#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14272#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15212#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15213#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 14656#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14530#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14531#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14260#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14261#L756 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15042#L761 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15077#L766 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15550#L771 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15567#L776 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 15432#L781 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14854#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14855#L1036-1 assume !(0 == ~M_E~0); 15229#L1041-1 assume !(0 == ~T1_E~0); 15230#L1046-1 assume !(0 == ~T2_E~0); 14614#L1051-1 assume !(0 == ~T3_E~0); 14615#L1056-1 assume !(0 == ~T4_E~0); 15371#L1061-1 assume !(0 == ~T5_E~0); 14521#L1066-1 assume !(0 == ~T6_E~0); 14522#L1071-1 assume !(0 == ~T7_E~0); 15356#L1076-1 assume !(0 == ~T8_E~0); 14407#L1081-1 assume !(0 == ~T9_E~0); 14408#L1086-1 assume !(0 == ~T10_E~0); 14817#L1091-1 assume !(0 == ~E_M~0); 15554#L1096-1 assume !(0 == ~E_1~0); 15555#L1101-1 assume !(0 == ~E_2~0); 14892#L1106-1 assume !(0 == ~E_3~0); 14893#L1111-1 assume !(0 == ~E_4~0); 15047#L1116-1 assume !(0 == ~E_5~0); 15048#L1121-1 assume !(0 == ~E_6~0); 14885#L1126-1 assume !(0 == ~E_7~0); 14886#L1131-1 assume !(0 == ~E_8~0); 15150#L1136-1 assume !(0 == ~E_9~0); 15248#L1141-1 assume !(0 == ~E_10~0); 15414#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15260#L514-13 assume 1 == ~m_pc~0; 15089#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15090#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14221#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14222#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 14548#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15489#L533-13 assume 1 == ~t1_pc~0; 14394#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14395#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14898#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14652#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 14653#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14574#L552-13 assume 1 == ~t2_pc~0; 14575#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15506#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14371#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14372#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 15352#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15129#L571-13 assume 1 == ~t3_pc~0; 15130#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15210#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14986#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14987#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15110#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15184#L590-13 assume 1 == ~t4_pc~0; 15209#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14362#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15428#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15111#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 15112#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15467#L609-13 assume 1 == ~t5_pc~0; 14612#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14216#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14217#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15574#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 15021#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14331#L628-13 assume 1 == ~t6_pc~0; 14332#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14647#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14648#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14782#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 14610#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14611#L647-13 assume 1 == ~t7_pc~0; 15492#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15233#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15234#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15160#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15161#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15228#L666-13 assume 1 == ~t8_pc~0; 14247#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14248#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15041#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15580#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 14320#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14321#L685-13 assume 1 == ~t9_pc~0; 15557#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14565#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14566#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15190#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 15133#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 15134#L704-13 assume 1 == ~t10_pc~0; 15316#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14246#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14266#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14267#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 14470#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14471#L1154-1 assume !(1 == ~M_E~0); 14475#L1159-1 assume !(1 == ~T1_E~0); 14596#L1164-1 assume !(1 == ~T2_E~0); 15070#L1169-1 assume !(1 == ~T3_E~0); 14947#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14733#L1179-1 assume !(1 == ~T5_E~0); 14580#L1184-1 assume !(1 == ~T6_E~0); 14581#L1189-1 assume !(1 == ~T7_E~0); 14662#L1194-1 assume !(1 == ~T8_E~0); 14795#L1199-1 assume !(1 == ~T9_E~0); 14746#L1204-1 assume !(1 == ~T10_E~0); 14747#L1209-1 assume !(1 == ~E_M~0); 15295#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15296#L1219-1 assume !(1 == ~E_2~0); 15605#L1224-1 assume !(1 == ~E_3~0); 15099#L1229-1 assume !(1 == ~E_4~0); 14462#L1234-1 assume !(1 == ~E_5~0); 14463#L1239-1 assume !(1 == ~E_6~0); 14528#L1244-1 assume !(1 == ~E_7~0); 14529#L1249-1 assume !(1 == ~E_8~0); 15362#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 14367#L1259-1 assume !(1 == ~E_10~0); 14368#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 14669#L1565 [2024-11-17 08:52:47,425 INFO L747 eck$LassoCheckResult]: Loop: 14669#L1565 assume true; 14670#L1565-1 assume !false; 15507#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14767#L861 assume true; 15176#L861-1 assume !false; 14912#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14539#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14226#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14692#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14592#L866 assume !(0 != eval_~tmp~0#1); 14594#L869 assume true; 15317#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14255#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14256#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 14342#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14382#L1046 assume !(0 == ~T2_E~0); 14383#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14716#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14717#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15454#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15408#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15409#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15611#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15434#L1086 assume !(0 == ~T10_E~0); 15396#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 14538#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 14415#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 14416#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 15619#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 14812#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 14297#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 14298#L1126 assume !(0 == ~E_7~0); 14783#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 15154#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 15143#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 15144#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14964#L514-1 assume 1 == ~m_pc~0; 14965#L515-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15368#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15590#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15591#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14929#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14930#L533-1 assume 1 == ~t1_pc~0; 15140#L534-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15141#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15528#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15478#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15430#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15431#L552-1 assume !(1 == ~t2_pc~0); 14887#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 14888#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14742#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14743#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14971#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14972#L571-1 assume 1 == ~t3_pc~0; 15220#L572-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14672#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14678#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14679#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14436#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14302#L590-1 assume !(1 == ~t4_pc~0); 14304#L600-1 is_transmit4_triggered_~__retres1~4#1 := 0; 14432#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14433#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15383#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14714#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14228#L609-1 assume 1 == ~t5_pc~0; 14229#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14587#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15087#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15088#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14635#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14636#L628-1 assume !(1 == ~t6_pc~0); 15570#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 15571#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15578#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15612#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15569#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14633#L647-1 assume !(1 == ~t7_pc~0); 14441#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 14442#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14599#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14410#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14411#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15417#L666-1 assume 1 == ~t8_pc~0; 14825#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14312#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14313#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15517#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15055#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15056#L685-1 assume 1 == ~t9_pc~0; 14805#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14806#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15563#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14389#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14359#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14360#L704-1 assume !(1 == ~t10_pc~0); 14629#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 14630#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14511#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14512#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14586#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14834#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 15325#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15480#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15124#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14943#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14944#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15293#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15525#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15071#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15058#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15059#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15272#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 15447#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 15448#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 15321#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 15098#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 14549#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 14550#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 14990#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 15195#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 15196#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 15333#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 15505#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 15379#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14340#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14917#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 15108#L1584 assume !(0 == start_simulation_~tmp~3#1); 14997#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14821#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 14564#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 15477#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 14889#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14890#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14849#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 14850#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 14669#L1565 [2024-11-17 08:52:47,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1254038435, now seen corresponding path program 1 times [2024-11-17 08:52:47,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558758926] [2024-11-17 08:52:47,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,464 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558758926] [2024-11-17 08:52:47,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558758926] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,465 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:47,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889317098] [2024-11-17 08:52:47,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,467 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:47,468 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,468 INFO L85 PathProgramCache]: Analyzing trace with hash 900293093, now seen corresponding path program 1 times [2024-11-17 08:52:47,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [908710065] [2024-11-17 08:52:47,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,533 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,533 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [908710065] [2024-11-17 08:52:47,533 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [908710065] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,533 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,534 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:47,534 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1560700626] [2024-11-17 08:52:47,534 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,534 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:47,535 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:47,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:47,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:47,536 INFO L87 Difference]: Start difference. First operand 1414 states and 2076 transitions. cyclomatic complexity: 663 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:47,553 INFO L93 Difference]: Finished difference Result 1414 states and 2075 transitions. [2024-11-17 08:52:47,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1414 states and 2075 transitions. [2024-11-17 08:52:47,558 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1414 states to 1414 states and 2075 transitions. [2024-11-17 08:52:47,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:47,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:47,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2075 transitions. [2024-11-17 08:52:47,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:47,564 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2075 transitions. [2024-11-17 08:52:47,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2075 transitions. [2024-11-17 08:52:47,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:47,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.4674681753889676) internal successors, (2075), 1413 states have internal predecessors, (2075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2075 transitions. [2024-11-17 08:52:47,579 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2075 transitions. [2024-11-17 08:52:47,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:47,582 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2075 transitions. [2024-11-17 08:52:47,582 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:52:47,582 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2075 transitions. [2024-11-17 08:52:47,588 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:47,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:47,589 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,589 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,589 INFO L745 eck$LassoCheckResult]: Stem: 18141#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 17108#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 17109#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18051#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18052#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 17495#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17367#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17368#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17097#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17098#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17880#L761 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17914#L766 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18387#L771 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18405#L776 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 18269#L781 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17691#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17692#L1036-1 assume !(0 == ~M_E~0); 18066#L1041-1 assume !(0 == ~T1_E~0); 18067#L1046-1 assume !(0 == ~T2_E~0); 17453#L1051-1 assume !(0 == ~T3_E~0); 17454#L1056-1 assume !(0 == ~T4_E~0); 18210#L1061-1 assume !(0 == ~T5_E~0); 17358#L1066-1 assume !(0 == ~T6_E~0); 17359#L1071-1 assume !(0 == ~T7_E~0); 18194#L1076-1 assume !(0 == ~T8_E~0); 17244#L1081-1 assume !(0 == ~T9_E~0); 17245#L1086-1 assume !(0 == ~T10_E~0); 17654#L1091-1 assume !(0 == ~E_M~0); 18391#L1096-1 assume !(0 == ~E_1~0); 18392#L1101-1 assume !(0 == ~E_2~0); 17729#L1106-1 assume !(0 == ~E_3~0); 17730#L1111-1 assume !(0 == ~E_4~0); 17884#L1116-1 assume !(0 == ~E_5~0); 17885#L1121-1 assume !(0 == ~E_6~0); 17722#L1126-1 assume !(0 == ~E_7~0); 17723#L1131-1 assume !(0 == ~E_8~0); 17990#L1136-1 assume !(0 == ~E_9~0); 18087#L1141-1 assume !(0 == ~E_10~0); 18251#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18097#L514-13 assume 1 == ~m_pc~0; 17926#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17927#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17058#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17059#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 17387#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18326#L533-13 assume 1 == ~t1_pc~0; 17231#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17232#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17739#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17489#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 17490#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17411#L552-13 assume 1 == ~t2_pc~0; 17412#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18343#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17210#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17211#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 18189#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17966#L571-13 assume 1 == ~t3_pc~0; 17967#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18047#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17823#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17824#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17948#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18021#L590-13 assume 1 == ~t4_pc~0; 18046#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17199#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18266#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17949#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 17950#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18304#L609-13 assume 1 == ~t5_pc~0; 17449#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17056#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17057#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18411#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 17858#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17168#L628-13 assume 1 == ~t6_pc~0; 17169#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17484#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17485#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17619#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 17447#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17448#L647-13 assume 1 == ~t7_pc~0; 18329#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18070#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18071#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17997#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17998#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18065#L666-13 assume 1 == ~t8_pc~0; 17086#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17087#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17878#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18417#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 17157#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17158#L685-13 assume 1 == ~t9_pc~0; 18394#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17407#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17408#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18027#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 17970#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17971#L704-13 assume 1 == ~t10_pc~0; 18153#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17083#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17105#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17106#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 17308#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17309#L1154-1 assume !(1 == ~M_E~0); 17312#L1159-1 assume !(1 == ~T1_E~0); 17436#L1164-1 assume !(1 == ~T2_E~0); 17907#L1169-1 assume !(1 == ~T3_E~0); 17784#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17570#L1179-1 assume !(1 == ~T5_E~0); 17417#L1184-1 assume !(1 == ~T6_E~0); 17418#L1189-1 assume !(1 == ~T7_E~0); 17499#L1194-1 assume !(1 == ~T8_E~0); 17632#L1199-1 assume !(1 == ~T9_E~0); 17583#L1204-1 assume !(1 == ~T10_E~0); 17584#L1209-1 assume !(1 == ~E_M~0); 18132#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18133#L1219-1 assume !(1 == ~E_2~0); 18442#L1224-1 assume !(1 == ~E_3~0); 17936#L1229-1 assume !(1 == ~E_4~0); 17299#L1234-1 assume !(1 == ~E_5~0); 17300#L1239-1 assume !(1 == ~E_6~0); 17365#L1244-1 assume !(1 == ~E_7~0); 17366#L1249-1 assume !(1 == ~E_8~0); 18199#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 17204#L1259-1 assume !(1 == ~E_10~0); 17205#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 17508#L1565 [2024-11-17 08:52:47,591 INFO L747 eck$LassoCheckResult]: Loop: 17508#L1565 assume true; 17509#L1565-1 assume !false; 18344#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17604#L861 assume true; 18013#L861-1 assume !false; 17750#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17376#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 17063#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17529#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 17430#L866 assume !(0 != eval_~tmp~0#1); 17432#L869 assume true; 18156#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17094#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17095#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 17179#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17219#L1046 assume !(0 == ~T2_E~0); 17220#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17555#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17556#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18291#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18245#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18246#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18448#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18271#L1086 assume !(0 == ~T10_E~0); 18234#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 17375#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 17252#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 17253#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 18456#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 17649#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 17137#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 17138#L1126 assume !(0 == ~E_7~0); 17622#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 17991#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 17980#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 17981#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17801#L514-1 assume 1 == ~m_pc~0; 17802#L515-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18205#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18427#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18428#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17766#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17767#L533-1 assume 1 == ~t1_pc~0; 17977#L534-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17978#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18365#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18315#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18267#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18268#L552-1 assume !(1 == ~t2_pc~0); 17724#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 17725#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17579#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17580#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17807#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17808#L571-1 assume !(1 == ~t3_pc~0); 17506#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 17507#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17515#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17516#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17273#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17139#L590-1 assume 1 == ~t4_pc~0; 17140#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17269#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17270#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18220#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17549#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17065#L609-1 assume 1 == ~t5_pc~0; 17066#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17424#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17922#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17923#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17472#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17473#L628-1 assume !(1 == ~t6_pc~0); 18407#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 18408#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18415#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18449#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18406#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17470#L647-1 assume !(1 == ~t7_pc~0); 17278#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 17279#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17435#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17247#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17248#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18254#L666-1 assume 1 == ~t8_pc~0; 17662#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17149#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17150#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18352#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17891#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17892#L685-1 assume 1 == ~t9_pc~0; 17642#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17643#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18400#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17226#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17196#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17197#L704-1 assume 1 == ~t10_pc~0; 17840#L705-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17467#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17341#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17342#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17421#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17671#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 18162#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18317#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17961#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17780#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17781#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18130#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18360#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17908#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17895#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17896#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18109#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 18283#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 18284#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 18158#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 17935#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 17385#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 17386#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 17827#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 18030#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 18031#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 18168#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 18341#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18216#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 17177#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 17754#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 17944#L1584 assume !(0 == start_simulation_~tmp~3#1); 17834#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17657#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 17401#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18313#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 17726#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17727#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17686#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 17687#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 17508#L1565 [2024-11-17 08:52:47,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,592 INFO L85 PathProgramCache]: Analyzing trace with hash -612952292, now seen corresponding path program 1 times [2024-11-17 08:52:47,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743745439] [2024-11-17 08:52:47,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [743745439] [2024-11-17 08:52:47,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [743745439] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,620 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,620 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:47,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132547918] [2024-11-17 08:52:47,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,620 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:47,621 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,621 INFO L85 PathProgramCache]: Analyzing trace with hash 616430178, now seen corresponding path program 1 times [2024-11-17 08:52:47,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957533326] [2024-11-17 08:52:47,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,672 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,673 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957533326] [2024-11-17 08:52:47,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [957533326] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,673 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,673 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:47,673 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642345655] [2024-11-17 08:52:47,673 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,673 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:47,674 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:47,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:47,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:47,674 INFO L87 Difference]: Start difference. First operand 1414 states and 2075 transitions. cyclomatic complexity: 662 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:47,691 INFO L93 Difference]: Finished difference Result 1414 states and 2074 transitions. [2024-11-17 08:52:47,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1414 states and 2074 transitions. [2024-11-17 08:52:47,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,700 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1414 states to 1414 states and 2074 transitions. [2024-11-17 08:52:47,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:47,701 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:47,701 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2074 transitions. [2024-11-17 08:52:47,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:47,702 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2074 transitions. [2024-11-17 08:52:47,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2074 transitions. [2024-11-17 08:52:47,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:47,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.4667609618104667) internal successors, (2074), 1413 states have internal predecessors, (2074), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2074 transitions. [2024-11-17 08:52:47,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2074 transitions. [2024-11-17 08:52:47,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:47,718 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2074 transitions. [2024-11-17 08:52:47,718 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:52:47,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2074 transitions. [2024-11-17 08:52:47,722 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,722 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:47,722 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:47,723 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,723 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,723 INFO L745 eck$LassoCheckResult]: Stem: 20973#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 19945#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19946#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20886#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20887#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 20330#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20204#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20205#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19934#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19935#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20716#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20751#L766 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21224#L771 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21241#L776 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 21106#L781 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20528#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20529#L1036-1 assume !(0 == ~M_E~0); 20903#L1041-1 assume !(0 == ~T1_E~0); 20904#L1046-1 assume !(0 == ~T2_E~0); 20288#L1051-1 assume !(0 == ~T3_E~0); 20289#L1056-1 assume !(0 == ~T4_E~0); 21045#L1061-1 assume !(0 == ~T5_E~0); 20195#L1066-1 assume !(0 == ~T6_E~0); 20196#L1071-1 assume !(0 == ~T7_E~0); 21030#L1076-1 assume !(0 == ~T8_E~0); 20081#L1081-1 assume !(0 == ~T9_E~0); 20082#L1086-1 assume !(0 == ~T10_E~0); 20491#L1091-1 assume !(0 == ~E_M~0); 21228#L1096-1 assume !(0 == ~E_1~0); 21229#L1101-1 assume !(0 == ~E_2~0); 20566#L1106-1 assume !(0 == ~E_3~0); 20567#L1111-1 assume !(0 == ~E_4~0); 20721#L1116-1 assume !(0 == ~E_5~0); 20722#L1121-1 assume !(0 == ~E_6~0); 20559#L1126-1 assume !(0 == ~E_7~0); 20560#L1131-1 assume !(0 == ~E_8~0); 20824#L1136-1 assume !(0 == ~E_9~0); 20922#L1141-1 assume !(0 == ~E_10~0); 21088#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20934#L514-13 assume 1 == ~m_pc~0; 20763#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20764#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19895#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19896#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 20222#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21163#L533-13 assume 1 == ~t1_pc~0; 20068#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20069#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20572#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20326#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 20327#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20248#L552-13 assume 1 == ~t2_pc~0; 20249#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21180#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20045#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20046#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 21026#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20803#L571-13 assume 1 == ~t3_pc~0; 20804#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20884#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20660#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20661#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20784#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20858#L590-13 assume 1 == ~t4_pc~0; 20883#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20036#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21102#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20785#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 20786#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21141#L609-13 assume 1 == ~t5_pc~0; 20286#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19890#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19891#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21248#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 20695#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20005#L628-13 assume 1 == ~t6_pc~0; 20006#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20321#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20322#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20456#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 20284#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20285#L647-13 assume 1 == ~t7_pc~0; 21166#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20907#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20908#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20834#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20835#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20902#L666-13 assume 1 == ~t8_pc~0; 19921#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19922#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20715#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21254#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 19994#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19995#L685-13 assume 1 == ~t9_pc~0; 21231#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20239#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20240#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20864#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 20807#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20808#L704-13 assume 1 == ~t10_pc~0; 20990#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19920#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19940#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19941#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 20144#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20145#L1154-1 assume !(1 == ~M_E~0); 20149#L1159-1 assume !(1 == ~T1_E~0); 20270#L1164-1 assume !(1 == ~T2_E~0); 20744#L1169-1 assume !(1 == ~T3_E~0); 20621#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20407#L1179-1 assume !(1 == ~T5_E~0); 20254#L1184-1 assume !(1 == ~T6_E~0); 20255#L1189-1 assume !(1 == ~T7_E~0); 20336#L1194-1 assume !(1 == ~T8_E~0); 20469#L1199-1 assume !(1 == ~T9_E~0); 20420#L1204-1 assume !(1 == ~T10_E~0); 20421#L1209-1 assume !(1 == ~E_M~0); 20969#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20970#L1219-1 assume !(1 == ~E_2~0); 21279#L1224-1 assume !(1 == ~E_3~0); 20773#L1229-1 assume !(1 == ~E_4~0); 20136#L1234-1 assume !(1 == ~E_5~0); 20137#L1239-1 assume !(1 == ~E_6~0); 20202#L1244-1 assume !(1 == ~E_7~0); 20203#L1249-1 assume !(1 == ~E_8~0); 21036#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 20041#L1259-1 assume !(1 == ~E_10~0); 20042#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 20343#L1565 [2024-11-17 08:52:47,742 INFO L747 eck$LassoCheckResult]: Loop: 20343#L1565 assume true; 20344#L1565-1 assume !false; 21181#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20441#L861 assume true; 20850#L861-1 assume !false; 20586#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20213#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19900#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20366#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 20266#L866 assume !(0 != eval_~tmp~0#1); 20268#L869 assume true; 20991#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19929#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19930#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 20016#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20056#L1046 assume !(0 == ~T2_E~0); 20057#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20390#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20391#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21128#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21082#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21083#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21285#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21108#L1086 assume !(0 == ~T10_E~0); 21070#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 20212#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 20089#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 20090#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 21293#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 20486#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 19971#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 19972#L1126 assume !(0 == ~E_7~0); 20457#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 20828#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 20817#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 20818#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20638#L514-1 assume !(1 == ~m_pc~0); 20640#L524-1 is_master_triggered_~__retres1~0#1 := 0; 21042#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21264#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21265#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20603#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20604#L533-1 assume !(1 == ~t1_pc~0); 20816#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 20815#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21202#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21152#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21104#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21105#L552-1 assume !(1 == ~t2_pc~0); 20561#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 20562#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20416#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20417#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20645#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20646#L571-1 assume !(1 == ~t3_pc~0); 20345#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 20346#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20352#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20353#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20110#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19976#L590-1 assume 1 == ~t4_pc~0; 19977#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20106#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20107#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21057#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20388#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19902#L609-1 assume !(1 == ~t5_pc~0); 19904#L619-1 is_transmit5_triggered_~__retres1~5#1 := 0; 20261#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20761#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20762#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20309#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20310#L628-1 assume 1 == ~t6_pc~0; 21296#L629-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21245#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21252#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21286#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21243#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20307#L647-1 assume !(1 == ~t7_pc~0); 20115#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 20116#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20273#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20084#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20085#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21091#L666-1 assume 1 == ~t8_pc~0; 20499#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19986#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19987#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21191#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20729#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20730#L685-1 assume !(1 == ~t9_pc~0); 20481#L695-1 is_transmit9_triggered_~__retres1~9#1 := 0; 20480#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21237#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20063#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20033#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20034#L704-1 assume 1 == ~t10_pc~0; 20679#L705-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20304#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20185#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20186#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20260#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20508#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 20999#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21154#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20798#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20617#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20618#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20967#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21199#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20745#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20732#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 20733#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20946#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 21121#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 21122#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 20995#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 20772#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 20223#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 20224#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 20664#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 20869#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 20870#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 21007#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 21179#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21053#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20014#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20591#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 20782#L1584 assume !(0 == start_simulation_~tmp~3#1); 20671#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 20495#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20238#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21151#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 20563#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20564#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20523#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 20524#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 20343#L1565 [2024-11-17 08:52:47,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,743 INFO L85 PathProgramCache]: Analyzing trace with hash -1839198083, now seen corresponding path program 1 times [2024-11-17 08:52:47,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,744 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93449278] [2024-11-17 08:52:47,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,778 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,778 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [93449278] [2024-11-17 08:52:47,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [93449278] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:47,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127270024] [2024-11-17 08:52:47,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,783 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:47,783 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,784 INFO L85 PathProgramCache]: Analyzing trace with hash -1200739605, now seen corresponding path program 1 times [2024-11-17 08:52:47,784 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,784 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1428575113] [2024-11-17 08:52:47,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1428575113] [2024-11-17 08:52:47,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1428575113] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,848 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,848 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:47,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1548263070] [2024-11-17 08:52:47,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,848 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:47,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:47,849 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:47,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:47,849 INFO L87 Difference]: Start difference. First operand 1414 states and 2074 transitions. cyclomatic complexity: 661 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:47,871 INFO L93 Difference]: Finished difference Result 1414 states and 2073 transitions. [2024-11-17 08:52:47,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1414 states and 2073 transitions. [2024-11-17 08:52:47,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,881 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1414 states to 1414 states and 2073 transitions. [2024-11-17 08:52:47,881 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:47,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:47,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2073 transitions. [2024-11-17 08:52:47,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:47,884 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2073 transitions. [2024-11-17 08:52:47,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2073 transitions. [2024-11-17 08:52:47,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:47,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.466053748231966) internal successors, (2073), 1413 states have internal predecessors, (2073), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:47,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2073 transitions. [2024-11-17 08:52:47,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2073 transitions. [2024-11-17 08:52:47,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:47,902 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2073 transitions. [2024-11-17 08:52:47,902 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:52:47,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2073 transitions. [2024-11-17 08:52:47,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:47,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:47,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:47,908 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,908 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:47,908 INFO L745 eck$LassoCheckResult]: Stem: 23810#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 22782#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 22783#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23723#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23724#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 23167#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23041#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23042#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22771#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22772#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23553#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23588#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24061#L771 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24079#L776 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 23943#L781 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 23365#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23366#L1036-1 assume !(0 == ~M_E~0); 23740#L1041-1 assume !(0 == ~T1_E~0); 23741#L1046-1 assume !(0 == ~T2_E~0); 23125#L1051-1 assume !(0 == ~T3_E~0); 23126#L1056-1 assume !(0 == ~T4_E~0); 23882#L1061-1 assume !(0 == ~T5_E~0); 23032#L1066-1 assume !(0 == ~T6_E~0); 23033#L1071-1 assume !(0 == ~T7_E~0); 23867#L1076-1 assume !(0 == ~T8_E~0); 22918#L1081-1 assume !(0 == ~T9_E~0); 22919#L1086-1 assume !(0 == ~T10_E~0); 23328#L1091-1 assume !(0 == ~E_M~0); 24065#L1096-1 assume !(0 == ~E_1~0); 24066#L1101-1 assume !(0 == ~E_2~0); 23403#L1106-1 assume !(0 == ~E_3~0); 23404#L1111-1 assume !(0 == ~E_4~0); 23558#L1116-1 assume !(0 == ~E_5~0); 23559#L1121-1 assume !(0 == ~E_6~0); 23396#L1126-1 assume !(0 == ~E_7~0); 23397#L1131-1 assume !(0 == ~E_8~0); 23661#L1136-1 assume !(0 == ~E_9~0); 23759#L1141-1 assume !(0 == ~E_10~0); 23925#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23771#L514-13 assume 1 == ~m_pc~0; 23600#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23601#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22732#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22733#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 23061#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24000#L533-13 assume 1 == ~t1_pc~0; 22905#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22906#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23411#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23163#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 23164#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23085#L552-13 assume 1 == ~t2_pc~0; 23086#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24017#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22882#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22883#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 23863#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23640#L571-13 assume 1 == ~t3_pc~0; 23641#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23721#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23497#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23498#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23621#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23695#L590-13 assume 1 == ~t4_pc~0; 23720#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22873#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23939#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23622#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 23623#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23978#L609-13 assume 1 == ~t5_pc~0; 23123#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22727#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22728#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24085#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 23532#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22842#L628-13 assume 1 == ~t6_pc~0; 22843#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23158#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23159#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23293#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 23121#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23122#L647-13 assume 1 == ~t7_pc~0; 24003#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23744#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23745#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23671#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23672#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23739#L666-13 assume 1 == ~t8_pc~0; 22758#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22759#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23552#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24091#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 22831#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22832#L685-13 assume 1 == ~t9_pc~0; 24068#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23076#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23077#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23701#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 23644#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23645#L704-13 assume 1 == ~t10_pc~0; 23827#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22757#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22777#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22778#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 22982#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22983#L1154-1 assume !(1 == ~M_E~0); 22986#L1159-1 assume !(1 == ~T1_E~0); 23107#L1164-1 assume !(1 == ~T2_E~0); 23581#L1169-1 assume !(1 == ~T3_E~0); 23458#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23244#L1179-1 assume !(1 == ~T5_E~0); 23091#L1184-1 assume !(1 == ~T6_E~0); 23092#L1189-1 assume !(1 == ~T7_E~0); 23173#L1194-1 assume !(1 == ~T8_E~0); 23306#L1199-1 assume !(1 == ~T9_E~0); 23257#L1204-1 assume !(1 == ~T10_E~0); 23258#L1209-1 assume !(1 == ~E_M~0); 23806#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 23807#L1219-1 assume !(1 == ~E_2~0); 24116#L1224-1 assume !(1 == ~E_3~0); 23610#L1229-1 assume !(1 == ~E_4~0); 22973#L1234-1 assume !(1 == ~E_5~0); 22974#L1239-1 assume !(1 == ~E_6~0); 23039#L1244-1 assume !(1 == ~E_7~0); 23040#L1249-1 assume !(1 == ~E_8~0); 23873#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 22878#L1259-1 assume !(1 == ~E_10~0); 22879#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 23180#L1565 [2024-11-17 08:52:47,909 INFO L747 eck$LassoCheckResult]: Loop: 23180#L1565 assume true; 23181#L1565-1 assume !false; 24018#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23278#L861 assume true; 23687#L861-1 assume !false; 23423#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23050#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22737#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23203#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 23103#L866 assume !(0 != eval_~tmp~0#1); 23105#L869 assume true; 23828#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22766#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22767#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 22853#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22893#L1046 assume !(0 == ~T2_E~0); 22894#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23227#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23228#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23965#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23919#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23920#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24122#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23945#L1086 assume !(0 == ~T10_E~0); 23907#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 23049#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 22926#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 22927#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 24130#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 23323#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 22808#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 22809#L1126 assume !(0 == ~E_7~0); 23294#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 23665#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 23654#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 23655#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23475#L514-1 assume 1 == ~m_pc~0; 23476#L515-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23879#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24101#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24102#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23440#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23441#L533-1 assume 1 == ~t1_pc~0; 23651#L534-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23652#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24039#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23989#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23941#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23942#L552-1 assume !(1 == ~t2_pc~0); 23398#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 23399#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23253#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23254#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23482#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23483#L571-1 assume 1 == ~t3_pc~0; 23731#L572-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23183#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23191#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23192#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22947#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22813#L590-1 assume 1 == ~t4_pc~0; 22814#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22943#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22944#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23894#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23225#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22741#L609-1 assume 1 == ~t5_pc~0; 22742#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23098#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23598#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23599#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23146#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23147#L628-1 assume !(1 == ~t6_pc~0); 24081#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 24082#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24089#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24123#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24080#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23144#L647-1 assume !(1 == ~t7_pc~0); 22952#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 22953#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23110#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22921#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22922#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23928#L666-1 assume 1 == ~t8_pc~0; 23336#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22823#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22824#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24026#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23565#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23566#L685-1 assume 1 == ~t9_pc~0; 23314#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23315#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24074#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22900#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 22868#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22869#L704-1 assume !(1 == ~t10_pc~0); 23138#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 23139#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23015#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23016#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23095#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23345#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 23836#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23991#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23635#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23454#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23455#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23804#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24034#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23582#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23569#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23570#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 23783#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 23957#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 23958#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 23832#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 23607#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 23059#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 23060#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 23501#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 23704#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 23705#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 23841#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 24015#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23888#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 22851#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23428#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 23617#L1584 assume !(0 == start_simulation_~tmp~3#1); 23508#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 23329#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23075#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23987#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 23400#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23401#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23360#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 23361#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 23180#L1565 [2024-11-17 08:52:47,909 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1169286908, now seen corresponding path program 1 times [2024-11-17 08:52:47,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1896240716] [2024-11-17 08:52:47,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:47,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:47,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:47,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1896240716] [2024-11-17 08:52:47,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1896240716] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:47,945 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:47,945 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:47,945 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [458120749] [2024-11-17 08:52:47,945 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:47,946 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:47,946 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:47,946 INFO L85 PathProgramCache]: Analyzing trace with hash -1190576606, now seen corresponding path program 1 times [2024-11-17 08:52:47,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:47,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155988020] [2024-11-17 08:52:47,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:47,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:47,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:48,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:48,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:48,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1155988020] [2024-11-17 08:52:48,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1155988020] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:48,008 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:48,008 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:48,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [252862154] [2024-11-17 08:52:48,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:48,009 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:48,009 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:48,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:48,009 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:48,009 INFO L87 Difference]: Start difference. First operand 1414 states and 2073 transitions. cyclomatic complexity: 660 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:48,026 INFO L93 Difference]: Finished difference Result 1414 states and 2072 transitions. [2024-11-17 08:52:48,026 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1414 states and 2072 transitions. [2024-11-17 08:52:48,030 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:48,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1414 states to 1414 states and 2072 transitions. [2024-11-17 08:52:48,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:48,035 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:48,035 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2072 transitions. [2024-11-17 08:52:48,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:48,037 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2072 transitions. [2024-11-17 08:52:48,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2072 transitions. [2024-11-17 08:52:48,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:48,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.4653465346534653) internal successors, (2072), 1413 states have internal predecessors, (2072), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2072 transitions. [2024-11-17 08:52:48,051 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2072 transitions. [2024-11-17 08:52:48,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:48,052 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2072 transitions. [2024-11-17 08:52:48,052 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:52:48,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2072 transitions. [2024-11-17 08:52:48,056 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:48,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:48,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:48,057 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:48,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:48,057 INFO L745 eck$LassoCheckResult]: Stem: 26652#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 25619#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 25620#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26562#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26563#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 26006#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25878#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25879#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25608#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25609#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26392#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26425#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26898#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26916#L776 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 26780#L781 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26208#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26209#L1036-1 assume !(0 == ~M_E~0); 26577#L1041-1 assume !(0 == ~T1_E~0); 26578#L1046-1 assume !(0 == ~T2_E~0); 25964#L1051-1 assume !(0 == ~T3_E~0); 25965#L1056-1 assume !(0 == ~T4_E~0); 26721#L1061-1 assume !(0 == ~T5_E~0); 25869#L1066-1 assume !(0 == ~T6_E~0); 25870#L1071-1 assume !(0 == ~T7_E~0); 26705#L1076-1 assume !(0 == ~T8_E~0); 25755#L1081-1 assume !(0 == ~T9_E~0); 25756#L1086-1 assume !(0 == ~T10_E~0); 26165#L1091-1 assume !(0 == ~E_M~0); 26902#L1096-1 assume !(0 == ~E_1~0); 26903#L1101-1 assume !(0 == ~E_2~0); 26240#L1106-1 assume !(0 == ~E_3~0); 26241#L1111-1 assume !(0 == ~E_4~0); 26395#L1116-1 assume !(0 == ~E_5~0); 26396#L1121-1 assume !(0 == ~E_6~0); 26233#L1126-1 assume !(0 == ~E_7~0); 26234#L1131-1 assume !(0 == ~E_8~0); 26501#L1136-1 assume !(0 == ~E_9~0); 26598#L1141-1 assume !(0 == ~E_10~0); 26762#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26608#L514-13 assume 1 == ~m_pc~0; 26437#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26438#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25569#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25570#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 25898#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26838#L533-13 assume 1 == ~t1_pc~0; 25742#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25743#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26250#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26002#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 26003#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25922#L552-13 assume 1 == ~t2_pc~0; 25923#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26854#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25724#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25725#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 26700#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26477#L571-13 assume 1 == ~t3_pc~0; 26478#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26558#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26334#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26335#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26459#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26532#L590-13 assume 1 == ~t4_pc~0; 26557#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25710#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26777#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26460#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 26461#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26815#L609-13 assume 1 == ~t5_pc~0; 25960#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25567#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25568#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26922#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 26369#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25679#L628-13 assume 1 == ~t6_pc~0; 25680#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25995#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25996#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26130#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 25958#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25959#L647-13 assume 1 == ~t7_pc~0; 26840#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26581#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26582#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26508#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26509#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26576#L666-13 assume 1 == ~t8_pc~0; 25597#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25598#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26389#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26928#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 25668#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25669#L685-13 assume 1 == ~t9_pc~0; 26905#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25920#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25921#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26538#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 26481#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26482#L704-13 assume 1 == ~t10_pc~0; 26664#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25594#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25616#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25617#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 25819#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25820#L1154-1 assume !(1 == ~M_E~0); 25823#L1159-1 assume !(1 == ~T1_E~0); 25947#L1164-1 assume !(1 == ~T2_E~0); 26418#L1169-1 assume !(1 == ~T3_E~0); 26295#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26081#L1179-1 assume !(1 == ~T5_E~0); 25928#L1184-1 assume !(1 == ~T6_E~0); 25929#L1189-1 assume !(1 == ~T7_E~0); 26010#L1194-1 assume !(1 == ~T8_E~0); 26144#L1199-1 assume !(1 == ~T9_E~0); 26094#L1204-1 assume !(1 == ~T10_E~0); 26095#L1209-1 assume !(1 == ~E_M~0); 26643#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 26644#L1219-1 assume !(1 == ~E_2~0); 26953#L1224-1 assume !(1 == ~E_3~0); 26447#L1229-1 assume !(1 == ~E_4~0); 25812#L1234-1 assume !(1 == ~E_5~0); 25813#L1239-1 assume !(1 == ~E_6~0); 25876#L1244-1 assume !(1 == ~E_7~0); 25877#L1249-1 assume !(1 == ~E_8~0); 26710#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 25717#L1259-1 assume !(1 == ~E_10~0); 25718#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 26019#L1565 [2024-11-17 08:52:48,058 INFO L747 eck$LassoCheckResult]: Loop: 26019#L1565 assume true; 26020#L1565-1 assume !false; 26855#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26117#L861 assume true; 26524#L861-1 assume !false; 26261#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25887#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25574#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 26040#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25941#L866 assume !(0 != eval_~tmp~0#1); 25943#L869 assume true; 26667#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25605#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25606#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 25690#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25730#L1046 assume !(0 == ~T2_E~0); 25731#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26066#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26067#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26802#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26756#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26757#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26959#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26782#L1086 assume !(0 == ~T10_E~0); 26745#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 25886#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 25763#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 25764#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 26967#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 26158#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 25645#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 25646#L1126 assume !(0 == ~E_7~0); 26131#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 26502#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 26491#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 26492#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26312#L514-1 assume 1 == ~m_pc~0; 26313#L515-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26716#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26938#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26939#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26277#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26278#L533-1 assume 1 == ~t1_pc~0; 26488#L534-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26489#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26876#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26826#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26778#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26779#L552-1 assume !(1 == ~t2_pc~0); 26235#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 26236#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26090#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26091#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26319#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26320#L571-1 assume !(1 == ~t3_pc~0); 26017#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 26018#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26026#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26027#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25784#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25650#L590-1 assume 1 == ~t4_pc~0; 25651#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25780#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25781#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26731#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26060#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25576#L609-1 assume 1 == ~t5_pc~0; 25577#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25935#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26433#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26434#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25983#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25984#L628-1 assume !(1 == ~t6_pc~0); 26918#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 26919#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26926#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26960#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26917#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25981#L647-1 assume !(1 == ~t7_pc~0); 25789#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 25790#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25946#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25758#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25759#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26765#L666-1 assume 1 == ~t8_pc~0; 26173#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25660#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25661#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26863#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26403#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26404#L685-1 assume 1 == ~t9_pc~0; 26153#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26154#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26911#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25737#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25707#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25708#L704-1 assume !(1 == ~t10_pc~0); 25977#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 25978#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25854#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25855#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25934#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26182#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 26673#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26828#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26472#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26291#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26292#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26641#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26871#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26419#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26406#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26407#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26620#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 26794#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 26795#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 26669#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 26446#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 25896#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 25897#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 26338#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 26541#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 26542#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 26681#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 26852#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 26727#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25688#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 26265#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 26456#L1584 assume !(0 == start_simulation_~tmp~3#1); 26345#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 26169#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 25912#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 26825#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 26237#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26238#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26197#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 26198#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 26019#L1565 [2024-11-17 08:52:48,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:48,058 INFO L85 PathProgramCache]: Analyzing trace with hash -811875171, now seen corresponding path program 1 times [2024-11-17 08:52:48,058 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:48,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [75627998] [2024-11-17 08:52:48,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:48,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:48,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:48,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:48,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:48,088 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [75627998] [2024-11-17 08:52:48,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [75627998] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:48,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:48,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:48,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265114770] [2024-11-17 08:52:48,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:48,089 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:48,089 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:48,090 INFO L85 PathProgramCache]: Analyzing trace with hash 52577189, now seen corresponding path program 2 times [2024-11-17 08:52:48,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:48,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107610258] [2024-11-17 08:52:48,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:48,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:48,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:48,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:48,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:48,133 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107610258] [2024-11-17 08:52:48,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2107610258] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:48,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:48,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:48,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191750057] [2024-11-17 08:52:48,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:48,134 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:48,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:48,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:48,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:48,134 INFO L87 Difference]: Start difference. First operand 1414 states and 2072 transitions. cyclomatic complexity: 659 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:48,151 INFO L93 Difference]: Finished difference Result 1414 states and 2071 transitions. [2024-11-17 08:52:48,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1414 states and 2071 transitions. [2024-11-17 08:52:48,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:48,159 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1414 states to 1414 states and 2071 transitions. [2024-11-17 08:52:48,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:48,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:48,160 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2071 transitions. [2024-11-17 08:52:48,161 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:48,161 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2071 transitions. [2024-11-17 08:52:48,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2071 transitions. [2024-11-17 08:52:48,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:48,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.4646393210749646) internal successors, (2071), 1413 states have internal predecessors, (2071), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2071 transitions. [2024-11-17 08:52:48,176 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2071 transitions. [2024-11-17 08:52:48,176 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:48,177 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2071 transitions. [2024-11-17 08:52:48,177 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:52:48,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2071 transitions. [2024-11-17 08:52:48,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:48,180 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:48,180 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:48,181 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:48,181 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:48,181 INFO L745 eck$LassoCheckResult]: Stem: 29484#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 28456#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 28457#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29397#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29398#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 28841#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28715#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28716#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28445#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28446#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29227#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29262#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29735#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29752#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29617#L781 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29039#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29040#L1036-1 assume !(0 == ~M_E~0); 29414#L1041-1 assume !(0 == ~T1_E~0); 29415#L1046-1 assume !(0 == ~T2_E~0); 28799#L1051-1 assume !(0 == ~T3_E~0); 28800#L1056-1 assume !(0 == ~T4_E~0); 29556#L1061-1 assume !(0 == ~T5_E~0); 28706#L1066-1 assume !(0 == ~T6_E~0); 28707#L1071-1 assume !(0 == ~T7_E~0); 29541#L1076-1 assume !(0 == ~T8_E~0); 28592#L1081-1 assume !(0 == ~T9_E~0); 28593#L1086-1 assume !(0 == ~T10_E~0); 29002#L1091-1 assume !(0 == ~E_M~0); 29739#L1096-1 assume !(0 == ~E_1~0); 29740#L1101-1 assume !(0 == ~E_2~0); 29077#L1106-1 assume !(0 == ~E_3~0); 29078#L1111-1 assume !(0 == ~E_4~0); 29232#L1116-1 assume !(0 == ~E_5~0); 29233#L1121-1 assume !(0 == ~E_6~0); 29070#L1126-1 assume !(0 == ~E_7~0); 29071#L1131-1 assume !(0 == ~E_8~0); 29335#L1136-1 assume !(0 == ~E_9~0); 29433#L1141-1 assume !(0 == ~E_10~0); 29599#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29445#L514-13 assume 1 == ~m_pc~0; 29274#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29275#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28406#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 28407#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 28733#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29674#L533-13 assume 1 == ~t1_pc~0; 28579#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28580#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29083#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28837#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 28838#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28759#L552-13 assume 1 == ~t2_pc~0; 28760#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29691#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28556#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28557#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 29537#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29314#L571-13 assume 1 == ~t3_pc~0; 29315#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29395#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29171#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29172#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29295#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29369#L590-13 assume 1 == ~t4_pc~0; 29394#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28547#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29613#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29296#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 29297#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29652#L609-13 assume 1 == ~t5_pc~0; 28797#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28401#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28402#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29759#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 29206#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28516#L628-13 assume 1 == ~t6_pc~0; 28517#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28832#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28833#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28967#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 28795#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28796#L647-13 assume 1 == ~t7_pc~0; 29677#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29418#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29419#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29345#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29346#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29413#L666-13 assume 1 == ~t8_pc~0; 28432#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28433#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29226#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29765#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 28505#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28506#L685-13 assume 1 == ~t9_pc~0; 29742#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28750#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28751#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29375#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 29318#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29319#L704-13 assume 1 == ~t10_pc~0; 29501#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28431#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28451#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28452#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 28655#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28656#L1154-1 assume !(1 == ~M_E~0); 28660#L1159-1 assume !(1 == ~T1_E~0); 28781#L1164-1 assume !(1 == ~T2_E~0); 29255#L1169-1 assume !(1 == ~T3_E~0); 29132#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28918#L1179-1 assume !(1 == ~T5_E~0); 28765#L1184-1 assume !(1 == ~T6_E~0); 28766#L1189-1 assume !(1 == ~T7_E~0); 28847#L1194-1 assume !(1 == ~T8_E~0); 28980#L1199-1 assume !(1 == ~T9_E~0); 28931#L1204-1 assume !(1 == ~T10_E~0); 28932#L1209-1 assume !(1 == ~E_M~0); 29480#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 29481#L1219-1 assume !(1 == ~E_2~0); 29790#L1224-1 assume !(1 == ~E_3~0); 29284#L1229-1 assume !(1 == ~E_4~0); 28647#L1234-1 assume !(1 == ~E_5~0); 28648#L1239-1 assume !(1 == ~E_6~0); 28713#L1244-1 assume !(1 == ~E_7~0); 28714#L1249-1 assume !(1 == ~E_8~0); 29547#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 28552#L1259-1 assume !(1 == ~E_10~0); 28553#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 28854#L1565 [2024-11-17 08:52:48,181 INFO L747 eck$LassoCheckResult]: Loop: 28854#L1565 assume true; 28855#L1565-1 assume !false; 29692#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28952#L861 assume true; 29361#L861-1 assume !false; 29097#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28724#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28411#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28877#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 28777#L866 assume !(0 != eval_~tmp~0#1); 28779#L869 assume true; 29502#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28440#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28441#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 28527#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28567#L1046 assume !(0 == ~T2_E~0); 28568#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28901#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28902#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29639#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29593#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29594#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29796#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29619#L1086 assume !(0 == ~T10_E~0); 29581#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 28723#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 28600#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 28601#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 29804#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 28997#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 28482#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 28483#L1126 assume !(0 == ~E_7~0); 28968#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 29339#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 29328#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 29329#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29149#L514-1 assume 1 == ~m_pc~0; 29150#L515-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29553#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29775#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29776#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29114#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29115#L533-1 assume 1 == ~t1_pc~0; 29325#L534-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29326#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29713#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29663#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29615#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29616#L552-1 assume !(1 == ~t2_pc~0); 29072#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 29073#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28927#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28928#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29156#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29157#L571-1 assume !(1 == ~t3_pc~0); 28856#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 28857#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28863#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28864#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28621#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28487#L590-1 assume 1 == ~t4_pc~0; 28488#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28617#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28618#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29568#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28899#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28413#L609-1 assume 1 == ~t5_pc~0; 28414#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28772#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29272#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29273#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28820#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28821#L628-1 assume !(1 == ~t6_pc~0); 29755#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 29756#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29763#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29797#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29754#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28818#L647-1 assume !(1 == ~t7_pc~0); 28626#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 28627#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28784#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28595#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28596#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29602#L666-1 assume 1 == ~t8_pc~0; 29010#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28497#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28498#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29702#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29240#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29241#L685-1 assume !(1 == ~t9_pc~0); 28992#L695-1 is_transmit9_triggered_~__retres1~9#1 := 0; 28991#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29748#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28574#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28544#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28545#L704-1 assume 1 == ~t10_pc~0; 29190#L705-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28815#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28696#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28697#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28771#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29019#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 29510#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29665#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29309#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29128#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29129#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29478#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29710#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29256#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29243#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29244#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29457#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 29632#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 29633#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 29506#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 29283#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 28734#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 28735#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 29175#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 29380#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 29381#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 29518#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 29690#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29564#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28525#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29102#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 29293#L1584 assume !(0 == start_simulation_~tmp~3#1); 29182#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 29006#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28749#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 29662#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 29074#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29075#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29034#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 29035#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 28854#L1565 [2024-11-17 08:52:48,182 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:48,182 INFO L85 PathProgramCache]: Analyzing trace with hash 371142364, now seen corresponding path program 1 times [2024-11-17 08:52:48,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:48,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114738057] [2024-11-17 08:52:48,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:48,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:48,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:48,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:48,216 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:48,216 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114738057] [2024-11-17 08:52:48,216 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2114738057] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:48,216 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:48,216 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:48,216 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992041109] [2024-11-17 08:52:48,216 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:48,216 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:48,217 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:48,217 INFO L85 PathProgramCache]: Analyzing trace with hash 659096933, now seen corresponding path program 1 times [2024-11-17 08:52:48,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:48,217 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589392718] [2024-11-17 08:52:48,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:48,217 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:48,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:48,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:48,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:48,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589392718] [2024-11-17 08:52:48,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1589392718] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:48,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:48,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:48,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701756400] [2024-11-17 08:52:48,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:48,296 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:48,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:48,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:48,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:48,298 INFO L87 Difference]: Start difference. First operand 1414 states and 2071 transitions. cyclomatic complexity: 658 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:48,317 INFO L93 Difference]: Finished difference Result 1414 states and 2070 transitions. [2024-11-17 08:52:48,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1414 states and 2070 transitions. [2024-11-17 08:52:48,322 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:48,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1414 states to 1414 states and 2070 transitions. [2024-11-17 08:52:48,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1414 [2024-11-17 08:52:48,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1414 [2024-11-17 08:52:48,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1414 states and 2070 transitions. [2024-11-17 08:52:48,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:48,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2070 transitions. [2024-11-17 08:52:48,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1414 states and 2070 transitions. [2024-11-17 08:52:48,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1414 to 1414. [2024-11-17 08:52:48,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1414 states, 1414 states have (on average 1.463932107496464) internal successors, (2070), 1413 states have internal predecessors, (2070), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1414 states to 1414 states and 2070 transitions. [2024-11-17 08:52:48,343 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1414 states and 2070 transitions. [2024-11-17 08:52:48,343 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:48,343 INFO L425 stractBuchiCegarLoop]: Abstraction has 1414 states and 2070 transitions. [2024-11-17 08:52:48,343 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:52:48,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1414 states and 2070 transitions. [2024-11-17 08:52:48,346 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1275 [2024-11-17 08:52:48,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:48,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:48,347 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:48,347 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:48,348 INFO L745 eck$LassoCheckResult]: Stem: 32325#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 31293#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 31294#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32236#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32237#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 31680#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31552#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31553#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31282#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31283#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32065#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32099#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32572#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32590#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32454#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 31876#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31877#L1036-1 assume !(0 == ~M_E~0); 32251#L1041-1 assume !(0 == ~T1_E~0); 32252#L1046-1 assume !(0 == ~T2_E~0); 31636#L1051-1 assume !(0 == ~T3_E~0); 31637#L1056-1 assume !(0 == ~T4_E~0); 32395#L1061-1 assume !(0 == ~T5_E~0); 31543#L1066-1 assume !(0 == ~T6_E~0); 31544#L1071-1 assume !(0 == ~T7_E~0); 32379#L1076-1 assume !(0 == ~T8_E~0); 31429#L1081-1 assume !(0 == ~T9_E~0); 31430#L1086-1 assume !(0 == ~T10_E~0); 31839#L1091-1 assume !(0 == ~E_M~0); 32576#L1096-1 assume !(0 == ~E_1~0); 32577#L1101-1 assume !(0 == ~E_2~0); 31914#L1106-1 assume !(0 == ~E_3~0); 31915#L1111-1 assume !(0 == ~E_4~0); 32069#L1116-1 assume !(0 == ~E_5~0); 32070#L1121-1 assume !(0 == ~E_6~0); 31907#L1126-1 assume !(0 == ~E_7~0); 31908#L1131-1 assume !(0 == ~E_8~0); 32172#L1136-1 assume !(0 == ~E_9~0); 32272#L1141-1 assume !(0 == ~E_10~0); 32436#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32282#L514-13 assume 1 == ~m_pc~0; 32111#L515-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32112#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31243#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31244#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 31572#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32511#L533-13 assume 1 == ~t1_pc~0; 31416#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31417#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31924#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31674#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 31675#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31596#L552-13 assume 1 == ~t2_pc~0; 31597#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32528#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31395#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31396#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 32374#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32151#L571-13 assume 1 == ~t3_pc~0; 32152#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32232#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32008#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 32009#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32132#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32206#L590-13 assume 1 == ~t4_pc~0; 32231#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31384#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32451#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32133#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 32134#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32489#L609-13 assume 1 == ~t5_pc~0; 31634#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31238#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31239#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32596#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 32043#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31353#L628-13 assume 1 == ~t6_pc~0; 31354#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31669#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31670#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31804#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 31632#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31633#L647-13 assume 1 == ~t7_pc~0; 32514#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32255#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32256#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32182#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32183#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32250#L666-13 assume 1 == ~t8_pc~0; 31269#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31270#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32063#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32602#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 31342#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31343#L685-13 assume 1 == ~t9_pc~0; 32579#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31589#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31590#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32212#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 32155#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32156#L704-13 assume 1 == ~t10_pc~0; 32338#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31268#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31290#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31291#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 31493#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31494#L1154-1 assume !(1 == ~M_E~0); 31497#L1159-1 assume !(1 == ~T1_E~0); 31619#L1164-1 assume !(1 == ~T2_E~0); 32092#L1169-1 assume !(1 == ~T3_E~0); 31969#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31755#L1179-1 assume !(1 == ~T5_E~0); 31602#L1184-1 assume !(1 == ~T6_E~0); 31603#L1189-1 assume !(1 == ~T7_E~0); 31684#L1194-1 assume !(1 == ~T8_E~0); 31817#L1199-1 assume !(1 == ~T9_E~0); 31768#L1204-1 assume !(1 == ~T10_E~0); 31769#L1209-1 assume !(1 == ~E_M~0); 32317#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 32318#L1219-1 assume !(1 == ~E_2~0); 32627#L1224-1 assume !(1 == ~E_3~0); 32121#L1229-1 assume !(1 == ~E_4~0); 31484#L1234-1 assume !(1 == ~E_5~0); 31485#L1239-1 assume !(1 == ~E_6~0); 31550#L1244-1 assume !(1 == ~E_7~0); 31551#L1249-1 assume !(1 == ~E_8~0); 32384#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 31389#L1259-1 assume !(1 == ~E_10~0); 31390#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 31691#L1565 [2024-11-17 08:52:48,348 INFO L747 eck$LassoCheckResult]: Loop: 31691#L1565 assume true; 31692#L1565-1 assume !false; 32529#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31789#L861 assume true; 32198#L861-1 assume !false; 31935#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 31561#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 31248#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 31714#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 31615#L866 assume !(0 != eval_~tmp~0#1); 31617#L869 assume true; 32339#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31277#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31278#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 31364#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31404#L1046 assume !(0 == ~T2_E~0); 31405#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31738#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31739#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32476#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32430#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32431#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32633#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32456#L1086 assume !(0 == ~T10_E~0); 32419#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 31560#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 31437#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 31438#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 32641#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 31834#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 31319#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 31320#L1126 assume !(0 == ~E_7~0); 31807#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 32176#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 32165#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 32166#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31986#L514-1 assume 1 == ~m_pc~0; 31987#L515-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32390#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32612#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32613#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31951#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31952#L533-1 assume 1 == ~t1_pc~0; 32162#L534-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32163#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32550#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32500#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32452#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32453#L552-1 assume !(1 == ~t2_pc~0); 31909#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 31910#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31764#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31765#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31993#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31994#L571-1 assume 1 == ~t3_pc~0; 32242#L572-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31694#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31702#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31703#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31458#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31324#L590-1 assume 1 == ~t4_pc~0; 31325#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31453#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31454#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32405#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31734#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31250#L609-1 assume 1 == ~t5_pc~0; 31251#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31609#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32107#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32108#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31657#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31658#L628-1 assume !(1 == ~t6_pc~0); 32592#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 32593#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32600#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32634#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32591#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31655#L647-1 assume !(1 == ~t7_pc~0); 31461#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 31462#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31618#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31432#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31433#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32439#L666-1 assume 1 == ~t8_pc~0; 31847#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31334#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31335#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32537#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32076#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32077#L685-1 assume 1 == ~t9_pc~0; 31825#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31826#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32585#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31411#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31379#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31380#L704-1 assume !(1 == ~t10_pc~0); 31651#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 31652#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31526#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31527#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31606#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31856#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 32347#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32502#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32146#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31965#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31966#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32315#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32545#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32093#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32080#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32081#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32294#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 32468#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 32469#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 32343#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 32118#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 31570#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 31571#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 32012#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 32215#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 32216#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 32353#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 32526#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 32401#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 31362#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 31939#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 32129#L1584 assume !(0 == start_simulation_~tmp~3#1); 32019#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 31840#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 31586#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 32498#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 31911#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31912#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31871#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 31872#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 31691#L1565 [2024-11-17 08:52:48,348 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:48,349 INFO L85 PathProgramCache]: Analyzing trace with hash 1517682877, now seen corresponding path program 1 times [2024-11-17 08:52:48,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:48,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767549245] [2024-11-17 08:52:48,349 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:48,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:48,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:48,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:48,387 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:48,387 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767549245] [2024-11-17 08:52:48,387 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1767549245] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:48,387 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:48,387 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:48,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [6010711] [2024-11-17 08:52:48,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:48,387 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:48,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:48,388 INFO L85 PathProgramCache]: Analyzing trace with hash -1190576606, now seen corresponding path program 2 times [2024-11-17 08:52:48,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:48,388 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314167080] [2024-11-17 08:52:48,388 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:48,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:48,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:48,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:48,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:48,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314167080] [2024-11-17 08:52:48,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1314167080] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:48,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:48,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:48,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020136164] [2024-11-17 08:52:48,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:48,443 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:48,444 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:48,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:48,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:48,444 INFO L87 Difference]: Start difference. First operand 1414 states and 2070 transitions. cyclomatic complexity: 657 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:48,561 INFO L93 Difference]: Finished difference Result 2666 states and 3868 transitions. [2024-11-17 08:52:48,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2666 states and 3868 transitions. [2024-11-17 08:52:48,569 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2526 [2024-11-17 08:52:48,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2666 states to 2666 states and 3868 transitions. [2024-11-17 08:52:48,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2666 [2024-11-17 08:52:48,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2666 [2024-11-17 08:52:48,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2666 states and 3868 transitions. [2024-11-17 08:52:48,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:48,583 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2666 states and 3868 transitions. [2024-11-17 08:52:48,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2666 states and 3868 transitions. [2024-11-17 08:52:48,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2666 to 2590. [2024-11-17 08:52:48,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2590 states, 2590 states have (on average 1.452123552123552) internal successors, (3761), 2589 states have internal predecessors, (3761), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2590 states to 2590 states and 3761 transitions. [2024-11-17 08:52:48,615 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2590 states and 3761 transitions. [2024-11-17 08:52:48,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:48,617 INFO L425 stractBuchiCegarLoop]: Abstraction has 2590 states and 3761 transitions. [2024-11-17 08:52:48,617 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:52:48,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2590 states and 3761 transitions. [2024-11-17 08:52:48,623 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2450 [2024-11-17 08:52:48,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:48,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:48,624 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:48,624 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:48,625 INFO L745 eck$LassoCheckResult]: Stem: 36419#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 35382#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 35383#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36322#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 36323#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 35770#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35642#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35643#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35371#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35372#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36153#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 36187#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36678#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36699#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36553#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 35970#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35971#L1036-1 assume !(0 == ~M_E~0); 36341#L1041-1 assume !(0 == ~T1_E~0); 36342#L1046-1 assume !(0 == ~T2_E~0); 35728#L1051-1 assume !(0 == ~T3_E~0); 35729#L1056-1 assume !(0 == ~T4_E~0); 36492#L1061-1 assume !(0 == ~T5_E~0); 35633#L1066-1 assume !(0 == ~T6_E~0); 35634#L1071-1 assume !(0 == ~T7_E~0); 36476#L1076-1 assume !(0 == ~T8_E~0); 35518#L1081-1 assume !(0 == ~T9_E~0); 35519#L1086-1 assume !(0 == ~T10_E~0); 35928#L1091-1 assume !(0 == ~E_M~0); 36682#L1096-1 assume !(0 == ~E_1~0); 36683#L1101-1 assume !(0 == ~E_2~0); 36002#L1106-1 assume !(0 == ~E_3~0); 36003#L1111-1 assume !(0 == ~E_4~0); 36156#L1116-1 assume !(0 == ~E_5~0); 36157#L1121-1 assume !(0 == ~E_6~0); 35995#L1126-1 assume !(0 == ~E_7~0); 35996#L1131-1 assume !(0 == ~E_8~0); 36261#L1136-1 assume !(0 == ~E_9~0); 36362#L1141-1 assume !(0 == ~E_10~0); 36535#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36372#L514-13 assume !(1 == ~m_pc~0); 36373#L524-13 is_master_triggered_~__retres1~0#1 := 0; 36705#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35332#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 35333#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 35662#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36617#L533-13 assume 1 == ~t1_pc~0; 35505#L534-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35506#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36012#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 35766#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 35767#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35686#L552-13 assume 1 == ~t2_pc~0; 35687#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36636#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35487#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35488#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 36471#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36237#L571-13 assume 1 == ~t3_pc~0; 36238#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36318#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36095#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36096#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36219#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36292#L590-13 assume 1 == ~t4_pc~0; 36317#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35473#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36550#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36220#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 36221#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36594#L609-13 assume 1 == ~t5_pc~0; 35724#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35330#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35331#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36706#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 36130#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35442#L628-13 assume 1 == ~t6_pc~0; 35443#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35759#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35760#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35893#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 35722#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35723#L647-13 assume 1 == ~t7_pc~0; 36620#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36348#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36349#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36268#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36269#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36340#L666-13 assume 1 == ~t8_pc~0; 35360#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35361#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36150#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36712#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 35431#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35432#L685-13 assume 1 == ~t9_pc~0; 36685#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35684#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35685#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36300#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 36241#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36242#L704-13 assume 1 == ~t10_pc~0; 36434#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35357#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35377#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35378#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 35582#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35583#L1154-1 assume !(1 == ~M_E~0); 35587#L1159-1 assume !(1 == ~T1_E~0); 35708#L1164-1 assume !(1 == ~T2_E~0); 36180#L1169-1 assume !(1 == ~T3_E~0); 36057#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35844#L1179-1 assume !(1 == ~T5_E~0); 35692#L1184-1 assume !(1 == ~T6_E~0); 35693#L1189-1 assume !(1 == ~T7_E~0); 35774#L1194-1 assume !(1 == ~T8_E~0); 35906#L1199-1 assume !(1 == ~T9_E~0); 35857#L1204-1 assume !(1 == ~T10_E~0); 35858#L1209-1 assume !(1 == ~E_M~0); 36410#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 36411#L1219-1 assume !(1 == ~E_2~0); 36737#L1224-1 assume !(1 == ~E_3~0); 36206#L1229-1 assume !(1 == ~E_4~0); 35574#L1234-1 assume !(1 == ~E_5~0); 35575#L1239-1 assume !(1 == ~E_6~0); 35640#L1244-1 assume !(1 == ~E_7~0); 35641#L1249-1 assume !(1 == ~E_8~0); 36481#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 35478#L1259-1 assume !(1 == ~E_10~0); 35479#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 35781#L1565 [2024-11-17 08:52:48,625 INFO L747 eck$LassoCheckResult]: Loop: 35781#L1565 assume true; 35782#L1565-1 assume !false; 36635#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35878#L861 assume true; 36284#L861-1 assume !false; 36022#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35651#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35337#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35804#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35704#L866 assume !(0 != eval_~tmp~0#1); 35706#L869 assume true; 36435#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35366#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35367#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 35453#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35493#L1046 assume !(0 == ~T2_E~0); 35494#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35828#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35829#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36581#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36528#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36529#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36743#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36555#L1086 assume !(0 == ~T10_E~0); 36515#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 35650#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 35526#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 35527#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 36757#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 35923#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 35408#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 35409#L1126 assume !(0 == ~E_7~0); 35894#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 36262#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 36251#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 36252#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36074#L514-1 assume !(1 == ~m_pc~0); 36075#L524-1 is_master_triggered_~__retres1~0#1 := 0; 36487#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36722#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36723#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36039#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36040#L533-1 assume 1 == ~t1_pc~0; 36248#L534-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36249#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36656#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36605#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36551#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36552#L552-1 assume 1 == ~t2_pc~0; 36386#L553-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35998#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35853#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35854#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36080#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36081#L571-1 assume !(1 == ~t3_pc~0); 35783#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 35784#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35790#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35791#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35547#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35413#L590-1 assume 1 == ~t4_pc~0; 35414#L591-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35543#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35544#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36502#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35826#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35339#L609-1 assume 1 == ~t5_pc~0; 35340#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35699#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36197#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36198#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 35747#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35748#L628-1 assume 1 == ~t6_pc~0; 36762#L629-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36702#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36710#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36744#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36700#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35745#L647-1 assume !(1 == ~t7_pc~0); 35552#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 35553#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35711#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35521#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35522#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36538#L666-1 assume 1 == ~t8_pc~0; 35936#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35423#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35424#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36646#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 36164#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36165#L685-1 assume 1 == ~t9_pc~0; 35916#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35917#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36691#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35500#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35470#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35471#L704-1 assume 1 == ~t10_pc~0; 36114#L705-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35742#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35623#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35624#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35698#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35945#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 36444#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36607#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36232#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36053#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36054#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36407#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36653#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 36181#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36168#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36169#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36385#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 36572#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 36573#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 36439#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 36205#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 35660#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 35661#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 36099#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 36303#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 36304#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 36452#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 36634#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 36498#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35451#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 36027#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 36215#L1584 assume !(0 == start_simulation_~tmp~3#1); 36106#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35932#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35676#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 36604#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 35999#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 36000#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35959#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 35960#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 35781#L1565 [2024-11-17 08:52:48,626 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:48,626 INFO L85 PathProgramCache]: Analyzing trace with hash 2127009792, now seen corresponding path program 1 times [2024-11-17 08:52:48,626 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:48,626 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875955066] [2024-11-17 08:52:48,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:48,626 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:48,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:48,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:48,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:48,677 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1875955066] [2024-11-17 08:52:48,677 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1875955066] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:48,677 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:48,677 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:48,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499333779] [2024-11-17 08:52:48,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:48,677 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:48,677 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:48,677 INFO L85 PathProgramCache]: Analyzing trace with hash -1755267681, now seen corresponding path program 1 times [2024-11-17 08:52:48,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:48,678 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440759269] [2024-11-17 08:52:48,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:48,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:48,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:48,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:48,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:48,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440759269] [2024-11-17 08:52:48,732 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440759269] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:48,732 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:48,732 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:48,732 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226446081] [2024-11-17 08:52:48,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:48,733 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:48,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:48,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:48,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:48,734 INFO L87 Difference]: Start difference. First operand 2590 states and 3761 transitions. cyclomatic complexity: 1173 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:48,823 INFO L93 Difference]: Finished difference Result 4857 states and 7010 transitions. [2024-11-17 08:52:48,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4857 states and 7010 transitions. [2024-11-17 08:52:48,839 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4712 [2024-11-17 08:52:48,859 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4857 states to 4857 states and 7010 transitions. [2024-11-17 08:52:48,859 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4857 [2024-11-17 08:52:48,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4857 [2024-11-17 08:52:48,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4857 states and 7010 transitions. [2024-11-17 08:52:48,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:48,919 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4857 states and 7010 transitions. [2024-11-17 08:52:48,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4857 states and 7010 transitions. [2024-11-17 08:52:48,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4857 to 4849. [2024-11-17 08:52:48,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4849 states, 4849 states have (on average 1.4440090740358837) internal successors, (7002), 4848 states have internal predecessors, (7002), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:48,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4849 states to 4849 states and 7002 transitions. [2024-11-17 08:52:48,985 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4849 states and 7002 transitions. [2024-11-17 08:52:48,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:48,986 INFO L425 stractBuchiCegarLoop]: Abstraction has 4849 states and 7002 transitions. [2024-11-17 08:52:48,986 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:52:48,986 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4849 states and 7002 transitions. [2024-11-17 08:52:48,996 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4704 [2024-11-17 08:52:48,997 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:48,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:48,998 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:48,998 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:48,998 INFO L745 eck$LassoCheckResult]: Stem: 43883#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 42838#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 42839#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43783#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43784#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 43220#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43093#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43094#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42827#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42828#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43607#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43644#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44156#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44176#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44020#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 43422#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43423#L1036-1 assume !(0 == ~M_E~0); 43803#L1041-1 assume !(0 == ~T1_E~0); 43804#L1046-1 assume !(0 == ~T2_E~0); 43178#L1051-1 assume !(0 == ~T3_E~0); 43179#L1056-1 assume !(0 == ~T4_E~0); 43958#L1061-1 assume !(0 == ~T5_E~0); 43084#L1066-1 assume !(0 == ~T6_E~0); 43085#L1071-1 assume !(0 == ~T7_E~0); 43939#L1076-1 assume !(0 == ~T8_E~0); 42972#L1081-1 assume !(0 == ~T9_E~0); 42973#L1086-1 assume !(0 == ~T10_E~0); 43380#L1091-1 assume !(0 == ~E_M~0); 44160#L1096-1 assume !(0 == ~E_1~0); 44161#L1101-1 assume !(0 == ~E_2~0); 43454#L1106-1 assume !(0 == ~E_3~0); 43455#L1111-1 assume !(0 == ~E_4~0); 43610#L1116-1 assume !(0 == ~E_5~0); 43611#L1121-1 assume !(0 == ~E_6~0); 43447#L1126-1 assume !(0 == ~E_7~0); 43448#L1131-1 assume !(0 == ~E_8~0); 43719#L1136-1 assume !(0 == ~E_9~0); 43824#L1141-1 assume !(0 == ~E_10~0); 43999#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43834#L514-13 assume !(1 == ~m_pc~0); 43835#L524-13 is_master_triggered_~__retres1~0#1 := 0; 44182#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42788#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42789#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 43112#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44087#L533-13 assume !(1 == ~t1_pc~0); 44088#L543-13 is_transmit1_triggered_~__retres1~1#1 := 0; 43851#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43464#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43214#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 43215#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43136#L552-13 assume 1 == ~t2_pc~0; 43137#L553-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44107#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42941#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42942#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 43934#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43695#L571-13 assume 1 == ~t3_pc~0; 43696#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43779#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43549#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43550#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43676#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43752#L590-13 assume 1 == ~t4_pc~0; 43778#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42930#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44017#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43677#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 43678#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44061#L609-13 assume 1 == ~t5_pc~0; 43174#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42786#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42787#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44183#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 43584#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42899#L628-13 assume 1 == ~t6_pc~0; 42900#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43209#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43210#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43345#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 43172#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43173#L647-13 assume 1 == ~t7_pc~0; 44090#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43807#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43808#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43728#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43729#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43802#L666-13 assume 1 == ~t8_pc~0; 42816#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42817#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43604#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44191#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 42888#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42889#L685-13 assume 1 == ~t9_pc~0; 44163#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43134#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43135#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 43758#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 43699#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43700#L704-13 assume 1 == ~t10_pc~0; 43897#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42813#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42835#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42836#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 43036#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43037#L1154-1 assume !(1 == ~M_E~0); 43040#L1159-1 assume !(1 == ~T1_E~0); 43161#L1164-1 assume !(1 == ~T2_E~0); 43637#L1169-1 assume !(1 == ~T3_E~0); 43509#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43294#L1179-1 assume !(1 == ~T5_E~0); 43142#L1184-1 assume !(1 == ~T6_E~0); 43143#L1189-1 assume !(1 == ~T7_E~0); 43224#L1194-1 assume !(1 == ~T8_E~0); 43359#L1199-1 assume !(1 == ~T9_E~0); 43307#L1204-1 assume !(1 == ~T10_E~0); 43308#L1209-1 assume !(1 == ~E_M~0); 43875#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 43876#L1219-1 assume !(1 == ~E_2~0); 44218#L1224-1 assume !(1 == ~E_3~0); 43664#L1229-1 assume !(1 == ~E_4~0); 43029#L1234-1 assume !(1 == ~E_5~0); 43030#L1239-1 assume !(1 == ~E_6~0); 43091#L1244-1 assume !(1 == ~E_7~0); 43092#L1249-1 assume !(1 == ~E_8~0); 43944#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 42935#L1259-1 assume !(1 == ~E_10~0); 42936#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 43233#L1565 [2024-11-17 08:52:48,999 INFO L747 eck$LassoCheckResult]: Loop: 43233#L1565 assume true; 43234#L1565-1 assume !false; 44106#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43330#L861 assume true; 43744#L861-1 assume !false; 43475#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 43101#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 42793#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 43254#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43154#L866 assume !(0 != eval_~tmp~0#1); 43156#L869 assume true; 43900#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42822#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42823#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 42910#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43865#L1046 assume !(0 == ~T2_E~0); 47328#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47327#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47326#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47325#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47324#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47323#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47322#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47321#L1086 assume !(0 == ~T10_E~0); 47320#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 47319#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 47318#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 47317#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 47316#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 47315#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 47314#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 47313#L1126 assume !(0 == ~E_7~0); 47312#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 43720#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 43709#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 43710#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43528#L514-1 assume !(1 == ~m_pc~0); 43529#L524-1 is_master_triggered_~__retres1~0#1 := 0; 47522#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47521#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 47520#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47519#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47518#L533-1 assume !(1 == ~t1_pc~0); 47517#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 47516#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47515#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47514#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47513#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47512#L552-1 assume !(1 == ~t2_pc~0); 47510#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 47509#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47508#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47507#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47506#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47505#L571-1 assume 1 == ~t3_pc~0; 47504#L572-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47502#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47501#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47500#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47499#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47498#L590-1 assume !(1 == ~t4_pc~0); 47496#L600-1 is_transmit4_triggered_~__retres1~4#1 := 0; 47495#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47494#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47493#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47492#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47491#L609-1 assume !(1 == ~t5_pc~0); 47489#L619-1 is_transmit5_triggered_~__retres1~5#1 := 0; 47488#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47487#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47486#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47485#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47484#L628-1 assume !(1 == ~t6_pc~0); 47482#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 47481#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47480#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47479#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47478#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47477#L647-1 assume !(1 == ~t7_pc~0); 47475#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 47474#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47473#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47472#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47471#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47470#L666-1 assume !(1 == ~t8_pc~0); 47468#L676-1 is_transmit8_triggered_~__retres1~8#1 := 0; 47467#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47466#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47465#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47464#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47463#L685-1 assume !(1 == ~t9_pc~0); 47461#L695-1 is_transmit9_triggered_~__retres1~9#1 := 0; 47460#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47459#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47458#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47457#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47456#L704-1 assume !(1 == ~t10_pc~0); 47454#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 47453#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47452#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47451#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47450#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47449#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 47448#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47447#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47446#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47445#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47444#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47443#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47442#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47441#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47440#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47439#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 47438#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 47437#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 47311#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 47310#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 47309#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 47308#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 47307#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 44252#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 43763#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 43764#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 43912#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 44104#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 43962#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 42908#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 43479#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 43671#L1584 assume !(0 == start_simulation_~tmp~3#1); 43560#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 43382#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 43126#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 44070#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 43451#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43452#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43411#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 43412#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 43233#L1565 [2024-11-17 08:52:48,999 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:48,999 INFO L85 PathProgramCache]: Analyzing trace with hash -924803709, now seen corresponding path program 1 times [2024-11-17 08:52:48,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:49,000 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2025404719] [2024-11-17 08:52:49,000 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:49,000 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:49,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:49,039 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:49,039 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:49,039 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2025404719] [2024-11-17 08:52:49,039 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2025404719] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:49,039 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:49,039 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:49,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303222110] [2024-11-17 08:52:49,040 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:49,041 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:49,041 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:49,041 INFO L85 PathProgramCache]: Analyzing trace with hash 1273003892, now seen corresponding path program 1 times [2024-11-17 08:52:49,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:49,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537942301] [2024-11-17 08:52:49,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:49,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:49,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:49,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:49,094 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:49,094 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1537942301] [2024-11-17 08:52:49,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1537942301] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:49,094 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:49,095 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:49,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [95738631] [2024-11-17 08:52:49,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:49,095 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:49,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:49,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:49,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:49,096 INFO L87 Difference]: Start difference. First operand 4849 states and 7002 transitions. cyclomatic complexity: 2157 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:49,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:49,186 INFO L93 Difference]: Finished difference Result 9196 states and 13211 transitions. [2024-11-17 08:52:49,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9196 states and 13211 transitions. [2024-11-17 08:52:49,210 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9036 [2024-11-17 08:52:49,225 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9196 states to 9196 states and 13211 transitions. [2024-11-17 08:52:49,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9196 [2024-11-17 08:52:49,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9196 [2024-11-17 08:52:49,229 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9196 states and 13211 transitions. [2024-11-17 08:52:49,235 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:49,235 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9196 states and 13211 transitions. [2024-11-17 08:52:49,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9196 states and 13211 transitions. [2024-11-17 08:52:49,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9196 to 9180. [2024-11-17 08:52:49,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9180 states, 9180 states have (on average 1.437363834422658) internal successors, (13195), 9179 states have internal predecessors, (13195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:49,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9180 states to 9180 states and 13195 transitions. [2024-11-17 08:52:49,322 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9180 states and 13195 transitions. [2024-11-17 08:52:49,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:49,323 INFO L425 stractBuchiCegarLoop]: Abstraction has 9180 states and 13195 transitions. [2024-11-17 08:52:49,323 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:52:49,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9180 states and 13195 transitions. [2024-11-17 08:52:49,340 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9020 [2024-11-17 08:52:49,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:49,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:49,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:49,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:49,342 INFO L745 eck$LassoCheckResult]: Stem: 57939#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 56891#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 56892#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 57835#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 57836#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 57271#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57145#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57146#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56880#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56881#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57657#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 57693#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 58225#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58251#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58084#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 57473#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57474#L1036-1 assume !(0 == ~M_E~0); 57851#L1041-1 assume !(0 == ~T1_E~0); 57852#L1046-1 assume !(0 == ~T2_E~0); 57230#L1051-1 assume !(0 == ~T3_E~0); 57231#L1056-1 assume !(0 == ~T4_E~0); 58020#L1061-1 assume !(0 == ~T5_E~0); 57136#L1066-1 assume !(0 == ~T6_E~0); 57137#L1071-1 assume !(0 == ~T7_E~0); 58002#L1076-1 assume !(0 == ~T8_E~0); 57023#L1081-1 assume !(0 == ~T9_E~0); 57024#L1086-1 assume !(0 == ~T10_E~0); 57431#L1091-1 assume !(0 == ~E_M~0); 58230#L1096-1 assume !(0 == ~E_1~0); 58231#L1101-1 assume !(0 == ~E_2~0); 57505#L1106-1 assume !(0 == ~E_3~0); 57506#L1111-1 assume !(0 == ~E_4~0); 57660#L1116-1 assume !(0 == ~E_5~0); 57661#L1121-1 assume !(0 == ~E_6~0); 57498#L1126-1 assume !(0 == ~E_7~0); 57499#L1131-1 assume !(0 == ~E_8~0); 57771#L1136-1 assume !(0 == ~E_9~0); 57872#L1141-1 assume !(0 == ~E_10~0); 58066#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57885#L514-13 assume !(1 == ~m_pc~0); 57886#L524-13 is_master_triggered_~__retres1~0#1 := 0; 58260#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56842#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 56843#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 57165#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58150#L533-13 assume !(1 == ~t1_pc~0); 58151#L543-13 is_transmit1_triggered_~__retres1~1#1 := 0; 57905#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57515#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 57267#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 57268#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57189#L552-13 assume !(1 == ~t2_pc~0); 57190#L562-13 is_transmit2_triggered_~__retres1~2#1 := 0; 58171#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56995#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56996#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 57996#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57745#L571-13 assume 1 == ~t3_pc~0; 57746#L572-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57831#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57598#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57599#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57727#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57802#L590-13 assume 1 == ~t4_pc~0; 57830#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 56981#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58081#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57728#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 57729#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58127#L609-13 assume 1 == ~t5_pc~0; 57226#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56840#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56841#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 58261#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 57634#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56950#L628-13 assume 1 == ~t6_pc~0; 56951#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57261#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57262#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57396#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 57224#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57225#L647-13 assume 1 == ~t7_pc~0; 58153#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57858#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57859#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 57778#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57779#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57850#L666-13 assume 1 == ~t8_pc~0; 56869#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56870#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57654#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 58267#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 56939#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56940#L685-13 assume 1 == ~t9_pc~0; 58233#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 57187#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57188#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57812#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 57749#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57750#L704-13 assume 1 == ~t10_pc~0; 57952#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56866#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56889#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56890#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 57087#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57088#L1154-1 assume !(1 == ~M_E~0); 57091#L1159-1 assume !(1 == ~T1_E~0); 57213#L1164-1 assume !(1 == ~T2_E~0); 57686#L1169-1 assume !(1 == ~T3_E~0); 57561#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57347#L1179-1 assume !(1 == ~T5_E~0); 57194#L1184-1 assume !(1 == ~T6_E~0); 57195#L1189-1 assume !(1 == ~T7_E~0); 57276#L1194-1 assume !(1 == ~T8_E~0); 57410#L1199-1 assume !(1 == ~T9_E~0); 57360#L1204-1 assume !(1 == ~T10_E~0); 57361#L1209-1 assume !(1 == ~E_M~0); 57930#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 57931#L1219-1 assume !(1 == ~E_2~0); 58306#L1224-1 assume !(1 == ~E_3~0); 57712#L1229-1 assume !(1 == ~E_4~0); 57080#L1234-1 assume !(1 == ~E_5~0); 57081#L1239-1 assume !(1 == ~E_6~0); 57143#L1244-1 assume !(1 == ~E_7~0); 57144#L1249-1 assume !(1 == ~E_8~0); 58008#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 56988#L1259-1 assume !(1 == ~E_10~0); 56989#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 57927#L1565 [2024-11-17 08:52:49,342 INFO L747 eck$LassoCheckResult]: Loop: 57927#L1565 assume true; 64196#L1565-1 assume !false; 64012#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64010#L861 assume true; 64008#L861-1 assume !false; 64005#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 63770#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 63769#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 63768#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 63711#L866 assume !(0 != eval_~tmp~0#1); 63712#L869 assume true; 64502#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64500#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 64498#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 64496#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64493#L1046 assume !(0 == ~T2_E~0); 64491#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 64489#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64487#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 64485#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64483#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64480#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64478#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64476#L1086 assume !(0 == ~T10_E~0); 64474#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 64472#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 64470#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 64467#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 64465#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 64463#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 64461#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 64459#L1126 assume !(0 == ~E_7~0); 64457#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 64454#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 64452#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 64450#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64448#L514-1 assume !(1 == ~m_pc~0); 64446#L524-1 is_master_triggered_~__retres1~0#1 := 0; 64444#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64441#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 64439#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 64437#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64435#L533-1 assume !(1 == ~t1_pc~0); 64433#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 64431#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64428#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 64426#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64424#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64422#L552-1 assume !(1 == ~t2_pc~0); 64420#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 64418#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64416#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64414#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64412#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64410#L571-1 assume !(1 == ~t3_pc~0); 64407#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 64405#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64403#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64401#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64399#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64397#L590-1 assume !(1 == ~t4_pc~0); 64394#L600-1 is_transmit4_triggered_~__retres1~4#1 := 0; 64392#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64390#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64388#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64386#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64384#L609-1 assume !(1 == ~t5_pc~0); 64381#L619-1 is_transmit5_triggered_~__retres1~5#1 := 0; 64379#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64377#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64375#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64373#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64372#L628-1 assume !(1 == ~t6_pc~0); 64370#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 64369#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64368#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64367#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64366#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64365#L647-1 assume !(1 == ~t7_pc~0); 64363#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 64362#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64361#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64360#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64359#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64358#L666-1 assume !(1 == ~t8_pc~0); 64355#L676-1 is_transmit8_triggered_~__retres1~8#1 := 0; 64353#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64351#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64349#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 64347#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64345#L685-1 assume !(1 == ~t9_pc~0); 64342#L695-1 is_transmit9_triggered_~__retres1~9#1 := 0; 64340#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64338#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64336#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 64334#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64332#L704-1 assume !(1 == ~t10_pc~0); 64329#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 64327#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 64325#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64323#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 64321#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64319#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 64317#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64315#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64313#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64310#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64308#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64306#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64304#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64302#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64300#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64297#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 64295#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 64293#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 64291#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 64289#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 64287#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 64284#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 64282#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 64280#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 64278#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 64276#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 64274#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 64271#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 64250#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 64245#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 64243#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 64240#L1584 assume !(0 == start_simulation_~tmp~3#1); 64237#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 64216#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 64211#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 64209#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 64206#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64204#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64202#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 64200#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 57927#L1565 [2024-11-17 08:52:49,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:49,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1166065990, now seen corresponding path program 1 times [2024-11-17 08:52:49,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:49,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673802563] [2024-11-17 08:52:49,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:49,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:49,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:49,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:49,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:49,431 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673802563] [2024-11-17 08:52:49,431 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673802563] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:49,431 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:49,431 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:49,431 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2098481325] [2024-11-17 08:52:49,431 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:49,431 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:49,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:49,432 INFO L85 PathProgramCache]: Analyzing trace with hash -1778809609, now seen corresponding path program 1 times [2024-11-17 08:52:49,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:49,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565718378] [2024-11-17 08:52:49,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:49,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:49,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:49,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:49,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:49,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565718378] [2024-11-17 08:52:49,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565718378] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:49,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:49,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:49,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [544050941] [2024-11-17 08:52:49,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:49,475 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:49,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:49,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:49,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:49,475 INFO L87 Difference]: Start difference. First operand 9180 states and 13195 transitions. cyclomatic complexity: 4023 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:49,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:49,585 INFO L93 Difference]: Finished difference Result 17503 states and 25044 transitions. [2024-11-17 08:52:49,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17503 states and 25044 transitions. [2024-11-17 08:52:49,641 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17304 [2024-11-17 08:52:49,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17503 states to 17503 states and 25044 transitions. [2024-11-17 08:52:49,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17503 [2024-11-17 08:52:49,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17503 [2024-11-17 08:52:49,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17503 states and 25044 transitions. [2024-11-17 08:52:49,704 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:49,705 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17503 states and 25044 transitions. [2024-11-17 08:52:49,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17503 states and 25044 transitions. [2024-11-17 08:52:50,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17503 to 17471. [2024-11-17 08:52:50,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17471 states, 17471 states have (on average 1.4316295575525155) internal successors, (25012), 17470 states have internal predecessors, (25012), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:50,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17471 states to 17471 states and 25012 transitions. [2024-11-17 08:52:50,086 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17471 states and 25012 transitions. [2024-11-17 08:52:50,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:50,087 INFO L425 stractBuchiCegarLoop]: Abstraction has 17471 states and 25012 transitions. [2024-11-17 08:52:50,087 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:52:50,087 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17471 states and 25012 transitions. [2024-11-17 08:52:50,129 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17272 [2024-11-17 08:52:50,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:50,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:50,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:50,132 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:50,132 INFO L745 eck$LassoCheckResult]: Stem: 84627#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 83583#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 83584#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84530#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84531#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 83961#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83836#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83837#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83572#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83573#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84350#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 84389#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 84916#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84937#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 84777#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 84156#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84157#L1036-1 assume !(0 == ~M_E~0); 84546#L1041-1 assume !(0 == ~T1_E~0); 84547#L1046-1 assume !(0 == ~T2_E~0); 83917#L1051-1 assume !(0 == ~T3_E~0); 83918#L1056-1 assume !(0 == ~T4_E~0); 84709#L1061-1 assume !(0 == ~T5_E~0); 83827#L1066-1 assume !(0 == ~T6_E~0); 83828#L1071-1 assume !(0 == ~T7_E~0); 84690#L1076-1 assume !(0 == ~T8_E~0); 83716#L1081-1 assume !(0 == ~T9_E~0); 83717#L1086-1 assume !(0 == ~T10_E~0); 84120#L1091-1 assume !(0 == ~E_M~0); 84920#L1096-1 assume !(0 == ~E_1~0); 84921#L1101-1 assume !(0 == ~E_2~0); 84194#L1106-1 assume !(0 == ~E_3~0); 84195#L1111-1 assume !(0 == ~E_4~0); 84355#L1116-1 assume !(0 == ~E_5~0); 84356#L1121-1 assume !(0 == ~E_6~0); 84187#L1126-1 assume !(0 == ~E_7~0); 84188#L1131-1 assume !(0 == ~E_8~0); 84464#L1136-1 assume !(0 == ~E_9~0); 84565#L1141-1 assume !(0 == ~E_10~0); 84753#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84578#L514-13 assume !(1 == ~m_pc~0); 84579#L524-13 is_master_triggered_~__retres1~0#1 := 0; 84943#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83534#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 83535#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 83853#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84844#L533-13 assume !(1 == ~t1_pc~0); 84845#L543-13 is_transmit1_triggered_~__retres1~1#1 := 0; 84597#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84200#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 83957#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 83958#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83878#L552-13 assume !(1 == ~t2_pc~0); 83879#L562-13 is_transmit2_triggered_~__retres1~2#1 := 0; 84864#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83683#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83684#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 84686#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84444#L571-13 assume !(1 == ~t3_pc~0); 84445#L581-13 is_transmit3_triggered_~__retres1~3#1 := 0; 84528#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84291#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84292#L1309-13 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 84424#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84500#L590-13 assume 1 == ~t4_pc~0; 84527#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 83674#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84773#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84425#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 84426#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84817#L609-13 assume 1 == ~t5_pc~0; 83915#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83529#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83530#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84946#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 84326#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83644#L628-13 assume 1 == ~t6_pc~0; 83645#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 83950#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83951#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 84085#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 83913#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83914#L647-13 assume 1 == ~t7_pc~0; 84848#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84550#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84551#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84476#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 84477#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84545#L666-13 assume 1 == ~t8_pc~0; 83559#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 83560#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 84349#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84952#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 83633#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83634#L685-13 assume 1 == ~t9_pc~0; 84923#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 83869#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83870#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84507#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 84448#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 84449#L704-13 assume 1 == ~t10_pc~0; 84647#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 83558#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 83578#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 83579#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 83778#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83779#L1154-1 assume !(1 == ~M_E~0); 83783#L1159-1 assume !(1 == ~T1_E~0); 83899#L1164-1 assume !(1 == ~T2_E~0); 84382#L1169-1 assume !(1 == ~T3_E~0); 84251#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84037#L1179-1 assume !(1 == ~T5_E~0); 83883#L1184-1 assume !(1 == ~T6_E~0); 83884#L1189-1 assume !(1 == ~T7_E~0); 83967#L1194-1 assume !(1 == ~T8_E~0); 84098#L1199-1 assume !(1 == ~T9_E~0); 84050#L1204-1 assume !(1 == ~T10_E~0); 84051#L1209-1 assume !(1 == ~E_M~0); 84623#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 84624#L1219-1 assume !(1 == ~E_2~0); 84979#L1224-1 assume !(1 == ~E_3~0); 84410#L1229-1 assume !(1 == ~E_4~0); 83770#L1234-1 assume !(1 == ~E_5~0); 83771#L1239-1 assume !(1 == ~E_6~0); 83834#L1244-1 assume !(1 == ~E_7~0); 83835#L1249-1 assume !(1 == ~E_8~0); 84697#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 83679#L1259-1 assume !(1 == ~E_10~0); 83680#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 84620#L1565 [2024-11-17 08:52:50,132 INFO L747 eck$LassoCheckResult]: Loop: 84620#L1565 assume true; 96277#L1565-1 assume !false; 95691#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95689#L861 assume true; 95687#L861-1 assume !false; 95685#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 95659#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 95657#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 95654#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 95651#L866 assume !(0 != eval_~tmp~0#1); 95652#L869 assume true; 96577#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 96576#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 96575#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 96574#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 96573#L1046 assume !(0 == ~T2_E~0); 96572#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 96571#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 96570#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96568#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 96566#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 96564#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 96562#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 96560#L1086 assume !(0 == ~T10_E~0); 96558#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 96556#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 96554#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 96552#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 96550#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 96548#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 96546#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 96544#L1126 assume !(0 == ~E_7~0); 96542#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 96540#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 96538#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 96536#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96534#L514-1 assume !(1 == ~m_pc~0); 96532#L524-1 is_master_triggered_~__retres1~0#1 := 0; 96530#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96528#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 96526#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 96524#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96522#L533-1 assume !(1 == ~t1_pc~0); 96520#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 96519#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96516#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96514#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 96512#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96510#L552-1 assume !(1 == ~t2_pc~0); 96508#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 96506#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96503#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96501#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 96499#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96497#L571-1 assume !(1 == ~t3_pc~0); 96495#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 96493#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96490#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96488#L1309-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 96486#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96484#L590-1 assume !(1 == ~t4_pc~0); 96481#L600-1 is_transmit4_triggered_~__retres1~4#1 := 0; 96479#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96476#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96474#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 96472#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96470#L609-1 assume !(1 == ~t5_pc~0); 96467#L619-1 is_transmit5_triggered_~__retres1~5#1 := 0; 96465#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96462#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 96460#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 96458#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96456#L628-1 assume !(1 == ~t6_pc~0); 96453#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 96451#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96448#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96446#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96444#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96442#L647-1 assume !(1 == ~t7_pc~0); 96439#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 96437#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96434#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 96432#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 96430#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96428#L666-1 assume !(1 == ~t8_pc~0); 96425#L676-1 is_transmit8_triggered_~__retres1~8#1 := 0; 96423#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96421#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96419#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 96417#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 96415#L685-1 assume 1 == ~t9_pc~0; 96413#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 96410#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96408#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 96406#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 96404#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 96402#L704-1 assume 1 == ~t10_pc~0; 96400#L705-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 96397#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 96395#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 96393#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 96391#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96389#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 96387#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 96385#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 96383#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96381#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96379#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 96378#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 96377#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 96376#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 96375#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 96373#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 96371#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 96369#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 96367#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 96365#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 96363#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 96361#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 96359#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 96357#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 96355#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 96353#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 96351#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 96349#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 96330#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 96326#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 96324#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 96320#L1584 assume !(0 == start_simulation_~tmp~3#1); 96317#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 96296#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 96291#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 96289#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 96287#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 96285#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 96283#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 96280#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 84620#L1565 [2024-11-17 08:52:50,133 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:50,133 INFO L85 PathProgramCache]: Analyzing trace with hash -1226067127, now seen corresponding path program 1 times [2024-11-17 08:52:50,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:50,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841376175] [2024-11-17 08:52:50,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:50,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:50,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:50,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:50,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:50,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841376175] [2024-11-17 08:52:50,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [841376175] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:50,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:50,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:50,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1503341200] [2024-11-17 08:52:50,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:50,197 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:50,198 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:50,198 INFO L85 PathProgramCache]: Analyzing trace with hash -1257623375, now seen corresponding path program 1 times [2024-11-17 08:52:50,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:50,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470447301] [2024-11-17 08:52:50,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:50,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:50,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:50,254 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:50,255 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:50,255 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470447301] [2024-11-17 08:52:50,255 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [470447301] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:50,255 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:50,255 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:50,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [187782878] [2024-11-17 08:52:50,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:50,256 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:50,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:50,256 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:52:50,256 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:52:50,257 INFO L87 Difference]: Start difference. First operand 17471 states and 25012 transitions. cyclomatic complexity: 7557 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:50,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:50,612 INFO L93 Difference]: Finished difference Result 17747 states and 25203 transitions. [2024-11-17 08:52:50,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17747 states and 25203 transitions. [2024-11-17 08:52:50,660 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17548 [2024-11-17 08:52:50,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17747 states to 17747 states and 25203 transitions. [2024-11-17 08:52:50,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17747 [2024-11-17 08:52:50,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17747 [2024-11-17 08:52:50,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17747 states and 25203 transitions. [2024-11-17 08:52:50,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:50,719 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17747 states and 25203 transitions. [2024-11-17 08:52:50,729 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17747 states and 25203 transitions. [2024-11-17 08:52:50,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17747 to 17747. [2024-11-17 08:52:50,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17747 states, 17747 states have (on average 1.4201273454668395) internal successors, (25203), 17746 states have internal predecessors, (25203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:50,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17747 states to 17747 states and 25203 transitions. [2024-11-17 08:52:50,933 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17747 states and 25203 transitions. [2024-11-17 08:52:50,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:52:50,935 INFO L425 stractBuchiCegarLoop]: Abstraction has 17747 states and 25203 transitions. [2024-11-17 08:52:50,935 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:52:50,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17747 states and 25203 transitions. [2024-11-17 08:52:50,979 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17548 [2024-11-17 08:52:50,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:50,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:50,981 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:50,981 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:50,981 INFO L745 eck$LassoCheckResult]: Stem: 119863#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 118812#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 118813#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 119761#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 119762#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 119189#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119065#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119066#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118801#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118802#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 119585#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 119622#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 120152#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 120170#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 120011#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 119389#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119390#L1036-1 assume !(0 == ~M_E~0); 119778#L1041-1 assume !(0 == ~T1_E~0); 119779#L1046-1 assume !(0 == ~T2_E~0); 119147#L1051-1 assume !(0 == ~T3_E~0); 119148#L1056-1 assume !(0 == ~T4_E~0); 119946#L1061-1 assume !(0 == ~T5_E~0); 119056#L1066-1 assume !(0 == ~T6_E~0); 119057#L1071-1 assume !(0 == ~T7_E~0); 119929#L1076-1 assume !(0 == ~T8_E~0); 118944#L1081-1 assume !(0 == ~T9_E~0); 118945#L1086-1 assume !(0 == ~T10_E~0); 119352#L1091-1 assume !(0 == ~E_M~0); 120156#L1096-1 assume !(0 == ~E_1~0); 120157#L1101-1 assume !(0 == ~E_2~0); 119428#L1106-1 assume !(0 == ~E_3~0); 119429#L1111-1 assume !(0 == ~E_4~0); 119590#L1116-1 assume !(0 == ~E_5~0); 119591#L1121-1 assume !(0 == ~E_6~0); 119421#L1126-1 assume !(0 == ~E_7~0); 119422#L1131-1 assume !(0 == ~E_8~0); 119696#L1136-1 assume !(0 == ~E_9~0); 119797#L1141-1 assume !(0 == ~E_10~0); 119990#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119812#L514-13 assume !(1 == ~m_pc~0); 119813#L524-13 is_master_triggered_~__retres1~0#1 := 0; 120177#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118763#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 118764#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 119083#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 120077#L533-13 assume !(1 == ~t1_pc~0); 120078#L543-13 is_transmit1_triggered_~__retres1~1#1 := 0; 119832#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119434#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 119185#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 119186#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119108#L552-13 assume !(1 == ~t2_pc~0); 119109#L562-13 is_transmit2_triggered_~__retres1~2#1 := 0; 120101#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118912#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 118913#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 119923#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119676#L571-13 assume !(1 == ~t3_pc~0); 119677#L581-13 is_transmit3_triggered_~__retres1~3#1 := 0; 119759#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119525#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 119526#L1309-13 assume !(0 != activate_threads_~tmp___2~0#1); 119657#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119732#L590-13 assume 1 == ~t4_pc~0; 119758#L591-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 118903#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 120007#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 119658#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 119659#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 120050#L609-13 assume 1 == ~t5_pc~0; 119145#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 118758#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118759#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 120180#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 119561#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 118871#L628-13 assume 1 == ~t6_pc~0; 118872#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 119180#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119181#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 119317#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 119143#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119144#L647-13 assume 1 == ~t7_pc~0; 120081#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 119782#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 119783#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 119706#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 119707#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 119777#L666-13 assume 1 == ~t8_pc~0; 118788#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 118789#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 119584#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 120187#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 118860#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 118861#L685-13 assume 1 == ~t9_pc~0; 120159#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 119099#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 119100#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 119739#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 119679#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 119680#L704-13 assume 1 == ~t10_pc~0; 119883#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 118787#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 118807#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 118808#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 119006#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119007#L1154-1 assume !(1 == ~M_E~0); 119011#L1159-1 assume !(1 == ~T1_E~0); 119129#L1164-1 assume !(1 == ~T2_E~0); 119615#L1169-1 assume !(1 == ~T3_E~0); 119485#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119266#L1179-1 assume !(1 == ~T5_E~0); 119113#L1184-1 assume !(1 == ~T6_E~0); 119114#L1189-1 assume !(1 == ~T7_E~0); 119195#L1194-1 assume !(1 == ~T8_E~0); 119330#L1199-1 assume !(1 == ~T9_E~0); 119280#L1204-1 assume !(1 == ~T10_E~0); 119281#L1209-1 assume !(1 == ~E_M~0); 119859#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 119860#L1219-1 assume !(1 == ~E_2~0); 120219#L1224-1 assume !(1 == ~E_3~0); 119643#L1229-1 assume !(1 == ~E_4~0); 118998#L1234-1 assume !(1 == ~E_5~0); 118999#L1239-1 assume !(1 == ~E_6~0); 119063#L1244-1 assume !(1 == ~E_7~0); 119064#L1249-1 assume !(1 == ~E_8~0); 119935#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 118908#L1259-1 assume !(1 == ~E_10~0); 118909#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 119856#L1565 [2024-11-17 08:52:50,981 INFO L747 eck$LassoCheckResult]: Loop: 119856#L1565 assume true; 130812#L1565-1 assume !false; 129403#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 129401#L861 assume true; 129398#L861-1 assume !false; 129394#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 129383#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 129382#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 129381#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 129379#L866 assume !(0 != eval_~tmp~0#1); 129380#L869 assume true; 131116#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 131114#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 131112#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 131110#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 131108#L1046 assume !(0 == ~T2_E~0); 131106#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 131103#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 131101#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 131099#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 131097#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 131095#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 131093#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 131090#L1086 assume !(0 == ~T10_E~0); 131088#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 131086#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 131084#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 131082#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 131080#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 131077#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 131075#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 131073#L1126 assume !(0 == ~E_7~0); 131071#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 131069#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 131067#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 131064#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 131062#L514-1 assume !(1 == ~m_pc~0); 131060#L524-1 is_master_triggered_~__retres1~0#1 := 0; 131058#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131056#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 131054#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 131051#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 131049#L533-1 assume !(1 == ~t1_pc~0); 131047#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 131045#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 131043#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 131041#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 131038#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 131036#L552-1 assume !(1 == ~t2_pc~0); 131034#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 131032#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 131030#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 131028#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 131026#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 131024#L571-1 assume !(1 == ~t3_pc~0); 131022#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 131020#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 131018#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 131016#L1309-1 assume !(0 != activate_threads_~tmp___2~0#1); 131014#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 131012#L590-1 assume !(1 == ~t4_pc~0); 131009#L600-1 is_transmit4_triggered_~__retres1~4#1 := 0; 131007#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 131005#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 131003#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 131001#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 130999#L609-1 assume 1 == ~t5_pc~0; 130997#L610-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 130994#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 130992#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 130990#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 130988#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 130986#L628-1 assume !(1 == ~t6_pc~0); 130983#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 130982#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 130981#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 130980#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 130979#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 130978#L647-1 assume 1 == ~t7_pc~0; 130977#L648-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 130975#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 130974#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 130973#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 130972#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 130971#L666-1 assume 1 == ~t8_pc~0; 130969#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 130966#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 130964#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 130962#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 130960#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 130958#L685-1 assume !(1 == ~t9_pc~0); 130955#L695-1 is_transmit9_triggered_~__retres1~9#1 := 0; 130953#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 130951#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 130949#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 130947#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 130945#L704-1 assume 1 == ~t10_pc~0; 130943#L705-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 130940#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 130938#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 130936#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 130934#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130932#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 130930#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 130928#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 130926#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 130924#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 130922#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 130920#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 130918#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 130916#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 130914#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 130911#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 130909#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 130907#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 130905#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 130903#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 130901#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 130898#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 130896#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 130894#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 130892#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 130890#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 130888#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 130885#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 130864#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 130859#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 130857#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 130854#L1584 assume !(0 == start_simulation_~tmp~3#1); 130851#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 130830#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 130825#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 130823#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 130820#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 130818#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 130816#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 130814#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 119856#L1565 [2024-11-17 08:52:50,982 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:50,982 INFO L85 PathProgramCache]: Analyzing trace with hash -1834143990, now seen corresponding path program 1 times [2024-11-17 08:52:50,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:50,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682402059] [2024-11-17 08:52:50,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:50,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:51,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:51,138 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:51,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:51,138 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682402059] [2024-11-17 08:52:51,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1682402059] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:51,138 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:51,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:51,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1866910818] [2024-11-17 08:52:51,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:51,138 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:51,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:51,139 INFO L85 PathProgramCache]: Analyzing trace with hash 619581612, now seen corresponding path program 1 times [2024-11-17 08:52:51,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:51,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1031464707] [2024-11-17 08:52:51,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:51,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:51,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:51,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:51,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:51,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1031464707] [2024-11-17 08:52:51,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1031464707] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:51,186 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:51,187 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:51,187 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1659623359] [2024-11-17 08:52:51,187 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:51,187 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:51,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:51,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:51,188 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:51,188 INFO L87 Difference]: Start difference. First operand 17747 states and 25203 transitions. cyclomatic complexity: 7472 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:51,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:51,334 INFO L93 Difference]: Finished difference Result 33894 states and 47928 transitions. [2024-11-17 08:52:51,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33894 states and 47928 transitions. [2024-11-17 08:52:51,447 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 33616 [2024-11-17 08:52:51,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33894 states to 33894 states and 47928 transitions. [2024-11-17 08:52:51,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33894 [2024-11-17 08:52:51,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33894 [2024-11-17 08:52:51,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33894 states and 47928 transitions. [2024-11-17 08:52:51,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:51,767 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33894 states and 47928 transitions. [2024-11-17 08:52:51,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33894 states and 47928 transitions. [2024-11-17 08:52:52,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33894 to 33830. [2024-11-17 08:52:52,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33830 states, 33830 states have (on average 1.4148389003842743) internal successors, (47864), 33829 states have internal predecessors, (47864), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:52,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33830 states to 33830 states and 47864 transitions. [2024-11-17 08:52:52,278 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33830 states and 47864 transitions. [2024-11-17 08:52:52,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:52,279 INFO L425 stractBuchiCegarLoop]: Abstraction has 33830 states and 47864 transitions. [2024-11-17 08:52:52,279 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:52:52,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33830 states and 47864 transitions. [2024-11-17 08:52:52,386 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 33552 [2024-11-17 08:52:52,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:52,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:52,388 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:52,389 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:52,389 INFO L745 eck$LassoCheckResult]: Stem: 171522#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 170462#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 170463#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 171419#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 171420#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 170841#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 170714#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 170715#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 170451#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 170452#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 171236#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 171276#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 171828#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 171851#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 171676#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 171043#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 171044#L1036-1 assume !(0 == ~M_E~0); 171436#L1041-1 assume !(0 == ~T1_E~0); 171437#L1046-1 assume !(0 == ~T2_E~0); 170797#L1051-1 assume !(0 == ~T3_E~0); 170798#L1056-1 assume !(0 == ~T4_E~0); 171607#L1061-1 assume !(0 == ~T5_E~0); 170705#L1066-1 assume !(0 == ~T6_E~0); 170706#L1071-1 assume !(0 == ~T7_E~0); 171589#L1076-1 assume !(0 == ~T8_E~0); 170593#L1081-1 assume !(0 == ~T9_E~0); 170594#L1086-1 assume !(0 == ~T10_E~0); 171001#L1091-1 assume !(0 == ~E_M~0); 171833#L1096-1 assume !(0 == ~E_1~0); 171834#L1101-1 assume !(0 == ~E_2~0); 171080#L1106-1 assume !(0 == ~E_3~0); 171081#L1111-1 assume !(0 == ~E_4~0); 171243#L1116-1 assume !(0 == ~E_5~0); 171244#L1121-1 assume !(0 == ~E_6~0); 171073#L1126-1 assume !(0 == ~E_7~0); 171074#L1131-1 assume !(0 == ~E_8~0); 171353#L1136-1 assume !(0 == ~E_9~0); 171456#L1141-1 assume !(0 == ~E_10~0); 171651#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 171474#L514-13 assume !(1 == ~m_pc~0); 171475#L524-13 is_master_triggered_~__retres1~0#1 := 0; 171858#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170413#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 170414#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 170731#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 171750#L533-13 assume !(1 == ~t1_pc~0); 171751#L543-13 is_transmit1_triggered_~__retres1~1#1 := 0; 171491#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 171086#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 170837#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 170838#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170756#L552-13 assume !(1 == ~t2_pc~0); 170757#L562-13 is_transmit2_triggered_~__retres1~2#1 := 0; 171774#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 170560#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 170561#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 171584#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171332#L571-13 assume !(1 == ~t3_pc~0); 171333#L581-13 is_transmit3_triggered_~__retres1~3#1 := 0; 171417#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171177#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 171178#L1309-13 assume !(0 != activate_threads_~tmp___2~0#1); 171312#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171391#L590-13 assume !(1 == ~t4_pc~0); 170550#L600-13 is_transmit4_triggered_~__retres1~4#1 := 0; 170551#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 171672#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171313#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 171314#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 171722#L609-13 assume 1 == ~t5_pc~0; 170795#L610-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 170408#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 170409#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 171861#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 171212#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 170521#L628-13 assume 1 == ~t6_pc~0; 170522#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 170830#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 170831#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 170965#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 170793#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 170794#L647-13 assume 1 == ~t7_pc~0; 171755#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 171440#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 171441#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 171365#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 171366#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 171435#L666-13 assume 1 == ~t8_pc~0; 170438#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 170439#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 171235#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 171870#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 170511#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 170512#L685-13 assume 1 == ~t9_pc~0; 171836#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 170747#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 170748#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 171397#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 171337#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 171338#L704-13 assume 1 == ~t10_pc~0; 171541#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 170437#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 170457#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 170458#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 170655#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 170656#L1154-1 assume !(1 == ~M_E~0); 170660#L1159-1 assume !(1 == ~T1_E~0); 170778#L1164-1 assume !(1 == ~T2_E~0); 171269#L1169-1 assume !(1 == ~T3_E~0); 171137#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 170915#L1179-1 assume !(1 == ~T5_E~0); 170761#L1184-1 assume !(1 == ~T6_E~0); 170762#L1189-1 assume !(1 == ~T7_E~0); 170847#L1194-1 assume !(1 == ~T8_E~0); 170978#L1199-1 assume !(1 == ~T9_E~0); 170928#L1204-1 assume !(1 == ~T10_E~0); 170929#L1209-1 assume !(1 == ~E_M~0); 171518#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 171519#L1219-1 assume !(1 == ~E_2~0); 171904#L1224-1 assume !(1 == ~E_3~0); 171296#L1229-1 assume !(1 == ~E_4~0); 170647#L1234-1 assume !(1 == ~E_5~0); 170648#L1239-1 assume !(1 == ~E_6~0); 170712#L1244-1 assume !(1 == ~E_7~0); 170713#L1249-1 assume !(1 == ~E_8~0); 171595#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 170556#L1259-1 assume !(1 == ~E_10~0); 170557#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 171514#L1565 [2024-11-17 08:52:52,389 INFO L747 eck$LassoCheckResult]: Loop: 171514#L1565 assume true; 190991#L1565-1 assume !false; 190507#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 190505#L861 assume true; 190503#L861-1 assume !false; 190500#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 190474#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 190472#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 190316#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 190314#L866 assume !(0 != eval_~tmp~0#1); 190315#L869 assume true; 191298#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 191296#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 191294#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 191292#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 191290#L1046 assume !(0 == ~T2_E~0); 191288#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 191286#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 191284#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 191282#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 191280#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 191278#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 191276#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 191273#L1086 assume !(0 == ~T10_E~0); 191271#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 191269#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 191267#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 191265#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 191263#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 191260#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 191258#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 191256#L1126 assume !(0 == ~E_7~0); 191254#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 191252#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 191250#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 191247#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 191245#L514-1 assume !(1 == ~m_pc~0); 191243#L524-1 is_master_triggered_~__retres1~0#1 := 0; 191241#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 191239#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 191237#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 191234#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 191232#L533-1 assume !(1 == ~t1_pc~0); 191230#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 191228#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 191226#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 191224#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 191221#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 191219#L552-1 assume !(1 == ~t2_pc~0); 191217#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 191215#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 191213#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 191211#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 191208#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 191206#L571-1 assume !(1 == ~t3_pc~0); 191204#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 191202#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 191200#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 191198#L1309-1 assume !(0 != activate_threads_~tmp___2~0#1); 191196#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 191194#L590-1 assume !(1 == ~t4_pc~0); 191192#L600-1 is_transmit4_triggered_~__retres1~4#1 := 0; 191190#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 191188#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 191186#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 191184#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 191182#L609-1 assume !(1 == ~t5_pc~0); 191179#L619-1 is_transmit5_triggered_~__retres1~5#1 := 0; 191177#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 191175#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 191173#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 191171#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 191169#L628-1 assume !(1 == ~t6_pc~0); 191166#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 191164#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 191162#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 191160#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 191158#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 191156#L647-1 assume 1 == ~t7_pc~0; 191154#L648-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 191152#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 191151#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 191150#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 191149#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 191148#L666-1 assume !(1 == ~t8_pc~0); 191146#L676-1 is_transmit8_triggered_~__retres1~8#1 := 0; 191145#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 191144#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 191142#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 191140#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 191138#L685-1 assume 1 == ~t9_pc~0; 191136#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 191133#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 191131#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 191129#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 191127#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 191125#L704-1 assume !(1 == ~t10_pc~0); 191122#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 191120#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 191118#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 191116#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 191114#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 191112#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 191110#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 191108#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 191106#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 191104#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 191102#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 191100#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 191098#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 191096#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 191094#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 191092#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 191090#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 191088#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 191086#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 191084#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 191082#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 191080#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 191078#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 191076#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 191073#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 191071#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 191069#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 191067#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 191044#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 191040#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 191038#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 191034#L1584 assume !(0 == start_simulation_~tmp~3#1); 191031#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 191010#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 191005#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 191003#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 191001#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 190999#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 190996#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 190994#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 171514#L1565 [2024-11-17 08:52:52,390 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:52,390 INFO L85 PathProgramCache]: Analyzing trace with hash -475357363, now seen corresponding path program 1 times [2024-11-17 08:52:52,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:52,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776324203] [2024-11-17 08:52:52,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:52,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:52,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:52,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:52,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:52,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776324203] [2024-11-17 08:52:52,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776324203] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:52,442 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:52,442 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:52,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [486453741] [2024-11-17 08:52:52,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:52,443 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:52,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:52,443 INFO L85 PathProgramCache]: Analyzing trace with hash -1547977294, now seen corresponding path program 1 times [2024-11-17 08:52:52,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:52,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312407202] [2024-11-17 08:52:52,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:52,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:52,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:52,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:52,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:52,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312407202] [2024-11-17 08:52:52,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312407202] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:52,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:52,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:52,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218117215] [2024-11-17 08:52:52,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:52,616 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:52,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:52,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:52,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:52,617 INFO L87 Difference]: Start difference. First operand 33830 states and 47864 transitions. cyclomatic complexity: 14066 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:52,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:52,887 INFO L93 Difference]: Finished difference Result 64661 states and 91141 transitions. [2024-11-17 08:52:52,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64661 states and 91141 transitions. [2024-11-17 08:52:53,367 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 64176 [2024-11-17 08:52:53,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64661 states to 64661 states and 91141 transitions. [2024-11-17 08:52:53,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64661 [2024-11-17 08:52:53,595 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64661 [2024-11-17 08:52:53,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64661 states and 91141 transitions. [2024-11-17 08:52:53,635 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:53,636 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64661 states and 91141 transitions. [2024-11-17 08:52:53,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64661 states and 91141 transitions. [2024-11-17 08:52:54,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64661 to 64533. [2024-11-17 08:52:54,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64533 states, 64533 states have (on average 1.410332697999473) internal successors, (91013), 64532 states have internal predecessors, (91013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:54,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64533 states to 64533 states and 91013 transitions. [2024-11-17 08:52:54,659 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64533 states and 91013 transitions. [2024-11-17 08:52:54,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:54,660 INFO L425 stractBuchiCegarLoop]: Abstraction has 64533 states and 91013 transitions. [2024-11-17 08:52:54,660 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:52:54,660 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64533 states and 91013 transitions. [2024-11-17 08:52:55,129 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 64048 [2024-11-17 08:52:55,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:55,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:55,135 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:55,135 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:55,138 INFO L745 eck$LassoCheckResult]: Stem: 270024#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 268963#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 268964#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 269914#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 269915#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 269336#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 269214#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 269215#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 268950#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 268951#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 269732#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 269770#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 270342#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 270367#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 270186#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 269534#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 269535#L1036-1 assume !(0 == ~M_E~0); 269937#L1041-1 assume !(0 == ~T1_E~0); 269938#L1046-1 assume !(0 == ~T2_E~0); 269295#L1051-1 assume !(0 == ~T3_E~0); 269296#L1056-1 assume !(0 == ~T4_E~0); 270113#L1061-1 assume !(0 == ~T5_E~0); 269205#L1066-1 assume !(0 == ~T6_E~0); 269206#L1071-1 assume !(0 == ~T7_E~0); 270096#L1076-1 assume !(0 == ~T8_E~0); 269092#L1081-1 assume !(0 == ~T9_E~0); 269093#L1086-1 assume !(0 == ~T10_E~0); 269496#L1091-1 assume !(0 == ~E_M~0); 270346#L1096-1 assume !(0 == ~E_1~0); 270347#L1101-1 assume !(0 == ~E_2~0); 269571#L1106-1 assume !(0 == ~E_3~0); 269572#L1111-1 assume !(0 == ~E_4~0); 269739#L1116-1 assume !(0 == ~E_5~0); 269740#L1121-1 assume !(0 == ~E_6~0); 269564#L1126-1 assume !(0 == ~E_7~0); 269565#L1131-1 assume !(0 == ~E_8~0); 269847#L1136-1 assume !(0 == ~E_9~0); 269956#L1141-1 assume !(0 == ~E_10~0); 270161#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269972#L514-13 assume !(1 == ~m_pc~0); 269973#L524-13 is_master_triggered_~__retres1~0#1 := 0; 270377#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 268913#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 268914#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 269235#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270260#L533-13 assume !(1 == ~t1_pc~0); 270261#L543-13 is_transmit1_triggered_~__retres1~1#1 := 0; 269992#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 269579#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 269333#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 269334#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 269258#L552-13 assume !(1 == ~t2_pc~0); 269259#L562-13 is_transmit2_triggered_~__retres1~2#1 := 0; 270283#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 269062#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 269063#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 270091#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 269827#L571-13 assume !(1 == ~t3_pc~0); 269828#L581-13 is_transmit3_triggered_~__retres1~3#1 := 0; 269912#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 269668#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 269669#L1309-13 assume !(0 != activate_threads_~tmp___2~0#1); 269807#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 269885#L590-13 assume !(1 == ~t4_pc~0); 269050#L600-13 is_transmit4_triggered_~__retres1~4#1 := 0; 269051#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 270179#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 269808#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 269809#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 270234#L609-13 assume !(1 == ~t5_pc~0); 270231#L619-13 is_transmit5_triggered_~__retres1~5#1 := 0; 268908#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 268909#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 270380#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 269708#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 269020#L628-13 assume 1 == ~t6_pc~0; 269021#L629-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 269328#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 269329#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 269459#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 269293#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 269294#L647-13 assume 1 == ~t7_pc~0; 270267#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 269941#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 269942#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 269859#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 269860#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 269936#L666-13 assume 1 == ~t8_pc~0; 268937#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 268938#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 269731#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 270388#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 269010#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 269011#L685-13 assume 1 == ~t9_pc~0; 270349#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 269249#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 269250#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 269893#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 269831#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 269832#L704-13 assume 1 == ~t10_pc~0; 270045#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 268936#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 268958#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 268959#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 269155#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 269156#L1154-1 assume !(1 == ~M_E~0); 269159#L1159-1 assume !(1 == ~T1_E~0); 269280#L1164-1 assume !(1 == ~T2_E~0); 269763#L1169-1 assume !(1 == ~T3_E~0); 269629#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 269410#L1179-1 assume !(1 == ~T5_E~0); 269263#L1184-1 assume !(1 == ~T6_E~0); 269264#L1189-1 assume !(1 == ~T7_E~0); 269342#L1194-1 assume !(1 == ~T8_E~0); 269474#L1199-1 assume !(1 == ~T9_E~0); 269423#L1204-1 assume !(1 == ~T10_E~0); 269424#L1209-1 assume !(1 == ~E_M~0); 270020#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 270021#L1219-1 assume !(1 == ~E_2~0); 270428#L1224-1 assume !(1 == ~E_3~0); 269791#L1229-1 assume !(1 == ~E_4~0); 269146#L1234-1 assume !(1 == ~E_5~0); 269147#L1239-1 assume !(1 == ~E_6~0); 269212#L1244-1 assume !(1 == ~E_7~0); 269213#L1249-1 assume !(1 == ~E_8~0); 270103#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 269056#L1259-1 assume !(1 == ~E_10~0); 269057#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 270018#L1565 [2024-11-17 08:52:55,139 INFO L747 eck$LassoCheckResult]: Loop: 270018#L1565 assume true; 289835#L1565-1 assume !false; 289472#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 289471#L861 assume true; 289470#L861-1 assume !false; 289469#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 289458#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 289457#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 289455#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 289452#L866 assume !(0 != eval_~tmp~0#1); 289453#L869 assume true; 290140#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 290138#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 290136#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 290134#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 290132#L1046 assume !(0 == ~T2_E~0); 290130#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 290128#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 290126#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 290124#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 290122#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 290120#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 290118#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 290116#L1086 assume !(0 == ~T10_E~0); 290114#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 290112#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 290110#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 290108#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 290106#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 290104#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 290102#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 290100#L1126 assume !(0 == ~E_7~0); 290097#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 290095#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 290093#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 290091#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 290089#L514-1 assume !(1 == ~m_pc~0); 290087#L524-1 is_master_triggered_~__retres1~0#1 := 0; 290084#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 290082#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 290080#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 290078#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 290076#L533-1 assume !(1 == ~t1_pc~0); 290074#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 290071#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 290069#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 290067#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 290065#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 290063#L552-1 assume !(1 == ~t2_pc~0); 290061#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 290058#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 290056#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 290054#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 290052#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 290050#L571-1 assume !(1 == ~t3_pc~0); 290048#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 290045#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 290043#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 290041#L1309-1 assume !(0 != activate_threads_~tmp___2~0#1); 290039#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 290037#L590-1 assume !(1 == ~t4_pc~0); 290035#L600-1 is_transmit4_triggered_~__retres1~4#1 := 0; 290033#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 290031#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 290029#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 290027#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 290025#L609-1 assume !(1 == ~t5_pc~0); 290023#L619-1 is_transmit5_triggered_~__retres1~5#1 := 0; 290021#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 290019#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 290017#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 290015#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 290013#L628-1 assume !(1 == ~t6_pc~0); 290010#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 290008#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 290006#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 290004#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 290002#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 290000#L647-1 assume !(1 == ~t7_pc~0); 289997#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 289995#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 289993#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 289991#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 289990#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 289989#L666-1 assume 1 == ~t8_pc~0; 289988#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 289986#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 289985#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 289984#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 289982#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 289980#L685-1 assume !(1 == ~t9_pc~0); 289977#L695-1 is_transmit9_triggered_~__retres1~9#1 := 0; 289975#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 289973#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 289971#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 289969#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 289967#L704-1 assume !(1 == ~t10_pc~0); 289964#L714-1 is_transmit10_triggered_~__retres1~10#1 := 0; 289962#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 289960#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 289958#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 289956#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 289954#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 289952#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 289950#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 289948#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 289946#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 289944#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 289942#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 289940#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 289938#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 289936#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 289934#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 289932#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 289930#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 289928#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 289926#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 289924#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 289922#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 289920#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 289918#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 289916#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 289914#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 289912#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 289910#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 289887#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 289883#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 289881#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 289878#L1584 assume !(0 == start_simulation_~tmp~3#1); 289874#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 289855#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 289850#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 289847#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 289845#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 289843#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 289841#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 289839#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 270018#L1565 [2024-11-17 08:52:55,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:55,139 INFO L85 PathProgramCache]: Analyzing trace with hash -628736560, now seen corresponding path program 1 times [2024-11-17 08:52:55,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:55,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107036461] [2024-11-17 08:52:55,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:55,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:55,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:55,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:55,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:55,199 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [107036461] [2024-11-17 08:52:55,199 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [107036461] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:55,199 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:55,199 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:55,199 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451969350] [2024-11-17 08:52:55,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:55,199 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:55,199 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:55,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1805183605, now seen corresponding path program 1 times [2024-11-17 08:52:55,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:55,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591506824] [2024-11-17 08:52:55,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:55,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:55,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:55,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:55,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:55,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1591506824] [2024-11-17 08:52:55,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1591506824] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:55,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:55,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:55,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123512755] [2024-11-17 08:52:55,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:55,251 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:55,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:55,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:55,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:55,252 INFO L87 Difference]: Start difference. First operand 64533 states and 91013 transitions. cyclomatic complexity: 26544 Second operand has 3 states, 3 states have (on average 42.666666666666664) internal successors, (128), 2 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:55,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:55,802 INFO L93 Difference]: Finished difference Result 123268 states and 173250 transitions. [2024-11-17 08:52:55,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123268 states and 173250 transitions. [2024-11-17 08:52:56,560 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 122304 [2024-11-17 08:52:57,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123268 states to 123268 states and 173250 transitions. [2024-11-17 08:52:57,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123268 [2024-11-17 08:52:57,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123268 [2024-11-17 08:52:57,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123268 states and 173250 transitions. [2024-11-17 08:52:57,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:57,261 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123268 states and 173250 transitions. [2024-11-17 08:52:57,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123268 states and 173250 transitions. [2024-11-17 08:52:58,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123268 to 123012. [2024-11-17 08:52:58,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 123012 states, 123012 states have (on average 1.406318082788671) internal successors, (172994), 123011 states have internal predecessors, (172994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123012 states to 123012 states and 172994 transitions. [2024-11-17 08:52:59,120 INFO L240 hiAutomatonCegarLoop]: Abstraction has 123012 states and 172994 transitions. [2024-11-17 08:52:59,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:59,124 INFO L425 stractBuchiCegarLoop]: Abstraction has 123012 states and 172994 transitions. [2024-11-17 08:52:59,125 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:52:59,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 123012 states and 172994 transitions. [2024-11-17 08:52:59,495 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 122048 [2024-11-17 08:52:59,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:59,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:59,497 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:59,497 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:59,497 INFO L745 eck$LassoCheckResult]: Stem: 457829#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 456771#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 456772#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 457722#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 457723#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 457145#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 457019#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 457020#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 456760#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 456761#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 457545#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 457579#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 458140#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 458163#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 457982#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 457347#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 457348#L1036-1 assume !(0 == ~M_E~0); 457742#L1041-1 assume !(0 == ~T1_E~0); 457743#L1046-1 assume !(0 == ~T2_E~0); 457101#L1051-1 assume !(0 == ~T3_E~0); 457102#L1056-1 assume !(0 == ~T4_E~0); 457915#L1061-1 assume !(0 == ~T5_E~0); 457010#L1066-1 assume !(0 == ~T6_E~0); 457011#L1071-1 assume !(0 == ~T7_E~0); 457897#L1076-1 assume !(0 == ~T8_E~0); 456898#L1081-1 assume !(0 == ~T9_E~0); 456899#L1086-1 assume !(0 == ~T10_E~0); 457307#L1091-1 assume !(0 == ~E_M~0); 458144#L1096-1 assume !(0 == ~E_1~0); 458145#L1101-1 assume !(0 == ~E_2~0); 457386#L1106-1 assume !(0 == ~E_3~0); 457387#L1111-1 assume !(0 == ~E_4~0); 457550#L1116-1 assume !(0 == ~E_5~0); 457551#L1121-1 assume !(0 == ~E_6~0); 457379#L1126-1 assume !(0 == ~E_7~0); 457380#L1131-1 assume !(0 == ~E_8~0); 457659#L1136-1 assume !(0 == ~E_9~0); 457762#L1141-1 assume !(0 == ~E_10~0); 457959#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 457778#L514-13 assume !(1 == ~m_pc~0); 457779#L524-13 is_master_triggered_~__retres1~0#1 := 0; 458175#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 456723#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 456724#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 457037#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 458054#L533-13 assume !(1 == ~t1_pc~0); 458055#L543-13 is_transmit1_triggered_~__retres1~1#1 := 0; 457796#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 457392#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 457142#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 457143#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 457062#L552-13 assume !(1 == ~t2_pc~0); 457063#L562-13 is_transmit2_triggered_~__retres1~2#1 := 0; 458078#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 456865#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 456866#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 457893#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 457635#L571-13 assume !(1 == ~t3_pc~0); 457636#L581-13 is_transmit3_triggered_~__retres1~3#1 := 0; 457720#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 457481#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 457482#L1309-13 assume !(0 != activate_threads_~tmp___2~0#1); 457617#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 457695#L590-13 assume !(1 == ~t4_pc~0); 456855#L600-13 is_transmit4_triggered_~__retres1~4#1 := 0; 456856#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 457977#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 457618#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 457619#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 458028#L609-13 assume !(1 == ~t5_pc~0); 458024#L619-13 is_transmit5_triggered_~__retres1~5#1 := 0; 456718#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 456719#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 458178#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 457519#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 456826#L628-13 assume !(1 == ~t6_pc~0); 456827#L638-13 is_transmit6_triggered_~__retres1~6#1 := 0; 457135#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 457136#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 457269#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 457099#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 457100#L647-13 assume 1 == ~t7_pc~0; 458059#L648-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 457747#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 457748#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 457668#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 457669#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 457741#L666-13 assume 1 == ~t8_pc~0; 456747#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 456748#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 457544#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 458187#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 456816#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 456817#L685-13 assume 1 == ~t9_pc~0; 458147#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 457053#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 457054#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 457701#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 457638#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 457639#L704-13 assume 1 == ~t10_pc~0; 457847#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 456746#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 456766#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 456767#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 456961#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 456962#L1154-1 assume !(1 == ~M_E~0); 456966#L1159-1 assume !(1 == ~T1_E~0); 457083#L1164-1 assume !(1 == ~T2_E~0); 457572#L1169-1 assume !(1 == ~T3_E~0); 457441#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 457220#L1179-1 assume !(1 == ~T5_E~0); 457067#L1184-1 assume !(1 == ~T6_E~0); 457068#L1189-1 assume !(1 == ~T7_E~0); 457151#L1194-1 assume !(1 == ~T8_E~0); 457284#L1199-1 assume !(1 == ~T9_E~0); 457233#L1204-1 assume !(1 == ~T10_E~0); 457234#L1209-1 assume !(1 == ~E_M~0); 457825#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 457826#L1219-1 assume !(1 == ~E_2~0); 458226#L1224-1 assume !(1 == ~E_3~0); 457600#L1229-1 assume !(1 == ~E_4~0); 456953#L1234-1 assume !(1 == ~E_5~0); 456954#L1239-1 assume !(1 == ~E_6~0); 457017#L1244-1 assume !(1 == ~E_7~0); 457018#L1249-1 assume !(1 == ~E_8~0); 457903#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 456861#L1259-1 assume !(1 == ~E_10~0); 456862#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 457821#L1565 [2024-11-17 08:52:59,498 INFO L747 eck$LassoCheckResult]: Loop: 457821#L1565 assume true; 520706#L1565-1 assume !false; 520536#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 520534#L861 assume true; 520532#L861-1 assume !false; 520530#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 520503#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 520501#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 520499#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 520496#L866 assume !(0 != eval_~tmp~0#1); 520497#L869 assume true; 521007#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 521005#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 521003#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 521001#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 520999#L1046 assume !(0 == ~T2_E~0); 520997#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 520995#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 520993#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 520991#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 520989#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 520987#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 520985#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 520983#L1086 assume !(0 == ~T10_E~0); 520981#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 520979#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 520977#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 520975#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 520973#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 520971#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 520969#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 520967#L1126 assume !(0 == ~E_7~0); 520964#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 520962#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 520960#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 520958#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 520956#L514-1 assume !(1 == ~m_pc~0); 520954#L524-1 is_master_triggered_~__retres1~0#1 := 0; 520951#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 520949#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 520947#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 520945#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 520943#L533-1 assume !(1 == ~t1_pc~0); 520941#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 520938#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 520936#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 520934#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 520932#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 520930#L552-1 assume !(1 == ~t2_pc~0); 520928#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 520925#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 520923#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 520921#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 520919#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 520917#L571-1 assume !(1 == ~t3_pc~0); 520915#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 520913#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 520911#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 520909#L1309-1 assume !(0 != activate_threads_~tmp___2~0#1); 520907#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 520905#L590-1 assume !(1 == ~t4_pc~0); 520903#L600-1 is_transmit4_triggered_~__retres1~4#1 := 0; 520901#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 520899#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 520897#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 520895#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 520893#L609-1 assume !(1 == ~t5_pc~0); 520891#L619-1 is_transmit5_triggered_~__retres1~5#1 := 0; 520889#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 520887#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 520885#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 520883#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 520881#L628-1 assume !(1 == ~t6_pc~0); 520879#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 520877#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 520875#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 520873#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 520872#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 520871#L647-1 assume 1 == ~t7_pc~0; 520870#L648-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 520868#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 520867#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 520866#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 520865#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 520864#L666-1 assume 1 == ~t8_pc~0; 520862#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 520859#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 520857#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 520855#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 520853#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 520851#L685-1 assume 1 == ~t9_pc~0; 520849#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 520846#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 520844#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 520842#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 520840#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 520838#L704-1 assume 1 == ~t10_pc~0; 520836#L705-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 520833#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 520831#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 520829#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 520827#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 520825#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 520823#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 520821#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 520819#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 520817#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 520815#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 520813#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 520811#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 520809#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 520807#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 520805#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 520803#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 520801#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 520799#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 520797#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 520795#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 520793#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 520791#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 520789#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 520787#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 520785#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 520783#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 520781#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 520760#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 520755#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 520753#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 520750#L1584 assume !(0 == start_simulation_~tmp~3#1); 520747#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 520726#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 520721#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 520719#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 520716#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 520714#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 520712#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 520710#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 457821#L1565 [2024-11-17 08:52:59,498 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:59,498 INFO L85 PathProgramCache]: Analyzing trace with hash 202357395, now seen corresponding path program 1 times [2024-11-17 08:52:59,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:59,499 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254076829] [2024-11-17 08:52:59,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:59,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:59,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,541 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254076829] [2024-11-17 08:52:59,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254076829] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,541 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,541 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:59,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058227208] [2024-11-17 08:52:59,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,541 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:59,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:59,542 INFO L85 PathProgramCache]: Analyzing trace with hash -1815218260, now seen corresponding path program 1 times [2024-11-17 08:52:59,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:59,542 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1036000773] [2024-11-17 08:52:59,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:59,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:59,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,579 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1036000773] [2024-11-17 08:52:59,580 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1036000773] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,580 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,580 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:59,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1293586433] [2024-11-17 08:52:59,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,580 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:59,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:59,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:52:59,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:52:59,581 INFO L87 Difference]: Start difference. First operand 123012 states and 172994 transitions. cyclomatic complexity: 50110 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:00,705 INFO L93 Difference]: Finished difference Result 291187 states and 407615 transitions. [2024-11-17 08:53:00,706 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 291187 states and 407615 transitions. [2024-11-17 08:53:02,522 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 288304 [2024-11-17 08:53:03,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 291187 states to 291187 states and 407615 transitions. [2024-11-17 08:53:03,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291187 [2024-11-17 08:53:03,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291187 [2024-11-17 08:53:03,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 291187 states and 407615 transitions. [2024-11-17 08:53:04,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:04,022 INFO L218 hiAutomatonCegarLoop]: Abstraction has 291187 states and 407615 transitions. [2024-11-17 08:53:04,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291187 states and 407615 transitions. [2024-11-17 08:53:05,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291187 to 234179. [2024-11-17 08:53:06,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 234179 states, 234179 states have (on average 1.4028200649930183) internal successors, (328511), 234178 states have internal predecessors, (328511), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234179 states to 234179 states and 328511 transitions. [2024-11-17 08:53:07,359 INFO L240 hiAutomatonCegarLoop]: Abstraction has 234179 states and 328511 transitions. [2024-11-17 08:53:07,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:07,359 INFO L425 stractBuchiCegarLoop]: Abstraction has 234179 states and 328511 transitions. [2024-11-17 08:53:07,359 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:53:07,360 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 234179 states and 328511 transitions. [2024-11-17 08:53:07,970 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 232384 [2024-11-17 08:53:07,970 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:07,970 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:07,975 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,975 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,976 INFO L745 eck$LassoCheckResult]: Stem: 872046#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 870985#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 870986#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 871941#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 871942#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 871362#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 871232#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 871233#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 870972#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 870973#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 871761#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 871798#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 872380#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 872405#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 872203#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 871561#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 871562#L1036-1 assume !(0 == ~M_E~0); 871962#L1041-1 assume !(0 == ~T1_E~0); 871963#L1046-1 assume !(0 == ~T2_E~0); 871319#L1051-1 assume !(0 == ~T3_E~0); 871320#L1056-1 assume !(0 == ~T4_E~0); 872133#L1061-1 assume !(0 == ~T5_E~0); 871223#L1066-1 assume !(0 == ~T6_E~0); 871224#L1071-1 assume !(0 == ~T7_E~0); 872116#L1076-1 assume !(0 == ~T8_E~0); 871114#L1081-1 assume !(0 == ~T9_E~0); 871115#L1086-1 assume !(0 == ~T10_E~0); 871522#L1091-1 assume !(0 == ~E_M~0); 872384#L1096-1 assume !(0 == ~E_1~0); 872385#L1101-1 assume !(0 == ~E_2~0); 871600#L1106-1 assume !(0 == ~E_3~0); 871601#L1111-1 assume !(0 == ~E_4~0); 871768#L1116-1 assume !(0 == ~E_5~0); 871769#L1121-1 assume !(0 == ~E_6~0); 871593#L1126-1 assume !(0 == ~E_7~0); 871594#L1131-1 assume !(0 == ~E_8~0); 871873#L1136-1 assume !(0 == ~E_9~0); 871982#L1141-1 assume !(0 == ~E_10~0); 872180#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 871999#L514-13 assume !(1 == ~m_pc~0); 872000#L524-13 is_master_triggered_~__retres1~0#1 := 0; 872415#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 870934#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 870935#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 871251#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 872292#L533-13 assume !(1 == ~t1_pc~0); 872293#L543-13 is_transmit1_triggered_~__retres1~1#1 := 0; 872017#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 871607#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 871358#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 871359#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 871278#L552-13 assume !(1 == ~t2_pc~0); 871279#L562-13 is_transmit2_triggered_~__retres1~2#1 := 0; 872313#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 871079#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 871080#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 872112#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 871853#L571-13 assume !(1 == ~t3_pc~0); 871854#L581-13 is_transmit3_triggered_~__retres1~3#1 := 0; 871939#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 871700#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 871701#L1309-13 assume !(0 != activate_threads_~tmp___2~0#1); 871835#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 871913#L590-13 assume !(1 == ~t4_pc~0); 871069#L600-13 is_transmit4_triggered_~__retres1~4#1 := 0; 871070#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 872198#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 871836#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 871837#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 872260#L609-13 assume !(1 == ~t5_pc~0); 872256#L619-13 is_transmit5_triggered_~__retres1~5#1 := 0; 870929#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 870930#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 872419#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 871734#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 871041#L628-13 assume !(1 == ~t6_pc~0); 871042#L638-13 is_transmit6_triggered_~__retres1~6#1 := 0; 871351#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 871352#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 871484#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 871317#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 871318#L647-13 assume !(1 == ~t7_pc~0); 872297#L657-13 is_transmit7_triggered_~__retres1~7#1 := 0; 871967#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 871968#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 871885#L1341-13 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 871886#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 871961#L666-13 assume 1 == ~t8_pc~0; 870959#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 870960#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 871760#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 872430#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 871031#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 871032#L685-13 assume 1 == ~t9_pc~0; 872388#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 871269#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 871270#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 871920#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 871856#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 871857#L704-13 assume 1 == ~t10_pc~0; 872067#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 870958#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 870980#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 870981#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 871175#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 871176#L1154-1 assume !(1 == ~M_E~0); 871180#L1159-1 assume !(1 == ~T1_E~0); 871300#L1164-1 assume !(1 == ~T2_E~0); 871791#L1169-1 assume !(1 == ~T3_E~0); 871662#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 871437#L1179-1 assume !(1 == ~T5_E~0); 871283#L1184-1 assume !(1 == ~T6_E~0); 871284#L1189-1 assume !(1 == ~T7_E~0); 871368#L1194-1 assume !(1 == ~T8_E~0); 871499#L1199-1 assume !(1 == ~T9_E~0); 871450#L1204-1 assume !(1 == ~T10_E~0); 871451#L1209-1 assume !(1 == ~E_M~0); 872042#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 872043#L1219-1 assume !(1 == ~E_2~0); 872476#L1224-1 assume !(1 == ~E_3~0); 871818#L1229-1 assume !(1 == ~E_4~0); 871167#L1234-1 assume !(1 == ~E_5~0); 871168#L1239-1 assume !(1 == ~E_6~0); 871230#L1244-1 assume !(1 == ~E_7~0); 871231#L1249-1 assume !(1 == ~E_8~0); 872122#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 871075#L1259-1 assume !(1 == ~E_10~0); 871076#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 872039#L1565 [2024-11-17 08:53:07,977 INFO L747 eck$LassoCheckResult]: Loop: 872039#L1565 assume true; 1041083#L1565-1 assume !false; 1040855#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1040853#L861 assume true; 1040851#L861-1 assume !false; 1040849#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1040823#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1040821#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1040819#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1040815#L866 assume !(0 != eval_~tmp~0#1); 1040816#L869 assume true; 1041366#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1041364#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1041363#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 1041362#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1041361#L1046 assume !(0 == ~T2_E~0); 1041360#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1041359#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1041358#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1041357#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1041356#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1041355#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1041354#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1041352#L1086 assume !(0 == ~T10_E~0); 1041350#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 1041348#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 1041346#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 1041344#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 1041342#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 1041340#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 1041338#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 1041336#L1126 assume !(0 == ~E_7~0); 1041334#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 1041332#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 1041330#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 1041328#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1041326#L514-1 assume !(1 == ~m_pc~0); 1041324#L524-1 is_master_triggered_~__retres1~0#1 := 0; 1041322#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1041320#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1041318#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1041316#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1041314#L533-1 assume !(1 == ~t1_pc~0); 1041312#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1041310#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1041308#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1041306#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1041304#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1041302#L552-1 assume !(1 == ~t2_pc~0); 1041300#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1041298#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1041296#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1041294#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1041292#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1041290#L571-1 assume !(1 == ~t3_pc~0); 1041288#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1041286#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1041284#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1041282#L1309-1 assume !(0 != activate_threads_~tmp___2~0#1); 1041280#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1041278#L590-1 assume !(1 == ~t4_pc~0); 1041276#L600-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1041274#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1041272#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1041270#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1041268#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1041267#L609-1 assume !(1 == ~t5_pc~0); 1041265#L619-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1041263#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1041261#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1041259#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1041257#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1041254#L628-1 assume !(1 == ~t6_pc~0); 1041252#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1041250#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1041248#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1041246#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1041244#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1041241#L647-1 assume !(1 == ~t7_pc~0); 966785#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1041238#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1041236#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1041234#L1341-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1041232#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1041229#L666-1 assume 1 == ~t8_pc~0; 1041227#L667-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1041224#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1041222#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1041220#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1041218#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1041216#L685-1 assume 1 == ~t9_pc~0; 1041214#L686-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1041211#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1041209#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1041207#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1041205#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1041203#L704-1 assume 1 == ~t10_pc~0; 1041201#L705-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1041198#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1041196#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1041194#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1041192#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1041190#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 1041188#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1041186#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1041184#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1041182#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1041180#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1041178#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1041176#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1041174#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1041173#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1041172#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1041171#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 1041169#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 1041167#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 1041165#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 1041163#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 1041161#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 1041159#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 1041157#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 1041155#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 1041153#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 1041151#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 1041149#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1041130#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1041126#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1041124#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1041121#L1584 assume !(0 == start_simulation_~tmp~3#1); 1041118#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1041101#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1041096#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1041094#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1041092#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1041090#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1041088#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1041086#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 872039#L1565 [2024-11-17 08:53:07,978 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,978 INFO L85 PathProgramCache]: Analyzing trace with hash 245024150, now seen corresponding path program 1 times [2024-11-17 08:53:07,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1092034194] [2024-11-17 08:53:07,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:08,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:08,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:08,027 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1092034194] [2024-11-17 08:53:08,027 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1092034194] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:08,027 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:08,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:08,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355997200] [2024-11-17 08:53:08,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:08,028 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:08,028 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:08,028 INFO L85 PathProgramCache]: Analyzing trace with hash -1968597457, now seen corresponding path program 1 times [2024-11-17 08:53:08,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:08,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [945884107] [2024-11-17 08:53:08,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:08,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:08,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:08,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:08,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:08,687 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [945884107] [2024-11-17 08:53:08,687 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [945884107] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:08,687 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:08,687 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:08,687 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1030351262] [2024-11-17 08:53:08,688 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:08,688 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:08,688 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:08,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:53:08,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:53:08,689 INFO L87 Difference]: Start difference. First operand 234179 states and 328511 transitions. cyclomatic complexity: 94460 Second operand has 5 states, 5 states have (on average 25.6) internal successors, (128), 5 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:09,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:09,645 INFO L93 Difference]: Finished difference Result 237827 states and 331070 transitions. [2024-11-17 08:53:09,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 237827 states and 331070 transitions. [2024-11-17 08:53:11,253 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 236032 [2024-11-17 08:53:11,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 237827 states to 237827 states and 331070 transitions. [2024-11-17 08:53:11,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 237827 [2024-11-17 08:53:12,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 237827 [2024-11-17 08:53:12,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 237827 states and 331070 transitions. [2024-11-17 08:53:12,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:12,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 237827 states and 331070 transitions. [2024-11-17 08:53:12,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237827 states and 331070 transitions. [2024-11-17 08:53:14,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237827 to 237827. [2024-11-17 08:53:14,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 237827 states, 237827 states have (on average 1.3920622973842331) internal successors, (331070), 237826 states have internal predecessors, (331070), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:15,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237827 states to 237827 states and 331070 transitions. [2024-11-17 08:53:15,308 INFO L240 hiAutomatonCegarLoop]: Abstraction has 237827 states and 331070 transitions. [2024-11-17 08:53:15,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:53:15,309 INFO L425 stractBuchiCegarLoop]: Abstraction has 237827 states and 331070 transitions. [2024-11-17 08:53:15,312 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:53:15,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 237827 states and 331070 transitions. [2024-11-17 08:53:16,616 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 236032 [2024-11-17 08:53:16,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:16,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:16,626 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:16,626 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:16,626 INFO L745 eck$LassoCheckResult]: Stem: 1344087#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~token~0 := 0;~local~0 := 0; 1343000#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1343001#L1528 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret30#1, start_simulation_#t~ret31#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1343975#L724-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1343976#L731 assume 1 == ~m_i~0;~m_st~0 := 0; 1343379#L736 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1343252#L741 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1343253#L746 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1342989#L751 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1342990#L756 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1343790#L761 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1343828#L766 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1344453#L771 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1344481#L776 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1344261#L781 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1343579#L787 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1343580#L1036-1 assume !(0 == ~M_E~0); 1343994#L1041-1 assume !(0 == ~T1_E~0); 1343995#L1046-1 assume !(0 == ~T2_E~0); 1343336#L1051-1 assume !(0 == ~T3_E~0); 1343337#L1056-1 assume !(0 == ~T4_E~0); 1344183#L1061-1 assume !(0 == ~T5_E~0); 1343243#L1066-1 assume !(0 == ~T6_E~0); 1343244#L1071-1 assume !(0 == ~T7_E~0); 1344165#L1076-1 assume !(0 == ~T8_E~0); 1343132#L1081-1 assume !(0 == ~T9_E~0); 1343133#L1086-1 assume !(0 == ~T10_E~0); 1343538#L1091-1 assume !(0 == ~E_M~0); 1344460#L1096-1 assume !(0 == ~E_1~0); 1344461#L1101-1 assume !(0 == ~E_2~0); 1343621#L1106-1 assume !(0 == ~E_3~0); 1343622#L1111-1 assume !(0 == ~E_4~0); 1343795#L1116-1 assume !(0 == ~E_5~0); 1343796#L1121-1 assume !(0 == ~E_6~0); 1343614#L1126-1 assume !(0 == ~E_7~0); 1343615#L1131-1 assume !(0 == ~E_8~0); 1343904#L1136-1 assume !(0 == ~E_9~0); 1344016#L1141-1 assume !(0 == ~E_10~0); 1344235#L1147-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1344035#L514-13 assume !(1 == ~m_pc~0); 1344036#L524-13 is_master_triggered_~__retres1~0#1 := 0; 1344493#L517-13 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1342951#L526-13 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1342952#L1285-13 assume !(0 != activate_threads_~tmp~1#1); 1343270#L1291-13 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1344343#L533-13 assume !(1 == ~t1_pc~0); 1344344#L543-13 is_transmit1_triggered_~__retres1~1#1 := 0; 1344056#L536-13 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1343628#L545-13 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1343376#L1293-13 assume !(0 != activate_threads_~tmp___0~0#1); 1343377#L1299-13 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1343295#L552-13 assume !(1 == ~t2_pc~0); 1343296#L562-13 is_transmit2_triggered_~__retres1~2#1 := 0; 1344373#L555-13 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1343097#L564-13 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1343098#L1301-13 assume !(0 != activate_threads_~tmp___1~0#1); 1344157#L1307-13 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1343883#L571-13 assume !(1 == ~t3_pc~0); 1343884#L581-13 is_transmit3_triggered_~__retres1~3#1 := 0; 1343972#L574-13 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1343725#L583-13 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1343726#L1309-13 assume !(0 != activate_threads_~tmp___2~0#1); 1343864#L1315-13 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1343946#L590-13 assume !(1 == ~t4_pc~0); 1343087#L600-13 is_transmit4_triggered_~__retres1~4#1 := 0; 1343088#L593-13 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1344256#L602-13 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1343865#L1317-13 assume !(0 != activate_threads_~tmp___3~0#1); 1343866#L1323-13 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1344310#L609-13 assume !(1 == ~t5_pc~0); 1344307#L619-13 is_transmit5_triggered_~__retres1~5#1 := 0; 1342946#L612-13 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1342947#L621-13 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1344496#L1325-13 assume !(0 != activate_threads_~tmp___4~0#1); 1343765#L1331-13 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1343059#L628-13 assume !(1 == ~t6_pc~0); 1343060#L638-13 is_transmit6_triggered_~__retres1~6#1 := 0; 1343369#L631-13 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1343370#L640-13 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1343503#L1333-13 assume !(0 != activate_threads_~tmp___5~0#1); 1343334#L1339-13 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1343335#L647-13 assume !(1 == ~t7_pc~0); 1344350#L657-13 is_transmit7_triggered_~__retres1~7#1 := 0; 1343999#L650-13 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1344000#L659-13 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1343918#L1341-13 assume !(0 != activate_threads_~tmp___6~0#1); 1343919#L1347-13 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1343993#L666-13 assume 1 == ~t8_pc~0; 1342976#L667-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1342977#L669-13 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1343789#L678-13 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1344508#L1349-13 assume !(0 != activate_threads_~tmp___7~0#1); 1343048#L1355-13 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1343049#L685-13 assume 1 == ~t9_pc~0; 1344463#L686-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1343286#L688-13 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1343287#L697-13 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1343952#L1357-13 assume !(0 != activate_threads_~tmp___8~0#1); 1343886#L1363-13 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1343887#L704-13 assume 1 == ~t10_pc~0; 1344105#L705-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1342975#L707-13 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1342995#L716-13 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1342996#L1365-13 assume !(0 != activate_threads_~tmp___9~0#1); 1343195#L1371-13 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1343196#L1154-1 assume !(1 == ~M_E~0); 1343200#L1159-1 assume !(1 == ~T1_E~0); 1343318#L1164-1 assume !(1 == ~T2_E~0); 1343819#L1169-1 assume !(1 == ~T3_E~0); 1343684#L1174-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1343454#L1179-1 assume !(1 == ~T5_E~0); 1343300#L1184-1 assume !(1 == ~T6_E~0); 1343301#L1189-1 assume !(1 == ~T7_E~0); 1343385#L1194-1 assume !(1 == ~T8_E~0); 1343516#L1199-1 assume !(1 == ~T9_E~0); 1343468#L1204-1 assume !(1 == ~T10_E~0); 1343469#L1209-1 assume !(1 == ~E_M~0); 1344083#L1214-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1344084#L1219-1 assume !(1 == ~E_2~0); 1344566#L1224-1 assume !(1 == ~E_3~0); 1343850#L1229-1 assume !(1 == ~E_4~0); 1343187#L1234-1 assume !(1 == ~E_5~0); 1343188#L1239-1 assume !(1 == ~E_6~0); 1343250#L1244-1 assume !(1 == ~E_7~0); 1343251#L1249-1 assume !(1 == ~E_8~0); 1344172#L1254-1 assume 1 == ~E_9~0;~E_9~0 := 2; 1343093#L1259-1 assume !(1 == ~E_10~0); 1343094#L1265-1 assume true;assume { :end_inline_reset_delta_events } true; 1344078#L1565 [2024-11-17 08:53:16,627 INFO L747 eck$LassoCheckResult]: Loop: 1344078#L1565 assume true; 1362520#L1565-1 assume !false; 1362350#start_simulation_while_12_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1362348#L861 assume true; 1362347#L861-1 assume !false; 1362345#eval_while_11_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1362334#L794-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1362332#L836-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1362331#L852-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1362328#L866 assume !(0 != eval_~tmp~0#1); 1362329#L869 assume true; 1577286#L1029 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1577279#L724 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1577272#L1036 assume 0 == ~M_E~0;~M_E~0 := 1; 1577267#L1041 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1577263#L1046 assume !(0 == ~T2_E~0); 1577259#L1051 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1577254#L1056 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1577248#L1061 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1577243#L1066 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1577239#L1071 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1577235#L1076 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1577230#L1081 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1577225#L1086 assume !(0 == ~T10_E~0); 1577222#L1091 assume 0 == ~E_M~0;~E_M~0 := 1; 1577218#L1096 assume 0 == ~E_1~0;~E_1~0 := 1; 1577215#L1101 assume 0 == ~E_2~0;~E_2~0 := 1; 1577210#L1106 assume 0 == ~E_3~0;~E_3~0 := 1; 1577203#L1111 assume 0 == ~E_4~0;~E_4~0 := 1; 1577198#L1116 assume 0 == ~E_5~0;~E_5~0 := 1; 1577192#L1121 assume 0 == ~E_6~0;~E_6~0 := 1; 1577187#L1126 assume !(0 == ~E_7~0); 1577184#L1131 assume 0 == ~E_8~0;~E_8~0 := 1; 1577180#L1136 assume 0 == ~E_9~0;~E_9~0 := 1; 1577175#L1141 assume 0 == ~E_10~0;~E_10~0 := 1; 1577171#L1147 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1577159#L514-1 assume !(1 == ~m_pc~0); 1577154#L524-1 is_master_triggered_~__retres1~0#1 := 0; 1577148#L517-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1577141#L526-1 assume true;activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1577135#L1285-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1577128#L1291-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1577123#L533-1 assume !(1 == ~t1_pc~0); 1577118#L543-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1577111#L536-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1577105#L545-1 assume true;activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1577098#L1293-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1577091#L1299-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1577084#L552-1 assume !(1 == ~t2_pc~0); 1577074#L562-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1577065#L555-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1577059#L564-1 assume true;activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1577052#L1301-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1577043#L1307-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1577036#L571-1 assume !(1 == ~t3_pc~0); 1577028#L581-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1577021#L574-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1577015#L583-1 assume true;activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1577006#L1309-1 assume !(0 != activate_threads_~tmp___2~0#1); 1577000#L1315-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1576995#L590-1 assume !(1 == ~t4_pc~0); 1576989#L600-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1576986#L593-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1576685#L602-1 assume true;activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1574953#L1317-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1573561#L1323-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1573560#L609-1 assume !(1 == ~t5_pc~0); 1573558#L619-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1573556#L612-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1573555#L621-1 assume true;activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1573554#L1325-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1573552#L1331-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1573550#L628-1 assume !(1 == ~t6_pc~0); 1573549#L638-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1573548#L631-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1573546#L640-1 assume true;activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1573545#L1333-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1573543#L1339-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1362679#L647-1 assume !(1 == ~t7_pc~0); 1362677#L657-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1362675#L650-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1362673#L659-1 assume true;activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1362671#L1341-1 assume !(0 != activate_threads_~tmp___6~0#1); 1362669#L1347-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1362667#L666-1 assume !(1 == ~t8_pc~0); 1362663#L676-1 is_transmit8_triggered_~__retres1~8#1 := 0; 1362661#L669-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1362659#L678-1 assume true;activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1362657#L1349-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1362655#L1355-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1362653#L685-1 assume !(1 == ~t9_pc~0); 1362649#L695-1 is_transmit9_triggered_~__retres1~9#1 := 0; 1362647#L688-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1362645#L697-1 assume true;activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1362643#L1357-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1362641#L1363-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1362639#L704-1 assume 1 == ~t10_pc~0; 1362636#L705-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1362633#L707-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1362631#L716-1 assume true;activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1362629#L1365-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1362627#L1371-1 assume true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1362625#L1154 assume 1 == ~M_E~0;~M_E~0 := 2; 1362623#L1159 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1362621#L1164 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1362619#L1169 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1362617#L1174 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1362615#L1179 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1362613#L1184 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1362611#L1189 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1362609#L1194 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1362607#L1199 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1362605#L1204 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1362603#L1209 assume 1 == ~E_M~0;~E_M~0 := 2; 1362601#L1214 assume 1 == ~E_1~0;~E_1~0 := 2; 1362599#L1219 assume 1 == ~E_2~0;~E_2~0 := 2; 1362597#L1224 assume 1 == ~E_3~0;~E_3~0 := 2; 1362595#L1229 assume 1 == ~E_4~0;~E_4~0 := 2; 1362593#L1234 assume 1 == ~E_5~0;~E_5~0 := 2; 1362591#L1239 assume 1 == ~E_6~0;~E_6~0 := 2; 1362589#L1244 assume 1 == ~E_7~0;~E_7~0 := 2; 1362587#L1249 assume 1 == ~E_8~0;~E_8~0 := 2; 1362585#L1254 assume 1 == ~E_9~0;~E_9~0 := 2; 1362583#L1259 assume 1 == ~E_10~0;~E_10~0 := 2; 1362582#L1265 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1362572#L794-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1362568#L836-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1362566#L852-1 assume true;start_simulation_#t~ret30#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret30#1;havoc start_simulation_#t~ret30#1; 1362563#L1584 assume !(0 == start_simulation_~tmp~3#1); 1362559#L1595 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1362540#L794 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1362535#L836 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1362532#L852 assume true;stop_simulation_#t~ret29#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret29#1;havoc stop_simulation_#t~ret29#1; 1362530#L1539 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1362528#L1541 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1362526#L1547 assume true;start_simulation_#t~ret31#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret29#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret31#1;havoc start_simulation_#t~ret31#1; 1362524#L1597 assume !(0 != start_simulation_~tmp___0~1#1); 1344078#L1565 [2024-11-17 08:53:16,627 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:16,627 INFO L85 PathProgramCache]: Analyzing trace with hash -203672489, now seen corresponding path program 1 times [2024-11-17 08:53:16,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:16,628 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [374472454] [2024-11-17 08:53:16,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:16,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:16,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:16,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:16,683 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:16,683 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [374472454] [2024-11-17 08:53:16,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [374472454] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:16,684 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:16,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:16,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [294035125] [2024-11-17 08:53:16,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:16,684 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:16,685 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:16,685 INFO L85 PathProgramCache]: Analyzing trace with hash -401444042, now seen corresponding path program 1 times [2024-11-17 08:53:16,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:16,685 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553578360] [2024-11-17 08:53:16,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:16,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:16,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:16,732 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:16,732 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:16,732 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [553578360] [2024-11-17 08:53:16,732 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [553578360] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:16,733 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:16,733 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:16,733 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964325605] [2024-11-17 08:53:16,733 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:16,733 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:16,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:16,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:16,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:16,734 INFO L87 Difference]: Start difference. First operand 237827 states and 331070 transitions. cyclomatic complexity: 93371 Second operand has 4 states, 4 states have (on average 32.0) internal successors, (128), 3 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:19,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:19,208 INFO L93 Difference]: Finished difference Result 560066 states and 776571 transitions. [2024-11-17 08:53:19,208 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 560066 states and 776571 transitions. [2024-11-17 08:53:21,886 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 554432 [2024-11-17 08:53:23,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 560066 states to 560066 states and 776571 transitions. [2024-11-17 08:53:23,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 560066 [2024-11-17 08:53:23,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 560066 [2024-11-17 08:53:23,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 560066 states and 776571 transitions. [2024-11-17 08:53:23,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:23,960 INFO L218 hiAutomatonCegarLoop]: Abstraction has 560066 states and 776571 transitions. [2024-11-17 08:53:24,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 560066 states and 776571 transitions.