./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.13.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.13.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:52:52,812 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:52:52,885 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:52:52,889 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:52:52,889 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:52:52,890 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:52:52,909 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:52:52,910 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:52:52,911 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:52:52,913 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:52:52,914 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:52:52,914 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:52:52,914 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:52:52,916 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:52:52,916 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:52:52,916 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:52:52,916 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:52:52,917 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:52:52,917 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:52:52,917 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:52:52,917 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:52:52,918 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:52:52,918 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:52:52,918 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:52:52,918 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:52:52,918 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:52:52,918 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:52:52,919 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:52:52,919 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:52:52,919 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:52:52,919 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:52:52,919 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:52:52,919 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:52:52,920 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:52:52,920 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:52:52,920 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:52:52,920 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:52:52,920 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:52:52,920 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:52:52,921 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:52:52,921 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1b2c6a3c4af8091017033117c21d8fbc40cee2009788b890a114045d77587077 [2024-11-17 08:52:53,120 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:52:53,144 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:52:53,147 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:52:53,148 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:52:53,148 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:52:53,149 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2024-11-17 08:52:54,332 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:52:54,505 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:52:54,507 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.13.cil-1.c [2024-11-17 08:52:54,519 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/86f0b775f/7684b8fb25154e89bd354ddb243a6d18/FLAG98957039b [2024-11-17 08:52:54,896 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/86f0b775f/7684b8fb25154e89bd354ddb243a6d18 [2024-11-17 08:52:54,898 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:52:54,899 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:52:54,900 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:54,900 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:52:54,904 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:52:54,904 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:54" (1/1) ... [2024-11-17 08:52:54,905 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@11d4edb4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:54, skipping insertion in model container [2024-11-17 08:52:54,905 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:52:54" (1/1) ... [2024-11-17 08:52:54,944 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:52:55,208 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:55,221 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:52:55,292 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:52:55,314 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:52:55,315 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55 WrapperNode [2024-11-17 08:52:55,315 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:52:55,316 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:55,316 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:52:55,316 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:52:55,321 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,335 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,409 INFO L138 Inliner]: procedures = 54, calls = 72, calls flagged for inlining = 67, calls inlined = 305, statements flattened = 4680 [2024-11-17 08:52:55,409 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:52:55,410 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:52:55,410 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:52:55,410 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:52:55,418 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,418 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,430 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,484 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:52:55,490 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,490 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,523 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,527 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,532 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,536 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,544 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:52:55,545 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:52:55,545 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:52:55,545 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:52:55,546 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (1/1) ... [2024-11-17 08:52:55,550 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:52:55,558 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:52:55,573 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:52:55,577 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:52:55,612 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:52:55,612 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:52:55,612 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:52:55,612 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:52:55,721 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:52:55,723 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:52:57,996 INFO L? ?]: Removed 1008 outVars from TransFormulas that were not future-live. [2024-11-17 08:52:57,996 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:52:58,039 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:52:58,040 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:52:58,040 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:58 BoogieIcfgContainer [2024-11-17 08:52:58,040 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:52:58,041 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:52:58,041 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:52:58,046 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:52:58,046 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:58,046 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:52:54" (1/3) ... [2024-11-17 08:52:58,048 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5b702adf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:58, skipping insertion in model container [2024-11-17 08:52:58,048 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:58,048 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:52:55" (2/3) ... [2024-11-17 08:52:58,049 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5b702adf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:52:58, skipping insertion in model container [2024-11-17 08:52:58,049 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:52:58,049 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:52:58" (3/3) ... [2024-11-17 08:52:58,050 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-1.c [2024-11-17 08:52:58,112 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:52:58,113 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:52:58,113 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:52:58,113 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:52:58,113 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:52:58,114 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:52:58,114 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:52:58,114 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:52:58,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2108 states, 2107 states have (on average 1.478405315614618) internal successors, (3115), 2107 states have internal predecessors, (3115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:58,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1928 [2024-11-17 08:52:58,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:58,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:58,215 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:58,215 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:58,215 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:52:58,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2108 states, 2107 states have (on average 1.478405315614618) internal successors, (3115), 2107 states have internal predecessors, (3115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:58,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1928 [2024-11-17 08:52:58,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:58,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:58,239 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:58,239 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:58,253 INFO L745 eck$LassoCheckResult]: Stem: 508#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1109#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1645#L1903true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1682#L907-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1908#L914true assume !(1 == ~m_i~0);~m_st~0 := 2; 1272#L919true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 218#L924true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1266#L929true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 354#L934true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1979#L939true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 669#L944true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 175#L949true assume 1 == ~t7_i~0;~t7_st~0 := 0; 1061#L954true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 767#L959true assume !(1 == ~t9_i~0);~t9_st~0 := 2; 1644#L964true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 158#L969true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1604#L974true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1691#L979true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 827#L985true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 272#L1291-1true assume 0 == ~M_E~0;~M_E~0 := 1; 1900#L1296-1true assume !(0 == ~T1_E~0); 761#L1301-1true assume !(0 == ~T2_E~0); 1300#L1306-1true assume !(0 == ~T3_E~0); 1261#L1311-1true assume !(0 == ~T4_E~0); 249#L1316-1true assume !(0 == ~T5_E~0); 1737#L1321-1true assume !(0 == ~T6_E~0); 773#L1326-1true assume !(0 == ~T7_E~0); 165#L1331-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 4#L1336-1true assume !(0 == ~T9_E~0); 1154#L1341-1true assume !(0 == ~T10_E~0); 44#L1346-1true assume !(0 == ~T11_E~0); 1526#L1351-1true assume !(0 == ~T12_E~0); 220#L1356-1true assume !(0 == ~T13_E~0); 2031#L1361-1true assume !(0 == ~E_M~0); 1706#L1366-1true assume !(0 == ~E_1~0); 241#L1371-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1493#L1376-1true assume !(0 == ~E_3~0); 820#L1381-1true assume !(0 == ~E_4~0); 1798#L1386-1true assume !(0 == ~E_5~0); 1950#L1391-1true assume !(0 == ~E_6~0); 1857#L1396-1true assume !(0 == ~E_7~0); 731#L1401-1true assume !(0 == ~E_8~0); 1356#L1406-1true assume !(0 == ~E_9~0); 973#L1411-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1759#L1416-1true assume !(0 == ~E_11~0); 671#L1421-1true assume !(0 == ~E_12~0); 336#L1426-1true assume !(0 == ~E_13~0); 348#L1432-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1230#L640-16true assume 1 == ~m_pc~0; 2010#L641-16true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 660#L643-16true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 408#L652-16true assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1571#L1603-16true assume !(0 != activate_threads_~tmp~1#1); 1011#L1609-16true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 534#L659-16true assume 1 == ~t1_pc~0; 302#L660-16true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1529#L662-16true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1099#L671-16true assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 235#L1611-16true assume !(0 != activate_threads_~tmp___0~0#1); 1951#L1617-16true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 296#L678-16true assume 1 == ~t2_pc~0; 1029#L679-16true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 459#L681-16true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 301#L690-16true assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1486#L1619-16true assume !(0 != activate_threads_~tmp___1~0#1); 2041#L1625-16true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1101#L697-16true assume 1 == ~t3_pc~0; 1310#L698-16true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 645#L700-16true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 268#L709-16true assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28#L1627-16true assume !(0 != activate_threads_~tmp___2~0#1); 570#L1633-16true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1331#L716-16true assume 1 == ~t4_pc~0; 1143#L717-16true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2051#L719-16true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 896#L728-16true assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1819#L1635-16true assume !(0 != activate_threads_~tmp___3~0#1); 2040#L1641-16true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1650#L735-16true assume 1 == ~t5_pc~0; 1246#L736-16true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1796#L738-16true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1625#L747-16true assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1003#L1643-16true assume !(0 != activate_threads_~tmp___4~0#1); 1551#L1649-16true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1275#L754-16true assume 1 == ~t6_pc~0; 1558#L755-16true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1923#L757-16true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 692#L766-16true assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1138#L1651-16true assume !(0 != activate_threads_~tmp___5~0#1); 1895#L1657-16true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1460#L773-16true assume 1 == ~t7_pc~0; 299#L774-16true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2054#L776-16true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2079#L785-16true assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14#L1659-16true assume !(0 != activate_threads_~tmp___6~0#1); 1591#L1665-16true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1202#L792-16true assume 1 == ~t8_pc~0; 1565#L793-16true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 695#L795-16true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 177#L804-16true assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2062#L1667-16true assume !(0 != activate_threads_~tmp___7~0#1); 1842#L1673-16true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 876#L811-16true assume 1 == ~t9_pc~0; 297#L812-16true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2052#L814-16true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1770#L823-16true assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 287#L1675-16true assume !(0 != activate_threads_~tmp___8~0#1); 978#L1681-16true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 62#L830-16true assume 1 == ~t10_pc~0; 49#L831-16true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 326#L833-16true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 610#L842-16true assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1945#L1683-16true assume !(0 != activate_threads_~tmp___9~0#1); 536#L1689-16true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 828#L849-16true assume 1 == ~t11_pc~0; 1593#L850-16true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1808#L852-16true assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1927#L861-16true assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 433#L1691-16true assume !(0 != activate_threads_~tmp___10~0#1); 1705#L1697-16true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 941#L868-16true assume 1 == ~t12_pc~0; 971#L869-16true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 966#L871-16true assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 195#L880-16true assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 356#L1699-16true assume !(0 != activate_threads_~tmp___11~0#1); 810#L1705-16true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 436#L887-16true assume 1 == ~t13_pc~0; 176#L888-16true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 877#L890-16true assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1188#L899-16true assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 68#L1707-16true assume !(0 != activate_threads_~tmp___12~0#1); 1281#L1713-16true assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1909#L1439-1true assume !(1 == ~M_E~0); 170#L1444-1true assume !(1 == ~T1_E~0); 982#L1449-1true assume !(1 == ~T2_E~0); 417#L1454-1true assume !(1 == ~T3_E~0); 1525#L1459-1true assume !(1 == ~T4_E~0); 868#L1464-1true assume !(1 == ~T5_E~0); 918#L1469-1true assume !(1 == ~T6_E~0); 1779#L1474-1true assume !(1 == ~T7_E~0); 672#L1479-1true assume !(1 == ~T8_E~0); 873#L1484-1true assume !(1 == ~T9_E~0); 1318#L1489-1true assume !(1 == ~T10_E~0); 572#L1494-1true assume !(1 == ~T11_E~0); 1891#L1499-1true assume !(1 == ~T12_E~0); 723#L1504-1true assume !(1 == ~T13_E~0); 1576#L1509-1true assume !(1 == ~E_M~0); 1316#L1514-1true assume !(1 == ~E_1~0); 948#L1519-1true assume !(1 == ~E_2~0); 2012#L1524-1true assume !(1 == ~E_3~0); 1750#L1529-1true assume !(1 == ~E_4~0); 1829#L1534-1true assume !(1 == ~E_5~0); 80#L1539-1true assume !(1 == ~E_6~0); 279#L1544-1true assume !(1 == ~E_7~0); 1671#L1549-1true assume !(1 == ~E_8~0); 1687#L1554-1true assume !(1 == ~E_9~0); 1668#L1559-1true assume !(1 == ~E_10~0); 1376#L1564-1true assume !(1 == ~E_11~0); 1730#L1569-1true assume !(1 == ~E_12~0); 1809#L1574-1true assume !(1 == ~E_13~0); 458#L1580-1true assume true;assume { :end_inline_reset_delta_events } true; 487#L1940true [2024-11-17 08:52:58,256 INFO L747 eck$LassoCheckResult]: Loop: 487#L1940true assume true; 625#L1940-1true assume !false; 542#start_simulation_while_15_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 424#L1074true assume !true; 881#L1082true assume true; 1546#L1284true assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2038#L907true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1957#L1291true assume 0 == ~M_E~0;~M_E~0 := 1; 1822#L1296true assume !(0 == ~T1_E~0); 768#L1301true assume 0 == ~T2_E~0;~T2_E~0 := 1; 227#L1306true assume 0 == ~T3_E~0;~T3_E~0 := 1; 904#L1311true assume 0 == ~T4_E~0;~T4_E~0 := 1; 930#L1316true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1453#L1321true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1311#L1326true assume 0 == ~T7_E~0;~T7_E~0 := 1; 886#L1331true assume 0 == ~T8_E~0;~T8_E~0 := 1; 750#L1336true assume !(0 == ~T9_E~0); 1320#L1341true assume 0 == ~T10_E~0;~T10_E~0 := 1; 2024#L1346true assume 0 == ~T11_E~0;~T11_E~0 := 1; 161#L1351true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1298#L1356true assume 0 == ~T13_E~0;~T13_E~0 := 1; 598#L1361true assume 0 == ~E_M~0;~E_M~0 := 1; 215#L1366true assume 0 == ~E_1~0;~E_1~0 := 1; 343#L1371true assume 0 == ~E_2~0;~E_2~0 := 1; 2074#L1376true assume !(0 == ~E_3~0); 2037#L1381true assume 0 == ~E_4~0;~E_4~0 := 1; 294#L1386true assume 0 == ~E_5~0;~E_5~0 := 1; 1498#L1391true assume 0 == ~E_6~0;~E_6~0 := 1; 1637#L1396true assume 0 == ~E_7~0;~E_7~0 := 1; 1974#L1401true assume 0 == ~E_8~0;~E_8~0 := 1; 485#L1406true assume 0 == ~E_9~0;~E_9~0 := 1; 759#L1411true assume 0 == ~E_10~0;~E_10~0 := 1; 2097#L1416true assume !(0 == ~E_11~0); 293#L1421true assume 0 == ~E_12~0;~E_12~0 := 1; 207#L1426true assume 0 == ~E_13~0;~E_13~0 := 1; 1282#L1432true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 932#L640-1true assume 1 == ~m_pc~0; 1653#L641-1true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1924#L643-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 679#L652-1true assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1012#L1603-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 928#L1609-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1854#L659-1true assume !(1 == ~t1_pc~0); 40#L669-1true is_transmit1_triggered_~__retres1~1#1 := 0; 464#L662-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 840#L671-1true assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 574#L1611-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1291#L1617-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1763#L678-1true assume 1 == ~t2_pc~0; 346#L679-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 372#L681-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 805#L690-1true assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 685#L1619-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1166#L1625-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1844#L697-1true assume !(1 == ~t3_pc~0); 869#L707-1true is_transmit3_triggered_~__retres1~3#1 := 0; 328#L700-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 726#L709-1true assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 416#L1627-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 600#L1633-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 120#L716-1true assume 1 == ~t4_pc~0; 317#L717-1true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 308#L719-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2028#L728-1true assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 482#L1635-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 51#L1641-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75#L735-1true assume 1 == ~t5_pc~0; 735#L736-1true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1111#L738-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1366#L747-1true assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 523#L1643-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 603#L1649-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1572#L754-1true assume !(1 == ~t6_pc~0); 493#L764-1true is_transmit6_triggered_~__retres1~6#1 := 0; 1708#L757-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 283#L766-1true assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1489#L1651-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1307#L1657-1true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 135#L773-1true assume 1 == ~t7_pc~0; 1534#L774-1true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1212#L776-1true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1851#L785-1true assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 145#L1659-1true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 537#L1665-1true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1140#L792-1true assume 1 == ~t8_pc~0; 280#L793-1true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1847#L795-1true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1487#L804-1true assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9#L1667-1true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 871#L1673-1true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1999#L811-1true assume 1 == ~t9_pc~0; 908#L812-1true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1775#L814-1true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 479#L823-1true assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 375#L1675-1true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 362#L1681-1true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 253#L830-1true assume 1 == ~t10_pc~0; 1469#L831-1true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 995#L833-1true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1630#L842-1true assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 563#L1683-1true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1392#L1689-1true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 976#L849-1true assume 1 == ~t11_pc~0; 1241#L850-1true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 366#L852-1true assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 548#L861-1true assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2080#L1691-1true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 310#L1697-1true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 888#L868-1true assume 1 == ~t12_pc~0; 1198#L869-1true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 457#L871-1true assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1159#L880-1true assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1561#L1699-1true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1470#L1705-1true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 964#L887-1true assume 1 == ~t13_pc~0; 1962#L888-1true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 462#L890-1true assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1032#L899-1true assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1608#L1707-1true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 154#L1713-1true assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1755#L1439true assume 1 == ~M_E~0;~M_E~0 := 2; 396#L1444true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1738#L1449true assume 1 == ~T2_E~0;~T2_E~0 := 2; 210#L1454true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1091#L1459true assume 1 == ~T4_E~0;~T4_E~0 := 2; 2091#L1464true assume 1 == ~T5_E~0;~T5_E~0 := 2; 945#L1469true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1656#L1474true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1325#L1479true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1520#L1484true assume 1 == ~T9_E~0;~T9_E~0 := 2; 432#L1489true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1274#L1494true assume 1 == ~T11_E~0;~T11_E~0 := 2; 181#L1499true assume 1 == ~T12_E~0;~T12_E~0 := 2; 798#L1504true assume 1 == ~T13_E~0;~T13_E~0 := 2; 309#L1509true assume 1 == ~E_M~0;~E_M~0 := 2; 1491#L1514true assume 1 == ~E_1~0;~E_1~0 := 2; 196#L1519true assume 1 == ~E_2~0;~E_2~0 := 2; 148#L1524true assume 1 == ~E_3~0;~E_3~0 := 2; 264#L1529true assume 1 == ~E_4~0;~E_4~0 := 2; 5#L1534true assume 1 == ~E_5~0;~E_5~0 := 2; 262#L1539true assume 1 == ~E_6~0;~E_6~0 := 2; 483#L1544true assume 1 == ~E_7~0;~E_7~0 := 2; 720#L1549true assume 1 == ~E_8~0;~E_8~0 := 2; 599#L1554true assume 1 == ~E_9~0;~E_9~0 := 2; 1704#L1559true assume 1 == ~E_10~0;~E_10~0 := 2; 1701#L1564true assume 1 == ~E_11~0;~E_11~0 := 2; 1054#L1569true assume 1 == ~E_12~0;~E_12~0 := 2; 724#L1574true assume 1 == ~E_13~0;~E_13~0 := 2; 339#L1580true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 133#L992-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1791#L1046-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 156#L1065-1true assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 138#L1959true assume !(0 == start_simulation_~tmp~3#1); 321#L1970true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 449#L992true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76#L1046true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 545#L1065true assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1485#L1914true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1364#L1916true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1537#L1922true assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1686#L1972true assume !(0 != start_simulation_~tmp___0~1#1); 487#L1940true [2024-11-17 08:52:58,268 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:58,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1347055624, now seen corresponding path program 1 times [2024-11-17 08:52:58,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:58,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919132354] [2024-11-17 08:52:58,276 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:58,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:58,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:58,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:58,546 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:58,546 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [919132354] [2024-11-17 08:52:58,546 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [919132354] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:58,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:58,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:58,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657210363] [2024-11-17 08:52:58,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:58,552 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:58,553 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:58,553 INFO L85 PathProgramCache]: Analyzing trace with hash 224671539, now seen corresponding path program 1 times [2024-11-17 08:52:58,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:58,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [558268640] [2024-11-17 08:52:58,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:58,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:58,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:58,614 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:58,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:58,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [558268640] [2024-11-17 08:52:58,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [558268640] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:58,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:58,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:52:58,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950642501] [2024-11-17 08:52:58,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:58,616 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:58,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:58,645 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-17 08:52:58,646 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-17 08:52:58,650 INFO L87 Difference]: Start difference. First operand has 2108 states, 2107 states have (on average 1.478405315614618) internal successors, (3115), 2107 states have internal predecessors, (3115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 80.5) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:58,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:58,704 INFO L93 Difference]: Finished difference Result 2090 states and 3063 transitions. [2024-11-17 08:52:58,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2090 states and 3063 transitions. [2024-11-17 08:52:58,718 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:52:58,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2090 states to 2083 states and 3056 transitions. [2024-11-17 08:52:58,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:52:58,736 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:52:58,736 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3056 transitions. [2024-11-17 08:52:58,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:58,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3056 transitions. [2024-11-17 08:52:58,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3056 transitions. [2024-11-17 08:52:58,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:52:58,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4671147383581373) internal successors, (3056), 2082 states have internal predecessors, (3056), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:58,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3056 transitions. [2024-11-17 08:52:58,822 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3056 transitions. [2024-11-17 08:52:58,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-17 08:52:58,826 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3056 transitions. [2024-11-17 08:52:58,827 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:52:58,827 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3056 transitions. [2024-11-17 08:52:58,834 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:52:58,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:58,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:58,837 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:58,837 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:58,838 INFO L745 eck$LassoCheckResult]: Stem: 5137#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 5138#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5858#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6207#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6220#L914 assume !(1 == ~m_i~0);~m_st~0 := 2; 5991#L919 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 4642#L924 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4643#L929 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4883#L934 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4884#L939 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5373#L944 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4557#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4558#L954 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5498#L959 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 5499#L964 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4528#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4529#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 6191#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5572#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4749#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 4750#L1296-1 assume !(0 == ~T1_E~0); 5490#L1301-1 assume !(0 == ~T2_E~0); 5491#L1306-1 assume !(0 == ~T3_E~0); 5983#L1311-1 assume !(0 == ~T4_E~0); 4706#L1316-1 assume !(0 == ~T5_E~0); 4707#L1321-1 assume !(0 == ~T6_E~0); 5507#L1326-1 assume !(0 == ~T7_E~0); 4539#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4211#L1336-1 assume !(0 == ~T9_E~0); 4212#L1341-1 assume !(0 == ~T10_E~0); 4299#L1346-1 assume !(0 == ~T11_E~0); 4300#L1351-1 assume !(0 == ~T12_E~0); 4646#L1356-1 assume !(0 == ~T13_E~0); 4647#L1361-1 assume !(0 == ~E_M~0); 6225#L1366-1 assume !(0 == ~E_1~0); 4692#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4693#L1376-1 assume !(0 == ~E_3~0); 5564#L1381-1 assume !(0 == ~E_4~0); 5565#L1386-1 assume !(0 == ~E_5~0); 6249#L1391-1 assume !(0 == ~E_6~0); 6266#L1396-1 assume !(0 == ~E_7~0); 5451#L1401-1 assume !(0 == ~E_8~0); 5452#L1406-1 assume !(0 == ~E_9~0); 5723#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5724#L1416-1 assume !(0 == ~E_11~0); 5378#L1421-1 assume !(0 == ~E_12~0); 4851#L1426-1 assume !(0 == ~E_13~0); 4852#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4874#L640-16 assume 1 == ~m_pc~0; 5962#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5358#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4979#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4980#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 5765#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5178#L659-16 assume 1 == ~t1_pc~0; 4802#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4803#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5848#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4676#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 4677#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4791#L678-16 assume 1 == ~t2_pc~0; 4792#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4728#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4800#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4801#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 6145#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5849#L697-16 assume 1 == ~t3_pc~0; 5850#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4335#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4740#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4264#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 4265#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5233#L716-16 assume 1 == ~t4_pc~0; 5892#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4404#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5648#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5649#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 6256#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6209#L735-16 assume 1 == ~t5_pc~0; 5975#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5976#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6199#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5758#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 5759#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5993#L754-16 assume 1 == ~t6_pc~0; 5994#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5151#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5404#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5405#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 5890#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6128#L773-16 assume 1 == ~t7_pc~0; 4797#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4799#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6289#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4233#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 4234#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5936#L792-16 assume 1 == ~t8_pc~0; 5937#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5408#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4562#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4563#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 6264#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5622#L811-16 assume 1 == ~t9_pc~0; 4793#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4794#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6244#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4774#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 4775#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4333#L830-16 assume 1 == ~t10_pc~0; 4310#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4311#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4834#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5287#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 5180#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5181#L849-16 assume 1 == ~t11_pc~0; 5573#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5773#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6251#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5021#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 5022#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5685#L868-16 assume 1 == ~t12_pc~0; 5686#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4256#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4597#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4598#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 4887#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5027#L887-16 assume 1 == ~t13_pc~0; 4559#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4560#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5623#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4343#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 4344#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5998#L1439-1 assume !(1 == ~M_E~0); 4546#L1444-1 assume !(1 == ~T1_E~0); 4547#L1449-1 assume !(1 == ~T2_E~0); 4994#L1454-1 assume !(1 == ~T3_E~0); 4995#L1459-1 assume !(1 == ~T4_E~0); 5612#L1464-1 assume !(1 == ~T5_E~0); 5613#L1469-1 assume !(1 == ~T6_E~0); 5667#L1474-1 assume !(1 == ~T7_E~0); 5379#L1479-1 assume !(1 == ~T8_E~0); 5380#L1484-1 assume !(1 == ~T9_E~0); 5619#L1489-1 assume !(1 == ~T10_E~0); 5236#L1494-1 assume !(1 == ~T11_E~0); 5237#L1499-1 assume !(1 == ~T12_E~0); 5442#L1504-1 assume !(1 == ~T13_E~0); 5443#L1509-1 assume !(1 == ~E_M~0); 6018#L1514-1 assume !(1 == ~E_1~0); 5696#L1519-1 assume !(1 == ~E_2~0); 5697#L1524-1 assume !(1 == ~E_3~0); 6239#L1529-1 assume !(1 == ~E_4~0); 6240#L1534-1 assume !(1 == ~E_5~0); 4368#L1539-1 assume !(1 == ~E_6~0); 4369#L1544-1 assume !(1 == ~E_7~0); 4762#L1549-1 assume !(1 == ~E_8~0); 6218#L1554-1 assume !(1 == ~E_9~0); 6215#L1559-1 assume !(1 == ~E_10~0); 6065#L1564-1 assume !(1 == ~E_11~0); 6066#L1569-1 assume !(1 == ~E_12~0); 6235#L1574-1 assume !(1 == ~E_13~0); 5060#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 5061#L1940 [2024-11-17 08:52:58,840 INFO L747 eck$LassoCheckResult]: Loop: 5061#L1940 assume true; 5101#L1940-1 assume !false; 5191#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5007#L1074 assume true; 5008#L1074-1 assume !false; 5719#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5707#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4469#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5915#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5916#L1079 assume !(0 != eval_~tmp~0#1); 5630#L1082 assume true; 5631#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6170#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6281#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 6257#L1296 assume !(0 == ~T1_E~0); 5500#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4661#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4662#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5657#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5676#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6016#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5636#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5476#L1336 assume !(0 == ~T9_E~0); 5477#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6019#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4534#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4535#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5274#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 4634#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 4635#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 4864#L1376 assume !(0 == ~E_3~0); 6287#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 4787#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 4788#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 6149#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 6204#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 5098#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 5099#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 5489#L1416 assume !(0 == ~E_11~0); 4786#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 4617#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 4618#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5677#L640-1 assume 1 == ~m_pc~0; 5678#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5955#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5387#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5388#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5674#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5675#L659-1 assume !(1 == ~t1_pc~0); 4290#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 4291#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5068#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5240#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5241#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6003#L678-1 assume 1 == ~t2_pc~0; 4869#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4870#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4912#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5395#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5396#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5910#L697-1 assume !(1 == ~t3_pc~0); 4416#L707-1 is_transmit3_triggered_~__retres1~3#1 := 0; 4415#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4836#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4992#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4993#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4451#L716-1 assume 1 == ~t4_pc~0; 4452#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4809#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4810#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5094#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4317#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4318#L735-1 assume !(1 == ~t5_pc~0); 4324#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 4325#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5859#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5163#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5164#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5279#L754-1 assume 1 == ~t6_pc~0; 4842#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4843#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4770#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4771#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6014#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4483#L773-1 assume 1 == ~t7_pc~0; 4484#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5944#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5945#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4504#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4505#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5182#L792-1 assume 1 == ~t8_pc~0; 4763#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4764#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6146#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4222#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4223#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5615#L811-1 assume !(1 == ~t9_pc~0); 5539#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 5540#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5092#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4917#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4895#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4715#L830-1 assume !(1 == ~t10_pc~0); 4716#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 5717#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5747#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5222#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5223#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5728#L849-1 assume 1 == ~t11_pc~0; 5729#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4900#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4901#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5199#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4815#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4816#L868-1 assume 1 == ~t12_pc~0; 5639#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 5058#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5059#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5904#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 6133#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5714#L887-1 assume 1 == ~t13_pc~0; 5715#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5064#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5065#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 5784#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4521#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4522#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 4960#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4961#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4623#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4624#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5841#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5688#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5689#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6025#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6026#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5019#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5020#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4570#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4571#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4811#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 4812#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 4599#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 4508#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 4509#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 4213#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 4214#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 4733#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 5095#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 5275#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 5276#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 6224#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 5810#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 5444#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 4857#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4478#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4225#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4525#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4490#L1959 assume !(0 == start_simulation_~tmp~3#1); 4492#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4825#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4361#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4362#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 5196#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6055#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6056#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 6162#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 5061#L1940 [2024-11-17 08:52:58,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:58,841 INFO L85 PathProgramCache]: Analyzing trace with hash 1347055624, now seen corresponding path program 2 times [2024-11-17 08:52:58,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:58,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698863021] [2024-11-17 08:52:58,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:58,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:58,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:58,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:58,928 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:58,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698863021] [2024-11-17 08:52:58,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698863021] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:58,929 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:58,929 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:58,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397095864] [2024-11-17 08:52:58,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:58,929 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:58,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:58,930 INFO L85 PathProgramCache]: Analyzing trace with hash 2049855424, now seen corresponding path program 1 times [2024-11-17 08:52:58,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:58,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212160115] [2024-11-17 08:52:58,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:58,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:58,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212160115] [2024-11-17 08:52:59,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212160115] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,082 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,082 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:59,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [997721566] [2024-11-17 08:52:59,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,083 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:59,083 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:59,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:59,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:59,084 INFO L87 Difference]: Start difference. First operand 2083 states and 3056 transitions. cyclomatic complexity: 974 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:59,121 INFO L93 Difference]: Finished difference Result 2083 states and 3055 transitions. [2024-11-17 08:52:59,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3055 transitions. [2024-11-17 08:52:59,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:52:59,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3055 transitions. [2024-11-17 08:52:59,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:52:59,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:52:59,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3055 transitions. [2024-11-17 08:52:59,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:59,143 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3055 transitions. [2024-11-17 08:52:59,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3055 transitions. [2024-11-17 08:52:59,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:52:59,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4666346615458474) internal successors, (3055), 2082 states have internal predecessors, (3055), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3055 transitions. [2024-11-17 08:52:59,172 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3055 transitions. [2024-11-17 08:52:59,173 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:59,176 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3055 transitions. [2024-11-17 08:52:59,176 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:52:59,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3055 transitions. [2024-11-17 08:52:59,184 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:52:59,184 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:59,184 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:59,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:59,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:59,190 INFO L745 eck$LassoCheckResult]: Stem: 9312#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 9313#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 10033#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10382#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10395#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 10166#L919 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 8817#L924 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8818#L929 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9058#L934 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9059#L939 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9548#L944 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8732#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 8733#L954 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9673#L959 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 9674#L964 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8703#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8704#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 10366#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9747#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8924#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 8925#L1296-1 assume !(0 == ~T1_E~0); 9665#L1301-1 assume !(0 == ~T2_E~0); 9666#L1306-1 assume !(0 == ~T3_E~0); 10158#L1311-1 assume !(0 == ~T4_E~0); 8881#L1316-1 assume !(0 == ~T5_E~0); 8882#L1321-1 assume !(0 == ~T6_E~0); 9682#L1326-1 assume !(0 == ~T7_E~0); 8714#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8388#L1336-1 assume !(0 == ~T9_E~0); 8389#L1341-1 assume !(0 == ~T10_E~0); 8474#L1346-1 assume !(0 == ~T11_E~0); 8475#L1351-1 assume !(0 == ~T12_E~0); 8821#L1356-1 assume !(0 == ~T13_E~0); 8822#L1361-1 assume !(0 == ~E_M~0); 10400#L1366-1 assume !(0 == ~E_1~0); 8867#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 8868#L1376-1 assume !(0 == ~E_3~0); 9739#L1381-1 assume !(0 == ~E_4~0); 9740#L1386-1 assume !(0 == ~E_5~0); 10424#L1391-1 assume !(0 == ~E_6~0); 10441#L1396-1 assume !(0 == ~E_7~0); 9626#L1401-1 assume !(0 == ~E_8~0); 9627#L1406-1 assume !(0 == ~E_9~0); 9898#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9899#L1416-1 assume !(0 == ~E_11~0); 9553#L1421-1 assume !(0 == ~E_12~0); 9026#L1426-1 assume !(0 == ~E_13~0); 9027#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9049#L640-16 assume 1 == ~m_pc~0; 10137#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9533#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9154#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9155#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 9940#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9353#L659-16 assume 1 == ~t1_pc~0; 8977#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8978#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10023#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8851#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 8852#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8966#L678-16 assume 1 == ~t2_pc~0; 8967#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8903#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8975#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8976#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 10320#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10024#L697-16 assume 1 == ~t3_pc~0; 10025#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8510#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8915#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8439#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 8440#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9408#L716-16 assume 1 == ~t4_pc~0; 10067#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8579#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9823#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9824#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 10431#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10384#L735-16 assume 1 == ~t5_pc~0; 10150#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10151#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10374#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9933#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 9934#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10168#L754-16 assume 1 == ~t6_pc~0; 10169#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9326#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9579#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9580#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 10065#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10303#L773-16 assume 1 == ~t7_pc~0; 8972#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8974#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10464#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8408#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 8409#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10111#L792-16 assume 1 == ~t8_pc~0; 10112#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9583#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8737#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8738#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 10439#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9797#L811-16 assume 1 == ~t9_pc~0; 8968#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8969#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10419#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8949#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 8950#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8508#L830-16 assume 1 == ~t10_pc~0; 8485#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8486#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9009#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9462#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 9355#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9356#L849-16 assume 1 == ~t11_pc~0; 9748#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9948#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10426#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9196#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 9197#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9860#L868-16 assume 1 == ~t12_pc~0; 9861#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8431#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8773#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8774#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 9062#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9202#L887-16 assume 1 == ~t13_pc~0; 8734#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8735#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9798#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 8518#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 8519#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10173#L1439-1 assume !(1 == ~M_E~0); 8721#L1444-1 assume !(1 == ~T1_E~0); 8722#L1449-1 assume !(1 == ~T2_E~0); 9169#L1454-1 assume !(1 == ~T3_E~0); 9170#L1459-1 assume !(1 == ~T4_E~0); 9787#L1464-1 assume !(1 == ~T5_E~0); 9788#L1469-1 assume !(1 == ~T6_E~0); 9842#L1474-1 assume !(1 == ~T7_E~0); 9554#L1479-1 assume !(1 == ~T8_E~0); 9555#L1484-1 assume !(1 == ~T9_E~0); 9794#L1489-1 assume !(1 == ~T10_E~0); 9411#L1494-1 assume !(1 == ~T11_E~0); 9412#L1499-1 assume !(1 == ~T12_E~0); 9617#L1504-1 assume !(1 == ~T13_E~0); 9618#L1509-1 assume !(1 == ~E_M~0); 10193#L1514-1 assume !(1 == ~E_1~0); 9871#L1519-1 assume !(1 == ~E_2~0); 9872#L1524-1 assume !(1 == ~E_3~0); 10414#L1529-1 assume !(1 == ~E_4~0); 10415#L1534-1 assume !(1 == ~E_5~0); 8543#L1539-1 assume !(1 == ~E_6~0); 8544#L1544-1 assume !(1 == ~E_7~0); 8937#L1549-1 assume !(1 == ~E_8~0); 10393#L1554-1 assume !(1 == ~E_9~0); 10390#L1559-1 assume !(1 == ~E_10~0); 10240#L1564-1 assume !(1 == ~E_11~0); 10241#L1569-1 assume !(1 == ~E_12~0); 10410#L1574-1 assume !(1 == ~E_13~0); 9235#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 9236#L1940 [2024-11-17 08:52:59,190 INFO L747 eck$LassoCheckResult]: Loop: 9236#L1940 assume true; 9276#L1940-1 assume !false; 9366#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9182#L1074 assume true; 9183#L1074-1 assume !false; 9894#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9882#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8644#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 10090#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 10091#L1079 assume !(0 != eval_~tmp~0#1); 9805#L1082 assume true; 9806#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10345#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10456#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 10432#L1296 assume !(0 == ~T1_E~0); 9675#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8836#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8837#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9832#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9851#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10191#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9811#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9651#L1336 assume !(0 == ~T9_E~0); 9652#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10194#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8709#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8710#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9451#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 8809#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 8810#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 9039#L1376 assume !(0 == ~E_3~0); 10462#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 8964#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 8965#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 10324#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 10379#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 9273#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 9274#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 9664#L1416 assume !(0 == ~E_11~0); 8961#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 8792#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 8793#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9852#L640-1 assume 1 == ~m_pc~0; 9853#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10130#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9562#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9563#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9849#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9850#L659-1 assume !(1 == ~t1_pc~0); 8465#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 8466#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9243#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9415#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9416#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10178#L678-1 assume 1 == ~t2_pc~0; 9044#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9045#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9087#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9570#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9571#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10085#L697-1 assume 1 == ~t3_pc~0; 8589#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8590#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9011#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9167#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9168#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8626#L716-1 assume 1 == ~t4_pc~0; 8627#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8984#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8985#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9270#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8492#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8493#L735-1 assume !(1 == ~t5_pc~0); 8499#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 8500#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10034#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9338#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9339#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9454#L754-1 assume 1 == ~t6_pc~0; 9017#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9018#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8945#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8946#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10189#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8658#L773-1 assume 1 == ~t7_pc~0; 8659#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10119#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10120#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8679#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8680#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9357#L792-1 assume 1 == ~t8_pc~0; 8938#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8939#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10321#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8397#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8398#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9790#L811-1 assume !(1 == ~t9_pc~0); 9714#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 9715#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9267#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9092#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9070#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8890#L830-1 assume !(1 == ~t10_pc~0); 8891#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 9892#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9922#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9397#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9398#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9903#L849-1 assume 1 == ~t11_pc~0; 9904#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9075#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9076#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9374#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8990#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8991#L868-1 assume 1 == ~t12_pc~0; 9814#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 9233#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9234#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 10079#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 10308#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9889#L887-1 assume 1 == ~t13_pc~0; 9890#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9239#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9240#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9959#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8696#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8697#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 9135#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9136#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8798#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8799#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10016#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9862#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9863#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10200#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10201#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9194#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9195#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8739#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8740#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8986#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 8987#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 8772#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 8681#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 8682#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 8386#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 8387#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 8908#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 9268#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 9449#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 9450#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 10399#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 9985#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 9619#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 9032#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8653#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8400#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8698#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8663#L1959 assume !(0 == start_simulation_~tmp~3#1); 8665#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9000#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8533#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8534#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 9368#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10230#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10231#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10337#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 9236#L1940 [2024-11-17 08:52:59,191 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:59,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1174641543, now seen corresponding path program 1 times [2024-11-17 08:52:59,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:59,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808670710] [2024-11-17 08:52:59,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:59,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:59,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,254 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,254 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808670710] [2024-11-17 08:52:59,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808670710] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,255 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:59,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2123162531] [2024-11-17 08:52:59,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,255 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:59,256 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:59,256 INFO L85 PathProgramCache]: Analyzing trace with hash 350020413, now seen corresponding path program 1 times [2024-11-17 08:52:59,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:59,256 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [327054725] [2024-11-17 08:52:59,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:59,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:59,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [327054725] [2024-11-17 08:52:59,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [327054725] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,336 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:59,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1643711815] [2024-11-17 08:52:59,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,336 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:59,336 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:59,337 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:59,337 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:59,337 INFO L87 Difference]: Start difference. First operand 2083 states and 3055 transitions. cyclomatic complexity: 973 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:59,370 INFO L93 Difference]: Finished difference Result 2083 states and 3054 transitions. [2024-11-17 08:52:59,370 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3054 transitions. [2024-11-17 08:52:59,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:52:59,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3054 transitions. [2024-11-17 08:52:59,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:52:59,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:52:59,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3054 transitions. [2024-11-17 08:52:59,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:59,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3054 transitions. [2024-11-17 08:52:59,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3054 transitions. [2024-11-17 08:52:59,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:52:59,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4661545847335573) internal successors, (3054), 2082 states have internal predecessors, (3054), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3054 transitions. [2024-11-17 08:52:59,418 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3054 transitions. [2024-11-17 08:52:59,418 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:59,419 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3054 transitions. [2024-11-17 08:52:59,419 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:52:59,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3054 transitions. [2024-11-17 08:52:59,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:52:59,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:59,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:59,428 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:59,428 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:59,428 INFO L745 eck$LassoCheckResult]: Stem: 13487#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 13488#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 14208#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14557#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14570#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 14341#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12992#L924 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 12993#L929 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13233#L934 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13234#L939 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13725#L944 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12907#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12908#L954 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13848#L959 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 13849#L964 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12878#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12879#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14541#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13922#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13099#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 13100#L1296-1 assume !(0 == ~T1_E~0); 13840#L1301-1 assume !(0 == ~T2_E~0); 13841#L1306-1 assume !(0 == ~T3_E~0); 14333#L1311-1 assume !(0 == ~T4_E~0); 13056#L1316-1 assume !(0 == ~T5_E~0); 13057#L1321-1 assume !(0 == ~T6_E~0); 13857#L1326-1 assume !(0 == ~T7_E~0); 12889#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12563#L1336-1 assume !(0 == ~T9_E~0); 12564#L1341-1 assume !(0 == ~T10_E~0); 12649#L1346-1 assume !(0 == ~T11_E~0); 12650#L1351-1 assume !(0 == ~T12_E~0); 12996#L1356-1 assume !(0 == ~T13_E~0); 12997#L1361-1 assume !(0 == ~E_M~0); 14575#L1366-1 assume !(0 == ~E_1~0); 13042#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 13043#L1376-1 assume !(0 == ~E_3~0); 13914#L1381-1 assume !(0 == ~E_4~0); 13915#L1386-1 assume !(0 == ~E_5~0); 14599#L1391-1 assume !(0 == ~E_6~0); 14616#L1396-1 assume !(0 == ~E_7~0); 13801#L1401-1 assume !(0 == ~E_8~0); 13802#L1406-1 assume !(0 == ~E_9~0); 14073#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 14074#L1416-1 assume !(0 == ~E_11~0); 13728#L1421-1 assume !(0 == ~E_12~0); 13201#L1426-1 assume !(0 == ~E_13~0); 13202#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13224#L640-16 assume 1 == ~m_pc~0; 14312#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13708#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13329#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13330#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 14115#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13528#L659-16 assume 1 == ~t1_pc~0; 13152#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13153#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14198#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13026#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 13027#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13141#L678-16 assume 1 == ~t2_pc~0; 13142#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13078#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13150#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13151#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 14495#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14199#L697-16 assume 1 == ~t3_pc~0; 14200#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12685#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13090#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12614#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 12615#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13583#L716-16 assume 1 == ~t4_pc~0; 14242#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12754#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13998#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13999#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 14606#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14559#L735-16 assume 1 == ~t5_pc~0; 14325#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14326#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14549#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14108#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 14109#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14343#L754-16 assume 1 == ~t6_pc~0; 14344#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13501#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13754#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13755#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 14240#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14478#L773-16 assume 1 == ~t7_pc~0; 13147#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13149#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14639#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12583#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 12584#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14286#L792-16 assume 1 == ~t8_pc~0; 14287#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13758#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12912#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12913#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 14614#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13972#L811-16 assume 1 == ~t9_pc~0; 13143#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13144#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14594#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13124#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 13125#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12683#L830-16 assume 1 == ~t10_pc~0; 12660#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12661#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13184#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13637#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 13530#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13531#L849-16 assume 1 == ~t11_pc~0; 13923#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 14123#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14601#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13371#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 13372#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14035#L868-16 assume 1 == ~t12_pc~0; 14036#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12606#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12948#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12949#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 13237#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13377#L887-16 assume 1 == ~t13_pc~0; 12909#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12910#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13973#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 12693#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 12694#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14348#L1439-1 assume !(1 == ~M_E~0); 12896#L1444-1 assume !(1 == ~T1_E~0); 12897#L1449-1 assume !(1 == ~T2_E~0); 13344#L1454-1 assume !(1 == ~T3_E~0); 13345#L1459-1 assume !(1 == ~T4_E~0); 13962#L1464-1 assume !(1 == ~T5_E~0); 13963#L1469-1 assume !(1 == ~T6_E~0); 14017#L1474-1 assume !(1 == ~T7_E~0); 13729#L1479-1 assume !(1 == ~T8_E~0); 13730#L1484-1 assume !(1 == ~T9_E~0); 13969#L1489-1 assume !(1 == ~T10_E~0); 13586#L1494-1 assume !(1 == ~T11_E~0); 13587#L1499-1 assume !(1 == ~T12_E~0); 13792#L1504-1 assume !(1 == ~T13_E~0); 13793#L1509-1 assume !(1 == ~E_M~0); 14368#L1514-1 assume !(1 == ~E_1~0); 14046#L1519-1 assume !(1 == ~E_2~0); 14047#L1524-1 assume !(1 == ~E_3~0); 14589#L1529-1 assume !(1 == ~E_4~0); 14590#L1534-1 assume !(1 == ~E_5~0); 12718#L1539-1 assume !(1 == ~E_6~0); 12719#L1544-1 assume !(1 == ~E_7~0); 13112#L1549-1 assume !(1 == ~E_8~0); 14568#L1554-1 assume !(1 == ~E_9~0); 14565#L1559-1 assume !(1 == ~E_10~0); 14415#L1564-1 assume !(1 == ~E_11~0); 14416#L1569-1 assume !(1 == ~E_12~0); 14585#L1574-1 assume !(1 == ~E_13~0); 13410#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 13411#L1940 [2024-11-17 08:52:59,428 INFO L747 eck$LassoCheckResult]: Loop: 13411#L1940 assume true; 13451#L1940-1 assume !false; 13541#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13357#L1074 assume true; 13358#L1074-1 assume !false; 14069#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 14057#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12819#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 14265#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 14266#L1079 assume !(0 != eval_~tmp~0#1); 13980#L1082 assume true; 13981#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14520#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14631#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 14607#L1296 assume !(0 == ~T1_E~0); 13850#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13011#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13012#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14007#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14026#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14366#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13986#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13826#L1336 assume !(0 == ~T9_E~0); 13827#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14369#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12884#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12885#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13626#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 12984#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 12985#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 13214#L1376 assume !(0 == ~E_3~0); 14637#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 13139#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 13140#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 14499#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 14554#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 13448#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 13449#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 13839#L1416 assume !(0 == ~E_11~0); 13136#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 12967#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 12968#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14027#L640-1 assume 1 == ~m_pc~0; 14028#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 14305#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13737#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13738#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14024#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14025#L659-1 assume !(1 == ~t1_pc~0); 12640#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 12641#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13418#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13590#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13591#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14353#L678-1 assume 1 == ~t2_pc~0; 13219#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13220#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13262#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13745#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13746#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14260#L697-1 assume 1 == ~t3_pc~0; 12764#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12765#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13186#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13342#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13343#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12801#L716-1 assume 1 == ~t4_pc~0; 12802#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13159#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13160#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13445#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12667#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12668#L735-1 assume !(1 == ~t5_pc~0); 12674#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 12675#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14212#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13513#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13514#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13629#L754-1 assume 1 == ~t6_pc~0; 13192#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13193#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13120#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13121#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14364#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12833#L773-1 assume 1 == ~t7_pc~0; 12834#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 14294#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14295#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12854#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12855#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13532#L792-1 assume 1 == ~t8_pc~0; 13113#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13114#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14496#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12572#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12573#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13965#L811-1 assume !(1 == ~t9_pc~0); 13889#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 13890#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13442#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13267#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13245#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13065#L830-1 assume !(1 == ~t10_pc~0); 13066#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 14067#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14096#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13572#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13573#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14076#L849-1 assume 1 == ~t11_pc~0; 14077#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13248#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13249#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13549#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13165#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13166#L868-1 assume 1 == ~t12_pc~0; 13987#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13408#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13409#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14254#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 14483#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14064#L887-1 assume 1 == ~t13_pc~0; 14065#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13414#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13415#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 14134#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 12868#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12869#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 13310#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13311#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12973#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12974#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14190#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14037#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14038#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14375#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14376#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13369#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13370#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12916#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12917#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13161#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 13162#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 12947#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 12856#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 12857#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 12561#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 12562#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 13083#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 13443#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 13624#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 13625#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 14574#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 14160#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 13794#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 13207#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12828#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12575#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12873#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12838#L1959 assume !(0 == start_simulation_~tmp~3#1); 12840#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13175#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12708#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12709#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 13543#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14405#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14406#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14512#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 13411#L1940 [2024-11-17 08:52:59,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:59,429 INFO L85 PathProgramCache]: Analyzing trace with hash -1463319512, now seen corresponding path program 1 times [2024-11-17 08:52:59,429 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:59,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740718146] [2024-11-17 08:52:59,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:59,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:59,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,469 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740718146] [2024-11-17 08:52:59,469 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740718146] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,470 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,470 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:59,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800115101] [2024-11-17 08:52:59,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,470 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:59,470 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:59,471 INFO L85 PathProgramCache]: Analyzing trace with hash 350020413, now seen corresponding path program 2 times [2024-11-17 08:52:59,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:59,471 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420646355] [2024-11-17 08:52:59,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:59,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:59,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,575 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,576 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1420646355] [2024-11-17 08:52:59,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1420646355] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,576 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:59,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247028004] [2024-11-17 08:52:59,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,577 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:59,577 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:59,578 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:59,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:59,578 INFO L87 Difference]: Start difference. First operand 2083 states and 3054 transitions. cyclomatic complexity: 972 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:59,603 INFO L93 Difference]: Finished difference Result 2083 states and 3053 transitions. [2024-11-17 08:52:59,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3053 transitions. [2024-11-17 08:52:59,611 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:52:59,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3053 transitions. [2024-11-17 08:52:59,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:52:59,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:52:59,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3053 transitions. [2024-11-17 08:52:59,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:59,622 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3053 transitions. [2024-11-17 08:52:59,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3053 transitions. [2024-11-17 08:52:59,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:52:59,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4656745079212674) internal successors, (3053), 2082 states have internal predecessors, (3053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3053 transitions. [2024-11-17 08:52:59,648 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3053 transitions. [2024-11-17 08:52:59,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:59,650 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3053 transitions. [2024-11-17 08:52:59,650 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:52:59,650 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3053 transitions. [2024-11-17 08:52:59,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:52:59,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:59,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:59,659 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:59,659 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:59,659 INFO L745 eck$LassoCheckResult]: Stem: 17662#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 17663#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 18383#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18732#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18745#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 18516#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17167#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17168#L929 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 17408#L934 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17409#L939 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17900#L944 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17082#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17083#L954 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18023#L959 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 18024#L964 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17053#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17054#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18716#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 18097#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17274#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 17275#L1296-1 assume !(0 == ~T1_E~0); 18015#L1301-1 assume !(0 == ~T2_E~0); 18016#L1306-1 assume !(0 == ~T3_E~0); 18508#L1311-1 assume !(0 == ~T4_E~0); 17231#L1316-1 assume !(0 == ~T5_E~0); 17232#L1321-1 assume !(0 == ~T6_E~0); 18032#L1326-1 assume !(0 == ~T7_E~0); 17064#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16738#L1336-1 assume !(0 == ~T9_E~0); 16739#L1341-1 assume !(0 == ~T10_E~0); 16824#L1346-1 assume !(0 == ~T11_E~0); 16825#L1351-1 assume !(0 == ~T12_E~0); 17171#L1356-1 assume !(0 == ~T13_E~0); 17172#L1361-1 assume !(0 == ~E_M~0); 18750#L1366-1 assume !(0 == ~E_1~0); 17217#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17218#L1376-1 assume !(0 == ~E_3~0); 18089#L1381-1 assume !(0 == ~E_4~0); 18090#L1386-1 assume !(0 == ~E_5~0); 18774#L1391-1 assume !(0 == ~E_6~0); 18791#L1396-1 assume !(0 == ~E_7~0); 17976#L1401-1 assume !(0 == ~E_8~0); 17977#L1406-1 assume !(0 == ~E_9~0); 18248#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 18249#L1416-1 assume !(0 == ~E_11~0); 17903#L1421-1 assume !(0 == ~E_12~0); 17376#L1426-1 assume !(0 == ~E_13~0); 17377#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17399#L640-16 assume 1 == ~m_pc~0; 18487#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17883#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17504#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17505#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 18290#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17703#L659-16 assume 1 == ~t1_pc~0; 17327#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17328#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18373#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17201#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 17202#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17316#L678-16 assume 1 == ~t2_pc~0; 17317#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17253#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17325#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17326#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 18670#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18374#L697-16 assume 1 == ~t3_pc~0; 18375#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16860#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17265#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16789#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 16790#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17758#L716-16 assume 1 == ~t4_pc~0; 18417#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16929#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18173#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18174#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 18781#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18734#L735-16 assume 1 == ~t5_pc~0; 18500#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18501#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18724#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18283#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 18284#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18518#L754-16 assume 1 == ~t6_pc~0; 18519#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17676#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17929#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17930#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 18415#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18653#L773-16 assume 1 == ~t7_pc~0; 17322#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17324#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18814#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16758#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 16759#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18461#L792-16 assume 1 == ~t8_pc~0; 18462#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17933#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17087#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17088#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 18789#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18147#L811-16 assume 1 == ~t9_pc~0; 17318#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17319#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18769#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17299#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 17300#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16858#L830-16 assume 1 == ~t10_pc~0; 16835#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16836#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17359#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17812#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 17705#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17706#L849-16 assume 1 == ~t11_pc~0; 18098#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18298#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18776#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17546#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 17547#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18210#L868-16 assume 1 == ~t12_pc~0; 18211#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16781#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17123#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17124#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 17412#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17552#L887-16 assume 1 == ~t13_pc~0; 17084#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17085#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 18148#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 16868#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 16869#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18523#L1439-1 assume !(1 == ~M_E~0); 17071#L1444-1 assume !(1 == ~T1_E~0); 17072#L1449-1 assume !(1 == ~T2_E~0); 17519#L1454-1 assume !(1 == ~T3_E~0); 17520#L1459-1 assume !(1 == ~T4_E~0); 18137#L1464-1 assume !(1 == ~T5_E~0); 18138#L1469-1 assume !(1 == ~T6_E~0); 18192#L1474-1 assume !(1 == ~T7_E~0); 17904#L1479-1 assume !(1 == ~T8_E~0); 17905#L1484-1 assume !(1 == ~T9_E~0); 18144#L1489-1 assume !(1 == ~T10_E~0); 17761#L1494-1 assume !(1 == ~T11_E~0); 17762#L1499-1 assume !(1 == ~T12_E~0); 17967#L1504-1 assume !(1 == ~T13_E~0); 17968#L1509-1 assume !(1 == ~E_M~0); 18543#L1514-1 assume !(1 == ~E_1~0); 18221#L1519-1 assume !(1 == ~E_2~0); 18222#L1524-1 assume !(1 == ~E_3~0); 18764#L1529-1 assume !(1 == ~E_4~0); 18765#L1534-1 assume !(1 == ~E_5~0); 16893#L1539-1 assume !(1 == ~E_6~0); 16894#L1544-1 assume !(1 == ~E_7~0); 17287#L1549-1 assume !(1 == ~E_8~0); 18743#L1554-1 assume !(1 == ~E_9~0); 18740#L1559-1 assume !(1 == ~E_10~0); 18590#L1564-1 assume !(1 == ~E_11~0); 18591#L1569-1 assume !(1 == ~E_12~0); 18760#L1574-1 assume !(1 == ~E_13~0); 17585#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 17586#L1940 [2024-11-17 08:52:59,660 INFO L747 eck$LassoCheckResult]: Loop: 17586#L1940 assume true; 17626#L1940-1 assume !false; 17716#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17532#L1074 assume true; 17533#L1074-1 assume !false; 18244#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 18232#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16994#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 18440#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18441#L1079 assume !(0 != eval_~tmp~0#1); 18155#L1082 assume true; 18156#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18695#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18806#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 18782#L1296 assume !(0 == ~T1_E~0); 18025#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17186#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17187#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18182#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18201#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18541#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18161#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18001#L1336 assume !(0 == ~T9_E~0); 18002#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18544#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17059#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17060#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17801#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 17159#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 17160#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 17389#L1376 assume !(0 == ~E_3~0); 18812#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 17314#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 17315#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 18674#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 18729#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 17623#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 17624#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 18014#L1416 assume !(0 == ~E_11~0); 17311#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 17142#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 17143#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18202#L640-1 assume 1 == ~m_pc~0; 18203#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18480#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17912#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17913#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18199#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18200#L659-1 assume 1 == ~t1_pc~0; 18784#L660-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16816#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17593#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17765#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17766#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18528#L678-1 assume 1 == ~t2_pc~0; 17394#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17395#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17437#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17920#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17921#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18435#L697-1 assume 1 == ~t3_pc~0; 16939#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16940#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17361#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17517#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17518#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16977#L716-1 assume 1 == ~t4_pc~0; 16978#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17334#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17335#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17620#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16842#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16843#L735-1 assume !(1 == ~t5_pc~0); 16849#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 16850#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18387#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17688#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17689#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17804#L754-1 assume 1 == ~t6_pc~0; 17367#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17368#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17295#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17296#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18539#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17008#L773-1 assume 1 == ~t7_pc~0; 17009#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18469#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18470#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17029#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17030#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17707#L792-1 assume 1 == ~t8_pc~0; 17288#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17289#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18671#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16747#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16748#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18140#L811-1 assume !(1 == ~t9_pc~0); 18064#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 18065#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17617#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17440#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17420#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17240#L830-1 assume !(1 == ~t10_pc~0); 17241#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 18242#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18271#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17747#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17748#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18251#L849-1 assume 1 == ~t11_pc~0; 18252#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17423#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17424#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17724#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 17340#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17341#L868-1 assume 1 == ~t12_pc~0; 18162#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17583#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17584#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18429#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 18658#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18239#L887-1 assume 1 == ~t13_pc~0; 18240#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17589#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17590#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18309#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 17043#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17044#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 17485#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17486#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17148#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17149#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18365#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18212#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18213#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18550#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18551#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17544#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17545#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17091#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 17092#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17336#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 17337#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 17122#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 17031#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 17032#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 16736#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 16737#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 17258#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 17618#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 17799#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 17800#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 18749#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 18335#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 17969#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 17382#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17003#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16750#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17048#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17013#L1959 assume !(0 == start_simulation_~tmp~3#1); 17015#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17350#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16883#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16884#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 17718#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18580#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18581#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 18687#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 17586#L1940 [2024-11-17 08:52:59,660 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:59,660 INFO L85 PathProgramCache]: Analyzing trace with hash -578583705, now seen corresponding path program 1 times [2024-11-17 08:52:59,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:59,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410986948] [2024-11-17 08:52:59,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:59,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:59,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,697 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1410986948] [2024-11-17 08:52:59,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1410986948] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,697 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:59,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191322761] [2024-11-17 08:52:59,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,697 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:59,698 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:59,698 INFO L85 PathProgramCache]: Analyzing trace with hash -851369158, now seen corresponding path program 1 times [2024-11-17 08:52:59,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:59,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583255210] [2024-11-17 08:52:59,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:59,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:59,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583255210] [2024-11-17 08:52:59,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583255210] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:59,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [332014176] [2024-11-17 08:52:59,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,771 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:59,771 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:59,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:59,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:59,772 INFO L87 Difference]: Start difference. First operand 2083 states and 3053 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:59,795 INFO L93 Difference]: Finished difference Result 2083 states and 3052 transitions. [2024-11-17 08:52:59,795 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3052 transitions. [2024-11-17 08:52:59,803 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:52:59,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3052 transitions. [2024-11-17 08:52:59,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:52:59,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:52:59,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3052 transitions. [2024-11-17 08:52:59,813 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:52:59,813 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3052 transitions. [2024-11-17 08:52:59,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3052 transitions. [2024-11-17 08:52:59,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:52:59,831 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4651944311089775) internal successors, (3052), 2082 states have internal predecessors, (3052), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3052 transitions. [2024-11-17 08:52:59,835 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3052 transitions. [2024-11-17 08:52:59,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:52:59,837 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3052 transitions. [2024-11-17 08:52:59,837 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:52:59,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3052 transitions. [2024-11-17 08:52:59,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:52:59,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:52:59,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:52:59,844 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:59,844 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:52:59,844 INFO L745 eck$LassoCheckResult]: Stem: 21837#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 21838#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 22558#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22907#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22920#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 22691#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21342#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21343#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21583#L934 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 21584#L939 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 22075#L944 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21257#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21258#L954 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22198#L959 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 22199#L964 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21228#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21229#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22891#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 22272#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21449#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 21450#L1296-1 assume !(0 == ~T1_E~0); 22190#L1301-1 assume !(0 == ~T2_E~0); 22191#L1306-1 assume !(0 == ~T3_E~0); 22683#L1311-1 assume !(0 == ~T4_E~0); 21406#L1316-1 assume !(0 == ~T5_E~0); 21407#L1321-1 assume !(0 == ~T6_E~0); 22207#L1326-1 assume !(0 == ~T7_E~0); 21239#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20913#L1336-1 assume !(0 == ~T9_E~0); 20914#L1341-1 assume !(0 == ~T10_E~0); 20999#L1346-1 assume !(0 == ~T11_E~0); 21000#L1351-1 assume !(0 == ~T12_E~0); 21346#L1356-1 assume !(0 == ~T13_E~0); 21347#L1361-1 assume !(0 == ~E_M~0); 22925#L1366-1 assume !(0 == ~E_1~0); 21392#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 21393#L1376-1 assume !(0 == ~E_3~0); 22264#L1381-1 assume !(0 == ~E_4~0); 22265#L1386-1 assume !(0 == ~E_5~0); 22949#L1391-1 assume !(0 == ~E_6~0); 22966#L1396-1 assume !(0 == ~E_7~0); 22151#L1401-1 assume !(0 == ~E_8~0); 22152#L1406-1 assume !(0 == ~E_9~0); 22423#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 22424#L1416-1 assume !(0 == ~E_11~0); 22078#L1421-1 assume !(0 == ~E_12~0); 21551#L1426-1 assume !(0 == ~E_13~0); 21552#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21574#L640-16 assume 1 == ~m_pc~0; 22662#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22058#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21679#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21680#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 22465#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21878#L659-16 assume 1 == ~t1_pc~0; 21502#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21503#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22548#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21376#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 21377#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21491#L678-16 assume 1 == ~t2_pc~0; 21492#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21428#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21500#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21501#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 22845#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22549#L697-16 assume 1 == ~t3_pc~0; 22550#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21035#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21440#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20964#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 20965#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21933#L716-16 assume 1 == ~t4_pc~0; 22592#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21104#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22348#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22349#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 22956#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22909#L735-16 assume 1 == ~t5_pc~0; 22675#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22676#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22899#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22458#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 22459#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22693#L754-16 assume 1 == ~t6_pc~0; 22694#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21851#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22104#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22105#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 22590#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22828#L773-16 assume 1 == ~t7_pc~0; 21497#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21499#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22989#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20933#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 20934#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22636#L792-16 assume 1 == ~t8_pc~0; 22637#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22108#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21262#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21263#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 22964#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22322#L811-16 assume 1 == ~t9_pc~0; 21493#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21494#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22944#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21474#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 21475#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21033#L830-16 assume 1 == ~t10_pc~0; 21010#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21011#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21534#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21987#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 21880#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21881#L849-16 assume 1 == ~t11_pc~0; 22273#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22473#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22951#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21721#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 21722#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22385#L868-16 assume 1 == ~t12_pc~0; 22386#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20956#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21298#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21299#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 21587#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21727#L887-16 assume 1 == ~t13_pc~0; 21259#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21260#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 22323#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21043#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 21044#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22698#L1439-1 assume !(1 == ~M_E~0); 21246#L1444-1 assume !(1 == ~T1_E~0); 21247#L1449-1 assume !(1 == ~T2_E~0); 21694#L1454-1 assume !(1 == ~T3_E~0); 21695#L1459-1 assume !(1 == ~T4_E~0); 22312#L1464-1 assume !(1 == ~T5_E~0); 22313#L1469-1 assume !(1 == ~T6_E~0); 22367#L1474-1 assume !(1 == ~T7_E~0); 22079#L1479-1 assume !(1 == ~T8_E~0); 22080#L1484-1 assume !(1 == ~T9_E~0); 22319#L1489-1 assume !(1 == ~T10_E~0); 21936#L1494-1 assume !(1 == ~T11_E~0); 21937#L1499-1 assume !(1 == ~T12_E~0); 22142#L1504-1 assume !(1 == ~T13_E~0); 22143#L1509-1 assume !(1 == ~E_M~0); 22718#L1514-1 assume !(1 == ~E_1~0); 22396#L1519-1 assume !(1 == ~E_2~0); 22397#L1524-1 assume !(1 == ~E_3~0); 22939#L1529-1 assume !(1 == ~E_4~0); 22940#L1534-1 assume !(1 == ~E_5~0); 21068#L1539-1 assume !(1 == ~E_6~0); 21069#L1544-1 assume !(1 == ~E_7~0); 21462#L1549-1 assume !(1 == ~E_8~0); 22918#L1554-1 assume !(1 == ~E_9~0); 22915#L1559-1 assume !(1 == ~E_10~0); 22765#L1564-1 assume !(1 == ~E_11~0); 22766#L1569-1 assume !(1 == ~E_12~0); 22935#L1574-1 assume !(1 == ~E_13~0); 21760#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 21761#L1940 [2024-11-17 08:52:59,845 INFO L747 eck$LassoCheckResult]: Loop: 21761#L1940 assume true; 21801#L1940-1 assume !false; 21891#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21707#L1074 assume true; 21708#L1074-1 assume !false; 22419#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 22407#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 21169#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 22615#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 22616#L1079 assume !(0 != eval_~tmp~0#1); 22330#L1082 assume true; 22331#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22870#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22981#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 22957#L1296 assume !(0 == ~T1_E~0); 22200#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21361#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21362#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22357#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22376#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22716#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22336#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22176#L1336 assume !(0 == ~T9_E~0); 22177#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22719#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21234#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21235#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21976#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 21334#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 21335#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 21564#L1376 assume !(0 == ~E_3~0); 22987#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 21489#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 21490#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 22849#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 22904#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 21798#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 21799#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 22189#L1416 assume !(0 == ~E_11~0); 21486#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 21317#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 21318#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22377#L640-1 assume 1 == ~m_pc~0; 22378#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22655#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22087#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22088#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22374#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22375#L659-1 assume !(1 == ~t1_pc~0); 20990#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 20991#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21768#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21940#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21941#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22703#L678-1 assume 1 == ~t2_pc~0; 21569#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21570#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21612#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22095#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22096#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22610#L697-1 assume 1 == ~t3_pc~0; 21114#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21115#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21536#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21692#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21693#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21152#L716-1 assume 1 == ~t4_pc~0; 21153#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21509#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21510#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21795#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21017#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21018#L735-1 assume !(1 == ~t5_pc~0); 21024#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 21025#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22562#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21863#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21864#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21979#L754-1 assume 1 == ~t6_pc~0; 21542#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21543#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21470#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21471#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22714#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21183#L773-1 assume 1 == ~t7_pc~0; 21184#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22644#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22645#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21204#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21205#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21882#L792-1 assume 1 == ~t8_pc~0; 21463#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21464#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22846#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20922#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20923#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22315#L811-1 assume 1 == ~t9_pc~0; 22359#L812-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22240#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21792#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21615#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21595#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21415#L830-1 assume !(1 == ~t10_pc~0); 21416#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 22417#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22446#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21922#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21923#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22426#L849-1 assume 1 == ~t11_pc~0; 22427#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21598#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21599#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21899#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 21515#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21516#L868-1 assume 1 == ~t12_pc~0; 22337#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 21758#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21759#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22604#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22833#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22414#L887-1 assume !(1 == ~t13_pc~0); 22416#L897-1 is_transmit13_triggered_~__retres1~13#1 := 0; 21764#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21765#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 22484#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 21218#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21219#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 21660#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21661#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21323#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21324#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22540#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22387#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22388#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22725#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22726#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21719#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21720#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21266#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21267#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21511#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 21512#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 21297#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 21206#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 21207#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 20911#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 20912#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 21433#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 21793#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 21974#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 21975#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 22924#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 22510#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 22144#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 21557#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21178#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20925#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21223#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 21188#L1959 assume !(0 == start_simulation_~tmp~3#1); 21190#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21525#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 21058#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21059#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21893#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22755#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22756#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 22862#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 21761#L1940 [2024-11-17 08:52:59,846 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:59,846 INFO L85 PathProgramCache]: Analyzing trace with hash -272949176, now seen corresponding path program 1 times [2024-11-17 08:52:59,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:59,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1906976640] [2024-11-17 08:52:59,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:59,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:59,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,881 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,882 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1906976640] [2024-11-17 08:52:59,884 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1906976640] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,884 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,884 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:52:59,884 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566583839] [2024-11-17 08:52:59,884 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,884 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:52:59,884 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:52:59,885 INFO L85 PathProgramCache]: Analyzing trace with hash -1510147011, now seen corresponding path program 1 times [2024-11-17 08:52:59,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:52:59,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192205772] [2024-11-17 08:52:59,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:52:59,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:52:59,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:52:59,970 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:52:59,971 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:52:59,971 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192205772] [2024-11-17 08:52:59,971 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192205772] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:52:59,971 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:52:59,971 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:52:59,971 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787382797] [2024-11-17 08:52:59,971 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:52:59,972 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:52:59,972 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:52:59,972 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:52:59,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:52:59,973 INFO L87 Difference]: Start difference. First operand 2083 states and 3052 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:52:59,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:52:59,995 INFO L93 Difference]: Finished difference Result 2083 states and 3051 transitions. [2024-11-17 08:52:59,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3051 transitions. [2024-11-17 08:53:00,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3051 transitions. [2024-11-17 08:53:00,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:53:00,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:53:00,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3051 transitions. [2024-11-17 08:53:00,014 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:00,014 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3051 transitions. [2024-11-17 08:53:00,015 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3051 transitions. [2024-11-17 08:53:00,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:53:00,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4647143542966874) internal successors, (3051), 2082 states have internal predecessors, (3051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3051 transitions. [2024-11-17 08:53:00,040 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3051 transitions. [2024-11-17 08:53:00,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:00,041 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3051 transitions. [2024-11-17 08:53:00,042 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:53:00,042 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3051 transitions. [2024-11-17 08:53:00,046 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:00,047 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:00,048 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,048 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,048 INFO L745 eck$LassoCheckResult]: Stem: 26012#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 26013#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 26733#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27082#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27095#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 26866#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25517#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25518#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25758#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25759#L939 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 26250#L944 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25432#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25433#L954 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26373#L959 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 26374#L964 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25403#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25404#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 27066#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 26447#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25624#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 25625#L1296-1 assume !(0 == ~T1_E~0); 26365#L1301-1 assume !(0 == ~T2_E~0); 26366#L1306-1 assume !(0 == ~T3_E~0); 26858#L1311-1 assume !(0 == ~T4_E~0); 25581#L1316-1 assume !(0 == ~T5_E~0); 25582#L1321-1 assume !(0 == ~T6_E~0); 26382#L1326-1 assume !(0 == ~T7_E~0); 25414#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25088#L1336-1 assume !(0 == ~T9_E~0); 25089#L1341-1 assume !(0 == ~T10_E~0); 25174#L1346-1 assume !(0 == ~T11_E~0); 25175#L1351-1 assume !(0 == ~T12_E~0); 25521#L1356-1 assume !(0 == ~T13_E~0); 25522#L1361-1 assume !(0 == ~E_M~0); 27100#L1366-1 assume !(0 == ~E_1~0); 25567#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 25568#L1376-1 assume !(0 == ~E_3~0); 26439#L1381-1 assume !(0 == ~E_4~0); 26440#L1386-1 assume !(0 == ~E_5~0); 27124#L1391-1 assume !(0 == ~E_6~0); 27141#L1396-1 assume !(0 == ~E_7~0); 26326#L1401-1 assume !(0 == ~E_8~0); 26327#L1406-1 assume !(0 == ~E_9~0); 26598#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 26599#L1416-1 assume !(0 == ~E_11~0); 26253#L1421-1 assume !(0 == ~E_12~0); 25726#L1426-1 assume !(0 == ~E_13~0); 25727#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25749#L640-16 assume 1 == ~m_pc~0; 26837#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26233#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25854#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25855#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 26640#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26053#L659-16 assume 1 == ~t1_pc~0; 25677#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25678#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26723#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25551#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 25552#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25666#L678-16 assume 1 == ~t2_pc~0; 25667#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25603#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25675#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25676#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 27020#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26724#L697-16 assume 1 == ~t3_pc~0; 26725#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25210#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25615#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25139#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 25140#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26108#L716-16 assume 1 == ~t4_pc~0; 26767#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25279#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26523#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26524#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 27131#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27084#L735-16 assume 1 == ~t5_pc~0; 26850#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26851#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27074#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26633#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 26634#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26868#L754-16 assume 1 == ~t6_pc~0; 26869#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26026#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26279#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26280#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 26765#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27003#L773-16 assume 1 == ~t7_pc~0; 25672#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25674#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27164#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25108#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 25109#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26811#L792-16 assume 1 == ~t8_pc~0; 26812#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26283#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25437#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25438#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 27139#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26497#L811-16 assume 1 == ~t9_pc~0; 25668#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25669#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27119#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25649#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 25650#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25208#L830-16 assume 1 == ~t10_pc~0; 25185#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25186#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25709#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26162#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 26056#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26057#L849-16 assume 1 == ~t11_pc~0; 26448#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26648#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27126#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25896#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 25897#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26560#L868-16 assume 1 == ~t12_pc~0; 26561#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25131#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25473#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25474#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 25762#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25902#L887-16 assume 1 == ~t13_pc~0; 25434#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25435#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 26498#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 25224#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 25225#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26873#L1439-1 assume !(1 == ~M_E~0); 25421#L1444-1 assume !(1 == ~T1_E~0); 25422#L1449-1 assume !(1 == ~T2_E~0); 25869#L1454-1 assume !(1 == ~T3_E~0); 25870#L1459-1 assume !(1 == ~T4_E~0); 26487#L1464-1 assume !(1 == ~T5_E~0); 26488#L1469-1 assume !(1 == ~T6_E~0); 26542#L1474-1 assume !(1 == ~T7_E~0); 26254#L1479-1 assume !(1 == ~T8_E~0); 26255#L1484-1 assume !(1 == ~T9_E~0); 26494#L1489-1 assume !(1 == ~T10_E~0); 26111#L1494-1 assume !(1 == ~T11_E~0); 26112#L1499-1 assume !(1 == ~T12_E~0); 26317#L1504-1 assume !(1 == ~T13_E~0); 26318#L1509-1 assume !(1 == ~E_M~0); 26893#L1514-1 assume !(1 == ~E_1~0); 26572#L1519-1 assume !(1 == ~E_2~0); 26573#L1524-1 assume !(1 == ~E_3~0); 27114#L1529-1 assume !(1 == ~E_4~0); 27115#L1534-1 assume !(1 == ~E_5~0); 25243#L1539-1 assume !(1 == ~E_6~0); 25244#L1544-1 assume !(1 == ~E_7~0); 25637#L1549-1 assume !(1 == ~E_8~0); 27093#L1554-1 assume !(1 == ~E_9~0); 27090#L1559-1 assume !(1 == ~E_10~0); 26940#L1564-1 assume !(1 == ~E_11~0); 26941#L1569-1 assume !(1 == ~E_12~0); 27110#L1574-1 assume !(1 == ~E_13~0); 25935#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 25936#L1940 [2024-11-17 08:53:00,049 INFO L747 eck$LassoCheckResult]: Loop: 25936#L1940 assume true; 25976#L1940-1 assume !false; 26066#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25882#L1074 assume true; 25883#L1074-1 assume !false; 26594#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 26582#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 25344#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 26790#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 26791#L1079 assume !(0 != eval_~tmp~0#1); 26505#L1082 assume true; 26506#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27045#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27156#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 27132#L1296 assume !(0 == ~T1_E~0); 26375#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25536#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25537#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26532#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26551#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26891#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26511#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26351#L1336 assume !(0 == ~T9_E~0); 26352#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26894#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25409#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25410#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 26151#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 25509#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 25510#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 25739#L1376 assume !(0 == ~E_3~0); 27162#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 25664#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 25665#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 27024#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 27079#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 25973#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 25974#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 26364#L1416 assume !(0 == ~E_11~0); 25661#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 25492#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 25493#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26552#L640-1 assume 1 == ~m_pc~0; 26553#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26830#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26262#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26263#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26549#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26550#L659-1 assume !(1 == ~t1_pc~0); 25165#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 25166#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25943#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26115#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26116#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26878#L678-1 assume 1 == ~t2_pc~0; 25744#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25745#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25787#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26270#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26271#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26785#L697-1 assume 1 == ~t3_pc~0; 25289#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25290#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25711#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25867#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25868#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25327#L716-1 assume 1 == ~t4_pc~0; 25328#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25684#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25685#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25970#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25192#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25193#L735-1 assume 1 == ~t5_pc~0; 25237#L736-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25200#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26737#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26038#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26039#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26154#L754-1 assume 1 == ~t6_pc~0; 25717#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25718#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25645#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25646#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26889#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25358#L773-1 assume !(1 == ~t7_pc~0); 25360#L783-1 is_transmit7_triggered_~__retres1~7#1 := 0; 26819#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26820#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25379#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25380#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26055#L792-1 assume 1 == ~t8_pc~0; 25638#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25639#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27021#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25097#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25098#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26490#L811-1 assume 1 == ~t9_pc~0; 26534#L812-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26415#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25967#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25792#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25770#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25590#L830-1 assume !(1 == ~t10_pc~0); 25591#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 26592#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26621#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26097#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26098#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26601#L849-1 assume 1 == ~t11_pc~0; 26602#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25773#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25774#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26074#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25690#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25691#L868-1 assume 1 == ~t12_pc~0; 26512#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25933#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25934#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26779#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27008#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26589#L887-1 assume 1 == ~t13_pc~0; 26590#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25939#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25940#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26659#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 25393#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25394#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 25835#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25836#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25498#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25499#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26715#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26562#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26563#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26900#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26901#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25894#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25895#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25441#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25442#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25686#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 25687#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 25472#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 25381#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 25382#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 25086#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 25087#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 25608#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 25968#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 26149#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 26150#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 27099#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 26685#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 26319#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 25732#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25353#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 25100#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25398#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 25363#L1959 assume !(0 == start_simulation_~tmp~3#1); 25365#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25700#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 25233#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25234#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 26068#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26930#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26931#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 27037#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 25936#L1940 [2024-11-17 08:53:00,050 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,050 INFO L85 PathProgramCache]: Analyzing trace with hash 429646663, now seen corresponding path program 1 times [2024-11-17 08:53:00,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,050 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335911432] [2024-11-17 08:53:00,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [335911432] [2024-11-17 08:53:00,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [335911432] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,082 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,082 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:00,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669573159] [2024-11-17 08:53:00,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,083 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:00,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,083 INFO L85 PathProgramCache]: Analyzing trace with hash 1690639802, now seen corresponding path program 1 times [2024-11-17 08:53:00,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085142293] [2024-11-17 08:53:00,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2085142293] [2024-11-17 08:53:00,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2085142293] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:00,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1064433897] [2024-11-17 08:53:00,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,148 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:00,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:00,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:00,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:00,149 INFO L87 Difference]: Start difference. First operand 2083 states and 3051 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:00,172 INFO L93 Difference]: Finished difference Result 2083 states and 3050 transitions. [2024-11-17 08:53:00,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3050 transitions. [2024-11-17 08:53:00,179 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3050 transitions. [2024-11-17 08:53:00,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:53:00,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:53:00,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3050 transitions. [2024-11-17 08:53:00,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:00,189 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3050 transitions. [2024-11-17 08:53:00,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3050 transitions. [2024-11-17 08:53:00,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:53:00,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4642342774843975) internal successors, (3050), 2082 states have internal predecessors, (3050), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3050 transitions. [2024-11-17 08:53:00,210 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3050 transitions. [2024-11-17 08:53:00,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:00,211 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3050 transitions. [2024-11-17 08:53:00,211 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:53:00,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3050 transitions. [2024-11-17 08:53:00,217 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:00,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:00,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,218 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,219 INFO L745 eck$LassoCheckResult]: Stem: 30187#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 30188#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 30908#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31257#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31270#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 31041#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29692#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29693#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29933#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29934#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30425#L944 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 29607#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29608#L954 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 30548#L959 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 30549#L964 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29578#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29579#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31241#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 30622#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29799#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 29800#L1296-1 assume !(0 == ~T1_E~0); 30540#L1301-1 assume !(0 == ~T2_E~0); 30541#L1306-1 assume !(0 == ~T3_E~0); 31033#L1311-1 assume !(0 == ~T4_E~0); 29756#L1316-1 assume !(0 == ~T5_E~0); 29757#L1321-1 assume !(0 == ~T6_E~0); 30557#L1326-1 assume !(0 == ~T7_E~0); 29589#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29263#L1336-1 assume !(0 == ~T9_E~0); 29264#L1341-1 assume !(0 == ~T10_E~0); 29349#L1346-1 assume !(0 == ~T11_E~0); 29350#L1351-1 assume !(0 == ~T12_E~0); 29696#L1356-1 assume !(0 == ~T13_E~0); 29697#L1361-1 assume !(0 == ~E_M~0); 31275#L1366-1 assume !(0 == ~E_1~0); 29742#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29743#L1376-1 assume !(0 == ~E_3~0); 30614#L1381-1 assume !(0 == ~E_4~0); 30615#L1386-1 assume !(0 == ~E_5~0); 31299#L1391-1 assume !(0 == ~E_6~0); 31316#L1396-1 assume !(0 == ~E_7~0); 30501#L1401-1 assume !(0 == ~E_8~0); 30502#L1406-1 assume !(0 == ~E_9~0); 30773#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 30774#L1416-1 assume !(0 == ~E_11~0); 30428#L1421-1 assume !(0 == ~E_12~0); 29901#L1426-1 assume !(0 == ~E_13~0); 29902#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29924#L640-16 assume 1 == ~m_pc~0; 31012#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30408#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30029#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30030#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 30815#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30228#L659-16 assume 1 == ~t1_pc~0; 29852#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29853#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30898#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29726#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 29727#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29841#L678-16 assume 1 == ~t2_pc~0; 29842#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29778#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29850#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29851#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 31195#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30899#L697-16 assume 1 == ~t3_pc~0; 30900#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29385#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29790#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29314#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 29315#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30283#L716-16 assume 1 == ~t4_pc~0; 30942#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29454#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30698#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30699#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 31306#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31259#L735-16 assume 1 == ~t5_pc~0; 31025#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31026#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31249#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30808#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 30809#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31043#L754-16 assume 1 == ~t6_pc~0; 31044#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30201#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30454#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30455#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 30940#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31178#L773-16 assume 1 == ~t7_pc~0; 29847#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29849#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31339#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29283#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 29284#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30986#L792-16 assume 1 == ~t8_pc~0; 30987#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30458#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29612#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29613#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 31314#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30672#L811-16 assume 1 == ~t9_pc~0; 29843#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29844#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31294#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29826#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 29827#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29383#L830-16 assume 1 == ~t10_pc~0; 29360#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 29361#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29884#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30337#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 30231#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30232#L849-16 assume 1 == ~t11_pc~0; 30623#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30823#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31301#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30071#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 30072#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30735#L868-16 assume 1 == ~t12_pc~0; 30736#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29306#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29648#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29649#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 29937#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30077#L887-16 assume 1 == ~t13_pc~0; 29609#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29610#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30673#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 29399#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 29400#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31048#L1439-1 assume !(1 == ~M_E~0); 29596#L1444-1 assume !(1 == ~T1_E~0); 29597#L1449-1 assume !(1 == ~T2_E~0); 30044#L1454-1 assume !(1 == ~T3_E~0); 30045#L1459-1 assume !(1 == ~T4_E~0); 30662#L1464-1 assume !(1 == ~T5_E~0); 30663#L1469-1 assume !(1 == ~T6_E~0); 30717#L1474-1 assume !(1 == ~T7_E~0); 30429#L1479-1 assume !(1 == ~T8_E~0); 30430#L1484-1 assume !(1 == ~T9_E~0); 30669#L1489-1 assume !(1 == ~T10_E~0); 30286#L1494-1 assume !(1 == ~T11_E~0); 30287#L1499-1 assume !(1 == ~T12_E~0); 30492#L1504-1 assume !(1 == ~T13_E~0); 30493#L1509-1 assume !(1 == ~E_M~0); 31068#L1514-1 assume !(1 == ~E_1~0); 30747#L1519-1 assume !(1 == ~E_2~0); 30748#L1524-1 assume !(1 == ~E_3~0); 31289#L1529-1 assume !(1 == ~E_4~0); 31290#L1534-1 assume !(1 == ~E_5~0); 29418#L1539-1 assume !(1 == ~E_6~0); 29419#L1544-1 assume !(1 == ~E_7~0); 29812#L1549-1 assume !(1 == ~E_8~0); 31268#L1554-1 assume !(1 == ~E_9~0); 31265#L1559-1 assume !(1 == ~E_10~0); 31115#L1564-1 assume !(1 == ~E_11~0); 31116#L1569-1 assume !(1 == ~E_12~0); 31285#L1574-1 assume !(1 == ~E_13~0); 30110#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 30111#L1940 [2024-11-17 08:53:00,219 INFO L747 eck$LassoCheckResult]: Loop: 30111#L1940 assume true; 30151#L1940-1 assume !false; 30241#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30057#L1074 assume true; 30058#L1074-1 assume !false; 30769#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 30757#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 29519#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 30965#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 30966#L1079 assume !(0 != eval_~tmp~0#1); 30680#L1082 assume true; 30681#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31220#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31331#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 31307#L1296 assume !(0 == ~T1_E~0); 30550#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29711#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29712#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 30707#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30726#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31066#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30686#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30526#L1336 assume !(0 == ~T9_E~0); 30527#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31069#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29584#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29585#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30326#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 29684#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 29685#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 29914#L1376 assume !(0 == ~E_3~0); 31337#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 29839#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 29840#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 31199#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 31254#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 30148#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 30149#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 30539#L1416 assume !(0 == ~E_11~0); 29836#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 29667#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 29668#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30727#L640-1 assume 1 == ~m_pc~0; 30728#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31005#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30437#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30438#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30724#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30725#L659-1 assume !(1 == ~t1_pc~0); 29340#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 29341#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30118#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30290#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30291#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31053#L678-1 assume !(1 == ~t2_pc~0); 29921#L688-1 is_transmit2_triggered_~__retres1~2#1 := 0; 29920#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29962#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30445#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30446#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30960#L697-1 assume 1 == ~t3_pc~0; 29464#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29465#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29886#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30042#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30043#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29502#L716-1 assume !(1 == ~t4_pc~0); 29504#L726-1 is_transmit4_triggered_~__retres1~4#1 := 0; 29859#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29860#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30145#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29367#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29368#L735-1 assume 1 == ~t5_pc~0; 29412#L736-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29375#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30912#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30213#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30214#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30329#L754-1 assume 1 == ~t6_pc~0; 29892#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29893#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29820#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29821#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31064#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29533#L773-1 assume 1 == ~t7_pc~0; 29534#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30994#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30995#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29551#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29552#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30230#L792-1 assume 1 == ~t8_pc~0; 29813#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29814#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31196#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29272#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29273#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30665#L811-1 assume 1 == ~t9_pc~0; 30709#L812-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30590#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30142#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29967#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29945#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29765#L830-1 assume !(1 == ~t10_pc~0); 29766#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 30767#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30796#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30272#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30273#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30776#L849-1 assume 1 == ~t11_pc~0; 30777#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29948#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29949#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30249#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29865#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29866#L868-1 assume !(1 == ~t12_pc~0); 30688#L878-1 is_transmit12_triggered_~__retres1~12#1 := 0; 30108#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30109#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30954#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 31183#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30764#L887-1 assume 1 == ~t13_pc~0; 30765#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30114#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30115#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30834#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 29568#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29569#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 30010#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30011#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29673#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29674#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30890#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30737#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30738#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31075#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 31076#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30069#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30070#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29616#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29617#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29861#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 29862#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 29647#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 29556#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 29557#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 29261#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 29262#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 29783#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 30143#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 30324#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 30325#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 31274#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 30860#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 30494#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 29907#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29528#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 29275#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29573#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29538#L1959 assume !(0 == start_simulation_~tmp~3#1); 29540#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29875#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 29408#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29409#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 30243#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31105#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31106#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 31212#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 30111#L1940 [2024-11-17 08:53:00,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,219 INFO L85 PathProgramCache]: Analyzing trace with hash -517520280, now seen corresponding path program 1 times [2024-11-17 08:53:00,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395437127] [2024-11-17 08:53:00,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395437127] [2024-11-17 08:53:00,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395437127] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,253 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:00,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465227075] [2024-11-17 08:53:00,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,253 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:00,254 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,254 INFO L85 PathProgramCache]: Analyzing trace with hash -880271872, now seen corresponding path program 1 times [2024-11-17 08:53:00,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846397759] [2024-11-17 08:53:00,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,334 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846397759] [2024-11-17 08:53:00,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1846397759] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,335 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:00,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609435348] [2024-11-17 08:53:00,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,336 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:00,336 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:00,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:00,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:00,336 INFO L87 Difference]: Start difference. First operand 2083 states and 3050 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:00,357 INFO L93 Difference]: Finished difference Result 2083 states and 3049 transitions. [2024-11-17 08:53:00,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3049 transitions. [2024-11-17 08:53:00,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,369 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3049 transitions. [2024-11-17 08:53:00,369 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:53:00,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:53:00,370 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3049 transitions. [2024-11-17 08:53:00,372 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:00,372 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3049 transitions. [2024-11-17 08:53:00,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3049 transitions. [2024-11-17 08:53:00,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:53:00,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4637542006721076) internal successors, (3049), 2082 states have internal predecessors, (3049), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3049 transitions. [2024-11-17 08:53:00,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3049 transitions. [2024-11-17 08:53:00,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:00,393 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3049 transitions. [2024-11-17 08:53:00,393 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:53:00,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3049 transitions. [2024-11-17 08:53:00,398 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:00,398 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:00,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,400 INFO L745 eck$LassoCheckResult]: Stem: 34362#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 34363#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 35083#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35432#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35445#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 35216#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33869#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33870#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34108#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34109#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34600#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33782#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33783#L954 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 34723#L959 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 34724#L964 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33753#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33754#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35416#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 34797#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33974#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 33975#L1296-1 assume !(0 == ~T1_E~0); 34715#L1301-1 assume !(0 == ~T2_E~0); 34716#L1306-1 assume !(0 == ~T3_E~0); 35208#L1311-1 assume !(0 == ~T4_E~0); 33931#L1316-1 assume !(0 == ~T5_E~0); 33932#L1321-1 assume !(0 == ~T6_E~0); 34732#L1326-1 assume !(0 == ~T7_E~0); 33764#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33438#L1336-1 assume !(0 == ~T9_E~0); 33439#L1341-1 assume !(0 == ~T10_E~0); 33524#L1346-1 assume !(0 == ~T11_E~0); 33525#L1351-1 assume !(0 == ~T12_E~0); 33871#L1356-1 assume !(0 == ~T13_E~0); 33872#L1361-1 assume !(0 == ~E_M~0); 35450#L1366-1 assume !(0 == ~E_1~0); 33917#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 33918#L1376-1 assume !(0 == ~E_3~0); 34789#L1381-1 assume !(0 == ~E_4~0); 34790#L1386-1 assume !(0 == ~E_5~0); 35474#L1391-1 assume !(0 == ~E_6~0); 35491#L1396-1 assume !(0 == ~E_7~0); 34676#L1401-1 assume !(0 == ~E_8~0); 34677#L1406-1 assume !(0 == ~E_9~0); 34948#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 34949#L1416-1 assume !(0 == ~E_11~0); 34603#L1421-1 assume !(0 == ~E_12~0); 34076#L1426-1 assume !(0 == ~E_13~0); 34077#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34099#L640-16 assume 1 == ~m_pc~0; 35187#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 34583#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34204#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34205#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 34990#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34403#L659-16 assume 1 == ~t1_pc~0; 34027#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34028#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35073#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33901#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 33902#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34016#L678-16 assume 1 == ~t2_pc~0; 34017#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33953#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34025#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34026#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 35370#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35074#L697-16 assume 1 == ~t3_pc~0; 35075#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33560#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33965#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33489#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 33490#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34458#L716-16 assume 1 == ~t4_pc~0; 35117#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33629#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34873#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34874#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 35481#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35434#L735-16 assume 1 == ~t5_pc~0; 35200#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35201#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35424#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34983#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 34984#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35218#L754-16 assume 1 == ~t6_pc~0; 35219#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34376#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34629#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34630#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 35115#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35353#L773-16 assume 1 == ~t7_pc~0; 34022#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34024#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35514#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33458#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 33459#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35161#L792-16 assume 1 == ~t8_pc~0; 35162#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34633#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33787#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33788#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 35489#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34847#L811-16 assume 1 == ~t9_pc~0; 34018#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34019#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35469#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34001#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 34002#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33558#L830-16 assume 1 == ~t10_pc~0; 33535#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33536#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34059#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34512#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 34406#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34407#L849-16 assume 1 == ~t11_pc~0; 34798#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34998#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35476#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34246#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 34247#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34910#L868-16 assume 1 == ~t12_pc~0; 34911#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 33481#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33823#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33824#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 34112#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34252#L887-16 assume 1 == ~t13_pc~0; 33784#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33785#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34848#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 33574#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 33575#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35223#L1439-1 assume !(1 == ~M_E~0); 33771#L1444-1 assume !(1 == ~T1_E~0); 33772#L1449-1 assume !(1 == ~T2_E~0); 34219#L1454-1 assume !(1 == ~T3_E~0); 34220#L1459-1 assume !(1 == ~T4_E~0); 34837#L1464-1 assume !(1 == ~T5_E~0); 34838#L1469-1 assume !(1 == ~T6_E~0); 34892#L1474-1 assume !(1 == ~T7_E~0); 34604#L1479-1 assume !(1 == ~T8_E~0); 34605#L1484-1 assume !(1 == ~T9_E~0); 34844#L1489-1 assume !(1 == ~T10_E~0); 34461#L1494-1 assume !(1 == ~T11_E~0); 34462#L1499-1 assume !(1 == ~T12_E~0); 34667#L1504-1 assume !(1 == ~T13_E~0); 34668#L1509-1 assume !(1 == ~E_M~0); 35243#L1514-1 assume !(1 == ~E_1~0); 34922#L1519-1 assume !(1 == ~E_2~0); 34923#L1524-1 assume !(1 == ~E_3~0); 35464#L1529-1 assume !(1 == ~E_4~0); 35465#L1534-1 assume !(1 == ~E_5~0); 33593#L1539-1 assume !(1 == ~E_6~0); 33594#L1544-1 assume !(1 == ~E_7~0); 33987#L1549-1 assume !(1 == ~E_8~0); 35443#L1554-1 assume !(1 == ~E_9~0); 35440#L1559-1 assume !(1 == ~E_10~0); 35290#L1564-1 assume !(1 == ~E_11~0); 35291#L1569-1 assume !(1 == ~E_12~0); 35460#L1574-1 assume !(1 == ~E_13~0); 34285#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 34286#L1940 [2024-11-17 08:53:00,400 INFO L747 eck$LassoCheckResult]: Loop: 34286#L1940 assume true; 34326#L1940-1 assume !false; 34416#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34232#L1074 assume true; 34233#L1074-1 assume !false; 34944#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34932#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33694#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35140#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 35141#L1079 assume !(0 != eval_~tmp~0#1); 34855#L1082 assume true; 34856#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35395#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35506#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 35482#L1296 assume !(0 == ~T1_E~0); 34725#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33886#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33887#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 34882#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 34901#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35241#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34861#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34701#L1336 assume !(0 == ~T9_E~0); 34702#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35244#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33759#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33760#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34501#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 33859#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 33860#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 34089#L1376 assume !(0 == ~E_3~0); 35512#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 34014#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 34015#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 35374#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 35429#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 34323#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 34324#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 34714#L1416 assume !(0 == ~E_11~0); 34011#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 33842#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 33843#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34902#L640-1 assume 1 == ~m_pc~0; 34903#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35180#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34612#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34613#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34899#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34900#L659-1 assume !(1 == ~t1_pc~0); 33515#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 33516#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34293#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34465#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34466#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35228#L678-1 assume !(1 == ~t2_pc~0); 34096#L688-1 is_transmit2_triggered_~__retres1~2#1 := 0; 34095#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34137#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34620#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34621#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35135#L697-1 assume 1 == ~t3_pc~0; 33639#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33640#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34061#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34217#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34218#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33677#L716-1 assume 1 == ~t4_pc~0; 33678#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34034#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34035#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34320#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 33542#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33543#L735-1 assume 1 == ~t5_pc~0; 33587#L736-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33550#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 35087#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34388#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34389#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34504#L754-1 assume 1 == ~t6_pc~0; 34067#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34068#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33993#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33994#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35239#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33705#L773-1 assume 1 == ~t7_pc~0; 33706#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35169#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35170#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33726#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33727#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34405#L792-1 assume 1 == ~t8_pc~0; 33988#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33989#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35371#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33447#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33448#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34840#L811-1 assume 1 == ~t9_pc~0; 34884#L812-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34765#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34317#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34142#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34120#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33940#L830-1 assume !(1 == ~t10_pc~0); 33941#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 34942#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34971#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34447#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34448#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34951#L849-1 assume 1 == ~t11_pc~0; 34952#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34125#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34126#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34424#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34040#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34041#L868-1 assume 1 == ~t12_pc~0; 34862#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34283#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34284#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 35129#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 35358#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34939#L887-1 assume 1 == ~t13_pc~0; 34940#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 34289#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34290#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 35009#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 33743#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33744#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 34185#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34186#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33848#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33849#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35065#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34912#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34913#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35250#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35251#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34244#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34245#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33791#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33792#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34036#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 34037#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 33822#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 33731#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 33732#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 33436#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 33437#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 33958#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 34318#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 34499#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 34500#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 35449#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 35035#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 34669#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 34082#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33703#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33450#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33748#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 33713#L1959 assume !(0 == start_simulation_~tmp~3#1); 33715#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34050#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33583#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33584#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 34418#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35280#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35281#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 35387#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 34286#L1940 [2024-11-17 08:53:00,401 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,401 INFO L85 PathProgramCache]: Analyzing trace with hash -1240810713, now seen corresponding path program 1 times [2024-11-17 08:53:00,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092507415] [2024-11-17 08:53:00,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,434 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092507415] [2024-11-17 08:53:00,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2092507415] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,434 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,435 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:00,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345724619] [2024-11-17 08:53:00,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,435 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:00,435 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,435 INFO L85 PathProgramCache]: Analyzing trace with hash -1307781510, now seen corresponding path program 1 times [2024-11-17 08:53:00,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801986635] [2024-11-17 08:53:00,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,495 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,495 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801986635] [2024-11-17 08:53:00,495 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801986635] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,495 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,495 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:00,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887371957] [2024-11-17 08:53:00,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,495 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:00,496 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:00,496 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:00,496 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:00,496 INFO L87 Difference]: Start difference. First operand 2083 states and 3049 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:00,518 INFO L93 Difference]: Finished difference Result 2083 states and 3048 transitions. [2024-11-17 08:53:00,518 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3048 transitions. [2024-11-17 08:53:00,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3048 transitions. [2024-11-17 08:53:00,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:53:00,536 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:53:00,537 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3048 transitions. [2024-11-17 08:53:00,539 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:00,539 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3048 transitions. [2024-11-17 08:53:00,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3048 transitions. [2024-11-17 08:53:00,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:53:00,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4632741238598175) internal successors, (3048), 2082 states have internal predecessors, (3048), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3048 transitions. [2024-11-17 08:53:00,567 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3048 transitions. [2024-11-17 08:53:00,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:00,568 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3048 transitions. [2024-11-17 08:53:00,568 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:53:00,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3048 transitions. [2024-11-17 08:53:00,573 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:00,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:00,575 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,575 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,575 INFO L745 eck$LassoCheckResult]: Stem: 38537#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 38538#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 39258#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39607#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39620#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 39391#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38044#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38045#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38283#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38284#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38775#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37957#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37958#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38898#L959 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 38899#L964 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37928#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37929#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39591#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38972#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38149#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 38150#L1296-1 assume !(0 == ~T1_E~0); 38890#L1301-1 assume !(0 == ~T2_E~0); 38891#L1306-1 assume !(0 == ~T3_E~0); 39383#L1311-1 assume !(0 == ~T4_E~0); 38106#L1316-1 assume !(0 == ~T5_E~0); 38107#L1321-1 assume !(0 == ~T6_E~0); 38907#L1326-1 assume !(0 == ~T7_E~0); 37939#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37613#L1336-1 assume !(0 == ~T9_E~0); 37614#L1341-1 assume !(0 == ~T10_E~0); 37699#L1346-1 assume !(0 == ~T11_E~0); 37700#L1351-1 assume !(0 == ~T12_E~0); 38046#L1356-1 assume !(0 == ~T13_E~0); 38047#L1361-1 assume !(0 == ~E_M~0); 39625#L1366-1 assume !(0 == ~E_1~0); 38092#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 38093#L1376-1 assume !(0 == ~E_3~0); 38964#L1381-1 assume !(0 == ~E_4~0); 38965#L1386-1 assume !(0 == ~E_5~0); 39649#L1391-1 assume !(0 == ~E_6~0); 39666#L1396-1 assume !(0 == ~E_7~0); 38851#L1401-1 assume !(0 == ~E_8~0); 38852#L1406-1 assume !(0 == ~E_9~0); 39123#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 39124#L1416-1 assume !(0 == ~E_11~0); 38778#L1421-1 assume !(0 == ~E_12~0); 38251#L1426-1 assume !(0 == ~E_13~0); 38252#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38274#L640-16 assume 1 == ~m_pc~0; 39362#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 38758#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38379#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38380#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 39165#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38578#L659-16 assume 1 == ~t1_pc~0; 38204#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38205#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39248#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38076#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 38077#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38191#L678-16 assume 1 == ~t2_pc~0; 38192#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38128#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38200#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38201#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 39545#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39249#L697-16 assume 1 == ~t3_pc~0; 39250#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37735#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38140#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37664#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 37665#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38633#L716-16 assume 1 == ~t4_pc~0; 39292#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37804#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39048#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39049#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 39656#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39609#L735-16 assume 1 == ~t5_pc~0; 39375#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39376#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39599#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39158#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 39159#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39393#L754-16 assume 1 == ~t6_pc~0; 39394#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38551#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38804#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38805#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 39290#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39528#L773-16 assume 1 == ~t7_pc~0; 38197#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38199#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39689#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37633#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 37634#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39336#L792-16 assume 1 == ~t8_pc~0; 39337#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38808#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37962#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37963#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 39664#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39022#L811-16 assume 1 == ~t9_pc~0; 38193#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38194#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39644#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38176#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 38177#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37733#L830-16 assume 1 == ~t10_pc~0; 37710#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37711#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38234#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38687#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 38581#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38582#L849-16 assume 1 == ~t11_pc~0; 38973#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39173#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39651#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38421#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 38422#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39085#L868-16 assume 1 == ~t12_pc~0; 39086#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37656#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37998#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37999#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 38287#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38427#L887-16 assume 1 == ~t13_pc~0; 37959#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37960#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39023#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 37749#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 37750#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39398#L1439-1 assume !(1 == ~M_E~0); 37946#L1444-1 assume !(1 == ~T1_E~0); 37947#L1449-1 assume !(1 == ~T2_E~0); 38396#L1454-1 assume !(1 == ~T3_E~0); 38397#L1459-1 assume !(1 == ~T4_E~0); 39012#L1464-1 assume !(1 == ~T5_E~0); 39013#L1469-1 assume !(1 == ~T6_E~0); 39067#L1474-1 assume !(1 == ~T7_E~0); 38779#L1479-1 assume !(1 == ~T8_E~0); 38780#L1484-1 assume !(1 == ~T9_E~0); 39019#L1489-1 assume !(1 == ~T10_E~0); 38636#L1494-1 assume !(1 == ~T11_E~0); 38637#L1499-1 assume !(1 == ~T12_E~0); 38842#L1504-1 assume !(1 == ~T13_E~0); 38843#L1509-1 assume !(1 == ~E_M~0); 39418#L1514-1 assume !(1 == ~E_1~0); 39097#L1519-1 assume !(1 == ~E_2~0); 39098#L1524-1 assume !(1 == ~E_3~0); 39639#L1529-1 assume !(1 == ~E_4~0); 39640#L1534-1 assume !(1 == ~E_5~0); 37768#L1539-1 assume !(1 == ~E_6~0); 37769#L1544-1 assume !(1 == ~E_7~0); 38162#L1549-1 assume !(1 == ~E_8~0); 39618#L1554-1 assume !(1 == ~E_9~0); 39615#L1559-1 assume !(1 == ~E_10~0); 39465#L1564-1 assume !(1 == ~E_11~0); 39466#L1569-1 assume !(1 == ~E_12~0); 39635#L1574-1 assume !(1 == ~E_13~0); 38460#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 38461#L1940 [2024-11-17 08:53:00,575 INFO L747 eck$LassoCheckResult]: Loop: 38461#L1940 assume true; 38501#L1940-1 assume !false; 38591#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38407#L1074 assume true; 38408#L1074-1 assume !false; 39119#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 39107#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37869#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39315#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 39316#L1079 assume !(0 != eval_~tmp~0#1); 39030#L1082 assume true; 39031#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39570#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 39681#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 39657#L1296 assume !(0 == ~T1_E~0); 38900#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38061#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38062#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39057#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39076#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39416#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39036#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38876#L1336 assume !(0 == ~T9_E~0); 38877#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39419#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37934#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37935#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38676#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 38034#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 38035#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 38264#L1376 assume !(0 == ~E_3~0); 39687#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 38189#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 38190#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 39549#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 39604#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 38498#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 38499#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 38889#L1416 assume !(0 == ~E_11~0); 38186#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 38017#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 38018#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39077#L640-1 assume 1 == ~m_pc~0; 39078#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39355#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38787#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38788#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 39074#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39075#L659-1 assume !(1 == ~t1_pc~0); 37690#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 37691#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38468#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38640#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38641#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39403#L678-1 assume 1 == ~t2_pc~0; 38269#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38270#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38312#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38795#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38796#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39310#L697-1 assume 1 == ~t3_pc~0; 37814#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37815#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38236#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38392#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38393#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37852#L716-1 assume 1 == ~t4_pc~0; 37853#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38209#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38210#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38495#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 37717#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37718#L735-1 assume 1 == ~t5_pc~0; 37762#L736-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37725#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39262#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38561#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38562#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38679#L754-1 assume 1 == ~t6_pc~0; 38240#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38241#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38170#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38171#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39414#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37880#L773-1 assume 1 == ~t7_pc~0; 37881#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39344#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39345#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37901#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37902#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38580#L792-1 assume 1 == ~t8_pc~0; 38163#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38164#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39546#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37622#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37623#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39015#L811-1 assume 1 == ~t9_pc~0; 39059#L812-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38940#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38492#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38317#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38295#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38115#L830-1 assume !(1 == ~t10_pc~0); 38116#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 39117#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39146#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38622#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38623#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39126#L849-1 assume 1 == ~t11_pc~0; 39127#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38300#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38301#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38599#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38215#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38216#L868-1 assume 1 == ~t12_pc~0; 39037#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38458#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38459#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 39304#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39533#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39114#L887-1 assume 1 == ~t13_pc~0; 39115#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38464#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38465#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 39184#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 37918#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37919#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 38360#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38361#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38023#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38024#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39240#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39087#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39088#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39425#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39426#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38419#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38420#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37966#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37967#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38211#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 38212#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 37997#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 37908#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 37909#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 37611#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 37612#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 38133#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 38493#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 38674#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 38675#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 39624#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 39210#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 38844#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 38257#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37878#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37625#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37923#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 37888#L1959 assume !(0 == start_simulation_~tmp~3#1); 37890#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38225#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37758#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37759#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38593#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39455#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39456#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 39562#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 38461#L1940 [2024-11-17 08:53:00,576 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,576 INFO L85 PathProgramCache]: Analyzing trace with hash -1433741914, now seen corresponding path program 1 times [2024-11-17 08:53:00,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2055385422] [2024-11-17 08:53:00,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,608 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,609 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2055385422] [2024-11-17 08:53:00,609 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2055385422] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,609 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,609 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:00,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [7316652] [2024-11-17 08:53:00,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,610 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:00,610 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,610 INFO L85 PathProgramCache]: Analyzing trace with hash 447486007, now seen corresponding path program 1 times [2024-11-17 08:53:00,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,610 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726063860] [2024-11-17 08:53:00,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,701 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,701 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726063860] [2024-11-17 08:53:00,701 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1726063860] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,701 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,702 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:00,702 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105217429] [2024-11-17 08:53:00,702 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,702 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:00,702 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:00,703 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:00,703 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:00,703 INFO L87 Difference]: Start difference. First operand 2083 states and 3048 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:00,732 INFO L93 Difference]: Finished difference Result 2083 states and 3047 transitions. [2024-11-17 08:53:00,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3047 transitions. [2024-11-17 08:53:00,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3047 transitions. [2024-11-17 08:53:00,745 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:53:00,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:53:00,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3047 transitions. [2024-11-17 08:53:00,748 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:00,748 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3047 transitions. [2024-11-17 08:53:00,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3047 transitions. [2024-11-17 08:53:00,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:53:00,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4627940470475276) internal successors, (3047), 2082 states have internal predecessors, (3047), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3047 transitions. [2024-11-17 08:53:00,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3047 transitions. [2024-11-17 08:53:00,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:00,780 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3047 transitions. [2024-11-17 08:53:00,781 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:53:00,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3047 transitions. [2024-11-17 08:53:00,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:00,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:00,788 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,788 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,788 INFO L745 eck$LassoCheckResult]: Stem: 42712#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 42713#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 43433#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43782#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43795#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 43566#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42219#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42220#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42458#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42459#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42950#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42132#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42133#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 43073#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 43074#L964 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 42103#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 42104#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43766#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 43147#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42324#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 42325#L1296-1 assume !(0 == ~T1_E~0); 43065#L1301-1 assume !(0 == ~T2_E~0); 43066#L1306-1 assume !(0 == ~T3_E~0); 43558#L1311-1 assume !(0 == ~T4_E~0); 42281#L1316-1 assume !(0 == ~T5_E~0); 42282#L1321-1 assume !(0 == ~T6_E~0); 43082#L1326-1 assume !(0 == ~T7_E~0); 42114#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41788#L1336-1 assume !(0 == ~T9_E~0); 41789#L1341-1 assume !(0 == ~T10_E~0); 41874#L1346-1 assume !(0 == ~T11_E~0); 41875#L1351-1 assume !(0 == ~T12_E~0); 42221#L1356-1 assume !(0 == ~T13_E~0); 42222#L1361-1 assume !(0 == ~E_M~0); 43800#L1366-1 assume !(0 == ~E_1~0); 42268#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 42269#L1376-1 assume !(0 == ~E_3~0); 43139#L1381-1 assume !(0 == ~E_4~0); 43140#L1386-1 assume !(0 == ~E_5~0); 43824#L1391-1 assume !(0 == ~E_6~0); 43841#L1396-1 assume !(0 == ~E_7~0); 43026#L1401-1 assume !(0 == ~E_8~0); 43027#L1406-1 assume !(0 == ~E_9~0); 43298#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 43299#L1416-1 assume !(0 == ~E_11~0); 42953#L1421-1 assume !(0 == ~E_12~0); 42426#L1426-1 assume !(0 == ~E_13~0); 42427#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42449#L640-16 assume 1 == ~m_pc~0; 43537#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 42933#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42554#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42555#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 43340#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42753#L659-16 assume 1 == ~t1_pc~0; 42379#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42380#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43423#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42251#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 42252#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42366#L678-16 assume 1 == ~t2_pc~0; 42367#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42305#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42375#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42376#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 43720#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43424#L697-16 assume 1 == ~t3_pc~0; 43425#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41910#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42315#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41839#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 41840#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42808#L716-16 assume 1 == ~t4_pc~0; 43467#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41979#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43223#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43224#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 43831#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43784#L735-16 assume 1 == ~t5_pc~0; 43550#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43551#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43774#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43333#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 43334#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43568#L754-16 assume 1 == ~t6_pc~0; 43569#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 42726#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42979#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42980#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 43465#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43703#L773-16 assume 1 == ~t7_pc~0; 42372#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42374#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43864#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41808#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 41809#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43511#L792-16 assume 1 == ~t8_pc~0; 43512#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42983#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42137#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42138#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 43839#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43197#L811-16 assume 1 == ~t9_pc~0; 42368#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42369#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43819#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42351#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 42352#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41908#L830-16 assume 1 == ~t10_pc~0; 41885#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41886#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42409#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42862#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 42756#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42757#L849-16 assume 1 == ~t11_pc~0; 43148#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43348#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43826#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42596#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 42597#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43260#L868-16 assume 1 == ~t12_pc~0; 43261#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 41831#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42173#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42174#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 42462#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42602#L887-16 assume 1 == ~t13_pc~0; 42134#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42135#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 43198#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 41924#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 41925#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43573#L1439-1 assume !(1 == ~M_E~0); 42121#L1444-1 assume !(1 == ~T1_E~0); 42122#L1449-1 assume !(1 == ~T2_E~0); 42571#L1454-1 assume !(1 == ~T3_E~0); 42572#L1459-1 assume !(1 == ~T4_E~0); 43187#L1464-1 assume !(1 == ~T5_E~0); 43188#L1469-1 assume !(1 == ~T6_E~0); 43242#L1474-1 assume !(1 == ~T7_E~0); 42954#L1479-1 assume !(1 == ~T8_E~0); 42955#L1484-1 assume !(1 == ~T9_E~0); 43194#L1489-1 assume !(1 == ~T10_E~0); 42811#L1494-1 assume !(1 == ~T11_E~0); 42812#L1499-1 assume !(1 == ~T12_E~0); 43017#L1504-1 assume !(1 == ~T13_E~0); 43018#L1509-1 assume !(1 == ~E_M~0); 43593#L1514-1 assume !(1 == ~E_1~0); 43272#L1519-1 assume !(1 == ~E_2~0); 43273#L1524-1 assume !(1 == ~E_3~0); 43814#L1529-1 assume !(1 == ~E_4~0); 43815#L1534-1 assume !(1 == ~E_5~0); 41943#L1539-1 assume !(1 == ~E_6~0); 41944#L1544-1 assume !(1 == ~E_7~0); 42337#L1549-1 assume !(1 == ~E_8~0); 43793#L1554-1 assume !(1 == ~E_9~0); 43790#L1559-1 assume !(1 == ~E_10~0); 43640#L1564-1 assume !(1 == ~E_11~0); 43641#L1569-1 assume !(1 == ~E_12~0); 43810#L1574-1 assume !(1 == ~E_13~0); 42635#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 42636#L1940 [2024-11-17 08:53:00,789 INFO L747 eck$LassoCheckResult]: Loop: 42636#L1940 assume true; 42676#L1940-1 assume !false; 42766#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42582#L1074 assume true; 42583#L1074-1 assume !false; 43294#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 43282#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 42044#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43490#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 43491#L1079 assume !(0 != eval_~tmp~0#1); 43205#L1082 assume true; 43206#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43745#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43856#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 43832#L1296 assume !(0 == ~T1_E~0); 43075#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42236#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42237#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43232#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43251#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43591#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43211#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43051#L1336 assume !(0 == ~T9_E~0); 43052#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43594#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 42109#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 42110#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42851#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 42209#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 42210#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 42439#L1376 assume !(0 == ~E_3~0); 43862#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 42364#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 42365#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 43724#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 43779#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 42673#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 42674#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 43064#L1416 assume !(0 == ~E_11~0); 42361#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 42192#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 42193#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43252#L640-1 assume 1 == ~m_pc~0; 43253#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 43530#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42962#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42963#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43249#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43250#L659-1 assume !(1 == ~t1_pc~0); 41865#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 41866#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42643#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42815#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42816#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43578#L678-1 assume 1 == ~t2_pc~0; 42444#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42445#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42487#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42970#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42971#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43485#L697-1 assume 1 == ~t3_pc~0; 41989#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41990#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42411#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42567#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42568#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42027#L716-1 assume 1 == ~t4_pc~0; 42028#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42384#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42385#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42670#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 41890#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41891#L735-1 assume !(1 == ~t5_pc~0); 41898#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 41899#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43434#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42736#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42737#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42854#L754-1 assume !(1 == ~t6_pc~0); 42417#L764-1 is_transmit6_triggered_~__retres1~6#1 := 0; 42416#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 42345#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42346#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43589#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42055#L773-1 assume 1 == ~t7_pc~0; 42056#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 43519#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43520#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42076#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42077#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42755#L792-1 assume 1 == ~t8_pc~0; 42338#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 42339#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43721#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41797#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41798#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43190#L811-1 assume 1 == ~t9_pc~0; 43234#L812-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 43115#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42667#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42492#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42470#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42290#L830-1 assume !(1 == ~t10_pc~0); 42291#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 43292#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 43321#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42797#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42798#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43301#L849-1 assume 1 == ~t11_pc~0; 43302#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42475#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42476#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42774#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 42390#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42391#L868-1 assume 1 == ~t12_pc~0; 43212#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42633#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42634#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 43479#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43708#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43289#L887-1 assume 1 == ~t13_pc~0; 43290#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42639#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42640#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 43359#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42093#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42094#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 42535#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42536#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42198#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42199#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43415#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43262#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 43263#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43600#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43601#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42594#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42595#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42141#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42142#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42386#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 42387#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 42172#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 42083#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 42084#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 41786#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 41787#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 42308#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 42668#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 42849#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 42850#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 43799#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 43385#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 43019#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 42432#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42053#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41800#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 42098#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 42063#L1959 assume !(0 == start_simulation_~tmp~3#1); 42065#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42400#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41934#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41935#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 42768#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43630#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43631#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 43737#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 42636#L1940 [2024-11-17 08:53:00,790 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,790 INFO L85 PathProgramCache]: Analyzing trace with hash -1301418169, now seen corresponding path program 1 times [2024-11-17 08:53:00,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357520423] [2024-11-17 08:53:00,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,832 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,832 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1357520423] [2024-11-17 08:53:00,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1357520423] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:00,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034660282] [2024-11-17 08:53:00,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,833 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:00,834 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,834 INFO L85 PathProgramCache]: Analyzing trace with hash -943486851, now seen corresponding path program 1 times [2024-11-17 08:53:00,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,834 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004624436] [2024-11-17 08:53:00,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2004624436] [2024-11-17 08:53:00,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2004624436] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:00,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704448580] [2024-11-17 08:53:00,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,899 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:00,899 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:00,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:00,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:00,900 INFO L87 Difference]: Start difference. First operand 2083 states and 3047 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:00,921 INFO L93 Difference]: Finished difference Result 2083 states and 3046 transitions. [2024-11-17 08:53:00,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3046 transitions. [2024-11-17 08:53:00,926 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3046 transitions. [2024-11-17 08:53:00,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:53:00,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:53:00,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3046 transitions. [2024-11-17 08:53:00,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:00,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3046 transitions. [2024-11-17 08:53:00,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3046 transitions. [2024-11-17 08:53:00,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:53:00,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4623139702352377) internal successors, (3046), 2082 states have internal predecessors, (3046), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:00,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3046 transitions. [2024-11-17 08:53:00,953 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3046 transitions. [2024-11-17 08:53:00,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:00,954 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3046 transitions. [2024-11-17 08:53:00,954 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:53:00,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3046 transitions. [2024-11-17 08:53:00,959 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:00,959 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:00,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:00,960 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,960 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:00,961 INFO L745 eck$LassoCheckResult]: Stem: 46887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 46888#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 47608#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47957#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47970#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 47741#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46394#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46395#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46633#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46634#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 47125#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46307#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46308#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 47248#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47249#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46278#L969 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 46279#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 47941#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 47322#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46499#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 46500#L1296-1 assume !(0 == ~T1_E~0); 47240#L1301-1 assume !(0 == ~T2_E~0); 47241#L1306-1 assume !(0 == ~T3_E~0); 47733#L1311-1 assume !(0 == ~T4_E~0); 46456#L1316-1 assume !(0 == ~T5_E~0); 46457#L1321-1 assume !(0 == ~T6_E~0); 47257#L1326-1 assume !(0 == ~T7_E~0); 46289#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45963#L1336-1 assume !(0 == ~T9_E~0); 45964#L1341-1 assume !(0 == ~T10_E~0); 46049#L1346-1 assume !(0 == ~T11_E~0); 46050#L1351-1 assume !(0 == ~T12_E~0); 46396#L1356-1 assume !(0 == ~T13_E~0); 46397#L1361-1 assume !(0 == ~E_M~0); 47975#L1366-1 assume !(0 == ~E_1~0); 46443#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 46444#L1376-1 assume !(0 == ~E_3~0); 47314#L1381-1 assume !(0 == ~E_4~0); 47315#L1386-1 assume !(0 == ~E_5~0); 47999#L1391-1 assume !(0 == ~E_6~0); 48016#L1396-1 assume !(0 == ~E_7~0); 47201#L1401-1 assume !(0 == ~E_8~0); 47202#L1406-1 assume !(0 == ~E_9~0); 47473#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 47474#L1416-1 assume !(0 == ~E_11~0); 47128#L1421-1 assume !(0 == ~E_12~0); 46601#L1426-1 assume !(0 == ~E_13~0); 46602#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46624#L640-16 assume 1 == ~m_pc~0; 47712#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47108#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46729#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46730#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 47515#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46928#L659-16 assume 1 == ~t1_pc~0; 46554#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46555#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47598#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46426#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 46427#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46541#L678-16 assume 1 == ~t2_pc~0; 46542#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46480#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46550#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46551#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 47895#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47599#L697-16 assume 1 == ~t3_pc~0; 47600#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46087#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46490#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46014#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 46015#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46983#L716-16 assume 1 == ~t4_pc~0; 47642#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46154#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47398#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47399#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 48006#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47959#L735-16 assume 1 == ~t5_pc~0; 47725#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47726#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47949#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47508#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 47509#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47743#L754-16 assume 1 == ~t6_pc~0; 47744#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46901#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47154#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47155#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 47640#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47878#L773-16 assume 1 == ~t7_pc~0; 46547#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46549#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48039#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 45983#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 45984#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47686#L792-16 assume 1 == ~t8_pc~0; 47687#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47158#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46312#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46313#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 48014#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47372#L811-16 assume 1 == ~t9_pc~0; 46543#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46544#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47994#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46526#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 46527#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46083#L830-16 assume 1 == ~t10_pc~0; 46060#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 46061#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46584#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47037#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 46931#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46932#L849-16 assume 1 == ~t11_pc~0; 47323#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47523#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48001#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46771#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 46772#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47435#L868-16 assume 1 == ~t12_pc~0; 47436#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46006#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46348#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46349#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 46637#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46777#L887-16 assume 1 == ~t13_pc~0; 46309#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46310#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 47373#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 46099#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 46100#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47748#L1439-1 assume !(1 == ~M_E~0); 46296#L1444-1 assume !(1 == ~T1_E~0); 46297#L1449-1 assume !(1 == ~T2_E~0); 46746#L1454-1 assume !(1 == ~T3_E~0); 46747#L1459-1 assume !(1 == ~T4_E~0); 47362#L1464-1 assume !(1 == ~T5_E~0); 47363#L1469-1 assume !(1 == ~T6_E~0); 47417#L1474-1 assume !(1 == ~T7_E~0); 47129#L1479-1 assume !(1 == ~T8_E~0); 47130#L1484-1 assume !(1 == ~T9_E~0); 47369#L1489-1 assume !(1 == ~T10_E~0); 46986#L1494-1 assume !(1 == ~T11_E~0); 46987#L1499-1 assume !(1 == ~T12_E~0); 47192#L1504-1 assume !(1 == ~T13_E~0); 47193#L1509-1 assume !(1 == ~E_M~0); 47768#L1514-1 assume !(1 == ~E_1~0); 47447#L1519-1 assume !(1 == ~E_2~0); 47448#L1524-1 assume !(1 == ~E_3~0); 47989#L1529-1 assume !(1 == ~E_4~0); 47990#L1534-1 assume !(1 == ~E_5~0); 46118#L1539-1 assume !(1 == ~E_6~0); 46119#L1544-1 assume !(1 == ~E_7~0); 46512#L1549-1 assume !(1 == ~E_8~0); 47968#L1554-1 assume !(1 == ~E_9~0); 47965#L1559-1 assume !(1 == ~E_10~0); 47815#L1564-1 assume !(1 == ~E_11~0); 47816#L1569-1 assume !(1 == ~E_12~0); 47985#L1574-1 assume !(1 == ~E_13~0); 46810#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 46811#L1940 [2024-11-17 08:53:00,961 INFO L747 eck$LassoCheckResult]: Loop: 46811#L1940 assume true; 46851#L1940-1 assume !false; 46941#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46757#L1074 assume true; 46758#L1074-1 assume !false; 47469#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 47457#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46219#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47665#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 47666#L1079 assume !(0 != eval_~tmp~0#1); 47380#L1082 assume true; 47381#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47920#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48031#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 48007#L1296 assume !(0 == ~T1_E~0); 47250#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46411#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46412#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47407#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47426#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 47766#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47386#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47226#L1336 assume !(0 == ~T9_E~0); 47227#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47769#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46284#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 46285#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 47026#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 46384#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 46385#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 46614#L1376 assume !(0 == ~E_3~0); 48037#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 46539#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 46540#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 47899#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 47954#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 46848#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 46849#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 47239#L1416 assume !(0 == ~E_11~0); 46536#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 46367#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 46368#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47427#L640-1 assume 1 == ~m_pc~0; 47428#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47705#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47137#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47138#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47424#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47425#L659-1 assume !(1 == ~t1_pc~0); 46040#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 46041#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46818#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46990#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46991#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47753#L678-1 assume 1 == ~t2_pc~0; 46619#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46620#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46662#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47145#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47146#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47660#L697-1 assume 1 == ~t3_pc~0; 46164#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46165#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46586#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46742#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46743#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46202#L716-1 assume 1 == ~t4_pc~0; 46203#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46559#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46560#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46843#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46065#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46066#L735-1 assume !(1 == ~t5_pc~0); 46073#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 46074#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47609#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46911#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46912#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47029#L754-1 assume !(1 == ~t6_pc~0); 46592#L764-1 is_transmit6_triggered_~__retres1~6#1 := 0; 46591#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46520#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46521#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47764#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46230#L773-1 assume 1 == ~t7_pc~0; 46231#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47694#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47695#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46251#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46252#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46930#L792-1 assume 1 == ~t8_pc~0; 46513#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 46514#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47896#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45972#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45973#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47365#L811-1 assume 1 == ~t9_pc~0; 47409#L812-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47290#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46842#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46667#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46645#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46465#L830-1 assume !(1 == ~t10_pc~0); 46466#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 47467#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47496#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46972#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46973#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47476#L849-1 assume 1 == ~t11_pc~0; 47477#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46650#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46651#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46949#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 46565#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46566#L868-1 assume 1 == ~t12_pc~0; 47389#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 46808#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46809#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 47654#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47883#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47464#L887-1 assume 1 == ~t13_pc~0; 47465#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46814#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46815#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 47534#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46271#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46272#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 46710#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46711#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46373#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46374#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47590#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47437#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47438#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47775#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47776#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46769#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46770#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46316#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 46317#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46561#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 46562#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 46347#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 46258#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 46259#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 45961#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 45962#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 46483#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 46844#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 47024#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 47025#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 47974#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 47560#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 47194#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 46607#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46228#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45975#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46273#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46238#L1959 assume !(0 == start_simulation_~tmp~3#1); 46240#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46575#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 46109#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 46110#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46943#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47805#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47806#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 47912#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 46811#L1940 [2024-11-17 08:53:00,962 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,962 INFO L85 PathProgramCache]: Analyzing trace with hash 2027986310, now seen corresponding path program 1 times [2024-11-17 08:53:00,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937076075] [2024-11-17 08:53:00,962 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:00,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:00,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:00,990 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:00,990 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [937076075] [2024-11-17 08:53:00,990 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [937076075] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:00,990 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:00,990 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:00,990 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333423377] [2024-11-17 08:53:00,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:00,991 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:00,991 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:00,991 INFO L85 PathProgramCache]: Analyzing trace with hash -943486851, now seen corresponding path program 2 times [2024-11-17 08:53:00,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:00,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586123467] [2024-11-17 08:53:00,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:00,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:01,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:01,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:01,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:01,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [586123467] [2024-11-17 08:53:01,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [586123467] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:01,046 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:01,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:01,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1533217447] [2024-11-17 08:53:01,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:01,046 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:01,046 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:01,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:01,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:01,047 INFO L87 Difference]: Start difference. First operand 2083 states and 3046 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:01,068 INFO L93 Difference]: Finished difference Result 2083 states and 3045 transitions. [2024-11-17 08:53:01,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3045 transitions. [2024-11-17 08:53:01,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:01,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3045 transitions. [2024-11-17 08:53:01,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:53:01,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:53:01,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3045 transitions. [2024-11-17 08:53:01,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:01,085 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3045 transitions. [2024-11-17 08:53:01,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3045 transitions. [2024-11-17 08:53:01,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:53:01,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4618338934229476) internal successors, (3045), 2082 states have internal predecessors, (3045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3045 transitions. [2024-11-17 08:53:01,108 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3045 transitions. [2024-11-17 08:53:01,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:01,109 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3045 transitions. [2024-11-17 08:53:01,109 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:53:01,109 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3045 transitions. [2024-11-17 08:53:01,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:01,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:01,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:01,116 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:01,116 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:01,116 INFO L745 eck$LassoCheckResult]: Stem: 51062#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 51063#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 51783#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52132#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52145#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 51916#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50569#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50570#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 50808#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50809#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51300#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50482#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50483#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 51423#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 51424#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50453#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50454#L974 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 52116#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 51497#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 50674#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 50675#L1296-1 assume !(0 == ~T1_E~0); 51415#L1301-1 assume !(0 == ~T2_E~0); 51416#L1306-1 assume !(0 == ~T3_E~0); 51908#L1311-1 assume !(0 == ~T4_E~0); 50631#L1316-1 assume !(0 == ~T5_E~0); 50632#L1321-1 assume !(0 == ~T6_E~0); 51432#L1326-1 assume !(0 == ~T7_E~0); 50464#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50138#L1336-1 assume !(0 == ~T9_E~0); 50139#L1341-1 assume !(0 == ~T10_E~0); 50224#L1346-1 assume !(0 == ~T11_E~0); 50225#L1351-1 assume !(0 == ~T12_E~0); 50571#L1356-1 assume !(0 == ~T13_E~0); 50572#L1361-1 assume !(0 == ~E_M~0); 52150#L1366-1 assume !(0 == ~E_1~0); 50618#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 50619#L1376-1 assume !(0 == ~E_3~0); 51489#L1381-1 assume !(0 == ~E_4~0); 51490#L1386-1 assume !(0 == ~E_5~0); 52174#L1391-1 assume !(0 == ~E_6~0); 52191#L1396-1 assume !(0 == ~E_7~0); 51376#L1401-1 assume !(0 == ~E_8~0); 51377#L1406-1 assume !(0 == ~E_9~0); 51648#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 51649#L1416-1 assume !(0 == ~E_11~0); 51303#L1421-1 assume !(0 == ~E_12~0); 50776#L1426-1 assume !(0 == ~E_13~0); 50777#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50799#L640-16 assume 1 == ~m_pc~0; 51887#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 51283#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50904#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50905#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 51690#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51103#L659-16 assume 1 == ~t1_pc~0; 50729#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50730#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51773#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50601#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 50602#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50716#L678-16 assume 1 == ~t2_pc~0; 50717#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50655#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50725#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50726#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 52070#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51774#L697-16 assume 1 == ~t3_pc~0; 51775#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50263#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50665#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50189#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 50190#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51158#L716-16 assume 1 == ~t4_pc~0; 51817#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50329#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 51573#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51574#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 52181#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52134#L735-16 assume 1 == ~t5_pc~0; 51900#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51901#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52124#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51683#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 51684#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51918#L754-16 assume 1 == ~t6_pc~0; 51919#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51076#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51329#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51330#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 51815#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52053#L773-16 assume 1 == ~t7_pc~0; 50722#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 50724#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52214#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50158#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 50159#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51861#L792-16 assume 1 == ~t8_pc~0; 51862#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51333#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 50487#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50488#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 52189#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51547#L811-16 assume 1 == ~t9_pc~0; 50718#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 50719#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52169#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50701#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 50702#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50258#L830-16 assume 1 == ~t10_pc~0; 50235#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 50236#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50759#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51212#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 51106#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51107#L849-16 assume 1 == ~t11_pc~0; 51498#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51698#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52176#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50946#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 50947#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51610#L868-16 assume 1 == ~t12_pc~0; 51611#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50181#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50523#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50524#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 50812#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50952#L887-16 assume 1 == ~t13_pc~0; 50484#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50485#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 51548#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 50274#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 50275#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51923#L1439-1 assume !(1 == ~M_E~0); 50471#L1444-1 assume !(1 == ~T1_E~0); 50472#L1449-1 assume !(1 == ~T2_E~0); 50921#L1454-1 assume !(1 == ~T3_E~0); 50922#L1459-1 assume !(1 == ~T4_E~0); 51537#L1464-1 assume !(1 == ~T5_E~0); 51538#L1469-1 assume !(1 == ~T6_E~0); 51592#L1474-1 assume !(1 == ~T7_E~0); 51304#L1479-1 assume !(1 == ~T8_E~0); 51305#L1484-1 assume !(1 == ~T9_E~0); 51544#L1489-1 assume !(1 == ~T10_E~0); 51161#L1494-1 assume !(1 == ~T11_E~0); 51162#L1499-1 assume !(1 == ~T12_E~0); 51367#L1504-1 assume !(1 == ~T13_E~0); 51368#L1509-1 assume !(1 == ~E_M~0); 51943#L1514-1 assume !(1 == ~E_1~0); 51622#L1519-1 assume !(1 == ~E_2~0); 51623#L1524-1 assume !(1 == ~E_3~0); 52164#L1529-1 assume !(1 == ~E_4~0); 52165#L1534-1 assume !(1 == ~E_5~0); 50293#L1539-1 assume !(1 == ~E_6~0); 50294#L1544-1 assume !(1 == ~E_7~0); 50687#L1549-1 assume !(1 == ~E_8~0); 52143#L1554-1 assume !(1 == ~E_9~0); 52140#L1559-1 assume !(1 == ~E_10~0); 51990#L1564-1 assume !(1 == ~E_11~0); 51991#L1569-1 assume !(1 == ~E_12~0); 52160#L1574-1 assume !(1 == ~E_13~0); 50985#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 50986#L1940 [2024-11-17 08:53:01,117 INFO L747 eck$LassoCheckResult]: Loop: 50986#L1940 assume true; 51026#L1940-1 assume !false; 51116#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 50932#L1074 assume true; 50933#L1074-1 assume !false; 51644#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 51632#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50394#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51840#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 51841#L1079 assume !(0 != eval_~tmp~0#1); 51555#L1082 assume true; 51556#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52095#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52206#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 52182#L1296 assume !(0 == ~T1_E~0); 51425#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 50586#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50587#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 51582#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51601#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51941#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51561#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51401#L1336 assume !(0 == ~T9_E~0); 51402#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51944#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50459#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 50460#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 51201#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 50559#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 50560#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 50789#L1376 assume !(0 == ~E_3~0); 52212#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 50714#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 50715#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 52074#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 52129#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 51023#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 51024#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 51414#L1416 assume !(0 == ~E_11~0); 50711#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 50542#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 50543#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51602#L640-1 assume 1 == ~m_pc~0; 51603#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 51880#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51312#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51313#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51599#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51600#L659-1 assume !(1 == ~t1_pc~0); 50215#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 50216#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50993#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51165#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51166#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51928#L678-1 assume 1 == ~t2_pc~0; 50794#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 50795#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50837#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51320#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51321#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51835#L697-1 assume 1 == ~t3_pc~0; 50342#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50343#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50761#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50917#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50918#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50376#L716-1 assume 1 == ~t4_pc~0; 50377#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50734#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50735#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51018#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50240#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50241#L735-1 assume !(1 == ~t5_pc~0); 50248#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 50249#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51784#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51086#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51087#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51204#L754-1 assume !(1 == ~t6_pc~0); 50769#L764-1 is_transmit6_triggered_~__retres1~6#1 := 0; 50768#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50695#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50696#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51939#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50405#L773-1 assume 1 == ~t7_pc~0; 50406#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51869#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51870#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50426#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 50427#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51105#L792-1 assume 1 == ~t8_pc~0; 50688#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 50689#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52071#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50147#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 50148#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51540#L811-1 assume 1 == ~t9_pc~0; 51584#L812-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51465#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51017#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50842#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50820#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50640#L830-1 assume !(1 == ~t10_pc~0); 50641#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 51642#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51671#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51147#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51148#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51651#L849-1 assume 1 == ~t11_pc~0; 51652#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50825#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50826#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51124#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 50740#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50741#L868-1 assume 1 == ~t12_pc~0; 51564#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 50983#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50984#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51829#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 52058#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51639#L887-1 assume 1 == ~t13_pc~0; 51640#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50989#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50990#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 51709#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50446#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50447#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 50885#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 50886#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50548#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50549#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51765#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51613#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51614#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51950#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 51951#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50944#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50945#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50491#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 50492#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 50736#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 50737#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 50522#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 50433#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 50434#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 50136#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 50137#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 50658#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 51019#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 51199#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 51200#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 52149#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 51735#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 51369#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 50782#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50403#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50150#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50448#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50413#L1959 assume !(0 == start_simulation_~tmp~3#1); 50415#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50750#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 50284#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 50285#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 51118#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51980#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51981#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 52087#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 50986#L1940 [2024-11-17 08:53:01,117 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:01,117 INFO L85 PathProgramCache]: Analyzing trace with hash -1605391513, now seen corresponding path program 1 times [2024-11-17 08:53:01,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:01,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952092910] [2024-11-17 08:53:01,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:01,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:01,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:01,171 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:01,172 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:01,172 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952092910] [2024-11-17 08:53:01,172 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952092910] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:01,172 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:01,172 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:01,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950783872] [2024-11-17 08:53:01,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:01,172 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:01,173 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:01,173 INFO L85 PathProgramCache]: Analyzing trace with hash -943486851, now seen corresponding path program 3 times [2024-11-17 08:53:01,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:01,173 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [320072832] [2024-11-17 08:53:01,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:01,173 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:01,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:01,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:01,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:01,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [320072832] [2024-11-17 08:53:01,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [320072832] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:01,227 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:01,227 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:01,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [538552012] [2024-11-17 08:53:01,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:01,228 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:01,228 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:01,228 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:01,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:01,229 INFO L87 Difference]: Start difference. First operand 2083 states and 3045 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:01,249 INFO L93 Difference]: Finished difference Result 2083 states and 3044 transitions. [2024-11-17 08:53:01,249 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3044 transitions. [2024-11-17 08:53:01,254 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:01,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3044 transitions. [2024-11-17 08:53:01,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:53:01,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:53:01,259 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3044 transitions. [2024-11-17 08:53:01,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:01,260 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3044 transitions. [2024-11-17 08:53:01,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3044 transitions. [2024-11-17 08:53:01,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:53:01,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4613538166106577) internal successors, (3044), 2082 states have internal predecessors, (3044), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3044 transitions. [2024-11-17 08:53:01,279 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3044 transitions. [2024-11-17 08:53:01,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:01,280 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3044 transitions. [2024-11-17 08:53:01,280 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:53:01,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3044 transitions. [2024-11-17 08:53:01,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:01,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:01,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:01,285 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:01,285 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:01,286 INFO L745 eck$LassoCheckResult]: Stem: 55237#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 55238#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 55958#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56307#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56320#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 56091#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54744#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54745#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54983#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54984#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55475#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54657#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54658#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55598#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 55599#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54628#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54629#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56291#L979 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 55672#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54849#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 54850#L1296-1 assume !(0 == ~T1_E~0); 55590#L1301-1 assume !(0 == ~T2_E~0); 55591#L1306-1 assume !(0 == ~T3_E~0); 56083#L1311-1 assume !(0 == ~T4_E~0); 54806#L1316-1 assume !(0 == ~T5_E~0); 54807#L1321-1 assume !(0 == ~T6_E~0); 55607#L1326-1 assume !(0 == ~T7_E~0); 54639#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 54313#L1336-1 assume !(0 == ~T9_E~0); 54314#L1341-1 assume !(0 == ~T10_E~0); 54399#L1346-1 assume !(0 == ~T11_E~0); 54400#L1351-1 assume !(0 == ~T12_E~0); 54746#L1356-1 assume !(0 == ~T13_E~0); 54747#L1361-1 assume !(0 == ~E_M~0); 56325#L1366-1 assume !(0 == ~E_1~0); 54793#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 54794#L1376-1 assume !(0 == ~E_3~0); 55664#L1381-1 assume !(0 == ~E_4~0); 55665#L1386-1 assume !(0 == ~E_5~0); 56349#L1391-1 assume !(0 == ~E_6~0); 56366#L1396-1 assume !(0 == ~E_7~0); 55551#L1401-1 assume !(0 == ~E_8~0); 55552#L1406-1 assume !(0 == ~E_9~0); 55823#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 55824#L1416-1 assume !(0 == ~E_11~0); 55478#L1421-1 assume !(0 == ~E_12~0); 54951#L1426-1 assume !(0 == ~E_13~0); 54952#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54974#L640-16 assume 1 == ~m_pc~0; 56062#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 55458#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55079#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55080#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 55865#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55278#L659-16 assume 1 == ~t1_pc~0; 54904#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 54905#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55948#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54776#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 54777#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54891#L678-16 assume 1 == ~t2_pc~0; 54892#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54830#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54900#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54901#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 56245#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55949#L697-16 assume 1 == ~t3_pc~0; 55950#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54438#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54840#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54364#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 54365#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55333#L716-16 assume 1 == ~t4_pc~0; 55992#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54504#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55748#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55749#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 56356#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56309#L735-16 assume 1 == ~t5_pc~0; 56075#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56076#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56299#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55858#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 55859#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56093#L754-16 assume 1 == ~t6_pc~0; 56094#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55251#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55504#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55505#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 55990#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56228#L773-16 assume 1 == ~t7_pc~0; 54897#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54899#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56389#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54333#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 54334#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56036#L792-16 assume 1 == ~t8_pc~0; 56037#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 55508#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 54662#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54663#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 56364#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55722#L811-16 assume 1 == ~t9_pc~0; 54893#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54894#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56344#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54876#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 54877#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54433#L830-16 assume 1 == ~t10_pc~0; 54410#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 54411#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54934#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55387#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 55281#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55282#L849-16 assume 1 == ~t11_pc~0; 55673#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55873#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56351#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55121#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 55122#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 55785#L868-16 assume 1 == ~t12_pc~0; 55786#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54356#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54698#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54699#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 54987#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 55127#L887-16 assume 1 == ~t13_pc~0; 54659#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54660#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55723#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 54449#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 54450#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56098#L1439-1 assume !(1 == ~M_E~0); 54646#L1444-1 assume !(1 == ~T1_E~0); 54647#L1449-1 assume !(1 == ~T2_E~0); 55096#L1454-1 assume !(1 == ~T3_E~0); 55097#L1459-1 assume !(1 == ~T4_E~0); 55712#L1464-1 assume !(1 == ~T5_E~0); 55713#L1469-1 assume !(1 == ~T6_E~0); 55767#L1474-1 assume !(1 == ~T7_E~0); 55479#L1479-1 assume !(1 == ~T8_E~0); 55480#L1484-1 assume !(1 == ~T9_E~0); 55719#L1489-1 assume !(1 == ~T10_E~0); 55336#L1494-1 assume !(1 == ~T11_E~0); 55337#L1499-1 assume !(1 == ~T12_E~0); 55542#L1504-1 assume !(1 == ~T13_E~0); 55543#L1509-1 assume !(1 == ~E_M~0); 56118#L1514-1 assume !(1 == ~E_1~0); 55797#L1519-1 assume !(1 == ~E_2~0); 55798#L1524-1 assume !(1 == ~E_3~0); 56339#L1529-1 assume !(1 == ~E_4~0); 56340#L1534-1 assume !(1 == ~E_5~0); 54468#L1539-1 assume !(1 == ~E_6~0); 54469#L1544-1 assume !(1 == ~E_7~0); 54862#L1549-1 assume !(1 == ~E_8~0); 56318#L1554-1 assume !(1 == ~E_9~0); 56315#L1559-1 assume !(1 == ~E_10~0); 56165#L1564-1 assume !(1 == ~E_11~0); 56166#L1569-1 assume !(1 == ~E_12~0); 56335#L1574-1 assume !(1 == ~E_13~0); 55160#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 55161#L1940 [2024-11-17 08:53:01,286 INFO L747 eck$LassoCheckResult]: Loop: 55161#L1940 assume true; 55201#L1940-1 assume !false; 55291#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55107#L1074 assume true; 55108#L1074-1 assume !false; 55819#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 55807#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 54569#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56015#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 56016#L1079 assume !(0 != eval_~tmp~0#1); 55730#L1082 assume true; 55731#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56270#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56381#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 56357#L1296 assume !(0 == ~T1_E~0); 55600#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54761#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54762#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55757#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55776#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56116#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55736#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 55576#L1336 assume !(0 == ~T9_E~0); 55577#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 56119#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 54634#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 54635#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 55376#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 54734#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 54735#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 54964#L1376 assume !(0 == ~E_3~0); 56387#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 54889#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 54890#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 56249#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 56304#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 55198#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 55199#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 55589#L1416 assume !(0 == ~E_11~0); 54886#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 54717#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 54718#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55777#L640-1 assume 1 == ~m_pc~0; 55778#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 56055#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55487#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55488#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55774#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55775#L659-1 assume !(1 == ~t1_pc~0); 54390#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 54391#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55168#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55340#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55341#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56103#L678-1 assume 1 == ~t2_pc~0; 54969#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54970#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55012#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55495#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55496#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56010#L697-1 assume 1 == ~t3_pc~0; 54512#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54513#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54936#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55092#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55093#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54551#L716-1 assume 1 == ~t4_pc~0; 54552#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54909#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54910#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55193#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54415#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54416#L735-1 assume !(1 == ~t5_pc~0); 54423#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 54424#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55959#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55261#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55262#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55379#L754-1 assume !(1 == ~t6_pc~0); 54944#L764-1 is_transmit6_triggered_~__retres1~6#1 := 0; 54943#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54870#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54871#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56114#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54580#L773-1 assume 1 == ~t7_pc~0; 54581#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 56044#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56045#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54602#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54603#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55280#L792-1 assume !(1 == ~t8_pc~0); 54865#L802-1 is_transmit8_triggered_~__retres1~8#1 := 0; 54864#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56246#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54322#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 54323#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55715#L811-1 assume !(1 == ~t9_pc~0); 55639#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 55640#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55192#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55017#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54995#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54815#L830-1 assume !(1 == ~t10_pc~0); 54816#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 55817#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55846#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55322#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55323#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55826#L849-1 assume 1 == ~t11_pc~0; 55827#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55000#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55001#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55299#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54915#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54916#L868-1 assume 1 == ~t12_pc~0; 55739#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 55158#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 55159#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 56004#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 56233#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 55814#L887-1 assume 1 == ~t13_pc~0; 55815#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 55164#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55165#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 55884#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54621#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54622#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 55060#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55061#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54723#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54724#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55940#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55788#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55789#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56125#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56126#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 55119#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 55120#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54666#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 54667#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 54911#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 54912#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 54697#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 54608#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 54609#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 54311#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 54312#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 54833#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 55194#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 55374#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 55375#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 56324#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 55910#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 55544#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 54957#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54578#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 54325#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54623#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54588#L1959 assume !(0 == start_simulation_~tmp~3#1); 54590#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54925#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 54459#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 54460#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 55293#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 56155#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56156#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 56262#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 55161#L1940 [2024-11-17 08:53:01,287 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:01,287 INFO L85 PathProgramCache]: Analyzing trace with hash 1741086054, now seen corresponding path program 1 times [2024-11-17 08:53:01,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:01,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742283017] [2024-11-17 08:53:01,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:01,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:01,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:01,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:01,318 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:01,318 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742283017] [2024-11-17 08:53:01,318 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742283017] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:01,318 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:01,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:01,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [704374519] [2024-11-17 08:53:01,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:01,319 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:01,319 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:01,320 INFO L85 PathProgramCache]: Analyzing trace with hash -1244750269, now seen corresponding path program 1 times [2024-11-17 08:53:01,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:01,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813759008] [2024-11-17 08:53:01,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:01,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:01,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:01,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:01,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:01,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1813759008] [2024-11-17 08:53:01,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1813759008] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:01,374 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:01,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:01,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2022875780] [2024-11-17 08:53:01,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:01,374 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:01,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:01,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:01,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:01,375 INFO L87 Difference]: Start difference. First operand 2083 states and 3044 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:01,395 INFO L93 Difference]: Finished difference Result 2083 states and 3043 transitions. [2024-11-17 08:53:01,396 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2083 states and 3043 transitions. [2024-11-17 08:53:01,402 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:01,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2083 states to 2083 states and 3043 transitions. [2024-11-17 08:53:01,406 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2083 [2024-11-17 08:53:01,407 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2083 [2024-11-17 08:53:01,407 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2083 states and 3043 transitions. [2024-11-17 08:53:01,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:01,409 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3043 transitions. [2024-11-17 08:53:01,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2083 states and 3043 transitions. [2024-11-17 08:53:01,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2083 to 2083. [2024-11-17 08:53:01,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2083 states, 2083 states have (on average 1.4608737397983678) internal successors, (3043), 2082 states have internal predecessors, (3043), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2083 states to 2083 states and 3043 transitions. [2024-11-17 08:53:01,427 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2083 states and 3043 transitions. [2024-11-17 08:53:01,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:01,429 INFO L425 stractBuchiCegarLoop]: Abstraction has 2083 states and 3043 transitions. [2024-11-17 08:53:01,429 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:53:01,429 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2083 states and 3043 transitions. [2024-11-17 08:53:01,433 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1908 [2024-11-17 08:53:01,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:01,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:01,434 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:01,434 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:01,435 INFO L745 eck$LassoCheckResult]: Stem: 59412#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59413#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60133#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60482#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60495#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 60266#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58919#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58920#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59158#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59159#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59650#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58832#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 58833#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59773#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59774#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 58803#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 58804#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60466#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59847#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59024#L1291-1 assume 0 == ~M_E~0;~M_E~0 := 1; 59025#L1296-1 assume !(0 == ~T1_E~0); 59765#L1301-1 assume !(0 == ~T2_E~0); 59766#L1306-1 assume !(0 == ~T3_E~0); 60258#L1311-1 assume !(0 == ~T4_E~0); 58981#L1316-1 assume !(0 == ~T5_E~0); 58982#L1321-1 assume !(0 == ~T6_E~0); 59782#L1326-1 assume !(0 == ~T7_E~0); 58814#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58488#L1336-1 assume !(0 == ~T9_E~0); 58489#L1341-1 assume !(0 == ~T10_E~0); 58574#L1346-1 assume !(0 == ~T11_E~0); 58575#L1351-1 assume !(0 == ~T12_E~0); 58921#L1356-1 assume !(0 == ~T13_E~0); 58922#L1361-1 assume !(0 == ~E_M~0); 60500#L1366-1 assume !(0 == ~E_1~0); 58968#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 58969#L1376-1 assume !(0 == ~E_3~0); 59839#L1381-1 assume !(0 == ~E_4~0); 59840#L1386-1 assume !(0 == ~E_5~0); 60524#L1391-1 assume !(0 == ~E_6~0); 60541#L1396-1 assume !(0 == ~E_7~0); 59726#L1401-1 assume !(0 == ~E_8~0); 59727#L1406-1 assume !(0 == ~E_9~0); 59998#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 59999#L1416-1 assume !(0 == ~E_11~0); 59653#L1421-1 assume !(0 == ~E_12~0); 59126#L1426-1 assume !(0 == ~E_13~0); 59127#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59149#L640-16 assume 1 == ~m_pc~0; 60237#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 59633#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59254#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59255#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 60040#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59453#L659-16 assume 1 == ~t1_pc~0; 59079#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59080#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60123#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 58951#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 58952#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59066#L678-16 assume 1 == ~t2_pc~0; 59067#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59005#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59075#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59076#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 60420#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60124#L697-16 assume 1 == ~t3_pc~0; 60125#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 58613#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59015#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58539#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 58540#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59508#L716-16 assume 1 == ~t4_pc~0; 60167#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58679#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59923#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59924#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 60531#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60484#L735-16 assume 1 == ~t5_pc~0; 60250#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60251#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60474#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60033#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 60034#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60268#L754-16 assume 1 == ~t6_pc~0; 60269#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59426#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59679#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59680#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 60165#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60403#L773-16 assume 1 == ~t7_pc~0; 59072#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59074#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60564#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58508#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 58509#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60211#L792-16 assume 1 == ~t8_pc~0; 60212#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59683#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 58837#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58838#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 60539#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59897#L811-16 assume 1 == ~t9_pc~0; 59068#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59069#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60519#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59051#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 59052#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58608#L830-16 assume 1 == ~t10_pc~0; 58585#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 58586#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59109#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59562#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 59456#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 59457#L849-16 assume 1 == ~t11_pc~0; 59848#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60048#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60526#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59296#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 59297#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59960#L868-16 assume 1 == ~t12_pc~0; 59961#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 58531#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58873#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 58874#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 59162#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59302#L887-16 assume 1 == ~t13_pc~0; 58834#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 58835#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59898#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 58624#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 58625#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60273#L1439-1 assume !(1 == ~M_E~0); 58821#L1444-1 assume !(1 == ~T1_E~0); 58822#L1449-1 assume !(1 == ~T2_E~0); 59271#L1454-1 assume !(1 == ~T3_E~0); 59272#L1459-1 assume !(1 == ~T4_E~0); 59887#L1464-1 assume !(1 == ~T5_E~0); 59888#L1469-1 assume !(1 == ~T6_E~0); 59942#L1474-1 assume !(1 == ~T7_E~0); 59654#L1479-1 assume !(1 == ~T8_E~0); 59655#L1484-1 assume !(1 == ~T9_E~0); 59894#L1489-1 assume !(1 == ~T10_E~0); 59511#L1494-1 assume !(1 == ~T11_E~0); 59512#L1499-1 assume !(1 == ~T12_E~0); 59717#L1504-1 assume !(1 == ~T13_E~0); 59718#L1509-1 assume !(1 == ~E_M~0); 60293#L1514-1 assume !(1 == ~E_1~0); 59972#L1519-1 assume !(1 == ~E_2~0); 59973#L1524-1 assume !(1 == ~E_3~0); 60514#L1529-1 assume !(1 == ~E_4~0); 60515#L1534-1 assume !(1 == ~E_5~0); 58643#L1539-1 assume !(1 == ~E_6~0); 58644#L1544-1 assume !(1 == ~E_7~0); 59037#L1549-1 assume !(1 == ~E_8~0); 60493#L1554-1 assume !(1 == ~E_9~0); 60490#L1559-1 assume !(1 == ~E_10~0); 60340#L1564-1 assume !(1 == ~E_11~0); 60341#L1569-1 assume !(1 == ~E_12~0); 60510#L1574-1 assume !(1 == ~E_13~0); 59335#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 59336#L1940 [2024-11-17 08:53:01,435 INFO L747 eck$LassoCheckResult]: Loop: 59336#L1940 assume true; 59376#L1940-1 assume !false; 59466#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59282#L1074 assume true; 59283#L1074-1 assume !false; 59994#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59982#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58744#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60190#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 60191#L1079 assume !(0 != eval_~tmp~0#1); 59905#L1082 assume true; 59906#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60445#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60556#L1291 assume 0 == ~M_E~0;~M_E~0 := 1; 60532#L1296 assume !(0 == ~T1_E~0); 59775#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 58936#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 58937#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 59932#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59951#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60291#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59911#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59751#L1336 assume !(0 == ~T9_E~0); 59752#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 60294#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 58809#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 58810#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 59551#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 58909#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 58910#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 59139#L1376 assume !(0 == ~E_3~0); 60562#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 59064#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 59065#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 60424#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 60479#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 59373#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 59374#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 59764#L1416 assume !(0 == ~E_11~0); 59061#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 58892#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 58893#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59952#L640-1 assume 1 == ~m_pc~0; 59953#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 60230#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59662#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59663#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59949#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59950#L659-1 assume !(1 == ~t1_pc~0); 58565#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 58566#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59343#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59515#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 59516#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60278#L678-1 assume 1 == ~t2_pc~0; 59144#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59145#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59187#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 59670#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 59671#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60185#L697-1 assume !(1 == ~t3_pc~0); 58689#L707-1 is_transmit3_triggered_~__retres1~3#1 := 0; 58688#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59111#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59267#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 59268#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58726#L716-1 assume 1 == ~t4_pc~0; 58727#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59084#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59085#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59368#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58590#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58591#L735-1 assume !(1 == ~t5_pc~0); 58598#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 58599#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60134#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59436#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59437#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59554#L754-1 assume 1 == ~t6_pc~0; 59117#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59118#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59045#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59046#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60289#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 58755#L773-1 assume 1 == ~t7_pc~0; 58756#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 60219#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60220#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 58777#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 58778#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59455#L792-1 assume !(1 == ~t8_pc~0); 59040#L802-1 is_transmit8_triggered_~__retres1~8#1 := 0; 59039#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60421#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 58497#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 58498#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59890#L811-1 assume !(1 == ~t9_pc~0); 59814#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 59815#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59367#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59192#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59170#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 58990#L830-1 assume 1 == ~t10_pc~0; 58992#L831-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59992#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60021#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59497#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59498#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60001#L849-1 assume 1 == ~t11_pc~0; 60002#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59175#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59176#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59474#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59090#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59091#L868-1 assume 1 == ~t12_pc~0; 59914#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 59333#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 59334#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60179#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60408#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59989#L887-1 assume 1 == ~t13_pc~0; 59990#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59339#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59340#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 60059#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 58796#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58797#L1439 assume 1 == ~M_E~0;~M_E~0 := 2; 59235#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59236#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58898#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58899#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60115#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 59963#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 59964#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60300#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60301#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 59294#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59295#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 58841#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 58842#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 59086#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 59087#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 58872#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 58783#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 58784#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 58486#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 58487#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 59008#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 59369#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 59549#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 59550#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 60499#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 60085#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 59719#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 59132#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 58753#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58500#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58798#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 58763#L1959 assume !(0 == start_simulation_~tmp~3#1); 58765#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59100#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58634#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 58635#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 59468#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60330#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60331#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 60437#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 59336#L1940 [2024-11-17 08:53:01,435 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:01,435 INFO L85 PathProgramCache]: Analyzing trace with hash 1571942279, now seen corresponding path program 1 times [2024-11-17 08:53:01,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:01,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322443287] [2024-11-17 08:53:01,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:01,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:01,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:01,495 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:01,495 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:01,495 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322443287] [2024-11-17 08:53:01,495 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322443287] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:01,495 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:01,495 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:01,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012380682] [2024-11-17 08:53:01,496 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:01,496 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:01,496 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:01,496 INFO L85 PathProgramCache]: Analyzing trace with hash -1513028800, now seen corresponding path program 1 times [2024-11-17 08:53:01,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:01,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593719905] [2024-11-17 08:53:01,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:01,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:01,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:01,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:01,551 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:01,551 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593719905] [2024-11-17 08:53:01,551 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [593719905] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:01,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:01,552 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:01,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062378838] [2024-11-17 08:53:01,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:01,552 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:01,552 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:01,552 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:01,552 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:01,553 INFO L87 Difference]: Start difference. First operand 2083 states and 3043 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:01,642 INFO L93 Difference]: Finished difference Result 3891 states and 5665 transitions. [2024-11-17 08:53:01,642 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3891 states and 5665 transitions. [2024-11-17 08:53:01,650 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3716 [2024-11-17 08:53:01,656 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3891 states to 3891 states and 5665 transitions. [2024-11-17 08:53:01,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3891 [2024-11-17 08:53:01,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3891 [2024-11-17 08:53:01,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3891 states and 5665 transitions. [2024-11-17 08:53:01,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:01,661 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3891 states and 5665 transitions. [2024-11-17 08:53:01,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3891 states and 5665 transitions. [2024-11-17 08:53:01,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3891 to 3891. [2024-11-17 08:53:01,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3891 states, 3891 states have (on average 1.4559239270110511) internal successors, (5665), 3890 states have internal predecessors, (5665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3891 states to 3891 states and 5665 transitions. [2024-11-17 08:53:01,700 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3891 states and 5665 transitions. [2024-11-17 08:53:01,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:01,701 INFO L425 stractBuchiCegarLoop]: Abstraction has 3891 states and 5665 transitions. [2024-11-17 08:53:01,701 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:53:01,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3891 states and 5665 transitions. [2024-11-17 08:53:01,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3716 [2024-11-17 08:53:01,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:01,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:01,711 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:01,711 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:01,711 INFO L745 eck$LassoCheckResult]: Stem: 65398#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 65399#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 66122#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 66479#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66494#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 66257#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64900#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64901#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65142#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65143#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65635#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 64815#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64816#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65760#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 65761#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 64786#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 64787#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 66463#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 65834#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65007#L1291-1 assume !(0 == ~M_E~0); 65008#L1296-1 assume !(0 == ~T1_E~0); 65752#L1301-1 assume !(0 == ~T2_E~0); 65753#L1306-1 assume !(0 == ~T3_E~0); 66248#L1311-1 assume !(0 == ~T4_E~0); 64964#L1316-1 assume !(0 == ~T5_E~0); 64965#L1321-1 assume !(0 == ~T6_E~0); 65769#L1326-1 assume !(0 == ~T7_E~0); 64797#L1331-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64469#L1336-1 assume !(0 == ~T9_E~0); 64470#L1341-1 assume !(0 == ~T10_E~0); 64557#L1346-1 assume !(0 == ~T11_E~0); 64558#L1351-1 assume !(0 == ~T12_E~0); 64904#L1356-1 assume !(0 == ~T13_E~0); 64905#L1361-1 assume !(0 == ~E_M~0); 66499#L1366-1 assume !(0 == ~E_1~0); 64950#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 64951#L1376-1 assume !(0 == ~E_3~0); 65826#L1381-1 assume !(0 == ~E_4~0); 65827#L1386-1 assume !(0 == ~E_5~0); 66525#L1391-1 assume !(0 == ~E_6~0); 66543#L1396-1 assume !(0 == ~E_7~0); 65713#L1401-1 assume !(0 == ~E_8~0); 65714#L1406-1 assume !(0 == ~E_9~0); 65986#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 65987#L1416-1 assume !(0 == ~E_11~0); 65638#L1421-1 assume !(0 == ~E_12~0); 65110#L1426-1 assume !(0 == ~E_13~0); 65111#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65133#L640-16 assume 1 == ~m_pc~0; 66227#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 65620#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65238#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65239#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 66028#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65439#L659-16 assume 1 == ~t1_pc~0; 65060#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 65061#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66112#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 64934#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 64935#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65049#L678-16 assume 1 == ~t2_pc~0; 65050#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64986#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65058#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65059#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 66416#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66113#L697-16 assume 1 == ~t3_pc~0; 66114#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64593#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64998#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64522#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 64523#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65494#L716-16 assume 1 == ~t4_pc~0; 66156#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64662#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65911#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65912#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 66532#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66481#L735-16 assume 1 == ~t5_pc~0; 66240#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66241#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66471#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66021#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 66022#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66259#L754-16 assume 1 == ~t6_pc~0; 66260#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65412#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65666#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65667#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 66154#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66398#L773-16 assume 1 == ~t7_pc~0; 65055#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 65057#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66570#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 64491#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 64492#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 66200#L792-16 assume 1 == ~t8_pc~0; 66201#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65670#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64820#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 64821#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 66541#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65885#L811-16 assume 1 == ~t9_pc~0; 65051#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 65052#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66518#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65032#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 65033#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64591#L830-16 assume 1 == ~t10_pc~0; 64568#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64569#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65093#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65549#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 65441#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65442#L849-16 assume 1 == ~t11_pc~0; 65835#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 66036#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66527#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 65280#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 65281#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65948#L868-16 assume 1 == ~t12_pc~0; 65949#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 64514#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64855#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 64856#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 65146#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 65286#L887-16 assume 1 == ~t13_pc~0; 64817#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 64818#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 65886#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 64601#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 64602#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66264#L1439-1 assume !(1 == ~M_E~0); 64804#L1444-1 assume !(1 == ~T1_E~0); 64805#L1449-1 assume !(1 == ~T2_E~0); 65253#L1454-1 assume !(1 == ~T3_E~0); 65254#L1459-1 assume !(1 == ~T4_E~0); 65875#L1464-1 assume !(1 == ~T5_E~0); 65876#L1469-1 assume !(1 == ~T6_E~0); 65930#L1474-1 assume !(1 == ~T7_E~0); 65639#L1479-1 assume !(1 == ~T8_E~0); 65640#L1484-1 assume !(1 == ~T9_E~0); 65880#L1489-1 assume !(1 == ~T10_E~0); 65497#L1494-1 assume !(1 == ~T11_E~0); 65498#L1499-1 assume !(1 == ~T12_E~0); 65704#L1504-1 assume !(1 == ~T13_E~0); 65705#L1509-1 assume !(1 == ~E_M~0); 66285#L1514-1 assume !(1 == ~E_1~0); 65956#L1519-1 assume !(1 == ~E_2~0); 65957#L1524-1 assume !(1 == ~E_3~0); 66513#L1529-1 assume !(1 == ~E_4~0); 66514#L1534-1 assume !(1 == ~E_5~0); 64626#L1539-1 assume !(1 == ~E_6~0); 64627#L1544-1 assume !(1 == ~E_7~0); 65020#L1549-1 assume !(1 == ~E_8~0); 66490#L1554-1 assume !(1 == ~E_9~0); 66488#L1559-1 assume !(1 == ~E_10~0); 66335#L1564-1 assume !(1 == ~E_11~0); 66336#L1569-1 assume !(1 == ~E_12~0); 66509#L1574-1 assume !(1 == ~E_13~0); 65319#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 65320#L1940 [2024-11-17 08:53:01,712 INFO L747 eck$LassoCheckResult]: Loop: 65320#L1940 assume true; 65362#L1940-1 assume !false; 65452#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65266#L1074 assume true; 65267#L1074-1 assume !false; 65981#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 65970#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 64727#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 66179#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 66180#L1079 assume !(0 != eval_~tmp~0#1); 65893#L1082 assume true; 65894#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66442#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66561#L1291 assume !(0 == ~M_E~0); 66562#L1296 assume !(0 == ~T1_E~0); 68355#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68354#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68353#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68352#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 68351#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 68350#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68349#L1331 assume 0 == ~T8_E~0;~T8_E~0 := 1; 68348#L1336 assume !(0 == ~T9_E~0); 68347#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 68346#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68345#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 68344#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 68343#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 68342#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 68341#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 68340#L1376 assume !(0 == ~E_3~0); 68339#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 68338#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 68337#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 68336#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 68335#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 68334#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 68333#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 68332#L1416 assume !(0 == ~E_11~0); 68331#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 68330#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 68329#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68328#L640-1 assume 1 == ~m_pc~0; 68327#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 68325#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65649#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65650#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65937#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65938#L659-1 assume !(1 == ~t1_pc~0); 64548#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 64549#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65852#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65501#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65502#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66270#L678-1 assume 1 == ~t2_pc~0; 65128#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65129#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65171#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65657#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65658#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66174#L697-1 assume 1 == ~t3_pc~0; 64672#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64673#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65095#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65251#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65252#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64709#L716-1 assume 1 == ~t4_pc~0; 64710#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 65067#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65068#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65355#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64573#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64574#L735-1 assume !(1 == ~t5_pc~0); 64581#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 64582#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66123#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65424#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 65425#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65541#L754-1 assume 1 == ~t6_pc~0; 65101#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65102#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65028#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 65029#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66418#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68127#L773-1 assume 1 == ~t7_pc~0; 68125#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68124#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68123#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68122#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68121#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68120#L792-1 assume !(1 == ~t8_pc~0); 68117#L802-1 is_transmit8_triggered_~__retres1~8#1 := 0; 68114#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68112#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68110#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68108#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68106#L811-1 assume !(1 == ~t9_pc~0); 68103#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 68100#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65353#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65176#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65154#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 64973#L830-1 assume !(1 == ~t10_pc~0); 64974#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 65980#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66010#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65483#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65484#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65991#L849-1 assume !(1 == ~t11_pc~0); 65993#L859-1 is_transmit11_triggered_~__retres1~11#1 := 0; 65159#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65160#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 65460#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65073#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65074#L868-1 assume !(1 == ~t12_pc~0); 65903#L878-1 is_transmit12_triggered_~__retres1~12#1 := 0; 65317#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65318#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 66168#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 66403#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 65977#L887-1 assume !(1 == ~t13_pc~0); 65979#L897-1 is_transmit13_triggered_~__retres1~13#1 := 0; 65324#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 65325#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 66047#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 64779#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64780#L1439 assume !(1 == ~M_E~0); 65219#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65220#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64881#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64882#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66105#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65951#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65952#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 66292#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66293#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65278#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65279#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 64828#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64829#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 65069#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 65070#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 64857#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 64766#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 64767#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 64471#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 64472#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 64991#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 65356#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 65537#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 65538#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 66498#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 66073#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 65706#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 65116#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 64736#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 64483#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 64783#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 64748#L1959 assume !(0 == start_simulation_~tmp~3#1); 64750#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 65084#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 64619#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 64620#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 65457#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66325#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66326#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 66434#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 65320#L1940 [2024-11-17 08:53:01,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:01,712 INFO L85 PathProgramCache]: Analyzing trace with hash -845756122, now seen corresponding path program 1 times [2024-11-17 08:53:01,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:01,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088663310] [2024-11-17 08:53:01,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:01,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:01,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:01,759 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:01,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:01,759 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088663310] [2024-11-17 08:53:01,759 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088663310] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:01,759 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:01,759 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:01,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1049897297] [2024-11-17 08:53:01,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:01,760 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:01,760 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:01,760 INFO L85 PathProgramCache]: Analyzing trace with hash 919976809, now seen corresponding path program 1 times [2024-11-17 08:53:01,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:01,761 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816652294] [2024-11-17 08:53:01,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:01,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:01,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:01,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:01,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:01,805 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816652294] [2024-11-17 08:53:01,805 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816652294] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:01,805 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:01,805 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:01,806 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [135638595] [2024-11-17 08:53:01,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:01,806 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:01,806 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:01,806 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:01,806 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:01,807 INFO L87 Difference]: Start difference. First operand 3891 states and 5665 transitions. cyclomatic complexity: 1775 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:01,887 INFO L93 Difference]: Finished difference Result 5691 states and 8269 transitions. [2024-11-17 08:53:01,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5691 states and 8269 transitions. [2024-11-17 08:53:01,900 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5496 [2024-11-17 08:53:01,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5691 states to 5691 states and 8269 transitions. [2024-11-17 08:53:01,908 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5691 [2024-11-17 08:53:01,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5691 [2024-11-17 08:53:01,912 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5691 states and 8269 transitions. [2024-11-17 08:53:01,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:01,916 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5691 states and 8269 transitions. [2024-11-17 08:53:01,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5691 states and 8269 transitions. [2024-11-17 08:53:01,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5691 to 3891. [2024-11-17 08:53:01,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3891 states, 3891 states have (on average 1.455152916987921) internal successors, (5662), 3890 states have internal predecessors, (5662), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:01,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3891 states to 3891 states and 5662 transitions. [2024-11-17 08:53:01,964 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3891 states and 5662 transitions. [2024-11-17 08:53:01,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:01,964 INFO L425 stractBuchiCegarLoop]: Abstraction has 3891 states and 5662 transitions. [2024-11-17 08:53:01,964 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:53:01,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3891 states and 5662 transitions. [2024-11-17 08:53:01,970 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3716 [2024-11-17 08:53:01,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:01,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:01,972 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:01,972 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:01,973 INFO L745 eck$LassoCheckResult]: Stem: 74990#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 74991#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 75711#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 76061#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76074#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 75845#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74494#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74495#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74735#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 74736#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75228#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74409#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 74410#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 75351#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 75352#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 74380#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 74381#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 76045#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 75425#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74601#L1291-1 assume !(0 == ~M_E~0); 74602#L1296-1 assume !(0 == ~T1_E~0); 75343#L1301-1 assume !(0 == ~T2_E~0); 75344#L1306-1 assume !(0 == ~T3_E~0); 75837#L1311-1 assume !(0 == ~T4_E~0); 74558#L1316-1 assume !(0 == ~T5_E~0); 74559#L1321-1 assume !(0 == ~T6_E~0); 75360#L1326-1 assume !(0 == ~T7_E~0); 74391#L1331-1 assume !(0 == ~T8_E~0); 74065#L1336-1 assume !(0 == ~T9_E~0); 74066#L1341-1 assume !(0 == ~T10_E~0); 74151#L1346-1 assume !(0 == ~T11_E~0); 74152#L1351-1 assume !(0 == ~T12_E~0); 74498#L1356-1 assume !(0 == ~T13_E~0); 74499#L1361-1 assume !(0 == ~E_M~0); 76079#L1366-1 assume !(0 == ~E_1~0); 74544#L1371-1 assume 0 == ~E_2~0;~E_2~0 := 1; 74545#L1376-1 assume !(0 == ~E_3~0); 75417#L1381-1 assume !(0 == ~E_4~0); 75418#L1386-1 assume !(0 == ~E_5~0); 76103#L1391-1 assume !(0 == ~E_6~0); 76120#L1396-1 assume !(0 == ~E_7~0); 75304#L1401-1 assume !(0 == ~E_8~0); 75305#L1406-1 assume !(0 == ~E_9~0); 75576#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 75577#L1416-1 assume !(0 == ~E_11~0); 75229#L1421-1 assume !(0 == ~E_12~0); 74703#L1426-1 assume !(0 == ~E_13~0); 74704#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74726#L640-16 assume 1 == ~m_pc~0; 75815#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 75211#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74831#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74832#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 75618#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75031#L659-16 assume 1 == ~t1_pc~0; 74654#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 74655#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75701#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 74528#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 74529#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74643#L678-16 assume 1 == ~t2_pc~0; 74644#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 74580#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74652#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74653#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 75999#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75702#L697-16 assume 1 == ~t3_pc~0; 75703#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 74187#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74592#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74116#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 74117#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75086#L716-16 assume 1 == ~t4_pc~0; 75745#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 74256#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75501#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75502#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 76110#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76063#L735-16 assume 1 == ~t5_pc~0; 75828#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 75829#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76053#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75611#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 75612#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75847#L754-16 assume 1 == ~t6_pc~0; 75848#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 75004#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75257#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 75258#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 75743#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75982#L773-16 assume 1 == ~t7_pc~0; 74649#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 74651#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76143#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74085#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 74086#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75789#L792-16 assume 1 == ~t8_pc~0; 75790#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 75261#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74414#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 74415#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 76118#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75475#L811-16 assume 1 == ~t9_pc~0; 74645#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 74646#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76098#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 74626#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 74627#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74185#L830-16 assume 1 == ~t10_pc~0; 74162#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 74163#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74686#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75140#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 75033#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75034#L849-16 assume 1 == ~t11_pc~0; 75426#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 75626#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76105#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 74873#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 74874#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75538#L868-16 assume 1 == ~t12_pc~0; 75539#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 74108#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 74450#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 74451#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 74739#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 74879#L887-16 assume 1 == ~t13_pc~0; 74411#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 74412#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 75476#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 74201#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 74202#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75852#L1439-1 assume !(1 == ~M_E~0); 74398#L1444-1 assume !(1 == ~T1_E~0); 74399#L1449-1 assume !(1 == ~T2_E~0); 74846#L1454-1 assume !(1 == ~T3_E~0); 74847#L1459-1 assume !(1 == ~T4_E~0); 75465#L1464-1 assume !(1 == ~T5_E~0); 75466#L1469-1 assume !(1 == ~T6_E~0); 75520#L1474-1 assume !(1 == ~T7_E~0); 75230#L1479-1 assume !(1 == ~T8_E~0); 75231#L1484-1 assume !(1 == ~T9_E~0); 75470#L1489-1 assume !(1 == ~T10_E~0); 75089#L1494-1 assume !(1 == ~T11_E~0); 75090#L1499-1 assume !(1 == ~T12_E~0); 75295#L1504-1 assume !(1 == ~T13_E~0); 75296#L1509-1 assume !(1 == ~E_M~0); 75872#L1514-1 assume !(1 == ~E_1~0); 75547#L1519-1 assume !(1 == ~E_2~0); 75548#L1524-1 assume !(1 == ~E_3~0); 76093#L1529-1 assume !(1 == ~E_4~0); 76094#L1534-1 assume !(1 == ~E_5~0); 74220#L1539-1 assume !(1 == ~E_6~0); 74221#L1544-1 assume !(1 == ~E_7~0); 74614#L1549-1 assume !(1 == ~E_8~0); 76071#L1554-1 assume !(1 == ~E_9~0); 76069#L1559-1 assume !(1 == ~E_10~0); 75919#L1564-1 assume !(1 == ~E_11~0); 75920#L1569-1 assume !(1 == ~E_12~0); 76089#L1574-1 assume !(1 == ~E_13~0); 74912#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 74913#L1940 [2024-11-17 08:53:01,973 INFO L747 eck$LassoCheckResult]: Loop: 74913#L1940 assume true; 74954#L1940-1 assume !false; 75044#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74859#L1074 assume true; 74860#L1074-1 assume !false; 75571#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 75560#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 74321#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75768#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 75769#L1079 assume !(0 != eval_~tmp~0#1); 75483#L1082 assume true; 75484#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76024#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76135#L1291 assume !(0 == ~M_E~0); 76111#L1296 assume !(0 == ~T1_E~0); 75353#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 74513#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 74514#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75510#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 75529#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 75870#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 75489#L1331 assume !(0 == ~T8_E~0); 75329#L1336 assume !(0 == ~T9_E~0); 75330#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 75873#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 74386#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 74387#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 75129#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 74486#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 74487#L1371 assume 0 == ~E_2~0;~E_2~0 := 1; 74716#L1376 assume !(0 == ~E_3~0); 76141#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 74639#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 74640#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 76003#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 76058#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 74951#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 74952#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 75342#L1416 assume !(0 == ~E_11~0); 74638#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 74469#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 74470#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75530#L640-1 assume 1 == ~m_pc~0; 75531#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 75808#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75240#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75241#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75527#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75528#L659-1 assume 1 == ~t1_pc~0; 76113#L660-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 74143#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74921#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75093#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75094#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75857#L678-1 assume 1 == ~t2_pc~0; 74721#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 74722#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 74764#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75248#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 75249#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75763#L697-1 assume 1 == ~t3_pc~0; 74266#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 74267#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74688#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74844#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74845#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74304#L716-1 assume 1 == ~t4_pc~0; 74305#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 74661#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74662#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74948#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 74167#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 74168#L735-1 assume 1 == ~t5_pc~0; 74212#L736-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 74176#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75715#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75016#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 75017#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75132#L754-1 assume 1 == ~t6_pc~0; 74694#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74695#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74622#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74623#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 75868#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74335#L773-1 assume !(1 == ~t7_pc~0); 74337#L783-1 is_transmit7_triggered_~__retres1~7#1 := 0; 75797#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75798#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74354#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 74355#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75035#L792-1 assume 1 == ~t8_pc~0; 74615#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 74616#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76000#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 74074#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 74075#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75468#L811-1 assume !(1 == ~t9_pc~0); 75392#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 75393#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74945#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 74769#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 74747#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74567#L830-1 assume 1 == ~t10_pc~0; 74569#L831-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 75570#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75599#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75075#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 75076#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75579#L849-1 assume !(1 == ~t11_pc~0); 75581#L859-1 is_transmit11_triggered_~__retres1~11#1 := 0; 74750#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 74751#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75052#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 74667#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 74668#L868-1 assume !(1 == ~t12_pc~0); 75491#L878-1 is_transmit12_triggered_~__retres1~12#1 := 0; 74910#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 74911#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 75757#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 75987#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 75567#L887-1 assume !(1 == ~t13_pc~0); 75569#L897-1 is_transmit13_triggered_~__retres1~13#1 := 0; 74917#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 74918#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 75637#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 74370#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74371#L1439 assume !(1 == ~M_E~0); 74812#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 74813#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 74475#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 74476#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 75693#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75540#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 75541#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 75879#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75880#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 74871#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 74872#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 74418#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 74419#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 74663#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 74664#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 74449#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 74358#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 74359#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 74063#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 74064#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 74585#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 74946#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 75127#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 75128#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 76078#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 75663#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 75297#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 74709#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74330#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 74077#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74375#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 74340#L1959 assume !(0 == start_simulation_~tmp~3#1); 74342#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74677#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 74213#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74214#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 75049#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75909#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75910#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 76016#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 74913#L1940 [2024-11-17 08:53:01,973 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:01,974 INFO L85 PathProgramCache]: Analyzing trace with hash 493007301, now seen corresponding path program 1 times [2024-11-17 08:53:01,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:01,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972915033] [2024-11-17 08:53:01,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:01,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:01,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:02,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:02,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:02,074 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [972915033] [2024-11-17 08:53:02,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [972915033] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:02,074 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:02,074 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:02,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1054280647] [2024-11-17 08:53:02,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:02,075 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:02,075 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:02,075 INFO L85 PathProgramCache]: Analyzing trace with hash -1149204993, now seen corresponding path program 1 times [2024-11-17 08:53:02,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:02,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996637348] [2024-11-17 08:53:02,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:02,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:02,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:02,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:02,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:02,133 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996637348] [2024-11-17 08:53:02,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [996637348] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:02,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:02,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:02,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830196021] [2024-11-17 08:53:02,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:02,134 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:02,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:02,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:02,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:02,134 INFO L87 Difference]: Start difference. First operand 3891 states and 5662 transitions. cyclomatic complexity: 1772 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:02,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:02,272 INFO L93 Difference]: Finished difference Result 5584 states and 8108 transitions. [2024-11-17 08:53:02,273 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5584 states and 8108 transitions. [2024-11-17 08:53:02,287 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5396 [2024-11-17 08:53:02,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5584 states to 5584 states and 8108 transitions. [2024-11-17 08:53:02,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5584 [2024-11-17 08:53:02,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5584 [2024-11-17 08:53:02,299 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5584 states and 8108 transitions. [2024-11-17 08:53:02,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:02,302 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5584 states and 8108 transitions. [2024-11-17 08:53:02,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5584 states and 8108 transitions. [2024-11-17 08:53:02,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5584 to 3891. [2024-11-17 08:53:02,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3891 states, 3891 states have (on average 1.4543819069647905) internal successors, (5659), 3890 states have internal predecessors, (5659), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:02,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3891 states to 3891 states and 5659 transitions. [2024-11-17 08:53:02,345 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3891 states and 5659 transitions. [2024-11-17 08:53:02,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:02,346 INFO L425 stractBuchiCegarLoop]: Abstraction has 3891 states and 5659 transitions. [2024-11-17 08:53:02,346 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:53:02,346 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3891 states and 5659 transitions. [2024-11-17 08:53:02,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3716 [2024-11-17 08:53:02,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:02,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:02,353 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:02,353 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:02,353 INFO L745 eck$LassoCheckResult]: Stem: 84477#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 84478#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 85199#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 85551#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 85564#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 85334#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83983#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83984#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84222#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84223#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84716#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 83896#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83897#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84839#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 84840#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 83867#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 83868#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 85535#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 84913#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84088#L1291-1 assume !(0 == ~M_E~0); 84089#L1296-1 assume !(0 == ~T1_E~0); 84831#L1301-1 assume !(0 == ~T2_E~0); 84832#L1306-1 assume !(0 == ~T3_E~0); 85326#L1311-1 assume !(0 == ~T4_E~0); 84045#L1316-1 assume !(0 == ~T5_E~0); 84046#L1321-1 assume !(0 == ~T6_E~0); 84848#L1326-1 assume !(0 == ~T7_E~0); 83878#L1331-1 assume !(0 == ~T8_E~0); 83552#L1336-1 assume !(0 == ~T9_E~0); 83553#L1341-1 assume !(0 == ~T10_E~0); 83638#L1346-1 assume !(0 == ~T11_E~0); 83639#L1351-1 assume !(0 == ~T12_E~0); 83985#L1356-1 assume !(0 == ~T13_E~0); 83986#L1361-1 assume !(0 == ~E_M~0); 85570#L1366-1 assume !(0 == ~E_1~0); 84034#L1371-1 assume !(0 == ~E_2~0); 84035#L1376-1 assume !(0 == ~E_3~0); 84905#L1381-1 assume !(0 == ~E_4~0); 84906#L1386-1 assume !(0 == ~E_5~0); 85593#L1391-1 assume !(0 == ~E_6~0); 85610#L1396-1 assume !(0 == ~E_7~0); 84792#L1401-1 assume !(0 == ~E_8~0); 84793#L1406-1 assume !(0 == ~E_9~0); 85065#L1411-1 assume 0 == ~E_10~0;~E_10~0 := 1; 85066#L1416-1 assume !(0 == ~E_11~0); 84717#L1421-1 assume !(0 == ~E_12~0); 84190#L1426-1 assume !(0 == ~E_13~0); 84191#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84213#L640-16 assume 1 == ~m_pc~0; 85303#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 84699#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84318#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84319#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 85106#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84518#L659-16 assume 1 == ~t1_pc~0; 84143#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 84144#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 85189#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84015#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 84016#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84130#L678-16 assume 1 == ~t2_pc~0; 84131#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 84069#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84139#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84140#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 85488#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85190#L697-16 assume 1 == ~t3_pc~0; 85191#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83677#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84079#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83603#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 83604#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84573#L716-16 assume 1 == ~t4_pc~0; 85233#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 83743#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84989#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84990#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 85600#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 85554#L735-16 assume 1 == ~t5_pc~0; 85316#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 85317#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85543#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85099#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 85100#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85336#L754-16 assume 1 == ~t6_pc~0; 85337#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 84491#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84745#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84746#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 85231#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85471#L773-16 assume 1 == ~t7_pc~0; 84136#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84138#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85634#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 83572#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 83573#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85277#L792-16 assume 1 == ~t8_pc~0; 85278#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84749#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83901#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83902#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 85608#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84963#L811-16 assume 1 == ~t9_pc~0; 84132#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84133#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85588#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 84115#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 84116#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 83672#L830-16 assume 1 == ~t10_pc~0; 83649#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 83650#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 84174#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84627#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 84521#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84522#L849-16 assume 1 == ~t11_pc~0; 84918#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 85114#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85595#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84360#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 84361#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85026#L868-16 assume 1 == ~t12_pc~0; 85027#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 83595#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83937#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 83938#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 84226#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 84366#L887-16 assume 1 == ~t13_pc~0; 83898#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 83899#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 84964#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 83690#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 83691#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 85341#L1439-1 assume !(1 == ~M_E~0); 83885#L1444-1 assume !(1 == ~T1_E~0); 83886#L1449-1 assume !(1 == ~T2_E~0); 84335#L1454-1 assume !(1 == ~T3_E~0); 84336#L1459-1 assume !(1 == ~T4_E~0); 84953#L1464-1 assume !(1 == ~T5_E~0); 84954#L1469-1 assume !(1 == ~T6_E~0); 85009#L1474-1 assume !(1 == ~T7_E~0); 84718#L1479-1 assume !(1 == ~T8_E~0); 84719#L1484-1 assume !(1 == ~T9_E~0); 84958#L1489-1 assume !(1 == ~T10_E~0); 84580#L1494-1 assume !(1 == ~T11_E~0); 84581#L1499-1 assume !(1 == ~T12_E~0); 84783#L1504-1 assume !(1 == ~T13_E~0); 84784#L1509-1 assume !(1 == ~E_M~0); 85361#L1514-1 assume !(1 == ~E_1~0); 85035#L1519-1 assume !(1 == ~E_2~0); 85036#L1524-1 assume !(1 == ~E_3~0); 85583#L1529-1 assume !(1 == ~E_4~0); 85584#L1534-1 assume !(1 == ~E_5~0); 83707#L1539-1 assume !(1 == ~E_6~0); 83708#L1544-1 assume !(1 == ~E_7~0); 84101#L1549-1 assume !(1 == ~E_8~0); 85561#L1554-1 assume !(1 == ~E_9~0); 85560#L1559-1 assume !(1 == ~E_10~0); 85408#L1564-1 assume !(1 == ~E_11~0); 85409#L1569-1 assume !(1 == ~E_12~0); 85579#L1574-1 assume !(1 == ~E_13~0); 84399#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 84400#L1940 [2024-11-17 08:53:02,354 INFO L747 eck$LassoCheckResult]: Loop: 84400#L1940 assume true; 84441#L1940-1 assume !false; 84531#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84346#L1074 assume true; 84347#L1074-1 assume !false; 85059#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85048#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 83808#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85256#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 85257#L1079 assume !(0 != eval_~tmp~0#1); 84971#L1082 assume true; 84972#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85514#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85625#L1291 assume !(0 == ~M_E~0); 85601#L1296 assume !(0 == ~T1_E~0); 84841#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 84000#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 84001#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 84998#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 85017#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 85359#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 84977#L1331 assume !(0 == ~T8_E~0); 84816#L1336 assume !(0 == ~T9_E~0); 84817#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 85362#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 83873#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 83874#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 84614#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 83973#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 83974#L1371 assume !(0 == ~E_2~0); 84201#L1376 assume !(0 == ~E_3~0); 85632#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 84126#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 84127#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 85493#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 85548#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 84438#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 84439#L1411 assume 0 == ~E_10~0;~E_10~0 := 1; 84830#L1416 assume !(0 == ~E_11~0); 84125#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 83956#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 83957#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85018#L640-1 assume 1 == ~m_pc~0; 85019#L641-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 85296#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84728#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84729#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85015#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85016#L659-1 assume 1 == ~t1_pc~0; 85603#L660-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 83630#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84408#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84578#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 84579#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85346#L678-1 assume 1 == ~t2_pc~0; 84208#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 84209#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84251#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84736#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 84737#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85251#L697-1 assume 1 == ~t3_pc~0; 83753#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83754#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84175#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 84331#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 84332#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83790#L716-1 assume !(1 == ~t4_pc~0); 83792#L726-1 is_transmit4_triggered_~__retres1~4#1 := 0; 84148#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84149#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84434#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83654#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83655#L735-1 assume 1 == ~t5_pc~0; 83699#L736-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83663#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85200#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84503#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 84504#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84619#L754-1 assume 1 == ~t6_pc~0; 84181#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 84182#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 84109#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84110#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 85357#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83822#L773-1 assume !(1 == ~t7_pc~0); 83824#L783-1 is_transmit7_triggered_~__retres1~7#1 := 0; 85285#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85286#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 83841#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 83842#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 84520#L792-1 assume 1 == ~t8_pc~0; 84102#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84103#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85489#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83561#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 83562#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 84956#L811-1 assume !(1 == ~t9_pc~0); 84880#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 84881#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84432#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 84256#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 84234#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 84054#L830-1 assume !(1 == ~t10_pc~0); 84055#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 85058#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 85087#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84562#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 84563#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 85069#L849-1 assume !(1 == ~t11_pc~0); 85071#L859-1 is_transmit11_triggered_~__retres1~11#1 := 0; 84239#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84240#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84539#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 84154#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84155#L868-1 assume !(1 == ~t12_pc~0); 84981#L878-1 is_transmit12_triggered_~__retres1~12#1 := 0; 84397#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84398#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85245#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 85476#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 85055#L887-1 assume !(1 == ~t13_pc~0); 85057#L897-1 is_transmit13_triggered_~__retres1~13#1 := 0; 84404#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 84405#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 85125#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 83860#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83861#L1439 assume !(1 == ~M_E~0); 84299#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84300#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83962#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83963#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 85182#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 85029#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85030#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 85368#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 85369#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 84358#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 84359#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 83909#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 83910#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 84150#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 84151#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 83936#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 83847#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 83848#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 83550#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 83551#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 84072#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 84435#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 84615#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 84616#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 85568#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 85151#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 84785#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 84196#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 83817#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 83564#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 83864#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 83829#L1959 assume !(0 == start_simulation_~tmp~3#1); 83831#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84164#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 83700#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 83701#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 84536#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 85398#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 85399#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 85506#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 84400#L1940 [2024-11-17 08:53:02,354 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:02,354 INFO L85 PathProgramCache]: Analyzing trace with hash 278178148, now seen corresponding path program 1 times [2024-11-17 08:53:02,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:02,355 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793388354] [2024-11-17 08:53:02,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:02,355 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:02,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:02,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:02,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:02,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793388354] [2024-11-17 08:53:02,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793388354] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:02,399 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:02,399 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:02,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360635145] [2024-11-17 08:53:02,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:02,400 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:02,400 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:02,400 INFO L85 PathProgramCache]: Analyzing trace with hash 885539364, now seen corresponding path program 1 times [2024-11-17 08:53:02,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:02,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028395372] [2024-11-17 08:53:02,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:02,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:02,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:02,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:02,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:02,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028395372] [2024-11-17 08:53:02,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1028395372] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:02,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:02,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:02,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069503376] [2024-11-17 08:53:02,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:02,446 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:02,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:02,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:02,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:02,446 INFO L87 Difference]: Start difference. First operand 3891 states and 5659 transitions. cyclomatic complexity: 1769 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:02,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:02,577 INFO L93 Difference]: Finished difference Result 5576 states and 8088 transitions. [2024-11-17 08:53:02,577 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5576 states and 8088 transitions. [2024-11-17 08:53:02,628 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5396 [2024-11-17 08:53:02,637 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5576 states to 5576 states and 8088 transitions. [2024-11-17 08:53:02,638 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5576 [2024-11-17 08:53:02,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5576 [2024-11-17 08:53:02,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5576 states and 8088 transitions. [2024-11-17 08:53:02,645 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:02,645 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5576 states and 8088 transitions. [2024-11-17 08:53:02,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5576 states and 8088 transitions. [2024-11-17 08:53:02,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5576 to 3891. [2024-11-17 08:53:02,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3891 states, 3891 states have (on average 1.4536108969416603) internal successors, (5656), 3890 states have internal predecessors, (5656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:02,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3891 states to 3891 states and 5656 transitions. [2024-11-17 08:53:02,694 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3891 states and 5656 transitions. [2024-11-17 08:53:02,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:02,694 INFO L425 stractBuchiCegarLoop]: Abstraction has 3891 states and 5656 transitions. [2024-11-17 08:53:02,695 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:53:02,695 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3891 states and 5656 transitions. [2024-11-17 08:53:02,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3716 [2024-11-17 08:53:02,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:02,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:02,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:02,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:02,704 INFO L745 eck$LassoCheckResult]: Stem: 93958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 93959#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 94684#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95040#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95053#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 94821#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93462#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93463#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 93702#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 93703#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94198#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 93375#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 93376#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 94321#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 94322#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 93346#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 93347#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 95023#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 94395#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93567#L1291-1 assume !(0 == ~M_E~0); 93568#L1296-1 assume !(0 == ~T1_E~0); 94313#L1301-1 assume !(0 == ~T2_E~0); 94314#L1306-1 assume !(0 == ~T3_E~0); 94814#L1311-1 assume !(0 == ~T4_E~0); 93524#L1316-1 assume !(0 == ~T5_E~0); 93525#L1321-1 assume !(0 == ~T6_E~0); 94330#L1326-1 assume !(0 == ~T7_E~0); 93357#L1331-1 assume !(0 == ~T8_E~0); 93031#L1336-1 assume !(0 == ~T9_E~0); 93032#L1341-1 assume !(0 == ~T10_E~0); 93117#L1346-1 assume !(0 == ~T11_E~0); 93118#L1351-1 assume !(0 == ~T12_E~0); 93464#L1356-1 assume !(0 == ~T13_E~0); 93465#L1361-1 assume !(0 == ~E_M~0); 95060#L1366-1 assume !(0 == ~E_1~0); 93513#L1371-1 assume !(0 == ~E_2~0); 93514#L1376-1 assume !(0 == ~E_3~0); 94387#L1381-1 assume !(0 == ~E_4~0); 94388#L1386-1 assume !(0 == ~E_5~0); 95085#L1391-1 assume !(0 == ~E_6~0); 95104#L1396-1 assume !(0 == ~E_7~0); 94274#L1401-1 assume !(0 == ~E_8~0); 94275#L1406-1 assume !(0 == ~E_9~0); 94550#L1411-1 assume !(0 == ~E_10~0); 94551#L1416-1 assume !(0 == ~E_11~0); 94201#L1421-1 assume !(0 == ~E_12~0); 93670#L1426-1 assume !(0 == ~E_13~0); 93671#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93693#L640-16 assume 1 == ~m_pc~0; 94793#L641-16 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 94181#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93798#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 93799#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 94591#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94000#L659-16 assume 1 == ~t1_pc~0; 93623#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 93624#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94674#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 93494#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 93495#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93609#L678-16 assume 1 == ~t2_pc~0; 93610#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 93548#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 93618#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 93619#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 94976#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94675#L697-16 assume 1 == ~t3_pc~0; 94676#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 93156#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93558#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 93082#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 93083#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94056#L716-16 assume 1 == ~t4_pc~0; 94719#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 93222#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94471#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 94472#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 95092#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95043#L735-16 assume 1 == ~t5_pc~0; 94805#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 94806#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95032#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 94584#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 94585#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94823#L754-16 assume 1 == ~t6_pc~0; 94824#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 93972#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94227#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 94228#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 94717#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94959#L773-16 assume 1 == ~t7_pc~0; 93615#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 93617#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 95133#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 93051#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 93052#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94763#L792-16 assume 1 == ~t8_pc~0; 94764#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 94231#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 93380#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 93381#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 95102#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94445#L811-16 assume 1 == ~t9_pc~0; 93611#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 93612#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 95079#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 93594#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 93595#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 93151#L830-16 assume 1 == ~t10_pc~0; 93128#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 93129#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 93654#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 94110#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 94004#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 94005#L849-16 assume 1 == ~t11_pc~0; 94400#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 94599#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95087#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 93840#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 93841#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 94509#L868-16 assume 1 == ~t12_pc~0; 94510#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 93074#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 93416#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 93417#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 93706#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 93846#L887-16 assume 1 == ~t13_pc~0; 93377#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 93378#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 94446#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 93169#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 93170#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94828#L1439-1 assume !(1 == ~M_E~0); 93364#L1444-1 assume !(1 == ~T1_E~0); 93365#L1449-1 assume !(1 == ~T2_E~0); 93815#L1454-1 assume !(1 == ~T3_E~0); 93816#L1459-1 assume !(1 == ~T4_E~0); 94435#L1464-1 assume !(1 == ~T5_E~0); 94436#L1469-1 assume !(1 == ~T6_E~0); 94492#L1474-1 assume !(1 == ~T7_E~0); 94202#L1479-1 assume !(1 == ~T8_E~0); 94203#L1484-1 assume !(1 == ~T9_E~0); 94442#L1489-1 assume !(1 == ~T10_E~0); 94063#L1494-1 assume !(1 == ~T11_E~0); 94064#L1499-1 assume !(1 == ~T12_E~0); 94265#L1504-1 assume !(1 == ~T13_E~0); 94266#L1509-1 assume !(1 == ~E_M~0); 94848#L1514-1 assume !(1 == ~E_1~0); 94521#L1519-1 assume !(1 == ~E_2~0); 94522#L1524-1 assume !(1 == ~E_3~0); 95074#L1529-1 assume !(1 == ~E_4~0); 95075#L1534-1 assume !(1 == ~E_5~0); 93186#L1539-1 assume !(1 == ~E_6~0); 93187#L1544-1 assume !(1 == ~E_7~0); 93580#L1549-1 assume !(1 == ~E_8~0); 95051#L1554-1 assume !(1 == ~E_9~0); 95049#L1559-1 assume !(1 == ~E_10~0); 94895#L1564-1 assume !(1 == ~E_11~0); 94896#L1569-1 assume !(1 == ~E_12~0); 95070#L1574-1 assume !(1 == ~E_13~0); 93879#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 93880#L1940 [2024-11-17 08:53:02,705 INFO L747 eck$LassoCheckResult]: Loop: 93880#L1940 assume true; 93922#L1940-1 assume !false; 94014#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 93826#L1074 assume true; 93827#L1074-1 assume !false; 94544#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 94531#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93287#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 94742#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 94743#L1079 assume !(0 != eval_~tmp~0#1); 94453#L1082 assume true; 94454#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 95002#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 95123#L1291 assume !(0 == ~M_E~0); 95093#L1296 assume !(0 == ~T1_E~0); 94323#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 93479#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 93480#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 94481#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94500#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 94846#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 94459#L1331 assume !(0 == ~T8_E~0); 94299#L1336 assume !(0 == ~T9_E~0); 94300#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 94849#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 93352#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 93353#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 94099#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 93452#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 93453#L1371 assume !(0 == ~E_2~0); 93683#L1376 assume !(0 == ~E_3~0); 95130#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 93607#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 93608#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 94980#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 95037#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 93919#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 93920#L1411 assume !(0 == ~E_10~0); 94312#L1416 assume !(0 == ~E_11~0); 93604#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 93435#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 93436#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94501#L640-1 assume !(1 == ~m_pc~0); 94503#L650-1 is_master_triggered_~__retres1~0#1 := 0; 94784#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94210#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 94211#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 94498#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94499#L659-1 assume !(1 == ~t1_pc~0); 93108#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 93109#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 93888#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94061#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 94062#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94833#L678-1 assume 1 == ~t2_pc~0; 93688#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 93689#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 93731#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94218#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 94219#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94737#L697-1 assume 1 == ~t3_pc~0; 93232#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 93233#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93655#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 93811#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 93812#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93270#L716-1 assume 1 == ~t4_pc~0; 93271#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 93627#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 93628#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 93916#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 93135#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 93136#L735-1 assume !(1 == ~t5_pc~0); 93142#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 93143#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94688#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 93984#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 93985#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94102#L754-1 assume 1 == ~t6_pc~0; 93661#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 93662#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 93588#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93589#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 94844#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 93298#L773-1 assume 1 == ~t7_pc~0; 93299#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 94773#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 94774#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 93319#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 93320#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94003#L792-1 assume 1 == ~t8_pc~0; 93581#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 93582#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 94977#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 93040#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 93041#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94438#L811-1 assume 1 == ~t9_pc~0; 94483#L812-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 94363#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 93913#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 93736#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 93714#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 93533#L830-1 assume 1 == ~t10_pc~0; 93535#L831-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 94541#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94572#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 94045#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 94046#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 94552#L849-1 assume 1 == ~t11_pc~0; 94553#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 93717#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 93718#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 94022#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 93633#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 93634#L868-1 assume !(1 == ~t12_pc~0); 94461#L878-1 is_transmit12_triggered_~__retres1~12#1 := 0; 93877#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 93878#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 94731#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 94964#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 94538#L887-1 assume 1 == ~t13_pc~0; 94539#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 93884#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 93885#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 94610#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 93336#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93337#L1439 assume !(1 == ~M_E~0); 93779#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 93780#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 93441#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 93442#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94666#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94511#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 94512#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 94855#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 94856#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 93838#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 93839#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 93384#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 93385#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 93629#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 93630#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 93415#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 93324#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 93325#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 93029#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 93030#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 93551#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 93914#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 94097#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 94098#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 95057#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 94636#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 94267#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 93676#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 93296#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93043#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 93341#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 93306#L1959 assume !(0 == start_simulation_~tmp~3#1); 93308#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 93643#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 93176#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 93177#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 94016#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 94885#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 94886#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 94994#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 93880#L1940 [2024-11-17 08:53:02,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:02,705 INFO L85 PathProgramCache]: Analyzing trace with hash 1504423939, now seen corresponding path program 1 times [2024-11-17 08:53:02,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:02,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [200733475] [2024-11-17 08:53:02,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:02,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:02,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:02,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:02,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:02,751 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [200733475] [2024-11-17 08:53:02,752 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [200733475] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:02,752 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:02,752 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:02,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18292799] [2024-11-17 08:53:02,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:02,753 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:02,753 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:02,753 INFO L85 PathProgramCache]: Analyzing trace with hash -571637510, now seen corresponding path program 1 times [2024-11-17 08:53:02,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:02,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956199361] [2024-11-17 08:53:02,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:02,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:02,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:02,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:02,813 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:02,813 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956199361] [2024-11-17 08:53:02,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956199361] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:02,813 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:02,814 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:02,814 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475362787] [2024-11-17 08:53:02,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:02,814 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:02,814 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:02,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:02,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:02,815 INFO L87 Difference]: Start difference. First operand 3891 states and 5656 transitions. cyclomatic complexity: 1766 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:02,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:02,934 INFO L93 Difference]: Finished difference Result 7557 states and 10919 transitions. [2024-11-17 08:53:02,934 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7557 states and 10919 transitions. [2024-11-17 08:53:02,954 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7379 [2024-11-17 08:53:02,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7557 states to 7557 states and 10919 transitions. [2024-11-17 08:53:02,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7557 [2024-11-17 08:53:02,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7557 [2024-11-17 08:53:02,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7557 states and 10919 transitions. [2024-11-17 08:53:02,978 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:02,978 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7557 states and 10919 transitions. [2024-11-17 08:53:02,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7557 states and 10919 transitions. [2024-11-17 08:53:03,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7557 to 7363. [2024-11-17 08:53:03,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7363 states, 7363 states have (on average 1.445742224636697) internal successors, (10645), 7362 states have internal predecessors, (10645), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:03,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7363 states to 7363 states and 10645 transitions. [2024-11-17 08:53:03,071 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7363 states and 10645 transitions. [2024-11-17 08:53:03,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:03,072 INFO L425 stractBuchiCegarLoop]: Abstraction has 7363 states and 10645 transitions. [2024-11-17 08:53:03,072 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:53:03,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7363 states and 10645 transitions. [2024-11-17 08:53:03,087 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7185 [2024-11-17 08:53:03,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:03,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:03,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:03,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:03,090 INFO L745 eck$LassoCheckResult]: Stem: 105424#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 105425#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 106205#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 106635#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 106655#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 106365#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104921#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104922#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105164#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 105165#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105678#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 104834#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 104835#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 105808#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 105809#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 104805#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 104806#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 106614#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 105887#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105026#L1291-1 assume !(0 == ~M_E~0); 105027#L1296-1 assume !(0 == ~T1_E~0); 105800#L1301-1 assume !(0 == ~T2_E~0); 105801#L1306-1 assume !(0 == ~T3_E~0); 106357#L1311-1 assume !(0 == ~T4_E~0); 104983#L1316-1 assume !(0 == ~T5_E~0); 104984#L1321-1 assume !(0 == ~T6_E~0); 105818#L1326-1 assume !(0 == ~T7_E~0); 104816#L1331-1 assume !(0 == ~T8_E~0); 104488#L1336-1 assume !(0 == ~T9_E~0); 104489#L1341-1 assume !(0 == ~T10_E~0); 104574#L1346-1 assume !(0 == ~T11_E~0); 104575#L1351-1 assume !(0 == ~T12_E~0); 104923#L1356-1 assume !(0 == ~T13_E~0); 104924#L1361-1 assume !(0 == ~E_M~0); 106666#L1366-1 assume !(0 == ~E_1~0); 104972#L1371-1 assume !(0 == ~E_2~0); 104973#L1376-1 assume !(0 == ~E_3~0); 105878#L1381-1 assume !(0 == ~E_4~0); 105879#L1386-1 assume !(0 == ~E_5~0); 106697#L1391-1 assume !(0 == ~E_6~0); 106718#L1396-1 assume !(0 == ~E_7~0); 105757#L1401-1 assume !(0 == ~E_8~0); 105758#L1406-1 assume !(0 == ~E_9~0); 106060#L1411-1 assume !(0 == ~E_10~0); 106061#L1416-1 assume !(0 == ~E_11~0); 105681#L1421-1 assume !(0 == ~E_12~0); 105131#L1426-1 assume !(0 == ~E_13~0); 105132#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105154#L640-16 assume !(1 == ~m_pc~0); 106334#L650-16 is_master_triggered_~__retres1~0#1 := 0; 105660#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105262#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 105263#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 106103#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105466#L659-16 assume 1 == ~t1_pc~0; 105085#L660-16 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 105086#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106194#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 104953#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 104954#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105071#L678-16 assume 1 == ~t2_pc~0; 105072#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 105007#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 105080#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 105081#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 106548#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106195#L697-16 assume 1 == ~t3_pc~0; 106196#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 104614#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 105017#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 104539#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 104540#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105524#L716-16 assume 1 == ~t4_pc~0; 106241#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 104680#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105967#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 105968#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 106704#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106638#L735-16 assume 1 == ~t5_pc~0; 106348#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 106349#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106625#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 106096#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 106097#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 106371#L754-16 assume 1 == ~t6_pc~0; 106372#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 105437#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 105709#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 105710#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 106238#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 106531#L773-16 assume 1 == ~t7_pc~0; 105077#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 105079#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 106764#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 104508#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 104509#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 106297#L792-16 assume 1 == ~t8_pc~0; 106298#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 105713#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 104839#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104840#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 106715#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 105941#L811-16 assume 1 == ~t9_pc~0; 105073#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 105074#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 106689#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 105055#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 105056#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 104609#L830-16 assume 1 == ~t10_pc~0; 104585#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 104586#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 105115#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 105583#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 105469#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 105470#L849-16 assume 1 == ~t11_pc~0; 105892#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 106111#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 106700#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 105305#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 105306#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 106018#L868-16 assume 1 == ~t12_pc~0; 106019#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 104531#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 104875#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 104876#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 105168#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 105311#L887-16 assume 1 == ~t13_pc~0; 104836#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 104837#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 105942#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 104627#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 104628#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106377#L1439-1 assume !(1 == ~M_E~0); 104823#L1444-1 assume !(1 == ~T1_E~0); 104824#L1449-1 assume !(1 == ~T2_E~0); 105279#L1454-1 assume !(1 == ~T3_E~0); 105280#L1459-1 assume !(1 == ~T4_E~0); 105930#L1464-1 assume !(1 == ~T5_E~0); 105931#L1469-1 assume !(1 == ~T6_E~0); 105996#L1474-1 assume !(1 == ~T7_E~0); 105682#L1479-1 assume !(1 == ~T8_E~0); 105683#L1484-1 assume !(1 == ~T9_E~0); 105937#L1489-1 assume !(1 == ~T10_E~0); 105534#L1494-1 assume !(1 == ~T11_E~0); 105535#L1499-1 assume !(1 == ~T12_E~0); 105747#L1504-1 assume !(1 == ~T13_E~0); 105748#L1509-1 assume !(1 == ~E_M~0); 106403#L1514-1 assume !(1 == ~E_1~0); 106030#L1519-1 assume !(1 == ~E_2~0); 106031#L1524-1 assume !(1 == ~E_3~0); 106682#L1529-1 assume !(1 == ~E_4~0); 106683#L1534-1 assume !(1 == ~E_5~0); 104644#L1539-1 assume !(1 == ~E_6~0); 104645#L1544-1 assume !(1 == ~E_7~0); 105041#L1549-1 assume !(1 == ~E_8~0); 106651#L1554-1 assume !(1 == ~E_9~0); 106649#L1559-1 assume !(1 == ~E_10~0); 106455#L1564-1 assume !(1 == ~E_11~0); 106456#L1569-1 assume !(1 == ~E_12~0); 106678#L1574-1 assume !(1 == ~E_13~0); 105345#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 105346#L1940 [2024-11-17 08:53:03,091 INFO L747 eck$LassoCheckResult]: Loop: 105346#L1940 assume true; 105390#L1940-1 assume !false; 105479#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105480#L1074 assume true; 106052#L1074-1 assume !false; 106053#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 106041#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 104746#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 106271#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 106272#L1079 assume !(0 != eval_~tmp~0#1); 105949#L1082 assume true; 105950#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106588#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 106758#L1291 assume !(0 == ~M_E~0); 110105#L1296 assume !(0 == ~T1_E~0); 110104#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 104938#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 104939#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 105980#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 106006#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 106401#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 105955#L1331 assume !(0 == ~T8_E~0); 105784#L1336 assume !(0 == ~T9_E~0); 105785#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 110097#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 110096#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 110095#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 110094#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 110093#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 110092#L1371 assume !(0 == ~E_2~0); 110091#L1376 assume !(0 == ~E_3~0); 110090#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 110089#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 110088#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 110087#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 110086#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 110085#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 110084#L1411 assume !(0 == ~E_10~0); 110082#L1416 assume !(0 == ~E_11~0); 110080#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 110078#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 110076#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110075#L640-1 assume !(1 == ~m_pc~0); 110072#L650-1 is_master_triggered_~__retres1~0#1 := 0; 110070#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110068#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 110066#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 110064#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110062#L659-1 assume 1 == ~t1_pc~0; 110059#L660-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 110056#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110054#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 110052#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 110050#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110048#L678-1 assume 1 == ~t2_pc~0; 110045#L679-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 110042#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110040#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 110038#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 110036#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110034#L697-1 assume !(1 == ~t3_pc~0); 110031#L707-1 is_transmit3_triggered_~__retres1~3#1 := 0; 110028#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110026#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 110024#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 110022#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110020#L716-1 assume 1 == ~t4_pc~0; 110017#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 110014#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110012#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 110010#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 110008#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110006#L735-1 assume 1 == ~t5_pc~0; 110003#L736-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 110000#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 109998#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 109996#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 109992#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 109989#L754-1 assume 1 == ~t6_pc~0; 109985#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 109981#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 109979#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 109977#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 109973#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 109971#L773-1 assume !(1 == ~t7_pc~0); 109968#L783-1 is_transmit7_triggered_~__retres1~7#1 := 0; 109965#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109963#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 109961#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 109959#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 109957#L792-1 assume 1 == ~t8_pc~0; 109953#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 109950#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 109948#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 109946#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 109944#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 109942#L811-1 assume !(1 == ~t9_pc~0); 109937#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 109935#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 109933#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 109931#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 109929#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 109685#L830-1 assume !(1 == ~t10_pc~0); 109682#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 109683#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 109678#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 109679#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 109674#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 109675#L849-1 assume 1 == ~t11_pc~0; 106341#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 105181#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 105182#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 105488#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 105095#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 105096#L868-1 assume !(1 == ~t12_pc~0); 105957#L878-1 is_transmit12_triggered_~__retres1~12#1 := 0; 109905#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 106259#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 106260#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 106536#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 106048#L887-1 assume 1 == ~t13_pc~0; 106049#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 109894#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 109893#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 109892#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 109889#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106684#L1439 assume !(1 == ~M_E~0); 105243#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 105244#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 104900#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 104901#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 111306#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 106020#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 106021#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 106411#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 106412#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 111272#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 106367#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 106368#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 105850#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 105091#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 105092#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 110572#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 110280#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 110279#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 110277#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 110275#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 110273#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 110270#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 110268#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 110266#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 110264#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 110262#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 110259#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 110258#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 110248#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 110242#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 110241#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 110240#L1959 assume !(0 == start_simulation_~tmp~3#1); 110238#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 105329#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 104636#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 104637#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 105485#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 106444#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 106445#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 106576#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 105346#L1940 [2024-11-17 08:53:03,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:03,091 INFO L85 PathProgramCache]: Analyzing trace with hash -250843578, now seen corresponding path program 1 times [2024-11-17 08:53:03,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:03,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396320172] [2024-11-17 08:53:03,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:03,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:03,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:03,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:03,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:03,139 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396320172] [2024-11-17 08:53:03,139 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396320172] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:03,139 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:03,139 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:03,139 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1691302737] [2024-11-17 08:53:03,139 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:03,140 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:03,140 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:03,140 INFO L85 PathProgramCache]: Analyzing trace with hash 2136915008, now seen corresponding path program 1 times [2024-11-17 08:53:03,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:03,140 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274784329] [2024-11-17 08:53:03,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:03,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:03,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:03,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:03,192 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:03,192 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274784329] [2024-11-17 08:53:03,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274784329] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:03,193 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:03,193 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:03,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1252669117] [2024-11-17 08:53:03,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:03,193 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:03,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:03,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:03,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:03,193 INFO L87 Difference]: Start difference. First operand 7363 states and 10645 transitions. cyclomatic complexity: 3284 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:03,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:03,301 INFO L93 Difference]: Finished difference Result 14089 states and 20279 transitions. [2024-11-17 08:53:03,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14089 states and 20279 transitions. [2024-11-17 08:53:03,340 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13900 [2024-11-17 08:53:03,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14089 states to 14089 states and 20279 transitions. [2024-11-17 08:53:03,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14089 [2024-11-17 08:53:03,377 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14089 [2024-11-17 08:53:03,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14089 states and 20279 transitions. [2024-11-17 08:53:03,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:03,388 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14089 states and 20279 transitions. [2024-11-17 08:53:03,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14089 states and 20279 transitions. [2024-11-17 08:53:03,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14089 to 14073. [2024-11-17 08:53:03,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14073 states, 14073 states have (on average 1.4398493569246074) internal successors, (20263), 14072 states have internal predecessors, (20263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:03,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14073 states to 14073 states and 20263 transitions. [2024-11-17 08:53:03,604 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14073 states and 20263 transitions. [2024-11-17 08:53:03,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:03,605 INFO L425 stractBuchiCegarLoop]: Abstraction has 14073 states and 20263 transitions. [2024-11-17 08:53:03,605 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:53:03,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14073 states and 20263 transitions. [2024-11-17 08:53:03,632 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13884 [2024-11-17 08:53:03,632 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:03,632 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:03,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:03,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:03,634 INFO L745 eck$LassoCheckResult]: Stem: 126881#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 126882#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 127627#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 128009#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 128024#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 127770#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126379#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126380#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126623#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126624#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 127120#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 126294#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 126295#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 127250#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 127251#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 126265#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 126266#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 127988#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 127326#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126487#L1291-1 assume !(0 == ~M_E~0); 126488#L1296-1 assume !(0 == ~T1_E~0); 127242#L1301-1 assume !(0 == ~T2_E~0); 127243#L1306-1 assume !(0 == ~T3_E~0); 127762#L1311-1 assume !(0 == ~T4_E~0); 126443#L1316-1 assume !(0 == ~T5_E~0); 126444#L1321-1 assume !(0 == ~T6_E~0); 127259#L1326-1 assume !(0 == ~T7_E~0); 126276#L1331-1 assume !(0 == ~T8_E~0); 125947#L1336-1 assume !(0 == ~T9_E~0); 125948#L1341-1 assume !(0 == ~T10_E~0); 126035#L1346-1 assume !(0 == ~T11_E~0); 126036#L1351-1 assume !(0 == ~T12_E~0); 126383#L1356-1 assume !(0 == ~T13_E~0); 126384#L1361-1 assume !(0 == ~E_M~0); 128029#L1366-1 assume !(0 == ~E_1~0); 126429#L1371-1 assume !(0 == ~E_2~0); 126430#L1376-1 assume !(0 == ~E_3~0); 127317#L1381-1 assume !(0 == ~E_4~0); 127318#L1386-1 assume !(0 == ~E_5~0); 128058#L1391-1 assume !(0 == ~E_6~0); 128077#L1396-1 assume !(0 == ~E_7~0); 127203#L1401-1 assume !(0 == ~E_8~0); 127204#L1406-1 assume !(0 == ~E_9~0); 127483#L1411-1 assume !(0 == ~E_10~0); 127484#L1416-1 assume !(0 == ~E_11~0); 127123#L1421-1 assume !(0 == ~E_12~0); 126589#L1426-1 assume !(0 == ~E_13~0); 126590#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126613#L640-16 assume !(1 == ~m_pc~0); 127739#L650-16 is_master_triggered_~__retres1~0#1 := 0; 127106#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126720#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126721#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 127529#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126923#L659-16 assume !(1 == ~t1_pc~0); 126924#L669-16 is_transmit1_triggered_~__retres1~1#1 := 0; 127196#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 127616#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126413#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 126414#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126531#L678-16 assume 1 == ~t2_pc~0; 126532#L679-16 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 126465#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126540#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126541#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 127934#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 127617#L697-16 assume 1 == ~t3_pc~0; 127618#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 126071#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126478#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 126000#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 126001#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126979#L716-16 assume 1 == ~t4_pc~0; 127661#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 126140#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 127403#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 127404#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 128066#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128011#L735-16 assume 1 == ~t5_pc~0; 127754#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 127755#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 128001#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 127522#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 127523#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 127772#L754-16 assume 1 == ~t6_pc~0; 127773#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 126894#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 127152#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 127153#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 127659#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 127917#L773-16 assume 1 == ~t7_pc~0; 126537#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 126539#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 128119#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125969#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 125970#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 127712#L792-16 assume 1 == ~t8_pc~0; 127713#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 127156#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 126299#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126300#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 128074#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 127377#L811-16 assume 1 == ~t9_pc~0; 126533#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 126534#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 128050#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 126514#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 126515#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 126069#L830-16 assume 1 == ~t10_pc~0; 126046#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 126047#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 126572#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 127034#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 126926#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 126927#L849-16 assume 1 == ~t11_pc~0; 127327#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 127538#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 128060#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 126761#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 126762#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 127445#L868-16 assume 1 == ~t12_pc~0; 127446#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 125992#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 126334#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 126335#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 126627#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 126767#L887-16 assume 1 == ~t13_pc~0; 126296#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 126297#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 127378#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 126079#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 126080#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127777#L1439-1 assume !(1 == ~M_E~0); 126283#L1444-1 assume !(1 == ~T1_E~0); 126284#L1449-1 assume !(1 == ~T2_E~0); 126734#L1454-1 assume !(1 == ~T3_E~0); 126735#L1459-1 assume !(1 == ~T4_E~0); 127367#L1464-1 assume !(1 == ~T5_E~0); 127368#L1469-1 assume !(1 == ~T6_E~0); 127427#L1474-1 assume !(1 == ~T7_E~0); 127124#L1479-1 assume !(1 == ~T8_E~0); 127125#L1484-1 assume !(1 == ~T9_E~0); 127372#L1489-1 assume !(1 == ~T10_E~0); 126982#L1494-1 assume !(1 == ~T11_E~0); 126983#L1499-1 assume !(1 == ~T12_E~0); 127192#L1504-1 assume !(1 == ~T13_E~0); 127193#L1509-1 assume !(1 == ~E_M~0); 127799#L1514-1 assume !(1 == ~E_1~0); 127453#L1519-1 assume !(1 == ~E_2~0); 127454#L1524-1 assume !(1 == ~E_3~0); 128045#L1529-1 assume !(1 == ~E_4~0); 128046#L1534-1 assume !(1 == ~E_5~0); 126104#L1539-1 assume !(1 == ~E_6~0); 126105#L1544-1 assume !(1 == ~E_7~0); 126502#L1549-1 assume !(1 == ~E_8~0); 128019#L1554-1 assume !(1 == ~E_9~0); 128017#L1559-1 assume !(1 == ~E_10~0); 127850#L1564-1 assume !(1 == ~E_11~0); 127851#L1569-1 assume !(1 == ~E_12~0); 128040#L1574-1 assume !(1 == ~E_13~0); 126800#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 126801#L1940 [2024-11-17 08:53:03,635 INFO L747 eck$LassoCheckResult]: Loop: 126801#L1940 assume true; 130998#L1940-1 assume !false; 130986#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 130978#L1074 assume true; 130976#L1074-1 assume !false; 130974#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 130965#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 130944#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 128296#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 128297#L1079 assume !(0 != eval_~tmp~0#1); 130938#L1082 assume true; 135956#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 135955#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 135954#L1291 assume !(0 == ~M_E~0); 135953#L1296 assume !(0 == ~T1_E~0); 135952#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 135951#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 135950#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 135949#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 135948#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 135947#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 135946#L1331 assume !(0 == ~T8_E~0); 135945#L1336 assume !(0 == ~T9_E~0); 135944#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 135943#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 135942#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 135941#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 135940#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 135939#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 135938#L1371 assume !(0 == ~E_2~0); 135937#L1376 assume !(0 == ~E_3~0); 135936#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 135935#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 135934#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 135933#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 135932#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 135931#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 135930#L1411 assume !(0 == ~E_10~0); 135929#L1416 assume !(0 == ~E_11~0); 135928#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 135927#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 135926#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 135925#L640-1 assume !(1 == ~m_pc~0); 135924#L650-1 is_master_triggered_~__retres1~0#1 := 0; 135923#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135922#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 135921#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 135920#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 135919#L659-1 assume !(1 == ~t1_pc~0); 135918#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 135917#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135916#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 135915#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 135914#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 135913#L678-1 assume !(1 == ~t2_pc~0); 135911#L688-1 is_transmit2_triggered_~__retres1~2#1 := 0; 135910#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 135909#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 135908#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 135907#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 135906#L697-1 assume 1 == ~t3_pc~0; 135904#L698-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 135903#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 135902#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 135901#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 135900#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 135899#L716-1 assume 1 == ~t4_pc~0; 135898#L717-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 135896#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 135895#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 135894#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 135893#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 135892#L735-1 assume !(1 == ~t5_pc~0); 135890#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 135889#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135888#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 135887#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 135886#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 135885#L754-1 assume !(1 == ~t6_pc~0); 135883#L764-1 is_transmit6_triggered_~__retres1~6#1 := 0; 135882#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 135881#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 135880#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 135879#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 135878#L773-1 assume 1 == ~t7_pc~0; 135876#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 135875#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 135874#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 135873#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 135872#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 135871#L792-1 assume 1 == ~t8_pc~0; 135870#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 135868#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 135867#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 135866#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 135865#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 135864#L811-1 assume !(1 == ~t9_pc~0); 135862#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 135861#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 135860#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 135859#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 135858#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 135857#L830-1 assume 1 == ~t10_pc~0; 135856#L831-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 135854#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 135853#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 135852#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 135851#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 135850#L849-1 assume 1 == ~t11_pc~0; 135848#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 135847#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 135846#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 135845#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 135844#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 135843#L868-1 assume 1 == ~t12_pc~0; 135842#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 135840#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 135839#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 135838#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 135837#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 135836#L887-1 assume !(1 == ~t13_pc~0); 135834#L897-1 is_transmit13_triggered_~__retres1~13#1 := 0; 135833#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 135832#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 135831#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 135830#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 135829#L1439 assume !(1 == ~M_E~0); 131398#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 135828#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 135827#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 135826#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 135825#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 135824#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 135823#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 135822#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 135821#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 135820#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 135819#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 135818#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 135817#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 135816#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 135815#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 135814#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 135813#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 135812#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 135811#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 135810#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 135809#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 135808#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 135807#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 135806#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 135805#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 135804#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 135803#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 135802#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 135792#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 135787#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 135786#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 126226#L1959 assume !(0 == start_simulation_~tmp~3#1); 126228#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 131184#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 131174#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 131172#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 131170#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 131041#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 131038#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 131035#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 126801#L1940 [2024-11-17 08:53:03,635 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:03,635 INFO L85 PathProgramCache]: Analyzing trace with hash 1448991433, now seen corresponding path program 1 times [2024-11-17 08:53:03,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:03,636 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1057170290] [2024-11-17 08:53:03,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:03,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:03,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:03,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:03,673 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:03,673 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1057170290] [2024-11-17 08:53:03,673 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1057170290] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:03,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:03,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:03,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1803390628] [2024-11-17 08:53:03,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:03,674 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:03,674 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:03,674 INFO L85 PathProgramCache]: Analyzing trace with hash -603171133, now seen corresponding path program 1 times [2024-11-17 08:53:03,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:03,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266248874] [2024-11-17 08:53:03,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:03,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:03,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:03,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:03,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:03,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266248874] [2024-11-17 08:53:03,717 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266248874] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:03,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:03,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:03,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188352408] [2024-11-17 08:53:03,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:03,717 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:03,718 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:03,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:03,718 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:03,718 INFO L87 Difference]: Start difference. First operand 14073 states and 20263 transitions. cyclomatic complexity: 6194 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:03,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:03,850 INFO L93 Difference]: Finished difference Result 27048 states and 38784 transitions. [2024-11-17 08:53:03,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27048 states and 38784 transitions. [2024-11-17 08:53:03,944 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26836 [2024-11-17 08:53:04,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27048 states to 27048 states and 38784 transitions. [2024-11-17 08:53:04,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27048 [2024-11-17 08:53:04,020 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27048 [2024-11-17 08:53:04,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27048 states and 38784 transitions. [2024-11-17 08:53:04,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:04,044 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27048 states and 38784 transitions. [2024-11-17 08:53:04,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27048 states and 38784 transitions. [2024-11-17 08:53:04,331 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27048 to 27016. [2024-11-17 08:53:04,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27016 states, 27016 states have (on average 1.4344092389694996) internal successors, (38752), 27015 states have internal predecessors, (38752), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:04,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27016 states to 27016 states and 38752 transitions. [2024-11-17 08:53:04,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27016 states and 38752 transitions. [2024-11-17 08:53:04,392 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:04,393 INFO L425 stractBuchiCegarLoop]: Abstraction has 27016 states and 38752 transitions. [2024-11-17 08:53:04,393 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:53:04,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27016 states and 38752 transitions. [2024-11-17 08:53:04,454 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26804 [2024-11-17 08:53:04,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:04,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:04,457 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:04,457 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:04,457 INFO L745 eck$LassoCheckResult]: Stem: 168013#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 168014#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 168779#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 169221#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169243#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 168937#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 167511#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 167512#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 167751#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 167752#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 168262#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 167425#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 167426#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 168391#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 168392#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 167396#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 167397#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 169196#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 168468#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 167618#L1291-1 assume !(0 == ~M_E~0); 167619#L1296-1 assume !(0 == ~T1_E~0); 168383#L1301-1 assume !(0 == ~T2_E~0); 168384#L1306-1 assume !(0 == ~T3_E~0); 168927#L1311-1 assume !(0 == ~T4_E~0); 167575#L1316-1 assume !(0 == ~T5_E~0); 167576#L1321-1 assume !(0 == ~T6_E~0); 168400#L1326-1 assume !(0 == ~T7_E~0); 167407#L1331-1 assume !(0 == ~T8_E~0); 167077#L1336-1 assume !(0 == ~T9_E~0); 167078#L1341-1 assume !(0 == ~T10_E~0); 167165#L1346-1 assume !(0 == ~T11_E~0); 167166#L1351-1 assume !(0 == ~T12_E~0); 167515#L1356-1 assume !(0 == ~T13_E~0); 167516#L1361-1 assume !(0 == ~E_M~0); 169249#L1366-1 assume !(0 == ~E_1~0); 167561#L1371-1 assume !(0 == ~E_2~0); 167562#L1376-1 assume !(0 == ~E_3~0); 168459#L1381-1 assume !(0 == ~E_4~0); 168460#L1386-1 assume !(0 == ~E_5~0); 169290#L1391-1 assume !(0 == ~E_6~0); 169315#L1396-1 assume !(0 == ~E_7~0); 168343#L1401-1 assume !(0 == ~E_8~0); 168344#L1406-1 assume !(0 == ~E_9~0); 168635#L1411-1 assume !(0 == ~E_10~0); 168636#L1416-1 assume !(0 == ~E_11~0); 168265#L1421-1 assume !(0 == ~E_12~0); 167718#L1426-1 assume !(0 == ~E_13~0); 167719#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 167741#L640-16 assume !(1 == ~m_pc~0); 168903#L650-16 is_master_triggered_~__retres1~0#1 := 0; 168247#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 167850#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 167851#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 168682#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 168057#L659-16 assume !(1 == ~t1_pc~0); 168058#L669-16 is_transmit1_triggered_~__retres1~1#1 := 0; 168337#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 168769#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 167545#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 167546#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 167661#L678-16 assume !(1 == ~t2_pc~0); 167596#L688-16 is_transmit2_triggered_~__retres1~2#1 := 0; 167597#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 167669#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 167670#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 169126#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 168770#L697-16 assume 1 == ~t3_pc~0; 168771#L698-16 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 167202#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 167609#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 167130#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 167131#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 168117#L716-16 assume 1 == ~t4_pc~0; 168813#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 167271#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 168546#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 168547#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 169297#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169225#L735-16 assume 1 == ~t5_pc~0; 168915#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 168916#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169208#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 168675#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 168676#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 168940#L754-16 assume 1 == ~t6_pc~0; 168941#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 168027#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168295#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 168296#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 168811#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169100#L773-16 assume 1 == ~t7_pc~0; 167666#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 167668#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169371#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 167099#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 167100#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 168871#L792-16 assume 1 == ~t8_pc~0; 168872#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 168299#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 167430#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 167431#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 169312#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 168519#L811-16 assume 1 == ~t9_pc~0; 167662#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 167663#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 169280#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 167644#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 167645#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 167200#L830-16 assume 1 == ~t10_pc~0; 167176#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 167177#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 167700#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 168175#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 168060#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 168061#L849-16 assume 1 == ~t11_pc~0; 168469#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 168691#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 169292#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 167891#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 167892#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 168595#L868-16 assume 1 == ~t12_pc~0; 168596#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 167122#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 167465#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 167466#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 167755#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 167897#L887-16 assume 1 == ~t13_pc~0; 167427#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 167428#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 168520#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 167210#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 167211#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168947#L1439-1 assume !(1 == ~M_E~0); 167414#L1444-1 assume !(1 == ~T1_E~0); 167415#L1449-1 assume !(1 == ~T2_E~0); 167864#L1454-1 assume !(1 == ~T3_E~0); 167865#L1459-1 assume !(1 == ~T4_E~0); 168509#L1464-1 assume !(1 == ~T5_E~0); 168510#L1469-1 assume !(1 == ~T6_E~0); 168572#L1474-1 assume !(1 == ~T7_E~0); 168266#L1479-1 assume !(1 == ~T8_E~0); 168267#L1484-1 assume !(1 == ~T9_E~0); 168514#L1489-1 assume !(1 == ~T10_E~0); 168120#L1494-1 assume !(1 == ~T11_E~0); 168121#L1499-1 assume !(1 == ~T12_E~0); 168334#L1504-1 assume !(1 == ~T13_E~0); 168335#L1509-1 assume !(1 == ~E_M~0); 168971#L1514-1 assume !(1 == ~E_1~0); 168603#L1519-1 assume !(1 == ~E_2~0); 168604#L1524-1 assume !(1 == ~E_3~0); 169272#L1529-1 assume !(1 == ~E_4~0); 169273#L1534-1 assume !(1 == ~E_5~0); 167235#L1539-1 assume !(1 == ~E_6~0); 167236#L1544-1 assume !(1 == ~E_7~0); 167631#L1549-1 assume !(1 == ~E_8~0); 169238#L1554-1 assume !(1 == ~E_9~0); 169236#L1559-1 assume !(1 == ~E_10~0); 169021#L1564-1 assume !(1 == ~E_11~0); 169022#L1569-1 assume !(1 == ~E_12~0); 169264#L1574-1 assume !(1 == ~E_13~0); 167930#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 167931#L1940 [2024-11-17 08:53:04,458 INFO L747 eck$LassoCheckResult]: Loop: 167931#L1940 assume true; 177006#L1940-1 assume !false; 177004#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 176999#L1074 assume true; 176996#L1074-1 assume !false; 176994#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 176977#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 176969#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 176968#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 176966#L1079 assume !(0 != eval_~tmp~0#1); 176963#L1082 assume true; 176960#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176958#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176956#L1291 assume !(0 == ~M_E~0); 176954#L1296 assume !(0 == ~T1_E~0); 176871#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 176869#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176866#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 176863#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 176860#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 176857#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 176853#L1331 assume !(0 == ~T8_E~0); 176849#L1336 assume !(0 == ~T9_E~0); 176845#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 176841#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 176837#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 176833#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 176829#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 176823#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 176818#L1371 assume !(0 == ~E_2~0); 176813#L1376 assume !(0 == ~E_3~0); 175130#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 175127#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 175125#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 175123#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 175121#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 175119#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 175117#L1411 assume !(0 == ~E_10~0); 175114#L1416 assume !(0 == ~E_11~0); 175112#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 175110#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 175108#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 175106#L640-1 assume !(1 == ~m_pc~0); 175104#L650-1 is_master_triggered_~__retres1~0#1 := 0; 175101#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 175099#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 175097#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 175095#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 175093#L659-1 assume !(1 == ~t1_pc~0); 175091#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 175090#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 175087#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 175085#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 175083#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175081#L678-1 assume !(1 == ~t2_pc~0); 175079#L688-1 is_transmit2_triggered_~__retres1~2#1 := 0; 175077#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 175074#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 175072#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 175070#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 175068#L697-1 assume !(1 == ~t3_pc~0); 175066#L707-1 is_transmit3_triggered_~__retres1~3#1 := 0; 175063#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 175060#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 175058#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 175056#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 175054#L716-1 assume !(1 == ~t4_pc~0); 175051#L726-1 is_transmit4_triggered_~__retres1~4#1 := 0; 175049#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 175046#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 175044#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 175042#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 175040#L735-1 assume 1 == ~t5_pc~0; 175038#L736-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 175035#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 175032#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 175030#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 175028#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 175026#L754-1 assume 1 == ~t6_pc~0; 175024#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 175021#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175018#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 175016#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 175014#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 175012#L773-1 assume !(1 == ~t7_pc~0); 175010#L783-1 is_transmit7_triggered_~__retres1~7#1 := 0; 175008#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 175007#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 175006#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 175005#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 175004#L792-1 assume !(1 == ~t8_pc~0); 175002#L802-1 is_transmit8_triggered_~__retres1~8#1 := 0; 175001#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 175000#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 174999#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 174998#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 174997#L811-1 assume !(1 == ~t9_pc~0); 174994#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 174992#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 174990#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 174988#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 174986#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 174984#L830-1 assume 1 == ~t10_pc~0; 174982#L831-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 174978#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 174976#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 174974#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 174972#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 174970#L849-1 assume 1 == ~t11_pc~0; 174967#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 174965#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 174963#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 174961#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 174959#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 174957#L868-1 assume !(1 == ~t12_pc~0); 174954#L878-1 is_transmit12_triggered_~__retres1~12#1 := 0; 174951#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 174949#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 174947#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 174945#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 174943#L887-1 assume !(1 == ~t13_pc~0); 174940#L897-1 is_transmit13_triggered_~__retres1~13#1 := 0; 174937#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 174935#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 174933#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 174931#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 174929#L1439 assume !(1 == ~M_E~0); 174925#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 174922#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 174920#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 174918#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 174916#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 174914#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 174912#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 174909#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 174907#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 174905#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 174903#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 174901#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 174899#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 174896#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 174894#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 174892#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 174890#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 174888#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 174886#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 174883#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 174881#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 174879#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 174877#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 174875#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 174873#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 174870#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 174868#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 174866#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 174842#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 174836#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 174834#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 174831#L1959 assume !(0 == start_simulation_~tmp~3#1); 174832#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 177030#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 177020#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 177018#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 177016#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 177014#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 177011#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 177009#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 167931#L1940 [2024-11-17 08:53:04,458 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:04,458 INFO L85 PathProgramCache]: Analyzing trace with hash 1045407116, now seen corresponding path program 1 times [2024-11-17 08:53:04,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:04,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108469855] [2024-11-17 08:53:04,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:04,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:04,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:04,498 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:04,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:04,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108469855] [2024-11-17 08:53:04,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1108469855] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:04,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:04,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:04,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690038466] [2024-11-17 08:53:04,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:04,500 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:04,500 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:04,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1954202572, now seen corresponding path program 1 times [2024-11-17 08:53:04,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:04,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342159861] [2024-11-17 08:53:04,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:04,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:04,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:04,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:04,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:04,671 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342159861] [2024-11-17 08:53:04,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342159861] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:04,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:04,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:04,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1033541809] [2024-11-17 08:53:04,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:04,672 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:04,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:04,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:04,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:04,672 INFO L87 Difference]: Start difference. First operand 27016 states and 38752 transitions. cyclomatic complexity: 11744 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:04,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:04,879 INFO L93 Difference]: Finished difference Result 52043 states and 74369 transitions. [2024-11-17 08:53:04,879 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52043 states and 74369 transitions. [2024-11-17 08:53:05,081 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51760 [2024-11-17 08:53:05,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52043 states to 52043 states and 74369 transitions. [2024-11-17 08:53:05,439 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52043 [2024-11-17 08:53:05,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52043 [2024-11-17 08:53:05,468 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52043 states and 74369 transitions. [2024-11-17 08:53:05,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:05,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52043 states and 74369 transitions. [2024-11-17 08:53:05,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52043 states and 74369 transitions. [2024-11-17 08:53:06,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52043 to 51979. [2024-11-17 08:53:06,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51979 states, 51979 states have (on average 1.429519613690144) internal successors, (74305), 51978 states have internal predecessors, (74305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51979 states to 51979 states and 74305 transitions. [2024-11-17 08:53:06,218 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51979 states and 74305 transitions. [2024-11-17 08:53:06,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:06,219 INFO L425 stractBuchiCegarLoop]: Abstraction has 51979 states and 74305 transitions. [2024-11-17 08:53:06,219 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-17 08:53:06,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51979 states and 74305 transitions. [2024-11-17 08:53:06,338 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51696 [2024-11-17 08:53:06,454 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:06,454 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:06,455 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,459 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,459 INFO L745 eck$LassoCheckResult]: Stem: 247114#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 247115#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 247908#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 248380#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 248401#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 248074#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 246584#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 246585#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 246833#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 246834#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 247361#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 246496#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 246497#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 247495#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 247496#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 246466#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 246467#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 248349#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 247582#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 246695#L1291-1 assume !(0 == ~M_E~0); 246696#L1296-1 assume !(0 == ~T1_E~0); 247487#L1301-1 assume !(0 == ~T2_E~0); 247488#L1306-1 assume !(0 == ~T3_E~0); 248062#L1311-1 assume !(0 == ~T4_E~0); 246650#L1316-1 assume !(0 == ~T5_E~0); 246651#L1321-1 assume !(0 == ~T6_E~0); 247504#L1326-1 assume !(0 == ~T7_E~0); 246478#L1331-1 assume !(0 == ~T8_E~0); 246145#L1336-1 assume !(0 == ~T9_E~0); 246146#L1341-1 assume !(0 == ~T10_E~0); 246233#L1346-1 assume !(0 == ~T11_E~0); 246234#L1351-1 assume !(0 == ~T12_E~0); 246588#L1356-1 assume !(0 == ~T13_E~0); 246589#L1361-1 assume !(0 == ~E_M~0); 248413#L1366-1 assume !(0 == ~E_1~0); 246635#L1371-1 assume !(0 == ~E_2~0); 246636#L1376-1 assume !(0 == ~E_3~0); 247571#L1381-1 assume !(0 == ~E_4~0); 247572#L1386-1 assume !(0 == ~E_5~0); 248465#L1391-1 assume !(0 == ~E_6~0); 248496#L1396-1 assume !(0 == ~E_7~0); 247444#L1401-1 assume !(0 == ~E_8~0); 247445#L1406-1 assume !(0 == ~E_9~0); 247752#L1411-1 assume !(0 == ~E_10~0); 247753#L1416-1 assume !(0 == ~E_11~0); 247364#L1421-1 assume !(0 == ~E_12~0); 246800#L1426-1 assume !(0 == ~E_13~0); 246801#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 246823#L640-16 assume !(1 == ~m_pc~0); 248034#L650-16 is_master_triggered_~__retres1~0#1 := 0; 247345#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 246939#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 246940#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 247798#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247157#L659-16 assume !(1 == ~t1_pc~0); 247158#L669-16 is_transmit1_triggered_~__retres1~1#1 := 0; 247438#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247897#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 246619#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 246620#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 246741#L678-16 assume !(1 == ~t2_pc~0); 246672#L688-16 is_transmit2_triggered_~__retres1~2#1 := 0; 246673#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 246749#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 246750#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 248266#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247899#L697-16 assume !(1 == ~t3_pc~0); 246270#L707-16 is_transmit3_triggered_~__retres1~3#1 := 0; 246271#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 246686#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 246198#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 246199#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247214#L716-16 assume 1 == ~t4_pc~0; 247948#L717-16 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 246341#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247664#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 247665#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 248478#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 248382#L735-16 assume 1 == ~t5_pc~0; 248049#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 248050#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 248364#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 247790#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 247791#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 248078#L754-16 assume 1 == ~t6_pc~0; 248079#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 247128#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247395#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 247396#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 247946#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 248242#L773-16 assume 1 == ~t7_pc~0; 246746#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 246748#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 248573#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 246167#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 246168#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 248003#L792-16 assume 1 == ~t8_pc~0; 248004#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 247399#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 246501#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 246502#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 248490#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 247637#L811-16 assume 1 == ~t9_pc~0; 246742#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 246743#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 248454#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 246722#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 246723#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 246269#L830-16 assume 1 == ~t10_pc~0; 246244#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 246245#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 246783#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 247272#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 247160#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 247161#L849-16 assume 1 == ~t11_pc~0; 247583#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 247809#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 248471#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 246984#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 246985#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 247708#L868-16 assume 1 == ~t12_pc~0; 247709#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 246190#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 246538#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 246539#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 246837#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 246990#L887-16 assume 1 == ~t13_pc~0; 246498#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 246499#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 247638#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 246280#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 246281#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 248085#L1439-1 assume !(1 == ~M_E~0); 246485#L1444-1 assume !(1 == ~T1_E~0); 246486#L1449-1 assume !(1 == ~T2_E~0); 246954#L1454-1 assume !(1 == ~T3_E~0); 246955#L1459-1 assume !(1 == ~T4_E~0); 247627#L1464-1 assume !(1 == ~T5_E~0); 247628#L1469-1 assume !(1 == ~T6_E~0); 247684#L1474-1 assume !(1 == ~T7_E~0); 247365#L1479-1 assume !(1 == ~T8_E~0); 247366#L1484-1 assume !(1 == ~T9_E~0); 247632#L1489-1 assume !(1 == ~T10_E~0); 247217#L1494-1 assume !(1 == ~T11_E~0); 247218#L1499-1 assume !(1 == ~T12_E~0); 247435#L1504-1 assume !(1 == ~T13_E~0); 247436#L1509-1 assume !(1 == ~E_M~0); 248110#L1514-1 assume !(1 == ~E_1~0); 247718#L1519-1 assume !(1 == ~E_2~0); 247719#L1524-1 assume !(1 == ~E_3~0); 248444#L1529-1 assume !(1 == ~E_4~0); 248445#L1534-1 assume !(1 == ~E_5~0); 246305#L1539-1 assume !(1 == ~E_6~0); 246306#L1544-1 assume !(1 == ~E_7~0); 246710#L1549-1 assume !(1 == ~E_8~0); 248396#L1554-1 assume !(1 == ~E_9~0); 248393#L1559-1 assume !(1 == ~E_10~0); 248168#L1564-1 assume !(1 == ~E_11~0); 248169#L1569-1 assume !(1 == ~E_12~0); 248437#L1574-1 assume !(1 == ~E_13~0); 247026#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 247027#L1940 [2024-11-17 08:53:06,461 INFO L747 eck$LassoCheckResult]: Loop: 247027#L1940 assume true; 262758#L1940-1 assume !false; 262726#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 262713#L1074 assume true; 262704#L1074-1 assume !false; 262699#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 262400#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 262392#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 262390#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 262387#L1079 assume !(0 != eval_~tmp~0#1); 262388#L1082 assume true; 273039#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 273033#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 273025#L1291 assume !(0 == ~M_E~0); 273019#L1296 assume !(0 == ~T1_E~0); 273014#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 273008#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 273002#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 272996#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 272990#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 272985#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 272979#L1331 assume !(0 == ~T8_E~0); 272972#L1336 assume !(0 == ~T9_E~0); 272965#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 272958#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 272951#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 272945#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 272939#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 272931#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 272922#L1371 assume !(0 == ~E_2~0); 272914#L1376 assume !(0 == ~E_3~0); 272908#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 272902#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 272896#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 272888#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 272882#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 272876#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 272871#L1411 assume !(0 == ~E_10~0); 272863#L1416 assume !(0 == ~E_11~0); 272856#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 272850#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 272843#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 272836#L640-1 assume !(1 == ~m_pc~0); 272830#L650-1 is_master_triggered_~__retres1~0#1 := 0; 272825#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 272820#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 272813#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 272806#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 272799#L659-1 assume !(1 == ~t1_pc~0); 272793#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 272787#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 272780#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 272773#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 272766#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 272759#L678-1 assume !(1 == ~t2_pc~0); 272753#L688-1 is_transmit2_triggered_~__retres1~2#1 := 0; 272747#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 272740#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 272733#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 272726#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 272719#L697-1 assume !(1 == ~t3_pc~0); 272713#L707-1 is_transmit3_triggered_~__retres1~3#1 := 0; 272707#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 272700#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 272693#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 272686#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 272679#L716-1 assume !(1 == ~t4_pc~0); 272672#L726-1 is_transmit4_triggered_~__retres1~4#1 := 0; 272666#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 272656#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 272648#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 272643#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 272637#L735-1 assume !(1 == ~t5_pc~0); 272631#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 272627#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272623#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 272617#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 272611#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 272605#L754-1 assume !(1 == ~t6_pc~0); 272598#L764-1 is_transmit6_triggered_~__retres1~6#1 := 0; 272591#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 272581#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 272554#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 272323#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 272320#L773-1 assume 1 == ~t7_pc~0; 272317#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 272315#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 272313#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 272295#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 272286#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 272277#L792-1 assume 1 == ~t8_pc~0; 272268#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 272259#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 272253#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 272252#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 272251#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 272250#L811-1 assume !(1 == ~t9_pc~0); 272248#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 272245#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 272244#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 272243#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 272240#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 272238#L830-1 assume 1 == ~t10_pc~0; 272236#L831-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 272233#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 272210#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 272202#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 272195#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 271746#L849-1 assume 1 == ~t11_pc~0; 271740#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 271735#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 271727#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 271722#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 271716#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 271711#L868-1 assume !(1 == ~t12_pc~0); 271705#L878-1 is_transmit12_triggered_~__retres1~12#1 := 0; 271700#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 271691#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 271685#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 271678#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 271672#L887-1 assume !(1 == ~t13_pc~0); 271665#L897-1 is_transmit13_triggered_~__retres1~13#1 := 0; 271659#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 271650#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 271644#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 271637#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 263401#L1439 assume !(1 == ~M_E~0); 263397#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 263395#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 263393#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 263391#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 263389#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 263387#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 263385#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 263383#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 263381#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 263379#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 263377#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 263375#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 263373#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 263371#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 263369#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 263366#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 263364#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 263362#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 263360#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 263358#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 263356#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 263353#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 263351#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 263349#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 263347#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 263345#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 263343#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 263342#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 262817#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 262811#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 262809#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 262806#L1959 assume !(0 == start_simulation_~tmp~3#1); 262802#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 262785#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 262774#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 262772#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 262770#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 262768#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 262766#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 262763#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 247027#L1940 [2024-11-17 08:53:06,462 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,462 INFO L85 PathProgramCache]: Analyzing trace with hash -954892657, now seen corresponding path program 1 times [2024-11-17 08:53:06,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070857266] [2024-11-17 08:53:06,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,537 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070857266] [2024-11-17 08:53:06,537 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070857266] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,537 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,537 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:06,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [684163347] [2024-11-17 08:53:06,537 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,537 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:06,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,538 INFO L85 PathProgramCache]: Analyzing trace with hash 1524173516, now seen corresponding path program 1 times [2024-11-17 08:53:06,538 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,538 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2100925420] [2024-11-17 08:53:06,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,538 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,585 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2100925420] [2024-11-17 08:53:06,585 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2100925420] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,585 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:06,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665801904] [2024-11-17 08:53:06,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,585 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:06,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:06,586 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:06,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:06,586 INFO L87 Difference]: Start difference. First operand 51979 states and 74305 transitions. cyclomatic complexity: 22342 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:07,155 INFO L93 Difference]: Finished difference Result 125598 states and 178602 transitions. [2024-11-17 08:53:07,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125598 states and 178602 transitions. [2024-11-17 08:53:07,857 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 124980 [2024-11-17 08:53:08,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125598 states to 125598 states and 178602 transitions. [2024-11-17 08:53:08,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125598 [2024-11-17 08:53:08,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125598 [2024-11-17 08:53:08,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125598 states and 178602 transitions. [2024-11-17 08:53:08,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:08,186 INFO L218 hiAutomatonCegarLoop]: Abstraction has 125598 states and 178602 transitions. [2024-11-17 08:53:08,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125598 states and 178602 transitions. [2024-11-17 08:53:09,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125598 to 100058. [2024-11-17 08:53:09,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100058 states, 100058 states have (on average 1.4249135501409183) internal successors, (142574), 100057 states have internal predecessors, (142574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:09,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100058 states to 100058 states and 142574 transitions. [2024-11-17 08:53:09,427 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100058 states and 142574 transitions. [2024-11-17 08:53:09,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:09,427 INFO L425 stractBuchiCegarLoop]: Abstraction has 100058 states and 142574 transitions. [2024-11-17 08:53:09,427 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-17 08:53:09,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100058 states and 142574 transitions. [2024-11-17 08:53:10,014 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 99664 [2024-11-17 08:53:10,015 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:10,015 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:10,017 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:10,017 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:10,017 INFO L745 eck$LassoCheckResult]: Stem: 424667#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 424668#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 425445#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 425853#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 425872#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 425593#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 424166#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 424167#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 424408#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 424409#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 424915#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 424080#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 424081#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 425052#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 425053#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 424050#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 424051#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 425830#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 425129#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 424273#L1291-1 assume !(0 == ~M_E~0); 424274#L1296-1 assume !(0 == ~T1_E~0); 425044#L1301-1 assume !(0 == ~T2_E~0); 425045#L1306-1 assume !(0 == ~T3_E~0); 425581#L1311-1 assume !(0 == ~T4_E~0); 424231#L1316-1 assume !(0 == ~T5_E~0); 424232#L1321-1 assume !(0 == ~T6_E~0); 425061#L1326-1 assume !(0 == ~T7_E~0); 424062#L1331-1 assume !(0 == ~T8_E~0); 423734#L1336-1 assume !(0 == ~T9_E~0); 423735#L1341-1 assume !(0 == ~T10_E~0); 423823#L1346-1 assume !(0 == ~T11_E~0); 423824#L1351-1 assume !(0 == ~T12_E~0); 424170#L1356-1 assume !(0 == ~T13_E~0); 424171#L1361-1 assume !(0 == ~E_M~0); 425880#L1366-1 assume !(0 == ~E_1~0); 424216#L1371-1 assume !(0 == ~E_2~0); 424217#L1376-1 assume !(0 == ~E_3~0); 425121#L1381-1 assume !(0 == ~E_4~0); 425122#L1386-1 assume !(0 == ~E_5~0); 425914#L1391-1 assume !(0 == ~E_6~0); 425931#L1396-1 assume !(0 == ~E_7~0); 425002#L1401-1 assume !(0 == ~E_8~0); 425003#L1406-1 assume !(0 == ~E_9~0); 425297#L1411-1 assume !(0 == ~E_10~0); 425298#L1416-1 assume !(0 == ~E_11~0); 424918#L1421-1 assume !(0 == ~E_12~0); 424376#L1426-1 assume !(0 == ~E_13~0); 424377#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 424399#L640-16 assume !(1 == ~m_pc~0); 425555#L650-16 is_master_triggered_~__retres1~0#1 := 0; 424899#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 424505#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 424506#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 425339#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 424708#L659-16 assume !(1 == ~t1_pc~0); 424709#L669-16 is_transmit1_triggered_~__retres1~1#1 := 0; 424995#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 425436#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 424200#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 424201#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 424315#L678-16 assume !(1 == ~t2_pc~0); 424250#L688-16 is_transmit2_triggered_~__retres1~2#1 := 0; 424251#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 424323#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 424324#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 425770#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 425437#L697-16 assume !(1 == ~t3_pc~0); 423858#L707-16 is_transmit3_triggered_~__retres1~3#1 := 0; 423859#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 424264#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 423789#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 423790#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 424768#L716-16 assume !(1 == ~t4_pc~0); 423927#L726-16 is_transmit4_triggered_~__retres1~4#1 := 0; 423928#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 425212#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 425213#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 425921#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 425855#L735-16 assume 1 == ~t5_pc~0; 425568#L736-16 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 425569#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 425844#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 425332#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 425333#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 425595#L754-16 assume 1 == ~t6_pc~0; 425596#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 424681#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 424952#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 424953#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 425476#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 425750#L773-16 assume 1 == ~t7_pc~0; 424320#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 424322#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 425980#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 423756#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 423757#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 425527#L792-16 assume 1 == ~t8_pc~0; 425528#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 424956#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 424085#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 424086#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 425929#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 425186#L811-16 assume 1 == ~t9_pc~0; 424316#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 424317#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 425906#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 424298#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 424299#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 423857#L830-16 assume 1 == ~t10_pc~0; 423834#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 423835#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 424359#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 424826#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 424711#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 424712#L849-16 assume 1 == ~t11_pc~0; 425130#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 425350#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 425916#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 424548#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 424549#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 425258#L868-16 assume 1 == ~t12_pc~0; 425259#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 423781#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 424122#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 424123#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 424412#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 424555#L887-16 assume 1 == ~t13_pc~0; 424082#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 424083#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 425187#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 423867#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 423868#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425601#L1439-1 assume !(1 == ~M_E~0); 424069#L1444-1 assume !(1 == ~T1_E~0); 424070#L1449-1 assume !(1 == ~T2_E~0); 424521#L1454-1 assume !(1 == ~T3_E~0); 424522#L1459-1 assume !(1 == ~T4_E~0); 425175#L1464-1 assume !(1 == ~T5_E~0); 425176#L1469-1 assume !(1 == ~T6_E~0); 425239#L1474-1 assume !(1 == ~T7_E~0); 424919#L1479-1 assume !(1 == ~T8_E~0); 424920#L1484-1 assume !(1 == ~T9_E~0); 425180#L1489-1 assume !(1 == ~T10_E~0); 424771#L1494-1 assume !(1 == ~T11_E~0); 424772#L1499-1 assume !(1 == ~T12_E~0); 424990#L1504-1 assume !(1 == ~T13_E~0); 424991#L1509-1 assume !(1 == ~E_M~0); 425625#L1514-1 assume !(1 == ~E_1~0); 425267#L1519-1 assume !(1 == ~E_2~0); 425268#L1524-1 assume !(1 == ~E_3~0); 425898#L1529-1 assume !(1 == ~E_4~0); 425899#L1534-1 assume !(1 == ~E_5~0); 423892#L1539-1 assume !(1 == ~E_6~0); 423893#L1544-1 assume !(1 == ~E_7~0); 424286#L1549-1 assume !(1 == ~E_8~0); 425868#L1554-1 assume !(1 == ~E_9~0); 425864#L1559-1 assume !(1 == ~E_10~0); 425681#L1564-1 assume !(1 == ~E_11~0); 425682#L1569-1 assume !(1 == ~E_12~0); 425892#L1574-1 assume !(1 == ~E_13~0); 424588#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 424589#L1940 [2024-11-17 08:53:10,018 INFO L747 eck$LassoCheckResult]: Loop: 424589#L1940 assume true; 484406#L1940-1 assume !false; 484404#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 484399#L1074 assume true; 484397#L1074-1 assume !false; 484395#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 484378#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 484370#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 484368#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 484365#L1079 assume !(0 != eval_~tmp~0#1); 484366#L1082 assume true; 498204#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 498202#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 498200#L1291 assume !(0 == ~M_E~0); 498197#L1296 assume !(0 == ~T1_E~0); 498195#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 498193#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 498191#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 498189#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 498187#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 498184#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 498182#L1331 assume !(0 == ~T8_E~0); 498180#L1336 assume !(0 == ~T9_E~0); 498178#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 498176#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 498174#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 498171#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 498169#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 498167#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 498165#L1371 assume !(0 == ~E_2~0); 498163#L1376 assume !(0 == ~E_3~0); 498161#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 498158#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 498156#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 498154#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 498152#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 498150#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 498148#L1411 assume !(0 == ~E_10~0); 498145#L1416 assume !(0 == ~E_11~0); 498143#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 498141#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 498139#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 498137#L640-1 assume !(1 == ~m_pc~0); 498136#L650-1 is_master_triggered_~__retres1~0#1 := 0; 498135#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 498134#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 498133#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 498132#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 498131#L659-1 assume !(1 == ~t1_pc~0); 498130#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 498129#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 498128#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 498127#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 498126#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 498125#L678-1 assume !(1 == ~t2_pc~0); 498124#L688-1 is_transmit2_triggered_~__retres1~2#1 := 0; 498123#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 498122#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 498121#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 498120#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 498119#L697-1 assume !(1 == ~t3_pc~0); 498118#L707-1 is_transmit3_triggered_~__retres1~3#1 := 0; 498116#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 498115#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 498113#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 498111#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 498109#L716-1 assume !(1 == ~t4_pc~0); 441012#L726-1 is_transmit4_triggered_~__retres1~4#1 := 0; 498107#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 498106#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 498105#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 498104#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 498103#L735-1 assume 1 == ~t5_pc~0; 498102#L736-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 498099#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 498096#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 498095#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 498094#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 498092#L754-1 assume 1 == ~t6_pc~0; 498089#L755-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 498083#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 498081#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 498079#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 498077#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 498075#L773-1 assume 1 == ~t7_pc~0; 498071#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 498069#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 498067#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 498065#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 498063#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 498061#L792-1 assume 1 == ~t8_pc~0; 498059#L793-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 498056#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 498054#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 498052#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 498050#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 498048#L811-1 assume 1 == ~t9_pc~0; 498046#L812-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 498043#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 498041#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 498039#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 498037#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 498035#L830-1 assume 1 == ~t10_pc~0; 498032#L831-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 498029#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 498027#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 498025#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 498023#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 498021#L849-1 assume !(1 == ~t11_pc~0); 498020#L859-1 is_transmit11_triggered_~__retres1~11#1 := 0; 498017#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 498015#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 498013#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 498011#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 498009#L868-1 assume 1 == ~t12_pc~0; 498006#L869-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 498003#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 498001#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 497999#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 497997#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 497995#L887-1 assume !(1 == ~t13_pc~0); 497991#L897-1 is_transmit13_triggered_~__retres1~13#1 := 0; 497989#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 497987#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 497985#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 497983#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 497981#L1439 assume !(1 == ~M_E~0); 483310#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 497977#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 497975#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 497973#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 497971#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 497969#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 497966#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 497964#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 497962#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 497960#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 497958#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 497956#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 497953#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 497951#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 497949#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 497947#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 497945#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 497943#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 497940#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 497938#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 497936#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 497934#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 497932#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 497930#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 497927#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 497925#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 497923#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 497921#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 497655#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 493854#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 493818#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 493806#L1959 assume !(0 == start_simulation_~tmp~3#1); 493797#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 484429#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 484419#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 484417#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 484415#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 484413#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 484411#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 484409#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 424589#L1940 [2024-11-17 08:53:10,018 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:10,018 INFO L85 PathProgramCache]: Analyzing trace with hash -345565742, now seen corresponding path program 1 times [2024-11-17 08:53:10,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:10,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853211622] [2024-11-17 08:53:10,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:10,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:10,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:10,054 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:10,054 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:10,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853211622] [2024-11-17 08:53:10,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [853211622] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:10,055 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:10,055 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:10,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53355297] [2024-11-17 08:53:10,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:10,055 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:10,055 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:10,055 INFO L85 PathProgramCache]: Analyzing trace with hash 27839043, now seen corresponding path program 1 times [2024-11-17 08:53:10,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:10,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430344102] [2024-11-17 08:53:10,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:10,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:10,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:10,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:10,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:10,095 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430344102] [2024-11-17 08:53:10,095 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430344102] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:10,095 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:10,095 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:10,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1584630384] [2024-11-17 08:53:10,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:10,096 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:10,096 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:10,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:10,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:10,096 INFO L87 Difference]: Start difference. First operand 100058 states and 142574 transitions. cyclomatic complexity: 42532 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:10,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:10,822 INFO L93 Difference]: Finished difference Result 192809 states and 273787 transitions. [2024-11-17 08:53:10,822 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 192809 states and 273787 transitions. [2024-11-17 08:53:11,706 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 192064 [2024-11-17 08:53:12,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 192809 states to 192809 states and 273787 transitions. [2024-11-17 08:53:12,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 192809 [2024-11-17 08:53:12,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 192809 [2024-11-17 08:53:12,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 192809 states and 273787 transitions. [2024-11-17 08:53:12,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:12,285 INFO L218 hiAutomatonCegarLoop]: Abstraction has 192809 states and 273787 transitions. [2024-11-17 08:53:12,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192809 states and 273787 transitions. [2024-11-17 08:53:13,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192809 to 192553. [2024-11-17 08:53:14,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 192553 states, 192553 states have (on average 1.4205491475074394) internal successors, (273531), 192552 states have internal predecessors, (273531), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:14,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192553 states to 192553 states and 273531 transitions. [2024-11-17 08:53:14,360 INFO L240 hiAutomatonCegarLoop]: Abstraction has 192553 states and 273531 transitions. [2024-11-17 08:53:14,360 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:14,361 INFO L425 stractBuchiCegarLoop]: Abstraction has 192553 states and 273531 transitions. [2024-11-17 08:53:14,361 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-17 08:53:14,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 192553 states and 273531 transitions. [2024-11-17 08:53:15,399 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 191808 [2024-11-17 08:53:15,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:15,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:15,401 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:15,401 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:15,401 INFO L745 eck$LassoCheckResult]: Stem: 717551#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 717552#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 718316#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 718734#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 718753#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 718476#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 717043#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 717044#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 717286#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 717287#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 717796#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 716954#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 716955#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 717928#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 717929#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 716925#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 716926#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 718708#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 718007#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 717149#L1291-1 assume !(0 == ~M_E~0); 717150#L1296-1 assume !(0 == ~T1_E~0); 717920#L1301-1 assume !(0 == ~T2_E~0); 717921#L1306-1 assume !(0 == ~T3_E~0); 718467#L1311-1 assume !(0 == ~T4_E~0); 717107#L1316-1 assume !(0 == ~T5_E~0); 717108#L1321-1 assume !(0 == ~T6_E~0); 717937#L1326-1 assume !(0 == ~T7_E~0); 716936#L1331-1 assume !(0 == ~T8_E~0); 716612#L1336-1 assume !(0 == ~T9_E~0); 716613#L1341-1 assume !(0 == ~T10_E~0); 716697#L1346-1 assume !(0 == ~T11_E~0); 716698#L1351-1 assume !(0 == ~T12_E~0); 717045#L1356-1 assume !(0 == ~T13_E~0); 717046#L1361-1 assume !(0 == ~E_M~0); 718763#L1366-1 assume !(0 == ~E_1~0); 717095#L1371-1 assume !(0 == ~E_2~0); 717096#L1376-1 assume !(0 == ~E_3~0); 717998#L1381-1 assume !(0 == ~E_4~0); 717999#L1386-1 assume !(0 == ~E_5~0); 718799#L1391-1 assume !(0 == ~E_6~0); 718821#L1396-1 assume !(0 == ~E_7~0); 717878#L1401-1 assume !(0 == ~E_8~0); 717879#L1406-1 assume !(0 == ~E_9~0); 718171#L1411-1 assume !(0 == ~E_10~0); 718172#L1416-1 assume !(0 == ~E_11~0); 717799#L1421-1 assume !(0 == ~E_12~0); 717253#L1426-1 assume !(0 == ~E_13~0); 717254#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 717277#L640-16 assume !(1 == ~m_pc~0); 718441#L650-16 is_master_triggered_~__retres1~0#1 := 0; 717778#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 717384#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 717385#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 718214#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 717594#L659-16 assume !(1 == ~t1_pc~0); 717595#L669-16 is_transmit1_triggered_~__retres1~1#1 := 0; 717871#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 718307#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 717075#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 717076#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 717193#L678-16 assume !(1 == ~t2_pc~0); 717128#L688-16 is_transmit2_triggered_~__retres1~2#1 := 0; 717129#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 717201#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 717202#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 718652#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 718308#L697-16 assume !(1 == ~t3_pc~0); 716735#L707-16 is_transmit3_triggered_~__retres1~3#1 := 0; 716736#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 717140#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 716663#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 716664#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 717649#L716-16 assume !(1 == ~t4_pc~0); 716801#L726-16 is_transmit4_triggered_~__retres1~4#1 := 0; 716802#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 718089#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 718090#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 718807#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 718737#L735-16 assume !(1 == ~t5_pc~0); 718738#L745-16 is_transmit5_triggered_~__retres1~5#1 := 0; 718769#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 718721#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 718207#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 718208#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 718478#L754-16 assume 1 == ~t6_pc~0; 718479#L755-16 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 717565#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 717827#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 717828#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 718350#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 718632#L773-16 assume 1 == ~t7_pc~0; 717198#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 717200#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 718874#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 716632#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 716633#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 718408#L792-16 assume 1 == ~t8_pc~0; 718409#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 717832#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 716959#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 716960#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 718817#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 718062#L811-16 assume 1 == ~t9_pc~0; 717194#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 717195#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 718791#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 717177#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 717178#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 716731#L830-16 assume 1 == ~t10_pc~0; 716708#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 716709#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 717237#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 717706#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 717598#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 717599#L849-16 assume 1 == ~t11_pc~0; 718013#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 718225#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 718801#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 717429#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 717430#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 718131#L868-16 assume 1 == ~t12_pc~0; 718132#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 716655#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 716997#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 716998#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 717291#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 717436#L887-16 assume 1 == ~t13_pc~0; 716956#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 716957#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 718063#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 716749#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 716750#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 718485#L1439-1 assume !(1 == ~M_E~0); 716943#L1444-1 assume !(1 == ~T1_E~0); 716944#L1449-1 assume !(1 == ~T2_E~0); 717402#L1454-1 assume !(1 == ~T3_E~0); 717403#L1459-1 assume !(1 == ~T4_E~0); 718053#L1464-1 assume !(1 == ~T5_E~0); 718054#L1469-1 assume !(1 == ~T6_E~0); 718111#L1474-1 assume !(1 == ~T7_E~0); 717800#L1479-1 assume !(1 == ~T8_E~0); 717801#L1484-1 assume !(1 == ~T9_E~0); 718060#L1489-1 assume !(1 == ~T10_E~0); 717657#L1494-1 assume !(1 == ~T11_E~0); 717658#L1499-1 assume !(1 == ~T12_E~0); 717867#L1504-1 assume !(1 == ~T13_E~0); 717868#L1509-1 assume !(1 == ~E_M~0); 718512#L1514-1 assume !(1 == ~E_1~0); 718143#L1519-1 assume !(1 == ~E_2~0); 718144#L1524-1 assume !(1 == ~E_3~0); 718783#L1529-1 assume !(1 == ~E_4~0); 718784#L1534-1 assume !(1 == ~E_5~0); 716766#L1539-1 assume !(1 == ~E_6~0); 716767#L1544-1 assume !(1 == ~E_7~0); 717162#L1549-1 assume !(1 == ~E_8~0); 718750#L1554-1 assume !(1 == ~E_9~0); 718748#L1559-1 assume !(1 == ~E_10~0); 718564#L1564-1 assume !(1 == ~E_11~0); 718565#L1569-1 assume !(1 == ~E_12~0); 718779#L1574-1 assume !(1 == ~E_13~0); 717471#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 717472#L1940 [2024-11-17 08:53:15,402 INFO L747 eck$LassoCheckResult]: Loop: 717472#L1940 assume true; 762672#L1940-1 assume !false; 762671#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 762667#L1074 assume true; 762666#L1074-1 assume !false; 762665#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 762652#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 762644#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 762642#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 762639#L1079 assume !(0 != eval_~tmp~0#1); 762640#L1082 assume true; 813632#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 813630#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 813628#L1291 assume !(0 == ~M_E~0); 813626#L1296 assume !(0 == ~T1_E~0); 813624#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 813622#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 813620#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 813618#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 813616#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 813614#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 813612#L1331 assume !(0 == ~T8_E~0); 813610#L1336 assume !(0 == ~T9_E~0); 813608#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 813606#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 813603#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 813601#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 813599#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 813597#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 813595#L1371 assume !(0 == ~E_2~0); 813593#L1376 assume !(0 == ~E_3~0); 813592#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 813590#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 813588#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 813586#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 813584#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 813582#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 813579#L1411 assume !(0 == ~E_10~0); 813577#L1416 assume !(0 == ~E_11~0); 813575#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 813573#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 813571#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 813569#L640-1 assume !(1 == ~m_pc~0); 813566#L650-1 is_master_triggered_~__retres1~0#1 := 0; 813564#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 813562#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 813560#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 813558#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 813556#L659-1 assume !(1 == ~t1_pc~0); 813553#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 813550#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 813547#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 813544#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 813541#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 813538#L678-1 assume !(1 == ~t2_pc~0); 813534#L688-1 is_transmit2_triggered_~__retres1~2#1 := 0; 813531#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 813527#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 813523#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 813519#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 813515#L697-1 assume !(1 == ~t3_pc~0); 813510#L707-1 is_transmit3_triggered_~__retres1~3#1 := 0; 813506#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 813502#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 813497#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 813492#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 813487#L716-1 assume !(1 == ~t4_pc~0); 790929#L726-1 is_transmit4_triggered_~__retres1~4#1 := 0; 813477#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 813472#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 813466#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 813461#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 813456#L735-1 assume !(1 == ~t5_pc~0); 813450#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 813445#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 813440#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 813433#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 813426#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 813419#L754-1 assume !(1 == ~t6_pc~0); 813410#L764-1 is_transmit6_triggered_~__retres1~6#1 := 0; 813403#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 813396#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 813390#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 813383#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 813376#L773-1 assume !(1 == ~t7_pc~0); 813368#L783-1 is_transmit7_triggered_~__retres1~7#1 := 0; 813360#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 813354#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 813347#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 813340#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 813333#L792-1 assume !(1 == ~t8_pc~0); 813327#L802-1 is_transmit8_triggered_~__retres1~8#1 := 0; 813322#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 813317#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 813312#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 813308#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 813302#L811-1 assume !(1 == ~t9_pc~0); 813296#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 813292#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 813288#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 813284#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 813279#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 813274#L830-1 assume !(1 == ~t10_pc~0); 813268#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 813262#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 813258#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 813254#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 813249#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 813243#L849-1 assume 1 == ~t11_pc~0; 813236#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 813230#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 813224#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 813218#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 813211#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 813206#L868-1 assume !(1 == ~t12_pc~0); 813199#L878-1 is_transmit12_triggered_~__retres1~12#1 := 0; 813192#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 813186#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 813178#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 813170#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 813161#L887-1 assume !(1 == ~t13_pc~0); 813153#L897-1 is_transmit13_triggered_~__retres1~13#1 := 0; 813145#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 813138#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 813130#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 813122#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 813114#L1439 assume !(1 == ~M_E~0); 804091#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 813100#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 813096#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 813091#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 813085#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 813078#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 813071#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 813063#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 813056#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 813048#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 813040#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 813033#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 813026#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 813018#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 813011#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 813003#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 812995#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 812988#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 812980#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 812972#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 812965#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 812957#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 812949#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 812942#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 812934#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 812926#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 812920#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 812916#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 812859#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 812851#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 812481#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 716886#L1959 assume !(0 == start_simulation_~tmp~3#1); 716888#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 762710#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 762699#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 762695#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 762691#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 762687#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 762683#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 762679#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 717472#L1940 [2024-11-17 08:53:15,402 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:15,403 INFO L85 PathProgramCache]: Analyzing trace with hash 897588053, now seen corresponding path program 1 times [2024-11-17 08:53:15,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:15,403 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711952943] [2024-11-17 08:53:15,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:15,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:15,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:15,440 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:15,440 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:15,440 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711952943] [2024-11-17 08:53:15,440 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [711952943] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:15,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:15,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:15,441 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498219275] [2024-11-17 08:53:15,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:15,441 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:15,441 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:15,441 INFO L85 PathProgramCache]: Analyzing trace with hash 1922016341, now seen corresponding path program 1 times [2024-11-17 08:53:15,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:15,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412277788] [2024-11-17 08:53:15,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:15,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:15,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:15,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:15,483 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:15,483 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412277788] [2024-11-17 08:53:15,484 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412277788] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:15,484 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:15,484 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:15,484 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489886490] [2024-11-17 08:53:15,484 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:15,484 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:15,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:15,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:15,485 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:15,485 INFO L87 Difference]: Start difference. First operand 192553 states and 273531 transitions. cyclomatic complexity: 81010 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:16,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:16,768 INFO L93 Difference]: Finished difference Result 370792 states and 524984 transitions. [2024-11-17 08:53:16,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 370792 states and 524984 transitions. [2024-11-17 08:53:18,712 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 369216 [2024-11-17 08:53:19,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 370792 states to 370792 states and 524984 transitions. [2024-11-17 08:53:19,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 370792 [2024-11-17 08:53:20,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 370792 [2024-11-17 08:53:20,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 370792 states and 524984 transitions. [2024-11-17 08:53:20,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:20,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 370792 states and 524984 transitions. [2024-11-17 08:53:20,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370792 states and 524984 transitions. [2024-11-17 08:53:22,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370792 to 370280. [2024-11-17 08:53:22,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 370280 states, 370280 states have (on average 1.4164200064815815) internal successors, (524472), 370279 states have internal predecessors, (524472), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:24,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 370280 states to 370280 states and 524472 transitions. [2024-11-17 08:53:24,438 INFO L240 hiAutomatonCegarLoop]: Abstraction has 370280 states and 524472 transitions. [2024-11-17 08:53:24,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:24,438 INFO L425 stractBuchiCegarLoop]: Abstraction has 370280 states and 524472 transitions. [2024-11-17 08:53:24,439 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-17 08:53:24,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 370280 states and 524472 transitions. [2024-11-17 08:53:25,974 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 368704 [2024-11-17 08:53:25,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:25,974 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:25,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:25,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:25,976 INFO L745 eck$LassoCheckResult]: Stem: 1280911#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1280912#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1281703#L1903 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1282168#L907-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1282193#L914 assume 1 == ~m_i~0;~m_st~0 := 0; 1281878#L919 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1280396#L924 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1280397#L929 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1280642#L934 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1280643#L939 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1281167#L944 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1280308#L949 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1280309#L954 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1281301#L959 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1281302#L964 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1280279#L969 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1280280#L974 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1282135#L979 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1281381#L985 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1280501#L1291-1 assume !(0 == ~M_E~0); 1280502#L1296-1 assume !(0 == ~T1_E~0); 1281292#L1301-1 assume !(0 == ~T2_E~0); 1281293#L1306-1 assume !(0 == ~T3_E~0); 1281866#L1311-1 assume !(0 == ~T4_E~0); 1280457#L1316-1 assume !(0 == ~T5_E~0); 1280458#L1321-1 assume !(0 == ~T6_E~0); 1281310#L1326-1 assume !(0 == ~T7_E~0); 1280290#L1331-1 assume !(0 == ~T8_E~0); 1279966#L1336-1 assume !(0 == ~T9_E~0); 1279967#L1341-1 assume !(0 == ~T10_E~0); 1280053#L1346-1 assume !(0 == ~T11_E~0); 1280054#L1351-1 assume !(0 == ~T12_E~0); 1280398#L1356-1 assume !(0 == ~T13_E~0); 1280399#L1361-1 assume !(0 == ~E_M~0); 1282204#L1366-1 assume !(0 == ~E_1~0); 1280446#L1371-1 assume !(0 == ~E_2~0); 1280447#L1376-1 assume !(0 == ~E_3~0); 1281371#L1381-1 assume !(0 == ~E_4~0); 1281372#L1386-1 assume !(0 == ~E_5~0); 1282252#L1391-1 assume !(0 == ~E_6~0); 1282276#L1396-1 assume !(0 == ~E_7~0); 1281251#L1401-1 assume !(0 == ~E_8~0); 1281252#L1406-1 assume !(0 == ~E_9~0); 1281549#L1411-1 assume !(0 == ~E_10~0); 1281550#L1416-1 assume !(0 == ~E_11~0); 1281170#L1421-1 assume !(0 == ~E_12~0); 1280609#L1426-1 assume !(0 == ~E_13~0); 1280610#L1432-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1280633#L640-16 assume !(1 == ~m_pc~0); 1281839#L650-16 is_master_triggered_~__retres1~0#1 := 0; 1281148#L643-16 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1280742#L652-16 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1280743#L1603-16 assume !(0 != activate_threads_~tmp~1#1); 1281595#L1609-16 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1280955#L659-16 assume !(1 == ~t1_pc~0); 1280956#L669-16 is_transmit1_triggered_~__retres1~1#1 := 0; 1281245#L662-16 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1281693#L671-16 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1280427#L1611-16 assume !(0 != activate_threads_~tmp___0~0#1); 1280428#L1617-16 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1280545#L678-16 assume !(1 == ~t2_pc~0); 1280478#L688-16 is_transmit2_triggered_~__retres1~2#1 := 0; 1280479#L681-16 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1280553#L690-16 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1280554#L1619-16 assume !(0 != activate_threads_~tmp___1~0#1); 1282059#L1625-16 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1281694#L697-16 assume !(1 == ~t3_pc~0); 1280091#L707-16 is_transmit3_triggered_~__retres1~3#1 := 0; 1280092#L700-16 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1280492#L709-16 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1280019#L1627-16 assume !(0 != activate_threads_~tmp___2~0#1); 1280020#L1633-16 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1281013#L716-16 assume !(1 == ~t4_pc~0); 1280156#L726-16 is_transmit4_triggered_~__retres1~4#1 := 0; 1280157#L719-16 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1281465#L728-16 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1281466#L1635-16 assume !(0 != activate_threads_~tmp___3~0#1); 1282260#L1641-16 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1282171#L735-16 assume !(1 == ~t5_pc~0); 1282172#L745-16 is_transmit5_triggered_~__retres1~5#1 := 0; 1282209#L738-16 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1282154#L747-16 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1281588#L1643-16 assume !(0 != activate_threads_~tmp___4~0#1); 1281589#L1649-16 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1281882#L754-16 assume !(1 == ~t6_pc~0); 1280924#L764-16 is_transmit6_triggered_~__retres1~6#1 := 0; 1280925#L757-16 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1281199#L766-16 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1281200#L1651-16 assume !(0 != activate_threads_~tmp___5~0#1); 1281739#L1657-16 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1282039#L773-16 assume 1 == ~t7_pc~0; 1280550#L774-16 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1280552#L776-16 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1282342#L785-16 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1279986#L1659-16 assume !(0 != activate_threads_~tmp___6~0#1); 1279987#L1665-16 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1281802#L792-16 assume 1 == ~t8_pc~0; 1281803#L793-16 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1281203#L795-16 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1280313#L804-16 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1280314#L1667-16 assume !(0 != activate_threads_~tmp___7~0#1); 1282270#L1673-16 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1281438#L811-16 assume 1 == ~t9_pc~0; 1280546#L812-16 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1280547#L814-16 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1282239#L823-16 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1280530#L1675-16 assume !(0 != activate_threads_~tmp___8~0#1); 1280531#L1681-16 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1280087#L830-16 assume 1 == ~t10_pc~0; 1280064#L831-16 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1280065#L833-16 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1280592#L842-16 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1281070#L1683-16 assume !(0 != activate_threads_~tmp___9~0#1); 1280960#L1689-16 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1280961#L849-16 assume 1 == ~t11_pc~0; 1281388#L850-16 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1281604#L852-16 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1282255#L861-16 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1280786#L1691-16 assume !(0 != activate_threads_~tmp___10~0#1); 1280787#L1697-16 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1281510#L868-16 assume 1 == ~t12_pc~0; 1281511#L869-16 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1280011#L871-16 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1280349#L880-16 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1280350#L1699-16 assume !(0 != activate_threads_~tmp___11~0#1); 1280646#L1705-16 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1280793#L887-16 assume 1 == ~t13_pc~0; 1280310#L888-16 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1280311#L890-16 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1281439#L899-16 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1280105#L1707-16 assume !(0 != activate_threads_~tmp___12~0#1); 1280106#L1713-16 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1281887#L1439-1 assume !(1 == ~M_E~0); 1280297#L1444-1 assume !(1 == ~T1_E~0); 1280298#L1449-1 assume !(1 == ~T2_E~0); 1280760#L1454-1 assume !(1 == ~T3_E~0); 1280761#L1459-1 assume !(1 == ~T4_E~0); 1281427#L1464-1 assume !(1 == ~T5_E~0); 1281428#L1469-1 assume !(1 == ~T6_E~0); 1281491#L1474-1 assume !(1 == ~T7_E~0); 1281171#L1479-1 assume !(1 == ~T8_E~0); 1281172#L1484-1 assume !(1 == ~T9_E~0); 1281435#L1489-1 assume !(1 == ~T10_E~0); 1281021#L1494-1 assume !(1 == ~T11_E~0); 1281022#L1499-1 assume !(1 == ~T12_E~0); 1281240#L1504-1 assume !(1 == ~T13_E~0); 1281241#L1509-1 assume !(1 == ~E_M~0); 1281912#L1514-1 assume !(1 == ~E_1~0); 1281522#L1519-1 assume !(1 == ~E_2~0); 1281523#L1524-1 assume !(1 == ~E_3~0); 1282229#L1529-1 assume !(1 == ~E_4~0); 1282230#L1534-1 assume !(1 == ~E_5~0); 1280122#L1539-1 assume !(1 == ~E_6~0); 1280123#L1544-1 assume !(1 == ~E_7~0); 1280516#L1549-1 assume !(1 == ~E_8~0); 1282188#L1554-1 assume !(1 == ~E_9~0); 1282186#L1559-1 assume !(1 == ~E_10~0); 1281966#L1564-1 assume !(1 == ~E_11~0); 1281967#L1569-1 assume !(1 == ~E_12~0); 1282222#L1574-1 assume !(1 == ~E_13~0); 1280826#L1580-1 assume true;assume { :end_inline_reset_delta_events } true; 1280827#L1940 [2024-11-17 08:53:25,976 INFO L747 eck$LassoCheckResult]: Loop: 1280827#L1940 assume true; 1316869#L1940-1 assume !false; 1316867#start_simulation_while_15_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1316862#L1074 assume true; 1316860#L1074-1 assume !false; 1316858#eval_while_14_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1316839#L992-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1316831#L1046-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1316829#L1065-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1316826#L1079 assume !(0 != eval_~tmp~0#1); 1316827#L1082 assume true; 1368311#L1284 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1368308#L907 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1368305#L1291 assume !(0 == ~M_E~0); 1368301#L1296 assume !(0 == ~T1_E~0); 1368297#L1301 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1368292#L1306 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1368288#L1311 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1368283#L1316 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1368279#L1321 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1368274#L1326 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1368270#L1331 assume !(0 == ~T8_E~0); 1368266#L1336 assume !(0 == ~T9_E~0); 1368263#L1341 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1368260#L1346 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1368256#L1351 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1368247#L1356 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1368239#L1361 assume 0 == ~E_M~0;~E_M~0 := 1; 1368234#L1366 assume 0 == ~E_1~0;~E_1~0 := 1; 1368229#L1371 assume !(0 == ~E_2~0); 1368224#L1376 assume !(0 == ~E_3~0); 1368219#L1381 assume 0 == ~E_4~0;~E_4~0 := 1; 1368214#L1386 assume 0 == ~E_5~0;~E_5~0 := 1; 1368210#L1391 assume 0 == ~E_6~0;~E_6~0 := 1; 1368205#L1396 assume 0 == ~E_7~0;~E_7~0 := 1; 1368201#L1401 assume 0 == ~E_8~0;~E_8~0 := 1; 1368197#L1406 assume 0 == ~E_9~0;~E_9~0 := 1; 1368194#L1411 assume !(0 == ~E_10~0); 1368190#L1416 assume !(0 == ~E_11~0); 1368188#L1421 assume 0 == ~E_12~0;~E_12~0 := 1; 1368186#L1426 assume 0 == ~E_13~0;~E_13~0 := 1; 1368182#L1432 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1368177#L640-1 assume !(1 == ~m_pc~0); 1368173#L650-1 is_master_triggered_~__retres1~0#1 := 0; 1368168#L643-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1368164#L652-1 assume true;activate_threads_#t~ret21#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1368160#L1603-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1368156#L1609-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1368151#L659-1 assume !(1 == ~t1_pc~0); 1368147#L669-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1368143#L662-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1368139#L671-1 assume true;activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1368135#L1611-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1368131#L1617-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1368127#L678-1 assume !(1 == ~t2_pc~0); 1368124#L688-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1368121#L681-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1368117#L690-1 assume true;activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1368112#L1619-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1368108#L1625-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1368103#L697-1 assume !(1 == ~t3_pc~0); 1368099#L707-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1368095#L700-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1368091#L709-1 assume true;activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1368086#L1627-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1368084#L1633-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1317098#L716-1 assume !(1 == ~t4_pc~0); 1317097#L726-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1317096#L719-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1317095#L728-1 assume true;activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1317094#L1635-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1317093#L1641-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1317092#L735-1 assume !(1 == ~t5_pc~0); 1317091#L745-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1317090#L738-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1317089#L747-1 assume true;activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1317088#L1643-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1317087#L1649-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1317086#L754-1 assume !(1 == ~t6_pc~0); 1317085#L764-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1317084#L757-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1317083#L766-1 assume true;activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1317082#L1651-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1317081#L1657-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1317079#L773-1 assume 1 == ~t7_pc~0; 1317076#L774-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1317074#L776-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1317072#L785-1 assume true;activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1317070#L1659-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1317068#L1665-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1317066#L792-1 assume !(1 == ~t8_pc~0); 1317063#L802-1 is_transmit8_triggered_~__retres1~8#1 := 0; 1317061#L795-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1317059#L804-1 assume true;activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1317057#L1667-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1317055#L1673-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1317053#L811-1 assume !(1 == ~t9_pc~0); 1317050#L821-1 is_transmit9_triggered_~__retres1~9#1 := 0; 1317048#L814-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1317046#L823-1 assume true;activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1317044#L1675-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1317042#L1681-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1317040#L830-1 assume !(1 == ~t10_pc~0); 1317037#L840-1 is_transmit10_triggered_~__retres1~10#1 := 0; 1317035#L833-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1317033#L842-1 assume true;activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1317031#L1683-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1317029#L1689-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1317027#L849-1 assume 1 == ~t11_pc~0; 1317024#L850-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1317023#L852-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1317022#L861-1 assume true;activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1317021#L1691-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1317020#L1697-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1317019#L868-1 assume !(1 == ~t12_pc~0); 1317017#L878-1 is_transmit12_triggered_~__retres1~12#1 := 0; 1317016#L871-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1317015#L880-1 assume true;activate_threads_#t~ret33#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1317014#L1699-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1317012#L1705-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1317010#L887-1 assume 1 == ~t13_pc~0; 1317008#L888-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1317005#L890-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1317003#L899-1 assume true;activate_threads_#t~ret34#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1317001#L1707-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1316999#L1713-1 assume true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1316997#L1439 assume !(1 == ~M_E~0); 1309915#L1444 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1316993#L1449 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1316991#L1454 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1316989#L1459 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1316987#L1464 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1316985#L1469 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1316983#L1474 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1316981#L1479 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1316979#L1484 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1316977#L1489 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1316975#L1494 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1316973#L1499 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1316971#L1504 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1316969#L1509 assume 1 == ~E_M~0;~E_M~0 := 2; 1316967#L1514 assume 1 == ~E_1~0;~E_1~0 := 2; 1316965#L1519 assume 1 == ~E_2~0;~E_2~0 := 2; 1316963#L1524 assume 1 == ~E_3~0;~E_3~0 := 2; 1316961#L1529 assume 1 == ~E_4~0;~E_4~0 := 2; 1316959#L1534 assume 1 == ~E_5~0;~E_5~0 := 2; 1316958#L1539 assume 1 == ~E_6~0;~E_6~0 := 2; 1316956#L1544 assume 1 == ~E_7~0;~E_7~0 := 2; 1316954#L1549 assume 1 == ~E_8~0;~E_8~0 := 2; 1316952#L1554 assume 1 == ~E_9~0;~E_9~0 := 2; 1316950#L1559 assume 1 == ~E_10~0;~E_10~0 := 2; 1316948#L1564 assume 1 == ~E_11~0;~E_11~0 := 2; 1316946#L1569 assume 1 == ~E_12~0;~E_12~0 := 2; 1316944#L1574 assume 1 == ~E_13~0;~E_13~0 := 2; 1316942#L1580 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1316920#L992-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1316914#L1046-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1316912#L1065-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1316910#L1959 assume !(0 == start_simulation_~tmp~3#1); 1316907#L1970 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1316894#L992 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1316883#L1046 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1316881#L1065 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1316879#L1914 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1316877#L1916 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1316875#L1922 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1316873#L1972 assume !(0 != start_simulation_~tmp___0~1#1); 1280827#L1940 [2024-11-17 08:53:25,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:25,977 INFO L85 PathProgramCache]: Analyzing trace with hash -1306509544, now seen corresponding path program 1 times [2024-11-17 08:53:25,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:25,977 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1064061938] [2024-11-17 08:53:25,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:25,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:25,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:26,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:26,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:26,010 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1064061938] [2024-11-17 08:53:26,011 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1064061938] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:26,011 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:26,011 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:26,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [639164245] [2024-11-17 08:53:26,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:26,011 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:26,011 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:26,012 INFO L85 PathProgramCache]: Analyzing trace with hash 636195791, now seen corresponding path program 1 times [2024-11-17 08:53:26,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:26,012 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267183174] [2024-11-17 08:53:26,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:26,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:26,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:26,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:26,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:26,050 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1267183174] [2024-11-17 08:53:26,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1267183174] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:26,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:26,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:26,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395483470] [2024-11-17 08:53:26,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:26,050 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:26,050 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:26,051 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:26,051 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:26,051 INFO L87 Difference]: Start difference. First operand 370280 states and 524472 transitions. cyclomatic complexity: 154256 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:28,174 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:28,174 INFO L93 Difference]: Finished difference Result 712359 states and 1005813 transitions. [2024-11-17 08:53:28,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 712359 states and 1005813 transitions. [2024-11-17 08:53:31,613 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 708864 [2024-11-17 08:53:33,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 712359 states to 712359 states and 1005813 transitions. [2024-11-17 08:53:33,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 712359 [2024-11-17 08:53:33,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 712359 [2024-11-17 08:53:33,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 712359 states and 1005813 transitions. [2024-11-17 08:53:34,129 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:34,130 INFO L218 hiAutomatonCegarLoop]: Abstraction has 712359 states and 1005813 transitions. [2024-11-17 08:53:34,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 712359 states and 1005813 transitions.