./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.14.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.14.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:52:59,094 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:52:59,137 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:52:59,140 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:52:59,140 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:52:59,141 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:52:59,157 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:52:59,157 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:52:59,158 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:52:59,158 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:52:59,158 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:52:59,159 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:52:59,159 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:52:59,159 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:52:59,160 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:52:59,160 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:52:59,160 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:52:59,161 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:52:59,161 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:52:59,161 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:52:59,161 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:52:59,162 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:52:59,162 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:52:59,163 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:52:59,163 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:52:59,163 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:52:59,163 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:52:59,164 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:52:59,164 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:52:59,164 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:52:59,164 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:52:59,165 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:52:59,165 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:52:59,165 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:52:59,165 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:52:59,166 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:52:59,166 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:52:59,166 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:52:59,166 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:52:59,167 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:52:59,167 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 78a96934dff25285973ef889167a345947d7e73ab8a2ec405d96bd61e690530f [2024-11-17 08:52:59,335 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:52:59,351 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:52:59,353 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:52:59,354 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:52:59,354 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:52:59,355 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.14.cil.c [2024-11-17 08:53:00,634 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:53:00,855 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:53:00,856 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.14.cil.c [2024-11-17 08:53:00,874 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/86b664184/4e76c88690d34201ab054e243122dea8/FLAG8f465a2b8 [2024-11-17 08:53:01,222 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/86b664184/4e76c88690d34201ab054e243122dea8 [2024-11-17 08:53:01,225 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:53:01,227 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:53:01,227 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:01,227 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:53:01,237 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:53:01,243 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:01,244 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@60cbaa13 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01, skipping insertion in model container [2024-11-17 08:53:01,247 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:01,324 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:53:01,787 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:01,798 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:53:01,868 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:01,896 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:53:01,897 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01 WrapperNode [2024-11-17 08:53:01,897 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:01,898 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:01,898 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:53:01,898 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:53:01,904 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:01,919 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:01,994 INFO L138 Inliner]: procedures = 52, calls = 69, calls flagged for inlining = 64, calls inlined = 272, statements flattened = 4158 [2024-11-17 08:53:01,995 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:01,995 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:53:01,995 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:53:01,995 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:53:02,010 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:02,010 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:02,018 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:02,048 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:53:02,048 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:02,048 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:02,076 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:02,080 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:02,083 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:02,088 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:02,096 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:53:02,097 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:53:02,097 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:53:02,097 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:53:02,098 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (1/1) ... [2024-11-17 08:53:02,102 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:53:02,123 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:53:02,137 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:53:02,141 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:53:02,174 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:53:02,174 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:53:02,174 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:53:02,174 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:53:02,259 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:53:02,260 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:53:04,685 INFO L? ?]: Removed 886 outVars from TransFormulas that were not future-live. [2024-11-17 08:53:04,685 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:53:04,731 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:53:04,732 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:53:04,732 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:04 BoogieIcfgContainer [2024-11-17 08:53:04,732 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:53:04,733 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:53:04,733 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:53:04,736 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:53:04,737 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:04,737 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:53:01" (1/3) ... [2024-11-17 08:53:04,738 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1f769927 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:04, skipping insertion in model container [2024-11-17 08:53:04,738 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:04,738 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:01" (2/3) ... [2024-11-17 08:53:04,738 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1f769927 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:04, skipping insertion in model container [2024-11-17 08:53:04,738 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:04,738 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:04" (3/3) ... [2024-11-17 08:53:04,739 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.14.cil.c [2024-11-17 08:53:04,819 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:53:04,819 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:53:04,819 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:53:04,819 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:53:04,820 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:53:04,820 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:53:04,820 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:53:04,821 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:53:04,830 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1868 states, 1867 states have (on average 1.4799143010176754) internal successors, (2763), 1867 states have internal predecessors, (2763), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:04,905 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1700 [2024-11-17 08:53:04,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:04,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:04,922 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:04,923 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:04,924 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:53:04,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1868 states, 1867 states have (on average 1.4799143010176754) internal successors, (2763), 1867 states have internal predecessors, (2763), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:04,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1700 [2024-11-17 08:53:04,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:04,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:04,944 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:04,944 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:04,954 INFO L745 eck$LassoCheckResult]: Stem: 483#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 978#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 157#L1773true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1490#L841-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1440#L848true assume !(1 == ~m_i~0);~m_st~0 := 2; 1218#L853true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1564#L858true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1317#L863true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1647#L868true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1660#L873true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 167#L878true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 875#L883true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 970#L888true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1699#L893true assume !(1 == ~t9_i~0);~t9_st~0 := 2; 568#L898true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 219#L903true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 425#L908true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1696#L914true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1591#L1201-1true assume !(0 == ~M_E~0); 1689#L1206-1true assume !(0 == ~T1_E~0); 1212#L1211-1true assume !(0 == ~T2_E~0); 1378#L1216-1true assume !(0 == ~T3_E~0); 315#L1221-1true assume !(0 == ~T4_E~0); 1308#L1226-1true assume !(0 == ~T5_E~0); 113#L1231-1true assume !(0 == ~T6_E~0); 1466#L1236-1true assume !(0 == ~T7_E~0); 1282#L1241-1true assume !(0 == ~T8_E~0); 343#L1246-1true assume !(0 == ~T9_E~0); 450#L1251-1true assume !(0 == ~T10_E~0); 937#L1256-1true assume !(0 == ~T11_E~0); 6#L1261-1true assume !(0 == ~T12_E~0); 1663#L1266-1true assume !(0 == ~E_M~0); 1603#L1271-1true assume !(0 == ~E_1~0); 897#L1276-1true assume !(0 == ~E_2~0); 1596#L1281-1true assume !(0 == ~E_3~0); 845#L1286-1true assume !(0 == ~E_4~0); 255#L1291-1true assume !(0 == ~E_5~0); 1687#L1296-1true assume !(0 == ~E_6~0); 679#L1301-1true assume !(0 == ~E_7~0); 1150#L1306-1true assume !(0 == ~E_8~0); 1115#L1311-1true assume !(0 == ~E_9~0); 230#L1316-1true assume !(0 == ~E_10~0); 1535#L1321-1true assume !(0 == ~E_11~0); 693#L1326-1true assume !(0 == ~E_12~0); 773#L1332-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1029#L593-15true assume 1 == ~m_pc~0; 724#L594-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 249#L596-15true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 891#L605-15true assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 638#L1492-15true assume !(0 != activate_threads_~tmp~1#1); 662#L1498-15true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1185#L612-15true assume 1 == ~t1_pc~0; 857#L613-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 757#L615-15true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1718#L624-15true assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1623#L1500-15true assume !(0 != activate_threads_~tmp___0~0#1); 63#L1506-15true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 717#L631-15true assume 1 == ~t2_pc~0; 1727#L632-15true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 799#L634-15true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1716#L643-15true assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 144#L1508-15true assume !(0 != activate_threads_~tmp___1~0#1); 1724#L1514-15true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1113#L650-15true assume 1 == ~t3_pc~0; 244#L651-15true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1164#L653-15true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1273#L662-15true assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 250#L1516-15true assume !(0 != activate_threads_~tmp___2~0#1); 1367#L1522-15true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 753#L669-15true assume 1 == ~t4_pc~0; 1635#L670-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 467#L672-15true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1055#L681-15true assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1507#L1524-15true assume !(0 != activate_threads_~tmp___3~0#1); 676#L1530-15true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1781#L688-15true assume 1 == ~t5_pc~0; 569#L689-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1523#L691-15true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 547#L700-15true assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 459#L1532-15true assume !(0 != activate_threads_~tmp___4~0#1); 1201#L1538-15true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 911#L707-15true assume 1 == ~t6_pc~0; 1695#L708-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 489#L710-15true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1783#L719-15true assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 739#L1540-15true assume !(0 != activate_threads_~tmp___5~0#1); 882#L1546-15true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1477#L726-15true assume 1 == ~t7_pc~0; 1842#L727-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 813#L729-15true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1031#L738-15true assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 954#L1548-15true assume !(0 != activate_threads_~tmp___6~0#1); 1174#L1554-15true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1843#L745-15true assume 1 == ~t8_pc~0; 1538#L746-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 168#L748-15true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 725#L757-15true assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 147#L1556-15true assume !(0 != activate_threads_~tmp___7~0#1); 1633#L1562-15true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 248#L764-15true assume 1 == ~t9_pc~0; 1829#L765-15true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1866#L767-15true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1401#L776-15true assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1421#L1564-15true assume !(0 != activate_threads_~tmp___8~0#1); 1803#L1570-15true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57#L783-15true assume 1 == ~t10_pc~0; 904#L784-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1810#L786-15true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 333#L795-15true assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1736#L1572-15true assume !(0 != activate_threads_~tmp___9~0#1); 670#L1578-15true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 89#L802-15true assume 1 == ~t11_pc~0; 1108#L803-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1130#L805-15true assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1425#L814-15true assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1768#L1580-15true assume !(0 != activate_threads_~tmp___10~0#1); 1423#L1586-15true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 917#L821-15true assume 1 == ~t12_pc~0; 1042#L822-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1558#L824-15true assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 583#L833-15true assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 71#L1588-15true assume !(0 != activate_threads_~tmp___11~0#1); 535#L1594-15true assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1657#L1339-1true assume !(1 == ~M_E~0); 1391#L1344-1true assume !(1 == ~T1_E~0); 1798#L1349-1true assume !(1 == ~T2_E~0); 684#L1354-1true assume !(1 == ~T3_E~0); 1053#L1359-1true assume !(1 == ~T4_E~0); 1632#L1364-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 280#L1369-1true assume !(1 == ~T6_E~0); 1026#L1374-1true assume !(1 == ~T7_E~0); 691#L1379-1true assume !(1 == ~T8_E~0); 747#L1384-1true assume !(1 == ~T9_E~0); 1839#L1389-1true assume !(1 == ~T10_E~0); 1291#L1394-1true assume !(1 == ~T11_E~0); 1719#L1399-1true assume !(1 == ~T12_E~0); 1512#L1404-1true assume 1 == ~E_M~0;~E_M~0 := 2; 346#L1409-1true assume !(1 == ~E_1~0); 1484#L1414-1true assume !(1 == ~E_2~0); 922#L1419-1true assume !(1 == ~E_3~0); 136#L1424-1true assume !(1 == ~E_4~0); 699#L1429-1true assume !(1 == ~E_5~0); 1327#L1434-1true assume !(1 == ~E_6~0); 1697#L1439-1true assume !(1 == ~E_7~0); 154#L1444-1true assume 1 == ~E_8~0;~E_8~0 := 2; 883#L1449-1true assume !(1 == ~E_9~0); 384#L1454-1true assume !(1 == ~E_10~0); 1374#L1459-1true assume !(1 == ~E_11~0); 774#L1464-1true assume !(1 == ~E_12~0); 630#L1470-1true assume true;assume { :end_inline_reset_delta_events } true; 1410#L1810true [2024-11-17 08:53:04,960 INFO L747 eck$LassoCheckResult]: Loop: 1410#L1810true assume true; 99#L1810-1true assume !false; 607#start_simulation_while_14_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 189#L998true assume !true; 1515#L1006true assume true; 1259#L1194true assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 199#L841true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 454#L1201true assume 0 == ~M_E~0;~M_E~0 := 1; 876#L1206true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1019#L1211true assume 0 == ~T2_E~0;~T2_E~0 := 1; 924#L1216true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1548#L1221true assume !(0 == ~T4_E~0); 62#L1226true assume 0 == ~T5_E~0;~T5_E~0 := 1; 660#L1231true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1791#L1236true assume 0 == ~T7_E~0;~T7_E~0 := 1; 36#L1241true assume 0 == ~T8_E~0;~T8_E~0 := 1; 754#L1246true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1112#L1251true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1215#L1256true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1574#L1261true assume !(0 == ~T12_E~0); 976#L1266true assume 0 == ~E_M~0;~E_M~0 := 1; 1353#L1271true assume 0 == ~E_1~0;~E_1~0 := 1; 803#L1276true assume 0 == ~E_2~0;~E_2~0 := 1; 484#L1281true assume 0 == ~E_3~0;~E_3~0 := 1; 1744#L1286true assume 0 == ~E_4~0;~E_4~0 := 1; 1733#L1291true assume 0 == ~E_5~0;~E_5~0 := 1; 1617#L1296true assume 0 == ~E_6~0;~E_6~0 := 1; 687#L1301true assume !(0 == ~E_7~0); 211#L1306true assume 0 == ~E_8~0;~E_8~0 := 1; 814#L1311true assume 0 == ~E_9~0;~E_9~0 := 1; 838#L1316true assume 0 == ~E_10~0;~E_10~0 := 1; 1305#L1321true assume 0 == ~E_11~0;~E_11~0 := 1; 1165#L1326true assume 0 == ~E_12~0;~E_12~0 := 1; 1172#L1332true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1034#L593-1true assume !(1 == ~m_pc~0); 1375#L603-1true is_master_triggered_~__retres1~0#1 := 0; 677#L596-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1336#L605-1true assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 254#L1492-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 734#L1498-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 470#L612-1true assume !(1 == ~t1_pc~0); 1211#L622-1true is_transmit1_triggered_~__retres1~1#1 := 0; 1598#L615-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1575#L624-1true assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1532#L1500-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 507#L1506-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 770#L631-1true assume !(1 == ~t2_pc~0); 1473#L641-1true is_transmit2_triggered_~__retres1~2#1 := 0; 47#L634-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1708#L643-1true assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1333#L1508-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1171#L1514-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1076#L650-1true assume 1 == ~t3_pc~0; 1345#L651-1true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1337#L653-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 435#L662-1true assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 478#L1516-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1281#L1522-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35#L669-1true assume 1 == ~t4_pc~0; 793#L670-1true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1234#L672-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 347#L681-1true assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1780#L1524-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 963#L1530-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 853#L688-1true assume !(1 == ~t5_pc~0); 85#L698-1true is_transmit5_triggered_~__retres1~5#1 := 0; 1292#L691-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 301#L700-1true assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1610#L1532-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 108#L1538-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 779#L707-1true assume 1 == ~t6_pc~0; 516#L708-1true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 421#L710-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 281#L719-1true assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1669#L1540-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1579#L1546-1true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1576#L726-1true assume !(1 == ~t7_pc~0); 656#L736-1true is_transmit7_triggered_~__retres1~7#1 := 0; 532#L729-1true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 983#L738-1true assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 633#L1548-1true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1504#L1554-1true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43#L745-1true assume !(1 == ~t8_pc~0); 305#L755-1true is_transmit8_triggered_~__retres1~8#1 := 0; 1313#L748-1true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1514#L757-1true assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 260#L1556-1true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 360#L1562-1true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 468#L764-1true assume 1 == ~t9_pc~0; 1822#L765-1true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1796#L767-1true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1071#L776-1true assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1228#L1564-1true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1756#L1570-1true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1508#L783-1true assume !(1 == ~t10_pc~0); 265#L793-1true is_transmit10_triggered_~__retres1~10#1 := 0; 936#L786-1true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1637#L795-1true assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1439#L1572-1true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1129#L1578-1true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1676#L802-1true assume 1 == ~t11_pc~0; 1004#L803-1true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 680#L805-1true assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1571#L814-1true assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 434#L1580-1true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1314#L1586-1true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 723#L821-1true assume !(1 == ~t12_pc~0); 1328#L831-1true is_transmit12_triggered_~__retres1~12#1 := 0; 235#L824-1true assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 894#L833-1true assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 890#L1588-1true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1747#L1594-1true assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 867#L1339true assume 1 == ~M_E~0;~M_E~0 := 2; 474#L1344true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1261#L1349true assume 1 == ~T2_E~0;~T2_E~0 := 2; 76#L1354true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1133#L1359true assume 1 == ~T4_E~0;~T4_E~0 := 2; 361#L1364true assume 1 == ~T5_E~0;~T5_E~0 := 2; 766#L1369true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1606#L1374true assume 1 == ~T7_E~0;~T7_E~0 := 2; 106#L1379true assume 1 == ~T8_E~0;~T8_E~0 := 2; 828#L1384true assume 1 == ~T9_E~0;~T9_E~0 := 2; 59#L1389true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1189#L1394true assume 1 == ~T11_E~0;~T11_E~0 := 2; 324#L1399true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1195#L1404true assume 1 == ~E_M~0;~E_M~0 := 2; 61#L1409true assume 1 == ~E_1~0;~E_1~0 := 2; 1123#L1414true assume 1 == ~E_2~0;~E_2~0 := 2; 701#L1419true assume 1 == ~E_3~0;~E_3~0 := 2; 1051#L1424true assume 1 == ~E_4~0;~E_4~0 := 2; 1300#L1429true assume 1 == ~E_5~0;~E_5~0 := 2; 1460#L1434true assume 1 == ~E_6~0;~E_6~0 := 2; 1553#L1439true assume 1 == ~E_7~0;~E_7~0 := 2; 369#L1444true assume 1 == ~E_8~0;~E_8~0 := 2; 1536#L1449true assume 1 == ~E_9~0;~E_9~0 := 2; 196#L1454true assume 1 == ~E_10~0;~E_10~0 := 2; 964#L1459true assume 1 == ~E_11~0;~E_11~0 := 2; 1848#L1464true assume 1 == ~E_12~0;~E_12~0 := 2; 1099#L1470true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 573#L921-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1451#L971-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 246#L989-1true assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1534#L1829true assume !(0 == start_simulation_~tmp~3#1); 465#L1840true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 585#L921true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 671#L971true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 391#L989true assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 848#L1784true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 804#L1786true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 558#L1792true assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 237#L1842true assume !(0 != start_simulation_~tmp___0~1#1); 1410#L1810true [2024-11-17 08:53:04,968 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:04,972 INFO L85 PathProgramCache]: Analyzing trace with hash 275593838, now seen corresponding path program 1 times [2024-11-17 08:53:04,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:04,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1555869039] [2024-11-17 08:53:04,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:04,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:05,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:05,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:05,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:05,295 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1555869039] [2024-11-17 08:53:05,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1555869039] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:05,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:05,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:05,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1208819966] [2024-11-17 08:53:05,298 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:05,302 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:05,303 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:05,304 INFO L85 PathProgramCache]: Analyzing trace with hash -140509057, now seen corresponding path program 1 times [2024-11-17 08:53:05,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:05,304 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051246191] [2024-11-17 08:53:05,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:05,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:05,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:05,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:05,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:05,401 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051246191] [2024-11-17 08:53:05,401 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051246191] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:05,402 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:05,402 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:05,402 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651127134] [2024-11-17 08:53:05,402 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:05,403 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:05,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:05,430 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:05,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:05,435 INFO L87 Difference]: Start difference. First operand has 1868 states, 1867 states have (on average 1.4799143010176754) internal successors, (2763), 1867 states have internal predecessors, (2763), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:05,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:05,526 INFO L93 Difference]: Finished difference Result 1851 states and 2713 transitions. [2024-11-17 08:53:05,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1851 states and 2713 transitions. [2024-11-17 08:53:05,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:05,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1851 states to 1844 states and 2706 transitions. [2024-11-17 08:53:05,586 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:05,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:05,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2706 transitions. [2024-11-17 08:53:05,594 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:05,594 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2706 transitions. [2024-11-17 08:53:05,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2706 transitions. [2024-11-17 08:53:05,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:05,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.467462039045553) internal successors, (2706), 1843 states have internal predecessors, (2706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:05,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2706 transitions. [2024-11-17 08:53:05,680 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2706 transitions. [2024-11-17 08:53:05,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:05,688 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2706 transitions. [2024-11-17 08:53:05,688 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:53:05,688 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2706 transitions. [2024-11-17 08:53:05,696 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:05,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:05,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:05,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:05,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:05,705 INFO L745 eck$LassoCheckResult]: Stem: 4613#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 4614#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 4052#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4053#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5491#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 5367#L853 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 5368#L858 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5427#L863 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5428#L868 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5549#L873 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4069#L878 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4070#L883 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5098#L888 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5183#L893 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 4741#L898 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4168#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4169#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4525#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5534#L1201-1 assume !(0 == ~M_E~0); 5535#L1206-1 assume !(0 == ~T1_E~0); 5361#L1211-1 assume !(0 == ~T2_E~0); 5362#L1216-1 assume !(0 == ~T3_E~0); 4338#L1221-1 assume !(0 == ~T4_E~0); 4339#L1226-1 assume !(0 == ~T5_E~0); 3961#L1231-1 assume !(0 == ~T6_E~0); 3962#L1236-1 assume !(0 == ~T7_E~0); 5410#L1241-1 assume !(0 == ~T8_E~0); 4386#L1246-1 assume !(0 == ~T9_E~0); 4387#L1251-1 assume !(0 == ~T10_E~0); 4561#L1256-1 assume !(0 == ~T11_E~0); 3734#L1261-1 assume !(0 == ~T12_E~0); 3735#L1266-1 assume !(0 == ~E_M~0); 5539#L1271-1 assume !(0 == ~E_1~0); 5110#L1276-1 assume !(0 == ~E_2~0); 5111#L1281-1 assume !(0 == ~E_3~0); 5073#L1286-1 assume !(0 == ~E_4~0); 4231#L1291-1 assume !(0 == ~E_5~0); 4232#L1296-1 assume !(0 == ~E_6~0); 4891#L1301-1 assume !(0 == ~E_7~0); 4892#L1306-1 assume !(0 == ~E_8~0); 5301#L1311-1 assume !(0 == ~E_9~0); 4183#L1316-1 assume !(0 == ~E_10~0); 4184#L1321-1 assume !(0 == ~E_11~0); 4906#L1326-1 assume !(0 == ~E_12~0); 4907#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5005#L593-15 assume 1 == ~m_pc~0; 4953#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4220#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4221#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4835#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 4836#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4870#L612-15 assume 1 == ~t1_pc~0; 5083#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4258#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4987#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5543#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 3859#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3860#L631-15 assume 1 == ~t2_pc~0; 4942#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5030#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5031#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4026#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 4027#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5300#L650-15 assume 1 == ~t3_pc~0; 4208#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4209#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5331#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4222#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 4223#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4981#L669-15 assume 1 == ~t4_pc~0; 4982#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4582#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4583#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5248#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 4886#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4887#L688-15 assume 1 == ~t5_pc~0; 4742#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4743#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4708#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4571#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 4572#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5118#L707-15 assume 1 == ~t6_pc~0; 5119#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4625#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4626#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4966#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 4967#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5102#L726-15 assume 1 == ~t7_pc~0; 5503#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5004#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5044#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5165#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 5166#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5340#L745-15 assume 1 == ~t8_pc~0; 5522#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4071#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4072#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4033#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 4034#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4217#L764-15 assume 1 == ~t9_pc~0; 4218#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5291#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5470#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5471#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 5479#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3847#L783-15 assume 1 == ~t10_pc~0; 3848#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5114#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4369#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4370#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 4879#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3912#L802-15 assume 1 == ~t11_pc~0; 3913#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4170#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5316#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5482#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 5481#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5124#L821-15 assume 1 == ~t12_pc~0; 5125#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 5237#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4760#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3873#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 3874#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4689#L1339-1 assume !(1 == ~M_E~0); 5464#L1344-1 assume !(1 == ~T1_E~0); 5465#L1349-1 assume !(1 == ~T2_E~0); 4899#L1354-1 assume !(1 == ~T3_E~0); 4900#L1359-1 assume !(1 == ~T4_E~0); 5246#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4277#L1369-1 assume !(1 == ~T6_E~0); 4278#L1374-1 assume !(1 == ~T7_E~0); 4904#L1379-1 assume !(1 == ~T8_E~0); 4905#L1384-1 assume !(1 == ~T9_E~0); 4974#L1389-1 assume !(1 == ~T10_E~0); 5414#L1394-1 assume !(1 == ~T11_E~0); 5415#L1399-1 assume !(1 == ~T12_E~0); 5511#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 4390#L1409-1 assume !(1 == ~E_1~0); 4391#L1414-1 assume !(1 == ~E_2~0); 5132#L1419-1 assume !(1 == ~E_3~0); 4011#L1424-1 assume !(1 == ~E_4~0); 4012#L1429-1 assume !(1 == ~E_5~0); 4912#L1434-1 assume !(1 == ~E_6~0); 5434#L1439-1 assume !(1 == ~E_7~0); 4047#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 4048#L1449-1 assume !(1 == ~E_9~0); 4455#L1454-1 assume !(1 == ~E_10~0); 4456#L1459-1 assume !(1 == ~E_11~0); 5006#L1464-1 assume !(1 == ~E_12~0); 4825#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 4197#L1810 [2024-11-17 08:53:05,706 INFO L747 eck$LassoCheckResult]: Loop: 4197#L1810 assume true; 3932#L1810-1 assume !false; 3933#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4109#L998 assume true; 4110#L998-1 assume !false; 5352#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 5286#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 4810#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 5028#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5203#L1003 assume !(0 != eval_~tmp~0#1); 5438#L1006 assume true; 5399#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4131#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4132#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 4565#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5099#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5134#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5135#L1221 assume !(0 == ~T4_E~0); 3857#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3858#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4868#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3802#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3803#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4984#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5299#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5365#L1261 assume !(0 == ~T12_E~0); 5188#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 5189#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 5034#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 4615#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 4616#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 5563#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 5542#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 4902#L1301 assume !(0 == ~E_7~0); 4152#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 4153#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 5045#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 5068#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 5332#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 5333#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5230#L593-1 assume 1 == ~m_pc~0; 4261#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4263#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4888#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4229#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4230#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4588#L612-1 assume 1 == ~t1_pc~0; 4589#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5257#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5528#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5520#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4644#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4645#L631-1 assume 1 == ~t2_pc~0; 4242#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3826#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3827#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5436#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5338#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5268#L650-1 assume 1 == ~t3_pc~0; 5269#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5437#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4536#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4537#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4603#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3799#L669-1 assume 1 == ~t4_pc~0; 3800#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4348#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4392#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4393#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5174#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5079#L688-1 assume !(1 == ~t5_pc~0); 3902#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 3903#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4316#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4317#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3950#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3951#L707-1 assume !(1 == ~t6_pc~0); 4291#L717-1 is_transmit6_triggered_~__retres1~6#1 := 0; 4292#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4279#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4280#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5531#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5529#L726-1 assume 1 == ~t7_pc~0; 5530#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4682#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4683#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4829#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4830#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3816#L745-1 assume 1 == ~t8_pc~0; 3817#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4324#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5426#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4239#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4240#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4418#L764-1 assume 1 == ~t9_pc~0; 4584#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5462#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5263#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5264#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5375#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5508#L783-1 assume 1 == ~t10_pc~0; 5509#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4249#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5148#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5490#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5314#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5315#L802-1 assume 1 == ~t11_pc~0; 5209#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4893#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4894#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4534#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4535#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4950#L821-1 assume 1 == ~t12_pc~0; 4951#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4191#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4192#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5107#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5108#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5091#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 4596#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4597#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3884#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3885#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4419#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4420#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4998#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3947#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3948#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3851#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3852#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4352#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4353#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 3855#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 3856#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 4914#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 4915#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 5244#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 5421#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 5500#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 4430#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 4431#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 4124#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 4125#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 5175#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 5295#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4749#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3940#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4213#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4214#L1829 assume !(0 == start_simulation_~tmp~3#1); 4578#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 4579#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 3871#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 4467#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4468#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5035#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4724#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4196#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 4197#L1810 [2024-11-17 08:53:05,707 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:05,707 INFO L85 PathProgramCache]: Analyzing trace with hash 937183311, now seen corresponding path program 1 times [2024-11-17 08:53:05,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:05,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479645309] [2024-11-17 08:53:05,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:05,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:05,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:05,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:05,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:05,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [479645309] [2024-11-17 08:53:05,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [479645309] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:05,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:05,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:05,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2094485874] [2024-11-17 08:53:05,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:05,838 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:05,838 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:05,838 INFO L85 PathProgramCache]: Analyzing trace with hash -1386487404, now seen corresponding path program 1 times [2024-11-17 08:53:05,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:05,839 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746579057] [2024-11-17 08:53:05,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:05,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:05,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:05,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:05,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:05,996 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [746579057] [2024-11-17 08:53:05,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [746579057] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:05,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,000 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:06,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [364471494] [2024-11-17 08:53:06,000 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,000 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:06,000 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:06,002 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:06,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:06,003 INFO L87 Difference]: Start difference. First operand 1844 states and 2706 transitions. cyclomatic complexity: 863 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:06,027 INFO L93 Difference]: Finished difference Result 1844 states and 2705 transitions. [2024-11-17 08:53:06,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2705 transitions. [2024-11-17 08:53:06,035 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:06,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2705 transitions. [2024-11-17 08:53:06,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:06,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:06,045 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2705 transitions. [2024-11-17 08:53:06,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:06,049 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2705 transitions. [2024-11-17 08:53:06,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2705 transitions. [2024-11-17 08:53:06,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:06,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4669197396963123) internal successors, (2705), 1843 states have internal predecessors, (2705), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2705 transitions. [2024-11-17 08:53:06,083 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2705 transitions. [2024-11-17 08:53:06,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:06,084 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2705 transitions. [2024-11-17 08:53:06,084 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:53:06,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2705 transitions. [2024-11-17 08:53:06,091 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:06,091 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:06,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:06,095 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,096 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,097 INFO L745 eck$LassoCheckResult]: Stem: 8310#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 8311#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 7749#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7750#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9188#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 9064#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9065#L858 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 9124#L863 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9125#L868 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9246#L873 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7766#L878 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7767#L883 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8795#L888 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8880#L893 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 8438#L898 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7865#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7866#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8222#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9231#L1201-1 assume !(0 == ~M_E~0); 9232#L1206-1 assume !(0 == ~T1_E~0); 9058#L1211-1 assume !(0 == ~T2_E~0); 9059#L1216-1 assume !(0 == ~T3_E~0); 8035#L1221-1 assume !(0 == ~T4_E~0); 8036#L1226-1 assume !(0 == ~T5_E~0); 7658#L1231-1 assume !(0 == ~T6_E~0); 7659#L1236-1 assume !(0 == ~T7_E~0); 9107#L1241-1 assume !(0 == ~T8_E~0); 8083#L1246-1 assume !(0 == ~T9_E~0); 8084#L1251-1 assume !(0 == ~T10_E~0); 8258#L1256-1 assume !(0 == ~T11_E~0); 7431#L1261-1 assume !(0 == ~T12_E~0); 7432#L1266-1 assume !(0 == ~E_M~0); 9236#L1271-1 assume !(0 == ~E_1~0); 8807#L1276-1 assume !(0 == ~E_2~0); 8808#L1281-1 assume !(0 == ~E_3~0); 8770#L1286-1 assume !(0 == ~E_4~0); 7928#L1291-1 assume !(0 == ~E_5~0); 7929#L1296-1 assume !(0 == ~E_6~0); 8588#L1301-1 assume !(0 == ~E_7~0); 8589#L1306-1 assume !(0 == ~E_8~0); 8998#L1311-1 assume !(0 == ~E_9~0); 7880#L1316-1 assume !(0 == ~E_10~0); 7881#L1321-1 assume !(0 == ~E_11~0); 8603#L1326-1 assume !(0 == ~E_12~0); 8604#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8702#L593-15 assume 1 == ~m_pc~0; 8650#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7917#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7918#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8532#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 8533#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8567#L612-15 assume 1 == ~t1_pc~0; 8780#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7955#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8684#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9240#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 7556#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7557#L631-15 assume 1 == ~t2_pc~0; 8639#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8727#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8728#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7723#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 7724#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8997#L650-15 assume 1 == ~t3_pc~0; 7905#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7906#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9028#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7919#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 7920#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8678#L669-15 assume 1 == ~t4_pc~0; 8679#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8279#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8280#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8945#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 8583#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8584#L688-15 assume 1 == ~t5_pc~0; 8439#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8440#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8405#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8268#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 8269#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8815#L707-15 assume 1 == ~t6_pc~0; 8816#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8322#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8323#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8663#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 8664#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8799#L726-15 assume 1 == ~t7_pc~0; 9200#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8701#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8741#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8862#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 8863#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9037#L745-15 assume 1 == ~t8_pc~0; 9219#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7768#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7769#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7730#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 7731#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7914#L764-15 assume 1 == ~t9_pc~0; 7915#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8988#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9167#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9168#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 9176#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7544#L783-15 assume 1 == ~t10_pc~0; 7545#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8811#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8066#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8067#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 8576#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7609#L802-15 assume 1 == ~t11_pc~0; 7610#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7867#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9013#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9179#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 9178#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8821#L821-15 assume 1 == ~t12_pc~0; 8822#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8934#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8457#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7570#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 7571#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8386#L1339-1 assume !(1 == ~M_E~0); 9161#L1344-1 assume !(1 == ~T1_E~0); 9162#L1349-1 assume !(1 == ~T2_E~0); 8596#L1354-1 assume !(1 == ~T3_E~0); 8597#L1359-1 assume !(1 == ~T4_E~0); 8943#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7974#L1369-1 assume !(1 == ~T6_E~0); 7975#L1374-1 assume !(1 == ~T7_E~0); 8601#L1379-1 assume !(1 == ~T8_E~0); 8602#L1384-1 assume !(1 == ~T9_E~0); 8671#L1389-1 assume !(1 == ~T10_E~0); 9111#L1394-1 assume !(1 == ~T11_E~0); 9112#L1399-1 assume !(1 == ~T12_E~0); 9208#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 8087#L1409-1 assume !(1 == ~E_1~0); 8088#L1414-1 assume !(1 == ~E_2~0); 8829#L1419-1 assume !(1 == ~E_3~0); 7708#L1424-1 assume !(1 == ~E_4~0); 7709#L1429-1 assume !(1 == ~E_5~0); 8609#L1434-1 assume !(1 == ~E_6~0); 9131#L1439-1 assume !(1 == ~E_7~0); 7744#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 7745#L1449-1 assume !(1 == ~E_9~0); 8152#L1454-1 assume !(1 == ~E_10~0); 8153#L1459-1 assume !(1 == ~E_11~0); 8703#L1464-1 assume !(1 == ~E_12~0); 8522#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 7894#L1810 [2024-11-17 08:53:06,098 INFO L747 eck$LassoCheckResult]: Loop: 7894#L1810 assume true; 7629#L1810-1 assume !false; 7630#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7806#L998 assume true; 7807#L998-1 assume !false; 9049#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8983#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 8507#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8725#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8900#L1003 assume !(0 != eval_~tmp~0#1); 9135#L1006 assume true; 9096#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7828#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7829#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 8262#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8796#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8831#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8832#L1221 assume !(0 == ~T4_E~0); 7554#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7555#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8565#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7499#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7500#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8681#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8996#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9062#L1261 assume !(0 == ~T12_E~0); 8885#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 8886#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 8731#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 8312#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 8313#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 9260#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 9239#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 8599#L1301 assume !(0 == ~E_7~0); 7849#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 7850#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 8742#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 8765#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 9029#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 9030#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8927#L593-1 assume 1 == ~m_pc~0; 7958#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7960#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8585#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7926#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7927#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8285#L612-1 assume 1 == ~t1_pc~0; 8286#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8954#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9225#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9217#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8341#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8342#L631-1 assume 1 == ~t2_pc~0; 7939#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7523#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7524#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9133#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9035#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8965#L650-1 assume 1 == ~t3_pc~0; 8966#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9134#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8233#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8234#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8300#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7496#L669-1 assume 1 == ~t4_pc~0; 7497#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8045#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8089#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8090#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8871#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8776#L688-1 assume 1 == ~t5_pc~0; 7840#L689-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7600#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8013#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8014#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7647#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7648#L707-1 assume 1 == ~t6_pc~0; 8352#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7989#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7976#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7977#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9228#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9226#L726-1 assume 1 == ~t7_pc~0; 9227#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8379#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8380#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8526#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8527#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7513#L745-1 assume 1 == ~t8_pc~0; 7514#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8021#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9123#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7936#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7937#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8115#L764-1 assume 1 == ~t9_pc~0; 8281#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9159#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8960#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8961#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9072#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9205#L783-1 assume 1 == ~t10_pc~0; 9206#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7946#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8845#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9187#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9011#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9012#L802-1 assume 1 == ~t11_pc~0; 8906#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8590#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8591#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8231#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8232#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8647#L821-1 assume 1 == ~t12_pc~0; 8648#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 7888#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7889#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8804#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8805#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8788#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 8293#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8294#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7581#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7582#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8116#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8117#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8695#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7644#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7645#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7548#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7549#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8049#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8050#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 7552#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 7553#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 8611#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 8612#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 8941#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 9118#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 9197#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 8127#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 8128#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 7821#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 7822#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 8872#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 8992#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8446#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7637#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 7910#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7911#L1829 assume !(0 == start_simulation_~tmp~3#1); 8275#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 8276#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 7568#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 8164#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 8165#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8732#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8421#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7893#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 7894#L1810 [2024-11-17 08:53:06,098 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,100 INFO L85 PathProgramCache]: Analyzing trace with hash -11306418, now seen corresponding path program 1 times [2024-11-17 08:53:06,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989333534] [2024-11-17 08:53:06,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1989333534] [2024-11-17 08:53:06,183 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1989333534] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,183 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,183 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:06,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199600772] [2024-11-17 08:53:06,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,184 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:06,184 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,185 INFO L85 PathProgramCache]: Analyzing trace with hash -1518023858, now seen corresponding path program 1 times [2024-11-17 08:53:06,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1991799633] [2024-11-17 08:53:06,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,258 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1991799633] [2024-11-17 08:53:06,258 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1991799633] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,258 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,259 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:06,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841902369] [2024-11-17 08:53:06,259 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,259 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:06,260 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:06,260 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:06,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:06,260 INFO L87 Difference]: Start difference. First operand 1844 states and 2705 transitions. cyclomatic complexity: 862 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:06,283 INFO L93 Difference]: Finished difference Result 1844 states and 2704 transitions. [2024-11-17 08:53:06,283 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2704 transitions. [2024-11-17 08:53:06,290 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:06,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2704 transitions. [2024-11-17 08:53:06,296 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:06,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:06,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2704 transitions. [2024-11-17 08:53:06,299 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:06,299 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2704 transitions. [2024-11-17 08:53:06,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2704 transitions. [2024-11-17 08:53:06,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:06,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4663774403470715) internal successors, (2704), 1843 states have internal predecessors, (2704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2704 transitions. [2024-11-17 08:53:06,320 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2704 transitions. [2024-11-17 08:53:06,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:06,321 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2704 transitions. [2024-11-17 08:53:06,321 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:53:06,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2704 transitions. [2024-11-17 08:53:06,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:06,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:06,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:06,329 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,329 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,330 INFO L745 eck$LassoCheckResult]: Stem: 12007#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 12008#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 11446#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11447#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12885#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 12761#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12762#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12821#L863 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12822#L868 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12943#L873 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11463#L878 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11464#L883 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12492#L888 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12577#L893 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 12135#L898 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 11562#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 11563#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 11919#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12928#L1201-1 assume !(0 == ~M_E~0); 12929#L1206-1 assume !(0 == ~T1_E~0); 12755#L1211-1 assume !(0 == ~T2_E~0); 12756#L1216-1 assume !(0 == ~T3_E~0); 11732#L1221-1 assume !(0 == ~T4_E~0); 11733#L1226-1 assume !(0 == ~T5_E~0); 11355#L1231-1 assume !(0 == ~T6_E~0); 11356#L1236-1 assume !(0 == ~T7_E~0); 12804#L1241-1 assume !(0 == ~T8_E~0); 11780#L1246-1 assume !(0 == ~T9_E~0); 11781#L1251-1 assume !(0 == ~T10_E~0); 11955#L1256-1 assume !(0 == ~T11_E~0); 11128#L1261-1 assume !(0 == ~T12_E~0); 11129#L1266-1 assume !(0 == ~E_M~0); 12933#L1271-1 assume !(0 == ~E_1~0); 12504#L1276-1 assume !(0 == ~E_2~0); 12505#L1281-1 assume !(0 == ~E_3~0); 12467#L1286-1 assume !(0 == ~E_4~0); 11625#L1291-1 assume !(0 == ~E_5~0); 11626#L1296-1 assume !(0 == ~E_6~0); 12285#L1301-1 assume !(0 == ~E_7~0); 12286#L1306-1 assume !(0 == ~E_8~0); 12695#L1311-1 assume !(0 == ~E_9~0); 11577#L1316-1 assume !(0 == ~E_10~0); 11578#L1321-1 assume !(0 == ~E_11~0); 12300#L1326-1 assume !(0 == ~E_12~0); 12301#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12399#L593-15 assume 1 == ~m_pc~0; 12347#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11614#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11615#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12229#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 12230#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12264#L612-15 assume 1 == ~t1_pc~0; 12477#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11652#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12381#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12937#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 11253#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11254#L631-15 assume 1 == ~t2_pc~0; 12336#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12424#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12425#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11420#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 11421#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12694#L650-15 assume 1 == ~t3_pc~0; 11602#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11603#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12725#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11616#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 11617#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12375#L669-15 assume 1 == ~t4_pc~0; 12376#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11976#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11977#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12642#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 12280#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12281#L688-15 assume 1 == ~t5_pc~0; 12136#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12137#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12102#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11965#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 11966#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12512#L707-15 assume 1 == ~t6_pc~0; 12513#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12019#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12020#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12360#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 12361#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12496#L726-15 assume 1 == ~t7_pc~0; 12897#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12398#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12438#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12559#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 12560#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12734#L745-15 assume 1 == ~t8_pc~0; 12916#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11465#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11466#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11427#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 11428#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11611#L764-15 assume 1 == ~t9_pc~0; 11612#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12685#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12864#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12865#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 12873#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11241#L783-15 assume 1 == ~t10_pc~0; 11242#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12508#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11763#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11764#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 12273#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11306#L802-15 assume 1 == ~t11_pc~0; 11307#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11564#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12710#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12876#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 12875#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12518#L821-15 assume 1 == ~t12_pc~0; 12519#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12631#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12154#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11267#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 11268#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12083#L1339-1 assume !(1 == ~M_E~0); 12858#L1344-1 assume !(1 == ~T1_E~0); 12859#L1349-1 assume !(1 == ~T2_E~0); 12293#L1354-1 assume !(1 == ~T3_E~0); 12294#L1359-1 assume !(1 == ~T4_E~0); 12640#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11671#L1369-1 assume !(1 == ~T6_E~0); 11672#L1374-1 assume !(1 == ~T7_E~0); 12298#L1379-1 assume !(1 == ~T8_E~0); 12299#L1384-1 assume !(1 == ~T9_E~0); 12368#L1389-1 assume !(1 == ~T10_E~0); 12808#L1394-1 assume !(1 == ~T11_E~0); 12809#L1399-1 assume !(1 == ~T12_E~0); 12905#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 11784#L1409-1 assume !(1 == ~E_1~0); 11785#L1414-1 assume !(1 == ~E_2~0); 12526#L1419-1 assume !(1 == ~E_3~0); 11405#L1424-1 assume !(1 == ~E_4~0); 11406#L1429-1 assume !(1 == ~E_5~0); 12306#L1434-1 assume !(1 == ~E_6~0); 12828#L1439-1 assume !(1 == ~E_7~0); 11441#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 11442#L1449-1 assume !(1 == ~E_9~0); 11849#L1454-1 assume !(1 == ~E_10~0); 11850#L1459-1 assume !(1 == ~E_11~0); 12400#L1464-1 assume !(1 == ~E_12~0); 12219#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 11591#L1810 [2024-11-17 08:53:06,330 INFO L747 eck$LassoCheckResult]: Loop: 11591#L1810 assume true; 11326#L1810-1 assume !false; 11327#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11503#L998 assume true; 11504#L998-1 assume !false; 12746#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12680#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 12204#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 12422#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12597#L1003 assume !(0 != eval_~tmp~0#1); 12832#L1006 assume true; 12793#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11525#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11526#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 11959#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12493#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12528#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12529#L1221 assume !(0 == ~T4_E~0); 11251#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11252#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12262#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11196#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11197#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12378#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12693#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12759#L1261 assume !(0 == ~T12_E~0); 12582#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 12583#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 12428#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 12009#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 12010#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 12957#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 12936#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 12296#L1301 assume !(0 == ~E_7~0); 11546#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 11547#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 12439#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 12462#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 12726#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 12727#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12624#L593-1 assume 1 == ~m_pc~0; 11655#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 11657#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12282#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11623#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11624#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11982#L612-1 assume !(1 == ~t1_pc~0); 11984#L622-1 is_transmit1_triggered_~__retres1~1#1 := 0; 12651#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12922#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12914#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12038#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12039#L631-1 assume 1 == ~t2_pc~0; 11636#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11220#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11221#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12830#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12732#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12662#L650-1 assume 1 == ~t3_pc~0; 12663#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12831#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11930#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11931#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11997#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11193#L669-1 assume 1 == ~t4_pc~0; 11194#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11742#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11786#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11787#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12568#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12473#L688-1 assume !(1 == ~t5_pc~0); 11296#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 11297#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11710#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11711#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11344#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11345#L707-1 assume 1 == ~t6_pc~0; 12049#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11686#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11673#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11674#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12925#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12923#L726-1 assume 1 == ~t7_pc~0; 12924#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12076#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12077#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12223#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12224#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11210#L745-1 assume 1 == ~t8_pc~0; 11211#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11718#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12820#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11633#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11634#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11812#L764-1 assume 1 == ~t9_pc~0; 11978#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12856#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12657#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12658#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12769#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12902#L783-1 assume 1 == ~t10_pc~0; 12903#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11643#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12542#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12884#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12708#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12709#L802-1 assume 1 == ~t11_pc~0; 12603#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12287#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12288#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11928#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11929#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12344#L821-1 assume 1 == ~t12_pc~0; 12345#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11585#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11586#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12501#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12502#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12485#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 11990#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11991#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11278#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11279#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11813#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11814#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12392#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11341#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11342#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11245#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11246#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 11746#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11747#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 11249#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 11250#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 12308#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 12309#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 12638#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 12815#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 12894#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 11824#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 11825#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 11518#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 11519#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 12569#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 12689#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 12143#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11334#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11607#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 11608#L1829 assume !(0 == start_simulation_~tmp~3#1); 11972#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 11973#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 11265#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 11861#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 11862#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12429#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12118#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11590#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 11591#L1810 [2024-11-17 08:53:06,332 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,333 INFO L85 PathProgramCache]: Analyzing trace with hash -180450193, now seen corresponding path program 1 times [2024-11-17 08:53:06,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498249135] [2024-11-17 08:53:06,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,381 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,381 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498249135] [2024-11-17 08:53:06,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498249135] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,382 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,382 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:06,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1987110011] [2024-11-17 08:53:06,384 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,384 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:06,385 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,385 INFO L85 PathProgramCache]: Analyzing trace with hash -692401580, now seen corresponding path program 1 times [2024-11-17 08:53:06,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,385 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961328892] [2024-11-17 08:53:06,385 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,385 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961328892] [2024-11-17 08:53:06,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961328892] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:06,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025487822] [2024-11-17 08:53:06,456 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,457 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:06,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:06,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:06,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:06,458 INFO L87 Difference]: Start difference. First operand 1844 states and 2704 transitions. cyclomatic complexity: 861 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:06,482 INFO L93 Difference]: Finished difference Result 1844 states and 2703 transitions. [2024-11-17 08:53:06,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2703 transitions. [2024-11-17 08:53:06,489 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:06,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2703 transitions. [2024-11-17 08:53:06,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:06,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:06,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2703 transitions. [2024-11-17 08:53:06,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:06,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2703 transitions. [2024-11-17 08:53:06,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2703 transitions. [2024-11-17 08:53:06,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:06,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4658351409978307) internal successors, (2703), 1843 states have internal predecessors, (2703), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2703 transitions. [2024-11-17 08:53:06,522 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2703 transitions. [2024-11-17 08:53:06,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:06,523 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2703 transitions. [2024-11-17 08:53:06,524 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:53:06,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2703 transitions. [2024-11-17 08:53:06,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:06,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:06,533 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:06,534 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,534 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,534 INFO L745 eck$LassoCheckResult]: Stem: 15704#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 15705#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 15143#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15144#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16582#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 16458#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16459#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16518#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16519#L868 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16640#L873 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15160#L878 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15161#L883 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16189#L888 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16274#L893 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 15832#L898 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15259#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15260#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 15616#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16625#L1201-1 assume !(0 == ~M_E~0); 16626#L1206-1 assume !(0 == ~T1_E~0); 16452#L1211-1 assume !(0 == ~T2_E~0); 16453#L1216-1 assume !(0 == ~T3_E~0); 15429#L1221-1 assume !(0 == ~T4_E~0); 15430#L1226-1 assume !(0 == ~T5_E~0); 15052#L1231-1 assume !(0 == ~T6_E~0); 15053#L1236-1 assume !(0 == ~T7_E~0); 16501#L1241-1 assume !(0 == ~T8_E~0); 15477#L1246-1 assume !(0 == ~T9_E~0); 15478#L1251-1 assume !(0 == ~T10_E~0); 15652#L1256-1 assume !(0 == ~T11_E~0); 14825#L1261-1 assume !(0 == ~T12_E~0); 14826#L1266-1 assume !(0 == ~E_M~0); 16630#L1271-1 assume !(0 == ~E_1~0); 16201#L1276-1 assume !(0 == ~E_2~0); 16202#L1281-1 assume !(0 == ~E_3~0); 16164#L1286-1 assume !(0 == ~E_4~0); 15322#L1291-1 assume !(0 == ~E_5~0); 15323#L1296-1 assume !(0 == ~E_6~0); 15982#L1301-1 assume !(0 == ~E_7~0); 15983#L1306-1 assume !(0 == ~E_8~0); 16392#L1311-1 assume !(0 == ~E_9~0); 15274#L1316-1 assume !(0 == ~E_10~0); 15275#L1321-1 assume !(0 == ~E_11~0); 15997#L1326-1 assume !(0 == ~E_12~0); 15998#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16096#L593-15 assume 1 == ~m_pc~0; 16044#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15311#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15312#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15926#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 15927#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15961#L612-15 assume 1 == ~t1_pc~0; 16174#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15349#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16078#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16634#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 14950#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14951#L631-15 assume 1 == ~t2_pc~0; 16033#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16121#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16122#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15117#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 15118#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16391#L650-15 assume 1 == ~t3_pc~0; 15299#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15300#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16422#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15313#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 15314#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16072#L669-15 assume 1 == ~t4_pc~0; 16073#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15673#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15674#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16339#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 15977#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15978#L688-15 assume 1 == ~t5_pc~0; 15833#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15834#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15799#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15662#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 15663#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16209#L707-15 assume 1 == ~t6_pc~0; 16210#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15716#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15717#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16057#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 16058#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16193#L726-15 assume 1 == ~t7_pc~0; 16594#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16095#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16135#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16256#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 16257#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16431#L745-15 assume 1 == ~t8_pc~0; 16613#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15162#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15163#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15124#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 15125#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15308#L764-15 assume 1 == ~t9_pc~0; 15309#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16382#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16561#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16562#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 16570#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14938#L783-15 assume 1 == ~t10_pc~0; 14939#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16205#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 15460#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15461#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 15970#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 15003#L802-15 assume 1 == ~t11_pc~0; 15004#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15261#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16407#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16573#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 16572#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16215#L821-15 assume 1 == ~t12_pc~0; 16216#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16328#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15851#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14964#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 14965#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15780#L1339-1 assume !(1 == ~M_E~0); 16555#L1344-1 assume !(1 == ~T1_E~0); 16556#L1349-1 assume !(1 == ~T2_E~0); 15990#L1354-1 assume !(1 == ~T3_E~0); 15991#L1359-1 assume !(1 == ~T4_E~0); 16337#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15368#L1369-1 assume !(1 == ~T6_E~0); 15369#L1374-1 assume !(1 == ~T7_E~0); 15995#L1379-1 assume !(1 == ~T8_E~0); 15996#L1384-1 assume !(1 == ~T9_E~0); 16065#L1389-1 assume !(1 == ~T10_E~0); 16505#L1394-1 assume !(1 == ~T11_E~0); 16506#L1399-1 assume !(1 == ~T12_E~0); 16602#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 15481#L1409-1 assume !(1 == ~E_1~0); 15482#L1414-1 assume !(1 == ~E_2~0); 16223#L1419-1 assume !(1 == ~E_3~0); 15102#L1424-1 assume !(1 == ~E_4~0); 15103#L1429-1 assume !(1 == ~E_5~0); 16003#L1434-1 assume !(1 == ~E_6~0); 16525#L1439-1 assume !(1 == ~E_7~0); 15138#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 15139#L1449-1 assume !(1 == ~E_9~0); 15546#L1454-1 assume !(1 == ~E_10~0); 15547#L1459-1 assume !(1 == ~E_11~0); 16097#L1464-1 assume !(1 == ~E_12~0); 15916#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 15288#L1810 [2024-11-17 08:53:06,535 INFO L747 eck$LassoCheckResult]: Loop: 15288#L1810 assume true; 15023#L1810-1 assume !false; 15024#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15200#L998 assume true; 15201#L998-1 assume !false; 16443#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 16377#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15901#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 16119#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 16294#L1003 assume !(0 != eval_~tmp~0#1); 16529#L1006 assume true; 16490#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15222#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15223#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 15656#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16190#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16225#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16226#L1221 assume !(0 == ~T4_E~0); 14948#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14949#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15959#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14893#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14894#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16075#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16390#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16456#L1261 assume !(0 == ~T12_E~0); 16279#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 16280#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 16125#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 15706#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 15707#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 16654#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 16633#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 15993#L1301 assume !(0 == ~E_7~0); 15243#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 15244#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 16136#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 16159#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 16423#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 16424#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16321#L593-1 assume 1 == ~m_pc~0; 15352#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15354#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15979#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15320#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15321#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15679#L612-1 assume 1 == ~t1_pc~0; 15680#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16348#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16619#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16611#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15735#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15736#L631-1 assume 1 == ~t2_pc~0; 15333#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14917#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14918#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16527#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16429#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16359#L650-1 assume 1 == ~t3_pc~0; 16360#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16528#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15627#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 15628#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15694#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14890#L669-1 assume 1 == ~t4_pc~0; 14891#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15439#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15483#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15484#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16265#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16170#L688-1 assume !(1 == ~t5_pc~0); 14993#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 14994#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15407#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15408#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15041#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15042#L707-1 assume 1 == ~t6_pc~0; 15746#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15383#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15370#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15371#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16622#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16620#L726-1 assume !(1 == ~t7_pc~0); 15952#L736-1 is_transmit7_triggered_~__retres1~7#1 := 0; 15773#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15774#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15920#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15921#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14907#L745-1 assume 1 == ~t8_pc~0; 14908#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15415#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16517#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15330#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15331#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15509#L764-1 assume 1 == ~t9_pc~0; 15675#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16553#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16354#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16355#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16466#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16599#L783-1 assume 1 == ~t10_pc~0; 16600#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15340#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16239#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16581#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16405#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16406#L802-1 assume 1 == ~t11_pc~0; 16300#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15984#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15985#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15625#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 15626#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16041#L821-1 assume 1 == ~t12_pc~0; 16042#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 15282#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 15283#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16198#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16199#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16182#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 15687#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15688#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14975#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14976#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15510#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15511#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16089#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15038#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15039#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14942#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14943#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15443#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15444#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 14946#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 14947#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 16005#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 16006#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 16335#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 16512#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 16591#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 15521#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 15522#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 15215#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 15216#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 16266#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 16386#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15840#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 15031#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15304#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 15305#L1829 assume !(0 == start_simulation_~tmp~3#1); 15669#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 15670#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 14962#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 15558#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 15559#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16126#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15815#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 15287#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 15288#L1810 [2024-11-17 08:53:06,535 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,535 INFO L85 PathProgramCache]: Analyzing trace with hash 1753756206, now seen corresponding path program 1 times [2024-11-17 08:53:06,535 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1271568825] [2024-11-17 08:53:06,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,603 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1271568825] [2024-11-17 08:53:06,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1271568825] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,604 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,604 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:06,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1515730593] [2024-11-17 08:53:06,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,604 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:06,605 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,605 INFO L85 PathProgramCache]: Analyzing trace with hash -2020241452, now seen corresponding path program 1 times [2024-11-17 08:53:06,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1935623527] [2024-11-17 08:53:06,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1935623527] [2024-11-17 08:53:06,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1935623527] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:06,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [133926577] [2024-11-17 08:53:06,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,675 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:06,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:06,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:06,675 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:06,676 INFO L87 Difference]: Start difference. First operand 1844 states and 2703 transitions. cyclomatic complexity: 860 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:06,702 INFO L93 Difference]: Finished difference Result 1844 states and 2702 transitions. [2024-11-17 08:53:06,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2702 transitions. [2024-11-17 08:53:06,709 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:06,715 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2702 transitions. [2024-11-17 08:53:06,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:06,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:06,716 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2702 transitions. [2024-11-17 08:53:06,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:06,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2702 transitions. [2024-11-17 08:53:06,720 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2702 transitions. [2024-11-17 08:53:06,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:06,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.46529284164859) internal successors, (2702), 1843 states have internal predecessors, (2702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2702 transitions. [2024-11-17 08:53:06,741 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2702 transitions. [2024-11-17 08:53:06,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:06,742 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2702 transitions. [2024-11-17 08:53:06,742 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:53:06,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2702 transitions. [2024-11-17 08:53:06,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:06,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:06,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:06,748 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,749 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,749 INFO L745 eck$LassoCheckResult]: Stem: 19401#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 19402#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 18840#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18841#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20279#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 20155#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20156#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20215#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20216#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20337#L873 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 18857#L878 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 18858#L883 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19886#L888 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19971#L893 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 19529#L898 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18956#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18957#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 19313#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20322#L1201-1 assume !(0 == ~M_E~0); 20323#L1206-1 assume !(0 == ~T1_E~0); 20149#L1211-1 assume !(0 == ~T2_E~0); 20150#L1216-1 assume !(0 == ~T3_E~0); 19126#L1221-1 assume !(0 == ~T4_E~0); 19127#L1226-1 assume !(0 == ~T5_E~0); 18749#L1231-1 assume !(0 == ~T6_E~0); 18750#L1236-1 assume !(0 == ~T7_E~0); 20198#L1241-1 assume !(0 == ~T8_E~0); 19174#L1246-1 assume !(0 == ~T9_E~0); 19175#L1251-1 assume !(0 == ~T10_E~0); 19349#L1256-1 assume !(0 == ~T11_E~0); 18522#L1261-1 assume !(0 == ~T12_E~0); 18523#L1266-1 assume !(0 == ~E_M~0); 20327#L1271-1 assume !(0 == ~E_1~0); 19898#L1276-1 assume !(0 == ~E_2~0); 19899#L1281-1 assume !(0 == ~E_3~0); 19861#L1286-1 assume !(0 == ~E_4~0); 19019#L1291-1 assume !(0 == ~E_5~0); 19020#L1296-1 assume !(0 == ~E_6~0); 19679#L1301-1 assume !(0 == ~E_7~0); 19680#L1306-1 assume !(0 == ~E_8~0); 20089#L1311-1 assume !(0 == ~E_9~0); 18971#L1316-1 assume !(0 == ~E_10~0); 18972#L1321-1 assume !(0 == ~E_11~0); 19694#L1326-1 assume !(0 == ~E_12~0); 19695#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19793#L593-15 assume 1 == ~m_pc~0; 19741#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19008#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19009#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19623#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 19624#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19658#L612-15 assume 1 == ~t1_pc~0; 19871#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19046#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19775#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20331#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 18647#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18648#L631-15 assume 1 == ~t2_pc~0; 19730#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19818#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19819#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18814#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 18815#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20088#L650-15 assume 1 == ~t3_pc~0; 18996#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18997#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20119#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19010#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 19011#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19769#L669-15 assume 1 == ~t4_pc~0; 19770#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19370#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19371#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20036#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 19674#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19675#L688-15 assume 1 == ~t5_pc~0; 19530#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19531#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19496#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19359#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 19360#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19906#L707-15 assume 1 == ~t6_pc~0; 19907#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19413#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19414#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19754#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 19755#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19890#L726-15 assume 1 == ~t7_pc~0; 20291#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19792#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19832#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19953#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 19954#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20128#L745-15 assume 1 == ~t8_pc~0; 20310#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18859#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18860#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18821#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 18822#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19005#L764-15 assume 1 == ~t9_pc~0; 19006#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20079#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20258#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20259#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 20267#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18635#L783-15 assume 1 == ~t10_pc~0; 18636#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19902#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19157#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19158#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 19667#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18700#L802-15 assume 1 == ~t11_pc~0; 18701#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18958#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20104#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20270#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 20269#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19912#L821-15 assume 1 == ~t12_pc~0; 19913#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20025#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 19548#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18661#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 18662#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19477#L1339-1 assume !(1 == ~M_E~0); 20252#L1344-1 assume !(1 == ~T1_E~0); 20253#L1349-1 assume !(1 == ~T2_E~0); 19687#L1354-1 assume !(1 == ~T3_E~0); 19688#L1359-1 assume !(1 == ~T4_E~0); 20034#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19065#L1369-1 assume !(1 == ~T6_E~0); 19066#L1374-1 assume !(1 == ~T7_E~0); 19692#L1379-1 assume !(1 == ~T8_E~0); 19693#L1384-1 assume !(1 == ~T9_E~0); 19762#L1389-1 assume !(1 == ~T10_E~0); 20202#L1394-1 assume !(1 == ~T11_E~0); 20203#L1399-1 assume !(1 == ~T12_E~0); 20299#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 19178#L1409-1 assume !(1 == ~E_1~0); 19179#L1414-1 assume !(1 == ~E_2~0); 19920#L1419-1 assume !(1 == ~E_3~0); 18799#L1424-1 assume !(1 == ~E_4~0); 18800#L1429-1 assume !(1 == ~E_5~0); 19700#L1434-1 assume !(1 == ~E_6~0); 20222#L1439-1 assume !(1 == ~E_7~0); 18835#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 18836#L1449-1 assume !(1 == ~E_9~0); 19243#L1454-1 assume !(1 == ~E_10~0); 19244#L1459-1 assume !(1 == ~E_11~0); 19794#L1464-1 assume !(1 == ~E_12~0); 19613#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 18985#L1810 [2024-11-17 08:53:06,750 INFO L747 eck$LassoCheckResult]: Loop: 18985#L1810 assume true; 18720#L1810-1 assume !false; 18721#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18897#L998 assume true; 18898#L998-1 assume !false; 20140#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 20074#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 19598#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 19816#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 19991#L1003 assume !(0 != eval_~tmp~0#1); 20226#L1006 assume true; 20187#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18919#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18920#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 19353#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19887#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19922#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19923#L1221 assume !(0 == ~T4_E~0); 18645#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18646#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19656#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18590#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18591#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19772#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20087#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20153#L1261 assume !(0 == ~T12_E~0); 19976#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 19977#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 19822#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 19403#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 19404#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 20351#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 20330#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 19690#L1301 assume !(0 == ~E_7~0); 18940#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 18941#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 19833#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 19856#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 20120#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 20121#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20018#L593-1 assume 1 == ~m_pc~0; 19049#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 19051#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19676#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19017#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19018#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19376#L612-1 assume 1 == ~t1_pc~0; 19377#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20045#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20316#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20308#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19432#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19433#L631-1 assume 1 == ~t2_pc~0; 19030#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18614#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18615#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20224#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20126#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20056#L650-1 assume 1 == ~t3_pc~0; 20057#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20225#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19324#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19325#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19391#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18587#L669-1 assume 1 == ~t4_pc~0; 18588#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19136#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19180#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19181#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19962#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19867#L688-1 assume !(1 == ~t5_pc~0); 18690#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 18691#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19104#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19105#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18738#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18739#L707-1 assume 1 == ~t6_pc~0; 19443#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19080#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19067#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19068#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20319#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20317#L726-1 assume !(1 == ~t7_pc~0); 19649#L736-1 is_transmit7_triggered_~__retres1~7#1 := 0; 19470#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19471#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19617#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19618#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18604#L745-1 assume 1 == ~t8_pc~0; 18605#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19112#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20214#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19027#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19028#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19206#L764-1 assume 1 == ~t9_pc~0; 19372#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20250#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20051#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20052#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20163#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20296#L783-1 assume 1 == ~t10_pc~0; 20297#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19037#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19936#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20278#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20102#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20103#L802-1 assume !(1 == ~t11_pc~0); 19840#L812-1 is_transmit11_triggered_~__retres1~11#1 := 0; 19681#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19682#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19322#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19323#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 19738#L821-1 assume 1 == ~t12_pc~0; 19739#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18979#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18980#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19895#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 19896#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19879#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 19384#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19385#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18672#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18673#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19207#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19208#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19786#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18735#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18736#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18639#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 18640#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19140#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19141#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 18643#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 18644#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 19702#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 19703#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 20032#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 20209#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 20288#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 19218#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 19219#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 18912#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 18913#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 19963#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 20083#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19537#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18728#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 19001#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19002#L1829 assume !(0 == start_simulation_~tmp~3#1); 19366#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 19367#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 18659#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 19255#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19256#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19823#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19512#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 18984#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 18985#L1810 [2024-11-17 08:53:06,750 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,750 INFO L85 PathProgramCache]: Analyzing trace with hash -123512689, now seen corresponding path program 1 times [2024-11-17 08:53:06,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795179381] [2024-11-17 08:53:06,751 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,789 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,789 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1795179381] [2024-11-17 08:53:06,789 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1795179381] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,789 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,789 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:06,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [90512279] [2024-11-17 08:53:06,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,790 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:06,790 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,791 INFO L85 PathProgramCache]: Analyzing trace with hash -405970601, now seen corresponding path program 1 times [2024-11-17 08:53:06,791 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,791 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666053956] [2024-11-17 08:53:06,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,852 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1666053956] [2024-11-17 08:53:06,852 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1666053956] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,852 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,852 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:06,852 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [657708633] [2024-11-17 08:53:06,852 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,853 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:06,853 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:06,853 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:06,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:06,853 INFO L87 Difference]: Start difference. First operand 1844 states and 2702 transitions. cyclomatic complexity: 859 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:06,872 INFO L93 Difference]: Finished difference Result 1844 states and 2701 transitions. [2024-11-17 08:53:06,872 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2701 transitions. [2024-11-17 08:53:06,877 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:06,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2701 transitions. [2024-11-17 08:53:06,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:06,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:06,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2701 transitions. [2024-11-17 08:53:06,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:06,885 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2701 transitions. [2024-11-17 08:53:06,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2701 transitions. [2024-11-17 08:53:06,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:06,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4647505422993492) internal successors, (2701), 1843 states have internal predecessors, (2701), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:06,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2701 transitions. [2024-11-17 08:53:06,904 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2701 transitions. [2024-11-17 08:53:06,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:06,905 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2701 transitions. [2024-11-17 08:53:06,905 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:53:06,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2701 transitions. [2024-11-17 08:53:06,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:06,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:06,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:06,910 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:06,910 INFO L745 eck$LassoCheckResult]: Stem: 23098#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 23099#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 22537#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22538#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23976#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 23852#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23853#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23913#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23914#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24034#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22554#L878 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 22555#L883 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23583#L888 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23668#L893 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 23226#L898 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22653#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22654#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 23012#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24019#L1201-1 assume !(0 == ~M_E~0); 24020#L1206-1 assume !(0 == ~T1_E~0); 23846#L1211-1 assume !(0 == ~T2_E~0); 23847#L1216-1 assume !(0 == ~T3_E~0); 22827#L1221-1 assume !(0 == ~T4_E~0); 22828#L1226-1 assume !(0 == ~T5_E~0); 22446#L1231-1 assume !(0 == ~T6_E~0); 22447#L1236-1 assume !(0 == ~T7_E~0); 23895#L1241-1 assume !(0 == ~T8_E~0); 22873#L1246-1 assume !(0 == ~T9_E~0); 22874#L1251-1 assume !(0 == ~T10_E~0); 23047#L1256-1 assume !(0 == ~T11_E~0); 22221#L1261-1 assume !(0 == ~T12_E~0); 22222#L1266-1 assume !(0 == ~E_M~0); 24024#L1271-1 assume !(0 == ~E_1~0); 23595#L1276-1 assume !(0 == ~E_2~0); 23596#L1281-1 assume !(0 == ~E_3~0); 23558#L1286-1 assume !(0 == ~E_4~0); 22716#L1291-1 assume !(0 == ~E_5~0); 22717#L1296-1 assume !(0 == ~E_6~0); 23376#L1301-1 assume !(0 == ~E_7~0); 23377#L1306-1 assume !(0 == ~E_8~0); 23787#L1311-1 assume !(0 == ~E_9~0); 22668#L1316-1 assume !(0 == ~E_10~0); 22669#L1321-1 assume !(0 == ~E_11~0); 23391#L1326-1 assume !(0 == ~E_12~0); 23392#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23490#L593-15 assume 1 == ~m_pc~0; 23438#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22705#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22706#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23320#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 23321#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23355#L612-15 assume 1 == ~t1_pc~0; 23568#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22743#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23472#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24028#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 22344#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22345#L631-15 assume 1 == ~t2_pc~0; 23427#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23515#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23516#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22511#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 22512#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23785#L650-15 assume 1 == ~t3_pc~0; 22693#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22694#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23816#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22707#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 22708#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23466#L669-15 assume 1 == ~t4_pc~0; 23467#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23067#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23068#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23733#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 23371#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23372#L688-15 assume 1 == ~t5_pc~0; 23228#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23229#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23193#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23056#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 23057#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23603#L707-15 assume 1 == ~t6_pc~0; 23604#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23110#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23111#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23451#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 23452#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23587#L726-15 assume 1 == ~t7_pc~0; 23988#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23489#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23529#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23650#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 23651#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23825#L745-15 assume 1 == ~t8_pc~0; 24007#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22558#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22559#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22521#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 22522#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22702#L764-15 assume 1 == ~t9_pc~0; 22703#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23776#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23955#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23956#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 23964#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22332#L783-15 assume 1 == ~t10_pc~0; 22333#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23599#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22854#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22855#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 23364#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22397#L802-15 assume 1 == ~t11_pc~0; 22398#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22655#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23801#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23967#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 23966#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23609#L821-15 assume 1 == ~t12_pc~0; 23610#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23722#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23245#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22358#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 22359#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23174#L1339-1 assume !(1 == ~M_E~0); 23949#L1344-1 assume !(1 == ~T1_E~0); 23950#L1349-1 assume !(1 == ~T2_E~0); 23384#L1354-1 assume !(1 == ~T3_E~0); 23385#L1359-1 assume !(1 == ~T4_E~0); 23731#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22762#L1369-1 assume !(1 == ~T6_E~0); 22763#L1374-1 assume !(1 == ~T7_E~0); 23389#L1379-1 assume !(1 == ~T8_E~0); 23390#L1384-1 assume !(1 == ~T9_E~0); 23459#L1389-1 assume !(1 == ~T10_E~0); 23899#L1394-1 assume !(1 == ~T11_E~0); 23900#L1399-1 assume !(1 == ~T12_E~0); 23996#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 22875#L1409-1 assume !(1 == ~E_1~0); 22876#L1414-1 assume !(1 == ~E_2~0); 23617#L1419-1 assume !(1 == ~E_3~0); 22496#L1424-1 assume !(1 == ~E_4~0); 22497#L1429-1 assume !(1 == ~E_5~0); 23397#L1434-1 assume !(1 == ~E_6~0); 23919#L1439-1 assume !(1 == ~E_7~0); 22532#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 22533#L1449-1 assume !(1 == ~E_9~0); 22940#L1454-1 assume !(1 == ~E_10~0); 22941#L1459-1 assume !(1 == ~E_11~0); 23491#L1464-1 assume !(1 == ~E_12~0); 23310#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 22682#L1810 [2024-11-17 08:53:06,911 INFO L747 eck$LassoCheckResult]: Loop: 22682#L1810 assume true; 22417#L1810-1 assume !false; 22418#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22594#L998 assume true; 22595#L998-1 assume !false; 23837#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 23771#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 23295#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 23513#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 23688#L1003 assume !(0 != eval_~tmp~0#1); 23923#L1006 assume true; 23884#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22616#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22617#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 23050#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23584#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23619#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23620#L1221 assume !(0 == ~T4_E~0); 22342#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22343#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23353#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22287#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22288#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23469#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23784#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23850#L1261 assume !(0 == ~T12_E~0); 23673#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 23674#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 23519#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 23100#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 23101#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 24048#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 24027#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 23387#L1301 assume !(0 == ~E_7~0); 22637#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 22638#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 23530#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 23553#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 23817#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 23818#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23715#L593-1 assume 1 == ~m_pc~0; 22746#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22748#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23373#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22714#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22715#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23073#L612-1 assume 1 == ~t1_pc~0; 23074#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23742#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24013#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24005#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23129#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23130#L631-1 assume 1 == ~t2_pc~0; 22727#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22311#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22312#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23921#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23823#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23753#L650-1 assume 1 == ~t3_pc~0; 23754#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23922#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23021#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23022#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23088#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22284#L669-1 assume 1 == ~t4_pc~0; 22285#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22833#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22877#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22878#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23659#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23564#L688-1 assume !(1 == ~t5_pc~0); 22387#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 22388#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22801#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22802#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22435#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22436#L707-1 assume 1 == ~t6_pc~0; 23140#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22777#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22764#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22765#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 24016#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24014#L726-1 assume !(1 == ~t7_pc~0); 23346#L736-1 is_transmit7_triggered_~__retres1~7#1 := 0; 23167#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23168#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23314#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23315#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22301#L745-1 assume 1 == ~t8_pc~0; 22302#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22809#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23911#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22724#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22725#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22903#L764-1 assume 1 == ~t9_pc~0; 23069#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23947#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23748#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23749#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 23860#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23993#L783-1 assume 1 == ~t10_pc~0; 23994#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22734#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23633#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23975#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23799#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23800#L802-1 assume !(1 == ~t11_pc~0); 23537#L812-1 is_transmit11_triggered_~__retres1~11#1 := 0; 23378#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23379#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23019#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 23020#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 23435#L821-1 assume 1 == ~t12_pc~0; 23436#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 22676#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22677#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23592#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23593#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23576#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 23081#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23082#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22369#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22370#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22904#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22905#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23483#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22432#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22433#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22336#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22337#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22837#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22838#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 22340#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 22341#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 23399#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 23400#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 23729#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 23906#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 23985#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 22915#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 22916#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 22609#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 22610#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 23660#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 23780#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 23234#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22425#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22698#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 22699#L1829 assume !(0 == start_simulation_~tmp~3#1); 23063#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 23064#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 22356#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 22952#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 22953#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23520#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23209#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 22681#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 22682#L1810 [2024-11-17 08:53:06,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,911 INFO L85 PathProgramCache]: Analyzing trace with hash -45522418, now seen corresponding path program 1 times [2024-11-17 08:53:06,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1044952567] [2024-11-17 08:53:06,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,939 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1044952567] [2024-11-17 08:53:06,940 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1044952567] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,940 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,940 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:06,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1065576985] [2024-11-17 08:53:06,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,940 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:06,941 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:06,941 INFO L85 PathProgramCache]: Analyzing trace with hash -405970601, now seen corresponding path program 2 times [2024-11-17 08:53:06,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:06,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448998902] [2024-11-17 08:53:06,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:06,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:06,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:06,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:06,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:06,994 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1448998902] [2024-11-17 08:53:06,994 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1448998902] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:06,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:06,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:06,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [913626692] [2024-11-17 08:53:06,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:06,995 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:06,995 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:06,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:06,996 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:06,996 INFO L87 Difference]: Start difference. First operand 1844 states and 2701 transitions. cyclomatic complexity: 858 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:07,048 INFO L93 Difference]: Finished difference Result 1844 states and 2700 transitions. [2024-11-17 08:53:07,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2700 transitions. [2024-11-17 08:53:07,053 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,058 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2700 transitions. [2024-11-17 08:53:07,058 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:07,059 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:07,059 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2700 transitions. [2024-11-17 08:53:07,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:07,061 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2700 transitions. [2024-11-17 08:53:07,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2700 transitions. [2024-11-17 08:53:07,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:07,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4642082429501084) internal successors, (2700), 1843 states have internal predecessors, (2700), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2700 transitions. [2024-11-17 08:53:07,080 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2700 transitions. [2024-11-17 08:53:07,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:07,081 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2700 transitions. [2024-11-17 08:53:07,081 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:53:07,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2700 transitions. [2024-11-17 08:53:07,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:07,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:07,086 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,086 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,086 INFO L745 eck$LassoCheckResult]: Stem: 26795#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 26796#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 26234#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26235#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27673#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 27549#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27550#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27610#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27611#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27731#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26251#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26252#L883 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27280#L888 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27365#L893 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 26923#L898 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26350#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26351#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 26709#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27716#L1201-1 assume !(0 == ~M_E~0); 27717#L1206-1 assume !(0 == ~T1_E~0); 27543#L1211-1 assume !(0 == ~T2_E~0); 27544#L1216-1 assume !(0 == ~T3_E~0); 26524#L1221-1 assume !(0 == ~T4_E~0); 26525#L1226-1 assume !(0 == ~T5_E~0); 26143#L1231-1 assume !(0 == ~T6_E~0); 26144#L1236-1 assume !(0 == ~T7_E~0); 27592#L1241-1 assume !(0 == ~T8_E~0); 26570#L1246-1 assume !(0 == ~T9_E~0); 26571#L1251-1 assume !(0 == ~T10_E~0); 26744#L1256-1 assume !(0 == ~T11_E~0); 25918#L1261-1 assume !(0 == ~T12_E~0); 25919#L1266-1 assume !(0 == ~E_M~0); 27721#L1271-1 assume !(0 == ~E_1~0); 27292#L1276-1 assume !(0 == ~E_2~0); 27293#L1281-1 assume !(0 == ~E_3~0); 27255#L1286-1 assume !(0 == ~E_4~0); 26413#L1291-1 assume !(0 == ~E_5~0); 26414#L1296-1 assume !(0 == ~E_6~0); 27073#L1301-1 assume !(0 == ~E_7~0); 27074#L1306-1 assume !(0 == ~E_8~0); 27484#L1311-1 assume !(0 == ~E_9~0); 26365#L1316-1 assume !(0 == ~E_10~0); 26366#L1321-1 assume !(0 == ~E_11~0); 27088#L1326-1 assume !(0 == ~E_12~0); 27089#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27187#L593-15 assume 1 == ~m_pc~0; 27135#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26402#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26403#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27017#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 27018#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27052#L612-15 assume 1 == ~t1_pc~0; 27265#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26440#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27169#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27725#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 26041#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26042#L631-15 assume 1 == ~t2_pc~0; 27124#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27212#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27213#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26208#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 26209#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27482#L650-15 assume 1 == ~t3_pc~0; 26390#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26391#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27513#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26404#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 26405#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27163#L669-15 assume 1 == ~t4_pc~0; 27164#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26764#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26765#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27430#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 27068#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27069#L688-15 assume 1 == ~t5_pc~0; 26925#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26926#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26890#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26753#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 26754#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27300#L707-15 assume 1 == ~t6_pc~0; 27301#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26807#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26808#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27148#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 27149#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27284#L726-15 assume 1 == ~t7_pc~0; 27685#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27186#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27226#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27347#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 27348#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27522#L745-15 assume 1 == ~t8_pc~0; 27704#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26255#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26256#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26217#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 26218#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26399#L764-15 assume 1 == ~t9_pc~0; 26400#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27473#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27653#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27654#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 27661#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26029#L783-15 assume 1 == ~t10_pc~0; 26030#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27296#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26552#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26553#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 27061#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26094#L802-15 assume 1 == ~t11_pc~0; 26095#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26354#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27498#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 27664#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 27663#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27306#L821-15 assume 1 == ~t12_pc~0; 27307#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27419#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26942#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26057#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 26058#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26871#L1339-1 assume !(1 == ~M_E~0); 27646#L1344-1 assume !(1 == ~T1_E~0); 27647#L1349-1 assume !(1 == ~T2_E~0); 27081#L1354-1 assume !(1 == ~T3_E~0); 27082#L1359-1 assume !(1 == ~T4_E~0); 27429#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26459#L1369-1 assume !(1 == ~T6_E~0); 26460#L1374-1 assume !(1 == ~T7_E~0); 27086#L1379-1 assume !(1 == ~T8_E~0); 27087#L1384-1 assume !(1 == ~T9_E~0); 27157#L1389-1 assume !(1 == ~T10_E~0); 27596#L1394-1 assume !(1 == ~T11_E~0); 27597#L1399-1 assume !(1 == ~T12_E~0); 27693#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 26574#L1409-1 assume !(1 == ~E_1~0); 26575#L1414-1 assume !(1 == ~E_2~0); 27314#L1419-1 assume !(1 == ~E_3~0); 26193#L1424-1 assume !(1 == ~E_4~0); 26194#L1429-1 assume !(1 == ~E_5~0); 27094#L1434-1 assume !(1 == ~E_6~0); 27616#L1439-1 assume !(1 == ~E_7~0); 26229#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 26230#L1449-1 assume !(1 == ~E_9~0); 26637#L1454-1 assume !(1 == ~E_10~0); 26638#L1459-1 assume !(1 == ~E_11~0); 27189#L1464-1 assume !(1 == ~E_12~0); 27007#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 26379#L1810 [2024-11-17 08:53:07,087 INFO L747 eck$LassoCheckResult]: Loop: 26379#L1810 assume true; 26114#L1810-1 assume !false; 26115#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26291#L998 assume true; 26292#L998-1 assume !false; 27534#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 27468#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26992#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 27211#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 27385#L1003 assume !(0 != eval_~tmp~0#1); 27620#L1006 assume true; 27581#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26313#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26314#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 26747#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27281#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27316#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27317#L1221 assume !(0 == ~T4_E~0); 26039#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26040#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27050#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25984#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25985#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27166#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27481#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 27548#L1261 assume !(0 == ~T12_E~0); 27370#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 27371#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 27216#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 26797#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 26798#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 27745#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 27724#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 27084#L1301 assume !(0 == ~E_7~0); 26334#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 26335#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 27227#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 27250#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 27514#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 27515#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27412#L593-1 assume 1 == ~m_pc~0; 26443#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26445#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27070#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26411#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 26412#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26770#L612-1 assume 1 == ~t1_pc~0; 26771#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27439#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27710#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27702#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26823#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26824#L631-1 assume 1 == ~t2_pc~0; 26424#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26008#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26009#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27618#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 27520#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27450#L650-1 assume 1 == ~t3_pc~0; 27451#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27619#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26718#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26719#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26785#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25981#L669-1 assume 1 == ~t4_pc~0; 25982#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26530#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26572#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26573#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27356#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27259#L688-1 assume !(1 == ~t5_pc~0); 26084#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 26085#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26498#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26499#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26132#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26133#L707-1 assume 1 == ~t6_pc~0; 26837#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26474#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26461#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26462#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27713#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27711#L726-1 assume 1 == ~t7_pc~0; 27712#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26864#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26865#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 27011#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27012#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25998#L745-1 assume !(1 == ~t8_pc~0); 26000#L755-1 is_transmit8_triggered_~__retres1~8#1 := 0; 26506#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27608#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26421#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26422#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26598#L764-1 assume 1 == ~t9_pc~0; 26766#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 27644#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27445#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27446#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27557#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27690#L783-1 assume 1 == ~t10_pc~0; 27691#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26431#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27330#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27672#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27496#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27497#L802-1 assume !(1 == ~t11_pc~0); 27234#L812-1 is_transmit11_triggered_~__retres1~11#1 := 0; 27075#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27076#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26716#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26717#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27132#L821-1 assume 1 == ~t12_pc~0; 27133#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 26373#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26374#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 27289#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27290#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27273#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 26778#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26779#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26066#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26067#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26601#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26602#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27178#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26129#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26130#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26033#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26034#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26532#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26533#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 26037#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 26038#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 27096#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 27097#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 27426#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 27603#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 27682#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 26612#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 26613#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 26306#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 26307#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 27357#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 27477#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26931#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26122#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26395#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 26396#L1829 assume !(0 == start_simulation_~tmp~3#1); 26760#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 26761#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 26053#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 26649#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26650#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27217#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26906#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 26378#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 26379#L1810 [2024-11-17 08:53:07,087 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,088 INFO L85 PathProgramCache]: Analyzing trace with hash 1896656047, now seen corresponding path program 1 times [2024-11-17 08:53:07,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,088 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479209584] [2024-11-17 08:53:07,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,117 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,117 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [479209584] [2024-11-17 08:53:07,117 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [479209584] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,117 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,118 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:07,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1666658360] [2024-11-17 08:53:07,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,118 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:07,118 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,119 INFO L85 PathProgramCache]: Analyzing trace with hash -1586053225, now seen corresponding path program 1 times [2024-11-17 08:53:07,119 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,119 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475617661] [2024-11-17 08:53:07,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475617661] [2024-11-17 08:53:07,171 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475617661] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,171 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:07,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1334440843] [2024-11-17 08:53:07,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,171 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:07,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:07,172 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:07,172 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:07,172 INFO L87 Difference]: Start difference. First operand 1844 states and 2700 transitions. cyclomatic complexity: 857 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:07,192 INFO L93 Difference]: Finished difference Result 1844 states and 2699 transitions. [2024-11-17 08:53:07,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2699 transitions. [2024-11-17 08:53:07,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2699 transitions. [2024-11-17 08:53:07,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:07,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:07,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2699 transitions. [2024-11-17 08:53:07,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:07,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2699 transitions. [2024-11-17 08:53:07,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2699 transitions. [2024-11-17 08:53:07,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:07,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4636659436008677) internal successors, (2699), 1843 states have internal predecessors, (2699), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2699 transitions. [2024-11-17 08:53:07,225 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2699 transitions. [2024-11-17 08:53:07,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:07,229 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2699 transitions. [2024-11-17 08:53:07,229 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:53:07,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2699 transitions. [2024-11-17 08:53:07,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:07,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:07,235 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,235 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,236 INFO L745 eck$LassoCheckResult]: Stem: 30492#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 30493#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 29931#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29932#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31370#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 31246#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31247#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31307#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31308#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31428#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29948#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29949#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30977#L888 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31062#L893 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 30620#L898 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30047#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 30048#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 30406#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31413#L1201-1 assume !(0 == ~M_E~0); 31414#L1206-1 assume !(0 == ~T1_E~0); 31240#L1211-1 assume !(0 == ~T2_E~0); 31241#L1216-1 assume !(0 == ~T3_E~0); 30221#L1221-1 assume !(0 == ~T4_E~0); 30222#L1226-1 assume !(0 == ~T5_E~0); 29840#L1231-1 assume !(0 == ~T6_E~0); 29841#L1236-1 assume !(0 == ~T7_E~0); 31289#L1241-1 assume !(0 == ~T8_E~0); 30267#L1246-1 assume !(0 == ~T9_E~0); 30268#L1251-1 assume !(0 == ~T10_E~0); 30441#L1256-1 assume !(0 == ~T11_E~0); 29615#L1261-1 assume !(0 == ~T12_E~0); 29616#L1266-1 assume !(0 == ~E_M~0); 31418#L1271-1 assume !(0 == ~E_1~0); 30989#L1276-1 assume !(0 == ~E_2~0); 30990#L1281-1 assume !(0 == ~E_3~0); 30952#L1286-1 assume !(0 == ~E_4~0); 30110#L1291-1 assume !(0 == ~E_5~0); 30111#L1296-1 assume !(0 == ~E_6~0); 30770#L1301-1 assume !(0 == ~E_7~0); 30771#L1306-1 assume !(0 == ~E_8~0); 31181#L1311-1 assume !(0 == ~E_9~0); 30062#L1316-1 assume !(0 == ~E_10~0); 30063#L1321-1 assume !(0 == ~E_11~0); 30785#L1326-1 assume !(0 == ~E_12~0); 30786#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30884#L593-15 assume 1 == ~m_pc~0; 30832#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30099#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30100#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30714#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 30715#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30749#L612-15 assume 1 == ~t1_pc~0; 30962#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30137#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30866#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31422#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 29738#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29739#L631-15 assume 1 == ~t2_pc~0; 30821#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30909#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30910#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29905#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 29906#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31179#L650-15 assume 1 == ~t3_pc~0; 30087#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30088#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31210#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30101#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 30102#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30860#L669-15 assume 1 == ~t4_pc~0; 30861#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30461#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30462#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31127#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 30765#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30766#L688-15 assume 1 == ~t5_pc~0; 30621#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30622#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30587#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30450#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 30451#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30997#L707-15 assume 1 == ~t6_pc~0; 30998#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30504#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30505#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30845#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 30846#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30981#L726-15 assume 1 == ~t7_pc~0; 31382#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30883#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30923#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31044#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 31045#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31219#L745-15 assume 1 == ~t8_pc~0; 31401#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29952#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29953#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29914#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 29915#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30096#L764-15 assume 1 == ~t9_pc~0; 30097#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31170#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31350#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31351#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 31358#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29726#L783-15 assume 1 == ~t10_pc~0; 29727#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30993#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30249#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30250#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 30758#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29791#L802-15 assume 1 == ~t11_pc~0; 29792#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30051#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31195#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31361#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 31360#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31003#L821-15 assume 1 == ~t12_pc~0; 31004#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31116#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30639#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29752#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 29753#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30568#L1339-1 assume !(1 == ~M_E~0); 31343#L1344-1 assume !(1 == ~T1_E~0); 31344#L1349-1 assume !(1 == ~T2_E~0); 30778#L1354-1 assume !(1 == ~T3_E~0); 30779#L1359-1 assume !(1 == ~T4_E~0); 31125#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30156#L1369-1 assume !(1 == ~T6_E~0); 30157#L1374-1 assume !(1 == ~T7_E~0); 30783#L1379-1 assume !(1 == ~T8_E~0); 30784#L1384-1 assume !(1 == ~T9_E~0); 30853#L1389-1 assume !(1 == ~T10_E~0); 31293#L1394-1 assume !(1 == ~T11_E~0); 31294#L1399-1 assume !(1 == ~T12_E~0); 31390#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 30271#L1409-1 assume !(1 == ~E_1~0); 30272#L1414-1 assume !(1 == ~E_2~0); 31011#L1419-1 assume !(1 == ~E_3~0); 29890#L1424-1 assume !(1 == ~E_4~0); 29891#L1429-1 assume !(1 == ~E_5~0); 30791#L1434-1 assume !(1 == ~E_6~0); 31313#L1439-1 assume !(1 == ~E_7~0); 29926#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 29927#L1449-1 assume !(1 == ~E_9~0); 30334#L1454-1 assume !(1 == ~E_10~0); 30335#L1459-1 assume !(1 == ~E_11~0); 30886#L1464-1 assume !(1 == ~E_12~0); 30704#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 30076#L1810 [2024-11-17 08:53:07,236 INFO L747 eck$LassoCheckResult]: Loop: 30076#L1810 assume true; 29811#L1810-1 assume !false; 29812#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29988#L998 assume true; 29989#L998-1 assume !false; 31231#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 31165#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 30689#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30908#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 31082#L1003 assume !(0 != eval_~tmp~0#1); 31317#L1006 assume true; 31278#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30010#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30011#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 30444#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30978#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31013#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31014#L1221 assume !(0 == ~T4_E~0); 29736#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29737#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30747#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29681#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29682#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30863#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31178#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 31245#L1261 assume !(0 == ~T12_E~0); 31067#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 31068#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 30913#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 30494#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 30495#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 31442#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 31421#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 30781#L1301 assume !(0 == ~E_7~0); 30031#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 30032#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 30924#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 30947#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 31212#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 31213#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31109#L593-1 assume 1 == ~m_pc~0; 30140#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 30142#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30767#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30108#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30109#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30467#L612-1 assume 1 == ~t1_pc~0; 30468#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31136#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31409#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31399#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30523#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30524#L631-1 assume 1 == ~t2_pc~0; 30121#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29705#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29706#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31315#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31217#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31147#L650-1 assume 1 == ~t3_pc~0; 31148#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31316#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30415#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30416#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30482#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29678#L669-1 assume !(1 == ~t4_pc~0); 29680#L679-1 is_transmit4_triggered_~__retres1~4#1 := 0; 30227#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30269#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30270#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31053#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30956#L688-1 assume !(1 == ~t5_pc~0); 29779#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 29780#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30195#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30196#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29829#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29830#L707-1 assume 1 == ~t6_pc~0; 30534#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30171#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30158#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30159#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31410#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31407#L726-1 assume 1 == ~t7_pc~0; 31408#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30561#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30562#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30708#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30709#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29695#L745-1 assume 1 == ~t8_pc~0; 29696#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30203#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31305#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30118#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30119#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30295#L764-1 assume !(1 == ~t9_pc~0); 30464#L774-1 is_transmit9_triggered_~__retres1~9#1 := 0; 31341#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31142#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31143#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31254#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31387#L783-1 assume 1 == ~t10_pc~0; 31388#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30128#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31027#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31369#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31192#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31193#L802-1 assume 1 == ~t11_pc~0; 31088#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30772#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30773#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30413#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 30414#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 30829#L821-1 assume 1 == ~t12_pc~0; 30830#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 30070#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30071#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30985#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30986#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30970#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 30475#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30476#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29763#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29764#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30298#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30299#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30875#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29826#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29827#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29730#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29731#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30229#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30230#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 29734#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 29735#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 30793#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 30794#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 31123#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 31300#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 31379#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 30309#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 30310#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 30003#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 30004#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 31054#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 31174#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30628#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29819#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30092#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 30093#L1829 assume !(0 == start_simulation_~tmp~3#1); 30457#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 30458#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 29750#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 30346#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 30347#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30914#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30603#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 30075#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 30076#L1810 [2024-11-17 08:53:07,237 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,237 INFO L85 PathProgramCache]: Analyzing trace with hash -1504376338, now seen corresponding path program 1 times [2024-11-17 08:53:07,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1421390573] [2024-11-17 08:53:07,237 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,271 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1421390573] [2024-11-17 08:53:07,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1421390573] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,271 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:07,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1048531061] [2024-11-17 08:53:07,271 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,272 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:07,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,272 INFO L85 PathProgramCache]: Analyzing trace with hash 993671703, now seen corresponding path program 1 times [2024-11-17 08:53:07,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000576971] [2024-11-17 08:53:07,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1000576971] [2024-11-17 08:53:07,329 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1000576971] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,329 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,329 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:07,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360467858] [2024-11-17 08:53:07,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,329 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:07,330 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:07,330 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:07,330 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:07,330 INFO L87 Difference]: Start difference. First operand 1844 states and 2699 transitions. cyclomatic complexity: 856 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:07,349 INFO L93 Difference]: Finished difference Result 1844 states and 2698 transitions. [2024-11-17 08:53:07,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2698 transitions. [2024-11-17 08:53:07,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2698 transitions. [2024-11-17 08:53:07,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:07,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:07,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2698 transitions. [2024-11-17 08:53:07,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:07,361 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2698 transitions. [2024-11-17 08:53:07,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2698 transitions. [2024-11-17 08:53:07,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:07,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4631236442516269) internal successors, (2698), 1843 states have internal predecessors, (2698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2698 transitions. [2024-11-17 08:53:07,381 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2698 transitions. [2024-11-17 08:53:07,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:07,382 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2698 transitions. [2024-11-17 08:53:07,382 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:53:07,382 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2698 transitions. [2024-11-17 08:53:07,386 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:07,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:07,387 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,387 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,387 INFO L745 eck$LassoCheckResult]: Stem: 34189#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 34190#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 33628#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33629#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35067#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 34943#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34944#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35003#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35004#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35125#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33645#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33646#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34674#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34759#L893 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 34317#L898 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33744#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33745#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 34103#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35110#L1201-1 assume !(0 == ~M_E~0); 35111#L1206-1 assume !(0 == ~T1_E~0); 34937#L1211-1 assume !(0 == ~T2_E~0); 34938#L1216-1 assume !(0 == ~T3_E~0); 33918#L1221-1 assume !(0 == ~T4_E~0); 33919#L1226-1 assume !(0 == ~T5_E~0); 33537#L1231-1 assume !(0 == ~T6_E~0); 33538#L1236-1 assume !(0 == ~T7_E~0); 34986#L1241-1 assume !(0 == ~T8_E~0); 33962#L1246-1 assume !(0 == ~T9_E~0); 33963#L1251-1 assume !(0 == ~T10_E~0); 34138#L1256-1 assume !(0 == ~T11_E~0); 33312#L1261-1 assume !(0 == ~T12_E~0); 33313#L1266-1 assume !(0 == ~E_M~0); 35115#L1271-1 assume !(0 == ~E_1~0); 34686#L1276-1 assume !(0 == ~E_2~0); 34687#L1281-1 assume !(0 == ~E_3~0); 34649#L1286-1 assume !(0 == ~E_4~0); 33807#L1291-1 assume !(0 == ~E_5~0); 33808#L1296-1 assume !(0 == ~E_6~0); 34467#L1301-1 assume !(0 == ~E_7~0); 34468#L1306-1 assume !(0 == ~E_8~0); 34877#L1311-1 assume !(0 == ~E_9~0); 33759#L1316-1 assume !(0 == ~E_10~0); 33760#L1321-1 assume !(0 == ~E_11~0); 34482#L1326-1 assume !(0 == ~E_12~0); 34483#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34581#L593-15 assume 1 == ~m_pc~0; 34529#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33796#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33797#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34411#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 34412#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34446#L612-15 assume 1 == ~t1_pc~0; 34659#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33834#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34563#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35119#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 33435#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33436#L631-15 assume 1 == ~t2_pc~0; 34518#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 34606#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34607#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33602#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 33603#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34876#L650-15 assume 1 == ~t3_pc~0; 33784#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33785#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34907#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33798#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 33799#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34557#L669-15 assume 1 == ~t4_pc~0; 34558#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34158#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34159#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34824#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 34462#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34463#L688-15 assume 1 == ~t5_pc~0; 34318#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34319#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34284#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34147#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 34148#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34694#L707-15 assume 1 == ~t6_pc~0; 34695#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34201#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34202#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34542#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 34543#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34678#L726-15 assume 1 == ~t7_pc~0; 35079#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34580#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34620#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34741#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 34742#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34916#L745-15 assume 1 == ~t8_pc~0; 35098#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33649#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33650#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33611#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 33612#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33793#L764-15 assume 1 == ~t9_pc~0; 33794#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34867#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35046#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35047#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 35055#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33423#L783-15 assume 1 == ~t10_pc~0; 33424#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34690#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33946#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33947#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 34455#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 33488#L802-15 assume 1 == ~t11_pc~0; 33489#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33748#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34892#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35058#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 35057#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34700#L821-15 assume 1 == ~t12_pc~0; 34701#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 34813#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34336#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 33449#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 33450#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34265#L1339-1 assume !(1 == ~M_E~0); 35040#L1344-1 assume !(1 == ~T1_E~0); 35041#L1349-1 assume !(1 == ~T2_E~0); 34475#L1354-1 assume !(1 == ~T3_E~0); 34476#L1359-1 assume !(1 == ~T4_E~0); 34822#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33853#L1369-1 assume !(1 == ~T6_E~0); 33854#L1374-1 assume !(1 == ~T7_E~0); 34480#L1379-1 assume !(1 == ~T8_E~0); 34481#L1384-1 assume !(1 == ~T9_E~0); 34550#L1389-1 assume !(1 == ~T10_E~0); 34990#L1394-1 assume !(1 == ~T11_E~0); 34991#L1399-1 assume !(1 == ~T12_E~0); 35087#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 33966#L1409-1 assume !(1 == ~E_1~0); 33967#L1414-1 assume !(1 == ~E_2~0); 34708#L1419-1 assume !(1 == ~E_3~0); 33587#L1424-1 assume !(1 == ~E_4~0); 33588#L1429-1 assume !(1 == ~E_5~0); 34488#L1434-1 assume !(1 == ~E_6~0); 35010#L1439-1 assume !(1 == ~E_7~0); 33623#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 33624#L1449-1 assume !(1 == ~E_9~0); 34031#L1454-1 assume !(1 == ~E_10~0); 34032#L1459-1 assume !(1 == ~E_11~0); 34583#L1464-1 assume !(1 == ~E_12~0); 34401#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 33773#L1810 [2024-11-17 08:53:07,388 INFO L747 eck$LassoCheckResult]: Loop: 33773#L1810 assume true; 33508#L1810-1 assume !false; 33509#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33685#L998 assume true; 33686#L998-1 assume !false; 34928#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34862#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 34386#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34605#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 34779#L1003 assume !(0 != eval_~tmp~0#1); 35014#L1006 assume true; 34975#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33707#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33708#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 34141#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34675#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34710#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34711#L1221 assume !(0 == ~T4_E~0); 33433#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33434#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34444#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33378#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33379#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34560#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34875#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34942#L1261 assume !(0 == ~T12_E~0); 34764#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 34765#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 34610#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 34191#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 34192#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 35139#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 35118#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 34478#L1301 assume !(0 == ~E_7~0); 33728#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 33729#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 34621#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 34644#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 34908#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 34909#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34806#L593-1 assume 1 == ~m_pc~0; 33837#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33839#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34464#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33805#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33806#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34164#L612-1 assume 1 == ~t1_pc~0; 34165#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34833#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35106#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35096#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34220#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34221#L631-1 assume 1 == ~t2_pc~0; 33818#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 33402#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33403#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35012#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34914#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34844#L650-1 assume 1 == ~t3_pc~0; 34845#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35013#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34112#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34113#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34179#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33375#L669-1 assume 1 == ~t4_pc~0; 33376#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33924#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33968#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33969#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34750#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34655#L688-1 assume !(1 == ~t5_pc~0); 33478#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 33479#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33893#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33894#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33526#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33527#L707-1 assume 1 == ~t6_pc~0; 34231#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33868#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33855#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33856#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35107#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35104#L726-1 assume 1 == ~t7_pc~0; 35105#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34258#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34259#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34405#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34406#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33392#L745-1 assume 1 == ~t8_pc~0; 33393#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33900#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35002#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33815#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33816#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33992#L764-1 assume 1 == ~t9_pc~0; 34160#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35038#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34839#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34840#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34951#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35084#L783-1 assume !(1 == ~t10_pc~0); 33824#L793-1 is_transmit10_triggered_~__retres1~10#1 := 0; 33825#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34723#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35066#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34889#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34890#L802-1 assume 1 == ~t11_pc~0; 34785#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34469#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34470#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34110#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 34111#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 34526#L821-1 assume !(1 == ~t12_pc~0); 34528#L831-1 is_transmit12_triggered_~__retres1~12#1 := 0; 33766#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33767#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34682#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34683#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34667#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 34172#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34173#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33460#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33461#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33995#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33996#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34572#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33523#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33524#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33427#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33428#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 33926#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33927#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 33431#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 33432#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 34490#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 34491#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 34820#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 34997#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 35076#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 34006#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 34007#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 33700#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 33701#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 34751#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 34871#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34324#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33516#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 33789#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 33790#L1829 assume !(0 == start_simulation_~tmp~3#1); 34154#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 34155#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 33447#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 34043#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 34044#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34611#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34300#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 33772#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 33773#L1810 [2024-11-17 08:53:07,388 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,389 INFO L85 PathProgramCache]: Analyzing trace with hash 1711048911, now seen corresponding path program 1 times [2024-11-17 08:53:07,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926412718] [2024-11-17 08:53:07,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,418 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926412718] [2024-11-17 08:53:07,419 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926412718] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,419 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,419 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:07,419 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [887961983] [2024-11-17 08:53:07,419 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,419 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:07,420 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,420 INFO L85 PathProgramCache]: Analyzing trace with hash -1061639593, now seen corresponding path program 1 times [2024-11-17 08:53:07,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [118156844] [2024-11-17 08:53:07,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,508 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [118156844] [2024-11-17 08:53:07,508 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [118156844] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,508 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,509 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:07,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1904209033] [2024-11-17 08:53:07,509 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,509 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:07,509 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:07,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:07,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:07,510 INFO L87 Difference]: Start difference. First operand 1844 states and 2698 transitions. cyclomatic complexity: 855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:07,529 INFO L93 Difference]: Finished difference Result 1844 states and 2697 transitions. [2024-11-17 08:53:07,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2697 transitions. [2024-11-17 08:53:07,534 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2697 transitions. [2024-11-17 08:53:07,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:07,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:07,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2697 transitions. [2024-11-17 08:53:07,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:07,541 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2697 transitions. [2024-11-17 08:53:07,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2697 transitions. [2024-11-17 08:53:07,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:07,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4625813449023861) internal successors, (2697), 1843 states have internal predecessors, (2697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2697 transitions. [2024-11-17 08:53:07,561 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2697 transitions. [2024-11-17 08:53:07,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:07,564 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2697 transitions. [2024-11-17 08:53:07,564 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:53:07,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2697 transitions. [2024-11-17 08:53:07,568 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:07,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:07,569 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,569 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,570 INFO L745 eck$LassoCheckResult]: Stem: 37886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 37887#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 37325#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37326#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38764#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 38640#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38641#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38700#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38701#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38822#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37342#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37343#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38371#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38456#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38014#L898 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37441#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37442#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37798#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38807#L1201-1 assume !(0 == ~M_E~0); 38808#L1206-1 assume !(0 == ~T1_E~0); 38634#L1211-1 assume !(0 == ~T2_E~0); 38635#L1216-1 assume !(0 == ~T3_E~0); 37613#L1221-1 assume !(0 == ~T4_E~0); 37614#L1226-1 assume !(0 == ~T5_E~0); 37234#L1231-1 assume !(0 == ~T6_E~0); 37235#L1236-1 assume !(0 == ~T7_E~0); 38683#L1241-1 assume !(0 == ~T8_E~0); 37659#L1246-1 assume !(0 == ~T9_E~0); 37660#L1251-1 assume !(0 == ~T10_E~0); 37835#L1256-1 assume !(0 == ~T11_E~0); 37007#L1261-1 assume !(0 == ~T12_E~0); 37008#L1266-1 assume !(0 == ~E_M~0); 38812#L1271-1 assume !(0 == ~E_1~0); 38383#L1276-1 assume !(0 == ~E_2~0); 38384#L1281-1 assume !(0 == ~E_3~0); 38346#L1286-1 assume !(0 == ~E_4~0); 37504#L1291-1 assume !(0 == ~E_5~0); 37505#L1296-1 assume !(0 == ~E_6~0); 38164#L1301-1 assume !(0 == ~E_7~0); 38165#L1306-1 assume !(0 == ~E_8~0); 38574#L1311-1 assume !(0 == ~E_9~0); 37456#L1316-1 assume !(0 == ~E_10~0); 37457#L1321-1 assume !(0 == ~E_11~0); 38179#L1326-1 assume !(0 == ~E_12~0); 38180#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38278#L593-15 assume 1 == ~m_pc~0; 38226#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37493#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37494#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38108#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 38109#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38143#L612-15 assume 1 == ~t1_pc~0; 38356#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37531#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38260#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38816#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 37132#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37133#L631-15 assume 1 == ~t2_pc~0; 38215#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38303#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38304#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37299#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 37300#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38573#L650-15 assume 1 == ~t3_pc~0; 37481#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37482#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38604#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37495#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 37496#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38254#L669-15 assume 1 == ~t4_pc~0; 38255#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37855#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37856#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38521#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 38159#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38160#L688-15 assume 1 == ~t5_pc~0; 38015#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38016#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37981#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37844#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 37845#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38391#L707-15 assume 1 == ~t6_pc~0; 38392#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37898#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37899#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38239#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 38240#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38375#L726-15 assume 1 == ~t7_pc~0; 38776#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38277#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38317#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38438#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 38439#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38613#L745-15 assume 1 == ~t8_pc~0; 38795#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37344#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37345#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37306#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 37307#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37490#L764-15 assume 1 == ~t9_pc~0; 37491#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38564#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38743#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38744#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 38752#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37120#L783-15 assume 1 == ~t10_pc~0; 37121#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38387#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37643#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37644#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 38152#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 37185#L802-15 assume 1 == ~t11_pc~0; 37186#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37445#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38589#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38755#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 38754#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38397#L821-15 assume 1 == ~t12_pc~0; 38398#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 38510#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38033#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 37146#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 37147#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37962#L1339-1 assume !(1 == ~M_E~0); 38737#L1344-1 assume !(1 == ~T1_E~0); 38738#L1349-1 assume !(1 == ~T2_E~0); 38172#L1354-1 assume !(1 == ~T3_E~0); 38173#L1359-1 assume !(1 == ~T4_E~0); 38519#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37550#L1369-1 assume !(1 == ~T6_E~0); 37551#L1374-1 assume !(1 == ~T7_E~0); 38177#L1379-1 assume !(1 == ~T8_E~0); 38178#L1384-1 assume !(1 == ~T9_E~0); 38247#L1389-1 assume !(1 == ~T10_E~0); 38687#L1394-1 assume !(1 == ~T11_E~0); 38688#L1399-1 assume !(1 == ~T12_E~0); 38784#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 37663#L1409-1 assume !(1 == ~E_1~0); 37664#L1414-1 assume !(1 == ~E_2~0); 38405#L1419-1 assume !(1 == ~E_3~0); 37284#L1424-1 assume !(1 == ~E_4~0); 37285#L1429-1 assume !(1 == ~E_5~0); 38185#L1434-1 assume !(1 == ~E_6~0); 38707#L1439-1 assume !(1 == ~E_7~0); 37320#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 37321#L1449-1 assume !(1 == ~E_9~0); 37728#L1454-1 assume !(1 == ~E_10~0); 37729#L1459-1 assume !(1 == ~E_11~0); 38279#L1464-1 assume !(1 == ~E_12~0); 38098#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 37470#L1810 [2024-11-17 08:53:07,570 INFO L747 eck$LassoCheckResult]: Loop: 37470#L1810 assume true; 37205#L1810-1 assume !false; 37206#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37382#L998 assume true; 37383#L998-1 assume !false; 38625#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38559#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 38083#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 38302#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 38476#L1003 assume !(0 != eval_~tmp~0#1); 38711#L1006 assume true; 38672#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37404#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37405#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 37838#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38372#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38407#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38408#L1221 assume !(0 == ~T4_E~0); 37130#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37131#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38141#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37075#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37076#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38257#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38572#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38638#L1261 assume !(0 == ~T12_E~0); 38461#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 38462#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 38307#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 37888#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 37889#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 38836#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 38815#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 38175#L1301 assume !(0 == ~E_7~0); 37425#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 37426#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 38318#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 38341#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 38605#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 38606#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38503#L593-1 assume 1 == ~m_pc~0; 37534#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37536#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38161#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37502#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37503#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37861#L612-1 assume 1 == ~t1_pc~0; 37862#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38530#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38801#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38793#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37917#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37918#L631-1 assume 1 == ~t2_pc~0; 37515#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37099#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37100#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38709#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38611#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38541#L650-1 assume 1 == ~t3_pc~0; 38542#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38710#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37809#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37810#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37876#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37072#L669-1 assume 1 == ~t4_pc~0; 37073#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37621#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37665#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37666#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38447#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38352#L688-1 assume !(1 == ~t5_pc~0); 37175#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 37176#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37589#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37590#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37223#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37224#L707-1 assume 1 == ~t6_pc~0; 37928#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37565#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37552#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37553#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38804#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38802#L726-1 assume 1 == ~t7_pc~0; 38803#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37955#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37956#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38102#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38103#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37089#L745-1 assume 1 == ~t8_pc~0; 37090#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37597#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38699#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37512#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37513#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37691#L764-1 assume 1 == ~t9_pc~0; 37857#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38735#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38536#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38537#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38648#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38781#L783-1 assume !(1 == ~t10_pc~0); 37521#L793-1 is_transmit10_triggered_~__retres1~10#1 := 0; 37522#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38421#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38763#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38587#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38588#L802-1 assume 1 == ~t11_pc~0; 38482#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38166#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38167#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37807#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37808#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38223#L821-1 assume 1 == ~t12_pc~0; 38224#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37464#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37465#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38380#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 38381#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38364#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 37869#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37870#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37157#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37158#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37692#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37693#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38271#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37220#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37221#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37124#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37125#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37625#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37626#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 37128#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 37129#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 38187#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 38188#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 38517#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 38694#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 38773#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 37703#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 37704#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 37397#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 37398#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 38448#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 38568#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 38023#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37213#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37488#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 37489#L1829 assume !(0 == start_simulation_~tmp~3#1); 37851#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 37852#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 37144#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 37740#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 37741#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38308#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37996#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 37469#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 37470#L1810 [2024-11-17 08:53:07,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,571 INFO L85 PathProgramCache]: Analyzing trace with hash 1676224974, now seen corresponding path program 1 times [2024-11-17 08:53:07,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675014816] [2024-11-17 08:53:07,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,602 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1675014816] [2024-11-17 08:53:07,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1675014816] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,603 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:07,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974005642] [2024-11-17 08:53:07,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,603 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:07,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,604 INFO L85 PathProgramCache]: Analyzing trace with hash -1410286956, now seen corresponding path program 1 times [2024-11-17 08:53:07,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901956980] [2024-11-17 08:53:07,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901956980] [2024-11-17 08:53:07,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [901956980] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,653 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:07,653 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1480170084] [2024-11-17 08:53:07,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,654 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:07,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:07,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:07,654 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:07,655 INFO L87 Difference]: Start difference. First operand 1844 states and 2697 transitions. cyclomatic complexity: 854 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:07,672 INFO L93 Difference]: Finished difference Result 1844 states and 2696 transitions. [2024-11-17 08:53:07,672 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2696 transitions. [2024-11-17 08:53:07,677 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2696 transitions. [2024-11-17 08:53:07,681 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:07,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:07,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2696 transitions. [2024-11-17 08:53:07,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:07,684 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2696 transitions. [2024-11-17 08:53:07,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2696 transitions. [2024-11-17 08:53:07,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:07,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4620390455531453) internal successors, (2696), 1843 states have internal predecessors, (2696), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2696 transitions. [2024-11-17 08:53:07,702 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2696 transitions. [2024-11-17 08:53:07,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:07,703 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2696 transitions. [2024-11-17 08:53:07,703 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:53:07,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2696 transitions. [2024-11-17 08:53:07,707 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:07,707 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:07,708 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,708 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,709 INFO L745 eck$LassoCheckResult]: Stem: 41583#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 41584#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 41022#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41023#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42461#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 42337#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42338#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42397#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42398#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42519#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41039#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41040#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42068#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42153#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41711#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41138#L903 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41139#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41495#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42504#L1201-1 assume !(0 == ~M_E~0); 42505#L1206-1 assume !(0 == ~T1_E~0); 42331#L1211-1 assume !(0 == ~T2_E~0); 42332#L1216-1 assume !(0 == ~T3_E~0); 41308#L1221-1 assume !(0 == ~T4_E~0); 41309#L1226-1 assume !(0 == ~T5_E~0); 40931#L1231-1 assume !(0 == ~T6_E~0); 40932#L1236-1 assume !(0 == ~T7_E~0); 42380#L1241-1 assume !(0 == ~T8_E~0); 41356#L1246-1 assume !(0 == ~T9_E~0); 41357#L1251-1 assume !(0 == ~T10_E~0); 41531#L1256-1 assume !(0 == ~T11_E~0); 40704#L1261-1 assume !(0 == ~T12_E~0); 40705#L1266-1 assume !(0 == ~E_M~0); 42509#L1271-1 assume !(0 == ~E_1~0); 42080#L1276-1 assume !(0 == ~E_2~0); 42081#L1281-1 assume !(0 == ~E_3~0); 42043#L1286-1 assume !(0 == ~E_4~0); 41201#L1291-1 assume !(0 == ~E_5~0); 41202#L1296-1 assume !(0 == ~E_6~0); 41861#L1301-1 assume !(0 == ~E_7~0); 41862#L1306-1 assume !(0 == ~E_8~0); 42271#L1311-1 assume !(0 == ~E_9~0); 41153#L1316-1 assume !(0 == ~E_10~0); 41154#L1321-1 assume !(0 == ~E_11~0); 41876#L1326-1 assume !(0 == ~E_12~0); 41877#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41975#L593-15 assume 1 == ~m_pc~0; 41923#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41190#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41191#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41805#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 41806#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41840#L612-15 assume 1 == ~t1_pc~0; 42053#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41228#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41957#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42513#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 40829#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40830#L631-15 assume 1 == ~t2_pc~0; 41912#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 42000#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42001#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40996#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 40997#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42270#L650-15 assume 1 == ~t3_pc~0; 41178#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41179#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42301#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41192#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 41193#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41951#L669-15 assume 1 == ~t4_pc~0; 41952#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41552#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41553#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42218#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 41856#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41857#L688-15 assume 1 == ~t5_pc~0; 41712#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41713#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41678#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41541#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 41542#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42088#L707-15 assume 1 == ~t6_pc~0; 42089#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41595#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41596#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41936#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 41937#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42072#L726-15 assume 1 == ~t7_pc~0; 42473#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41974#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42014#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42135#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 42136#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42310#L745-15 assume 1 == ~t8_pc~0; 42492#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41041#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41042#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41003#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 41004#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41187#L764-15 assume 1 == ~t9_pc~0; 41188#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42261#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42440#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42441#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 42449#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40817#L783-15 assume 1 == ~t10_pc~0; 40818#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42084#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41339#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41340#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 41849#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40882#L802-15 assume 1 == ~t11_pc~0; 40883#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41140#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42286#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42452#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 42451#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42094#L821-15 assume 1 == ~t12_pc~0; 42095#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 42207#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41730#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40843#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 40844#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41659#L1339-1 assume !(1 == ~M_E~0); 42434#L1344-1 assume !(1 == ~T1_E~0); 42435#L1349-1 assume !(1 == ~T2_E~0); 41869#L1354-1 assume !(1 == ~T3_E~0); 41870#L1359-1 assume !(1 == ~T4_E~0); 42216#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41247#L1369-1 assume !(1 == ~T6_E~0); 41248#L1374-1 assume !(1 == ~T7_E~0); 41874#L1379-1 assume !(1 == ~T8_E~0); 41875#L1384-1 assume !(1 == ~T9_E~0); 41944#L1389-1 assume !(1 == ~T10_E~0); 42384#L1394-1 assume !(1 == ~T11_E~0); 42385#L1399-1 assume !(1 == ~T12_E~0); 42481#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 41360#L1409-1 assume !(1 == ~E_1~0); 41361#L1414-1 assume !(1 == ~E_2~0); 42102#L1419-1 assume !(1 == ~E_3~0); 40981#L1424-1 assume !(1 == ~E_4~0); 40982#L1429-1 assume !(1 == ~E_5~0); 41882#L1434-1 assume !(1 == ~E_6~0); 42404#L1439-1 assume !(1 == ~E_7~0); 41017#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 41018#L1449-1 assume !(1 == ~E_9~0); 41425#L1454-1 assume !(1 == ~E_10~0); 41426#L1459-1 assume !(1 == ~E_11~0); 41976#L1464-1 assume !(1 == ~E_12~0); 41795#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 41167#L1810 [2024-11-17 08:53:07,709 INFO L747 eck$LassoCheckResult]: Loop: 41167#L1810 assume true; 40902#L1810-1 assume !false; 40903#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41079#L998 assume true; 41080#L998-1 assume !false; 42322#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 42256#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 41780#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41998#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 42173#L1003 assume !(0 != eval_~tmp~0#1); 42408#L1006 assume true; 42369#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41101#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41102#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 41535#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42069#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42104#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42105#L1221 assume !(0 == ~T4_E~0); 40827#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40828#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41838#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40772#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40773#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41954#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 42269#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 42335#L1261 assume !(0 == ~T12_E~0); 42158#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 42159#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 42004#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 41585#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 41586#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 42533#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 42512#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 41872#L1301 assume !(0 == ~E_7~0); 41122#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 41123#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 42015#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 42038#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 42302#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 42303#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42200#L593-1 assume !(1 == ~m_pc~0); 41232#L603-1 is_master_triggered_~__retres1~0#1 := 0; 41233#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41858#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41199#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41200#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41558#L612-1 assume 1 == ~t1_pc~0; 41559#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42227#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42498#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42490#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41614#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41615#L631-1 assume 1 == ~t2_pc~0; 41212#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40796#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40797#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42406#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42308#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42238#L650-1 assume !(1 == ~t3_pc~0); 42240#L660-1 is_transmit3_triggered_~__retres1~3#1 := 0; 42407#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41506#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41507#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41573#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40769#L669-1 assume 1 == ~t4_pc~0; 40770#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41318#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41362#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41363#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42144#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42049#L688-1 assume !(1 == ~t5_pc~0); 40872#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 40873#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41286#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41287#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40920#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40921#L707-1 assume 1 == ~t6_pc~0; 41625#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41262#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41249#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41250#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42501#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42499#L726-1 assume 1 == ~t7_pc~0; 42500#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41652#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41653#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41799#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41800#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40786#L745-1 assume 1 == ~t8_pc~0; 40787#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41294#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42396#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41209#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41210#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41388#L764-1 assume 1 == ~t9_pc~0; 41554#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42432#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42233#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42234#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42345#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42478#L783-1 assume !(1 == ~t10_pc~0); 41218#L793-1 is_transmit10_triggered_~__retres1~10#1 := 0; 41219#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42118#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42460#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42284#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42285#L802-1 assume 1 == ~t11_pc~0; 42179#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41863#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41864#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41504#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41505#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41920#L821-1 assume 1 == ~t12_pc~0; 41921#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 41161#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41162#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42077#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42078#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42061#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 41566#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41567#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40854#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40855#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41389#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41390#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41968#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40917#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40918#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40821#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40822#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41322#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41323#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 40825#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 40826#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 41884#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 41885#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 42214#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 42391#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 42470#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 41400#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 41401#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 41094#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 41095#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 42145#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 42265#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 41719#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40910#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41183#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 41184#L1829 assume !(0 == start_simulation_~tmp~3#1); 41548#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 41549#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 40841#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 41437#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 41438#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42005#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41694#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 41166#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 41167#L1810 [2024-11-17 08:53:07,709 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,710 INFO L85 PathProgramCache]: Analyzing trace with hash -680203025, now seen corresponding path program 1 times [2024-11-17 08:53:07,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1639228410] [2024-11-17 08:53:07,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,737 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1639228410] [2024-11-17 08:53:07,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1639228410] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:07,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561282956] [2024-11-17 08:53:07,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,738 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:07,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,739 INFO L85 PathProgramCache]: Analyzing trace with hash -1664205094, now seen corresponding path program 1 times [2024-11-17 08:53:07,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [484049831] [2024-11-17 08:53:07,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,788 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [484049831] [2024-11-17 08:53:07,788 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [484049831] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,788 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,788 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:07,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947714418] [2024-11-17 08:53:07,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,788 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:07,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:07,789 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:07,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:07,790 INFO L87 Difference]: Start difference. First operand 1844 states and 2696 transitions. cyclomatic complexity: 853 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,807 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:07,807 INFO L93 Difference]: Finished difference Result 1844 states and 2695 transitions. [2024-11-17 08:53:07,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2695 transitions. [2024-11-17 08:53:07,812 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2695 transitions. [2024-11-17 08:53:07,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:07,817 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:07,817 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2695 transitions. [2024-11-17 08:53:07,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:07,818 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2695 transitions. [2024-11-17 08:53:07,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2695 transitions. [2024-11-17 08:53:07,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:07,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4614967462039046) internal successors, (2695), 1843 states have internal predecessors, (2695), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2695 transitions. [2024-11-17 08:53:07,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2695 transitions. [2024-11-17 08:53:07,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:07,864 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2695 transitions. [2024-11-17 08:53:07,864 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:53:07,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2695 transitions. [2024-11-17 08:53:07,867 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:07,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:07,869 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,869 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:07,869 INFO L745 eck$LassoCheckResult]: Stem: 45280#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 45281#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 44719#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44720#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46158#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 46034#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46035#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46094#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46095#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46216#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44736#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44737#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45765#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45850#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45408#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44835#L903 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44836#L908 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45192#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46201#L1201-1 assume !(0 == ~M_E~0); 46202#L1206-1 assume !(0 == ~T1_E~0); 46028#L1211-1 assume !(0 == ~T2_E~0); 46029#L1216-1 assume !(0 == ~T3_E~0); 45005#L1221-1 assume !(0 == ~T4_E~0); 45006#L1226-1 assume !(0 == ~T5_E~0); 44628#L1231-1 assume !(0 == ~T6_E~0); 44629#L1236-1 assume !(0 == ~T7_E~0); 46077#L1241-1 assume !(0 == ~T8_E~0); 45053#L1246-1 assume !(0 == ~T9_E~0); 45054#L1251-1 assume !(0 == ~T10_E~0); 45228#L1256-1 assume !(0 == ~T11_E~0); 44401#L1261-1 assume !(0 == ~T12_E~0); 44402#L1266-1 assume !(0 == ~E_M~0); 46206#L1271-1 assume !(0 == ~E_1~0); 45777#L1276-1 assume !(0 == ~E_2~0); 45778#L1281-1 assume !(0 == ~E_3~0); 45740#L1286-1 assume !(0 == ~E_4~0); 44898#L1291-1 assume !(0 == ~E_5~0); 44899#L1296-1 assume !(0 == ~E_6~0); 45558#L1301-1 assume !(0 == ~E_7~0); 45559#L1306-1 assume !(0 == ~E_8~0); 45968#L1311-1 assume !(0 == ~E_9~0); 44850#L1316-1 assume !(0 == ~E_10~0); 44851#L1321-1 assume !(0 == ~E_11~0); 45573#L1326-1 assume !(0 == ~E_12~0); 45574#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45672#L593-15 assume 1 == ~m_pc~0; 45620#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44887#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44888#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45502#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 45503#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45537#L612-15 assume 1 == ~t1_pc~0; 45750#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44925#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45654#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46210#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 44526#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44527#L631-15 assume 1 == ~t2_pc~0; 45609#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45697#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45698#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44693#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 44694#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45967#L650-15 assume 1 == ~t3_pc~0; 44875#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44876#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45998#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44889#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 44890#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45648#L669-15 assume 1 == ~t4_pc~0; 45649#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45249#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45250#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45915#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 45553#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45554#L688-15 assume 1 == ~t5_pc~0; 45409#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45410#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45375#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45238#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 45239#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45785#L707-15 assume 1 == ~t6_pc~0; 45786#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45292#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45293#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45633#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 45634#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45769#L726-15 assume 1 == ~t7_pc~0; 46170#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45671#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45711#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45832#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 45833#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46007#L745-15 assume 1 == ~t8_pc~0; 46189#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44738#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44739#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44700#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 44701#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44884#L764-15 assume 1 == ~t9_pc~0; 44885#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45958#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46137#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46138#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 46146#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44514#L783-15 assume 1 == ~t10_pc~0; 44515#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45781#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45036#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45037#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 45546#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44579#L802-15 assume 1 == ~t11_pc~0; 44580#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44837#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45983#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46149#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 46148#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45791#L821-15 assume 1 == ~t12_pc~0; 45792#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 45904#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45427#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44540#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 44541#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45356#L1339-1 assume !(1 == ~M_E~0); 46131#L1344-1 assume !(1 == ~T1_E~0); 46132#L1349-1 assume !(1 == ~T2_E~0); 45566#L1354-1 assume !(1 == ~T3_E~0); 45567#L1359-1 assume !(1 == ~T4_E~0); 45913#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44944#L1369-1 assume !(1 == ~T6_E~0); 44945#L1374-1 assume !(1 == ~T7_E~0); 45571#L1379-1 assume !(1 == ~T8_E~0); 45572#L1384-1 assume !(1 == ~T9_E~0); 45641#L1389-1 assume !(1 == ~T10_E~0); 46081#L1394-1 assume !(1 == ~T11_E~0); 46082#L1399-1 assume !(1 == ~T12_E~0); 46178#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 45057#L1409-1 assume !(1 == ~E_1~0); 45058#L1414-1 assume !(1 == ~E_2~0); 45799#L1419-1 assume !(1 == ~E_3~0); 44678#L1424-1 assume !(1 == ~E_4~0); 44679#L1429-1 assume !(1 == ~E_5~0); 45579#L1434-1 assume !(1 == ~E_6~0); 46101#L1439-1 assume !(1 == ~E_7~0); 44714#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 44715#L1449-1 assume !(1 == ~E_9~0); 45122#L1454-1 assume !(1 == ~E_10~0); 45123#L1459-1 assume !(1 == ~E_11~0); 45673#L1464-1 assume !(1 == ~E_12~0); 45492#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 44864#L1810 [2024-11-17 08:53:07,870 INFO L747 eck$LassoCheckResult]: Loop: 44864#L1810 assume true; 44599#L1810-1 assume !false; 44600#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44776#L998 assume true; 44777#L998-1 assume !false; 46019#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45953#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 45477#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45695#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 45870#L1003 assume !(0 != eval_~tmp~0#1); 46105#L1006 assume true; 46066#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44798#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44799#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 45232#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45766#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45801#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45802#L1221 assume !(0 == ~T4_E~0); 44524#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44525#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45535#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44469#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44470#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45651#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45966#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46032#L1261 assume !(0 == ~T12_E~0); 45855#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 45856#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 45701#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 45282#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 45283#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 46230#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 46209#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 45569#L1301 assume !(0 == ~E_7~0); 44819#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 44820#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 45712#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 45735#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 45999#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 46000#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45897#L593-1 assume 1 == ~m_pc~0; 44928#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 44930#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45555#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44896#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44897#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45255#L612-1 assume 1 == ~t1_pc~0; 45256#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45924#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46195#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46187#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45311#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45312#L631-1 assume 1 == ~t2_pc~0; 44909#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44493#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44494#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46103#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46005#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45935#L650-1 assume 1 == ~t3_pc~0; 45936#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46104#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45203#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45204#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45270#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44466#L669-1 assume 1 == ~t4_pc~0; 44467#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45015#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45059#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45060#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45841#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45746#L688-1 assume !(1 == ~t5_pc~0); 44569#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 44570#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44983#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44984#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 44617#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 44618#L707-1 assume 1 == ~t6_pc~0; 45322#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 44959#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 44946#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44947#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46198#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46196#L726-1 assume 1 == ~t7_pc~0; 46197#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45349#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45350#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45496#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45497#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 44483#L745-1 assume 1 == ~t8_pc~0; 44484#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44991#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46093#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44906#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44907#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45085#L764-1 assume 1 == ~t9_pc~0; 45251#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46129#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45930#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45931#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46042#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46175#L783-1 assume 1 == ~t10_pc~0; 46176#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44916#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45815#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46157#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45981#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45982#L802-1 assume 1 == ~t11_pc~0; 45876#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 45560#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45561#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45201#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45202#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45617#L821-1 assume 1 == ~t12_pc~0; 45618#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44858#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44859#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 45774#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 45775#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45758#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 45263#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45264#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44551#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44552#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45086#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 45087#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45665#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44614#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44615#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44518#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44519#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45019#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45020#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 44522#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 44523#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 45581#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 45582#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 45911#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 46088#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 46167#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 45097#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 45098#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 44791#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 44792#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 45842#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 45962#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45416#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44607#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 44880#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 44881#L1829 assume !(0 == start_simulation_~tmp~3#1); 45245#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 45246#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 44538#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 45134#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 45135#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45702#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 45391#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 44863#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 44864#L1810 [2024-11-17 08:53:07,870 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,870 INFO L85 PathProgramCache]: Analyzing trace with hash 767803822, now seen corresponding path program 1 times [2024-11-17 08:53:07,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988306232] [2024-11-17 08:53:07,870 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,898 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988306232] [2024-11-17 08:53:07,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [988306232] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:07,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [966237605] [2024-11-17 08:53:07,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,899 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:07,899 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:07,899 INFO L85 PathProgramCache]: Analyzing trace with hash -2000070831, now seen corresponding path program 1 times [2024-11-17 08:53:07,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:07,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145349517] [2024-11-17 08:53:07,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:07,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:07,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:07,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:07,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:07,948 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145349517] [2024-11-17 08:53:07,948 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2145349517] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:07,948 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:07,949 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:07,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942208607] [2024-11-17 08:53:07,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:07,949 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:07,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:07,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:07,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:07,949 INFO L87 Difference]: Start difference. First operand 1844 states and 2695 transitions. cyclomatic complexity: 852 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:07,968 INFO L93 Difference]: Finished difference Result 1844 states and 2694 transitions. [2024-11-17 08:53:07,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1844 states and 2694 transitions. [2024-11-17 08:53:07,972 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:07,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1844 states to 1844 states and 2694 transitions. [2024-11-17 08:53:07,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1844 [2024-11-17 08:53:07,977 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1844 [2024-11-17 08:53:07,977 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1844 states and 2694 transitions. [2024-11-17 08:53:07,979 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:07,979 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2694 transitions. [2024-11-17 08:53:07,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1844 states and 2694 transitions. [2024-11-17 08:53:07,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1844 to 1844. [2024-11-17 08:53:07,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1844 states, 1844 states have (on average 1.4609544468546638) internal successors, (2694), 1843 states have internal predecessors, (2694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:07,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1844 states to 1844 states and 2694 transitions. [2024-11-17 08:53:07,996 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1844 states and 2694 transitions. [2024-11-17 08:53:07,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:07,997 INFO L425 stractBuchiCegarLoop]: Abstraction has 1844 states and 2694 transitions. [2024-11-17 08:53:07,997 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:53:07,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1844 states and 2694 transitions. [2024-11-17 08:53:08,001 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1681 [2024-11-17 08:53:08,001 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:08,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:08,002 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:08,002 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:08,002 INFO L745 eck$LassoCheckResult]: Stem: 48977#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 48978#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 48416#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48417#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49855#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 49731#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49732#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49791#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49792#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49913#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48433#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48434#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49462#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49547#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49105#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48532#L903 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48533#L908 assume 1 == ~t12_i~0;~t12_st~0 := 0; 48889#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49898#L1201-1 assume !(0 == ~M_E~0); 49899#L1206-1 assume !(0 == ~T1_E~0); 49725#L1211-1 assume !(0 == ~T2_E~0); 49726#L1216-1 assume !(0 == ~T3_E~0); 48702#L1221-1 assume !(0 == ~T4_E~0); 48703#L1226-1 assume !(0 == ~T5_E~0); 48325#L1231-1 assume !(0 == ~T6_E~0); 48326#L1236-1 assume !(0 == ~T7_E~0); 49774#L1241-1 assume !(0 == ~T8_E~0); 48750#L1246-1 assume !(0 == ~T9_E~0); 48751#L1251-1 assume !(0 == ~T10_E~0); 48925#L1256-1 assume !(0 == ~T11_E~0); 48098#L1261-1 assume !(0 == ~T12_E~0); 48099#L1266-1 assume !(0 == ~E_M~0); 49903#L1271-1 assume !(0 == ~E_1~0); 49474#L1276-1 assume !(0 == ~E_2~0); 49475#L1281-1 assume !(0 == ~E_3~0); 49437#L1286-1 assume !(0 == ~E_4~0); 48595#L1291-1 assume !(0 == ~E_5~0); 48596#L1296-1 assume !(0 == ~E_6~0); 49255#L1301-1 assume !(0 == ~E_7~0); 49256#L1306-1 assume !(0 == ~E_8~0); 49665#L1311-1 assume !(0 == ~E_9~0); 48547#L1316-1 assume !(0 == ~E_10~0); 48548#L1321-1 assume !(0 == ~E_11~0); 49270#L1326-1 assume !(0 == ~E_12~0); 49271#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49369#L593-15 assume 1 == ~m_pc~0; 49317#L594-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48584#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48585#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49199#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 49200#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49234#L612-15 assume 1 == ~t1_pc~0; 49447#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48622#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49351#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49907#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 48223#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48224#L631-15 assume 1 == ~t2_pc~0; 49306#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49394#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49395#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48390#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 48391#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49664#L650-15 assume 1 == ~t3_pc~0; 48572#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48573#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49695#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48586#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 48587#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49345#L669-15 assume 1 == ~t4_pc~0; 49346#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48946#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48947#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49612#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 49250#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49251#L688-15 assume 1 == ~t5_pc~0; 49106#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49107#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49072#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48935#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 48936#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49482#L707-15 assume 1 == ~t6_pc~0; 49483#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48989#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48990#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49330#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 49331#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49466#L726-15 assume 1 == ~t7_pc~0; 49867#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49368#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49408#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49529#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 49530#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49704#L745-15 assume 1 == ~t8_pc~0; 49886#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48435#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48436#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48397#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 48398#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48581#L764-15 assume 1 == ~t9_pc~0; 48582#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49655#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49834#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49835#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 49843#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48211#L783-15 assume 1 == ~t10_pc~0; 48212#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49478#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48733#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48734#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 49243#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48276#L802-15 assume 1 == ~t11_pc~0; 48277#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48534#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49680#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49846#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 49845#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49488#L821-15 assume 1 == ~t12_pc~0; 49489#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 49601#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49124#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48237#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 48238#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49053#L1339-1 assume !(1 == ~M_E~0); 49828#L1344-1 assume !(1 == ~T1_E~0); 49829#L1349-1 assume !(1 == ~T2_E~0); 49263#L1354-1 assume !(1 == ~T3_E~0); 49264#L1359-1 assume !(1 == ~T4_E~0); 49610#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48641#L1369-1 assume !(1 == ~T6_E~0); 48642#L1374-1 assume !(1 == ~T7_E~0); 49268#L1379-1 assume !(1 == ~T8_E~0); 49269#L1384-1 assume !(1 == ~T9_E~0); 49338#L1389-1 assume !(1 == ~T10_E~0); 49778#L1394-1 assume !(1 == ~T11_E~0); 49779#L1399-1 assume !(1 == ~T12_E~0); 49875#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 48754#L1409-1 assume !(1 == ~E_1~0); 48755#L1414-1 assume !(1 == ~E_2~0); 49496#L1419-1 assume !(1 == ~E_3~0); 48375#L1424-1 assume !(1 == ~E_4~0); 48376#L1429-1 assume !(1 == ~E_5~0); 49276#L1434-1 assume !(1 == ~E_6~0); 49798#L1439-1 assume !(1 == ~E_7~0); 48411#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 48412#L1449-1 assume !(1 == ~E_9~0); 48819#L1454-1 assume !(1 == ~E_10~0); 48820#L1459-1 assume !(1 == ~E_11~0); 49370#L1464-1 assume !(1 == ~E_12~0); 49189#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 48561#L1810 [2024-11-17 08:53:08,003 INFO L747 eck$LassoCheckResult]: Loop: 48561#L1810 assume true; 48296#L1810-1 assume !false; 48297#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48473#L998 assume true; 48474#L998-1 assume !false; 49716#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49650#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 49174#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 49392#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 49567#L1003 assume !(0 != eval_~tmp~0#1); 49802#L1006 assume true; 49763#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48495#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48496#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 48929#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49463#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49498#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49499#L1221 assume !(0 == ~T4_E~0); 48221#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48222#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49232#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 48166#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48167#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49348#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49663#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49729#L1261 assume !(0 == ~T12_E~0); 49552#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 49553#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 49398#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 48979#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 48980#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 49927#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 49906#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 49266#L1301 assume !(0 == ~E_7~0); 48516#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 48517#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 49409#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 49432#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 49696#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 49697#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49594#L593-1 assume 1 == ~m_pc~0; 48625#L594-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 48627#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49252#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48593#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48594#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48952#L612-1 assume 1 == ~t1_pc~0; 48953#L613-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49621#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49892#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49884#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49008#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49009#L631-1 assume 1 == ~t2_pc~0; 48606#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48190#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48191#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49800#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49702#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49632#L650-1 assume 1 == ~t3_pc~0; 49633#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49801#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48900#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48901#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48967#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48163#L669-1 assume 1 == ~t4_pc~0; 48164#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48712#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48756#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48757#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49538#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49443#L688-1 assume !(1 == ~t5_pc~0); 48266#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 48267#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48680#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48681#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48314#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48315#L707-1 assume 1 == ~t6_pc~0; 49019#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48656#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48643#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48644#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49895#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49893#L726-1 assume 1 == ~t7_pc~0; 49894#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49046#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49047#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49193#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49194#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48180#L745-1 assume 1 == ~t8_pc~0; 48181#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48688#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49790#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48603#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48604#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48782#L764-1 assume 1 == ~t9_pc~0; 48948#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49826#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49627#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49628#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 49739#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49872#L783-1 assume 1 == ~t10_pc~0; 49873#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48613#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49512#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49854#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49678#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 49679#L802-1 assume 1 == ~t11_pc~0; 49573#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 49257#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49258#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48898#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48899#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49314#L821-1 assume 1 == ~t12_pc~0; 49315#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48555#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48556#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 49471#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 49472#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49455#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 48960#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48961#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48248#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48249#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48783#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48784#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49362#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48311#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48312#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48215#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48216#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48716#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48717#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 48219#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 48220#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 49278#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 49279#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 49608#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 49785#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 49864#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 48794#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 48795#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 48488#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 48489#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 49539#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 49659#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 49113#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 48304#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 48577#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 48578#L1829 assume !(0 == start_simulation_~tmp~3#1); 48942#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 48943#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 48235#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 48831#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 48832#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 49399#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 49088#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 48560#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 48561#L1810 [2024-11-17 08:53:08,003 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:08,003 INFO L85 PathProgramCache]: Analyzing trace with hash -570959601, now seen corresponding path program 1 times [2024-11-17 08:53:08,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:08,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274713339] [2024-11-17 08:53:08,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:08,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:08,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:08,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:08,040 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:08,040 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274713339] [2024-11-17 08:53:08,040 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274713339] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:08,040 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:08,040 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:08,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124942258] [2024-11-17 08:53:08,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:08,041 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:08,041 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:08,041 INFO L85 PathProgramCache]: Analyzing trace with hash -2000070831, now seen corresponding path program 2 times [2024-11-17 08:53:08,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:08,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854259338] [2024-11-17 08:53:08,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:08,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:08,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:08,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:08,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:08,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854259338] [2024-11-17 08:53:08,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854259338] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:08,086 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:08,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:08,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2092546997] [2024-11-17 08:53:08,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:08,087 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:08,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:08,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:08,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:08,088 INFO L87 Difference]: Start difference. First operand 1844 states and 2694 transitions. cyclomatic complexity: 851 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:08,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:08,191 INFO L93 Difference]: Finished difference Result 3502 states and 5076 transitions. [2024-11-17 08:53:08,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3502 states and 5076 transitions. [2024-11-17 08:53:08,201 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3338 [2024-11-17 08:53:08,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3502 states to 3502 states and 5076 transitions. [2024-11-17 08:53:08,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3502 [2024-11-17 08:53:08,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3502 [2024-11-17 08:53:08,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3502 states and 5076 transitions. [2024-11-17 08:53:08,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:08,212 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3502 states and 5076 transitions. [2024-11-17 08:53:08,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3502 states and 5076 transitions. [2024-11-17 08:53:08,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3502 to 3412. [2024-11-17 08:53:08,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3412 states, 3412 states have (on average 1.4504689331770222) internal successors, (4949), 3411 states have internal predecessors, (4949), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:08,252 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3412 states to 3412 states and 4949 transitions. [2024-11-17 08:53:08,252 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3412 states and 4949 transitions. [2024-11-17 08:53:08,252 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:08,252 INFO L425 stractBuchiCegarLoop]: Abstraction has 3412 states and 4949 transitions. [2024-11-17 08:53:08,253 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:53:08,253 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3412 states and 4949 transitions. [2024-11-17 08:53:08,333 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3248 [2024-11-17 08:53:08,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:08,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:08,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:08,335 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:08,335 INFO L745 eck$LassoCheckResult]: Stem: 54335#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 54336#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 53770#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53771#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55299#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 55141#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55142#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55215#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55216#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55386#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53786#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53787#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 54835#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54929#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54465#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53884#L903 assume 1 == ~t11_i~0;~t11_st~0 := 0; 53885#L908 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54244#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55362#L1201-1 assume !(0 == ~M_E~0); 55363#L1206-1 assume !(0 == ~T1_E~0); 55134#L1211-1 assume !(0 == ~T2_E~0); 55135#L1216-1 assume !(0 == ~T3_E~0); 54055#L1221-1 assume !(0 == ~T4_E~0); 54056#L1226-1 assume !(0 == ~T5_E~0); 53680#L1231-1 assume !(0 == ~T6_E~0); 53681#L1236-1 assume !(0 == ~T7_E~0); 55191#L1241-1 assume !(0 == ~T8_E~0); 54103#L1246-1 assume !(0 == ~T9_E~0); 54104#L1251-1 assume !(0 == ~T10_E~0); 54280#L1256-1 assume !(0 == ~T11_E~0); 53453#L1261-1 assume !(0 == ~T12_E~0); 53454#L1266-1 assume !(0 == ~E_M~0); 55369#L1271-1 assume !(0 == ~E_1~0); 54849#L1276-1 assume !(0 == ~E_2~0); 54850#L1281-1 assume !(0 == ~E_3~0); 54809#L1286-1 assume !(0 == ~E_4~0); 53946#L1291-1 assume !(0 == ~E_5~0); 53947#L1296-1 assume !(0 == ~E_6~0); 54619#L1301-1 assume !(0 == ~E_7~0); 54620#L1306-1 assume !(0 == ~E_8~0); 55065#L1311-1 assume !(0 == ~E_9~0); 53899#L1316-1 assume !(0 == ~E_10~0); 53900#L1321-1 assume !(0 == ~E_11~0); 54636#L1326-1 assume !(0 == ~E_12~0); 54637#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54740#L593-15 assume !(1 == ~m_pc~0); 54900#L603-15 is_master_triggered_~__retres1~0#1 := 0; 53936#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53937#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54562#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 54563#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54598#L612-15 assume 1 == ~t1_pc~0; 54819#L613-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53973#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54722#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55376#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 53578#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53579#L631-15 assume 1 == ~t2_pc~0; 54675#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54765#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54766#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53744#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 53745#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55064#L650-15 assume 1 == ~t3_pc~0; 53924#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 53925#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55099#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53938#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 53939#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54716#L669-15 assume 1 == ~t4_pc~0; 54717#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54303#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54304#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55009#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 54614#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54615#L688-15 assume 1 == ~t5_pc~0; 54466#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54467#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54432#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54291#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 54292#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54858#L707-15 assume 1 == ~t6_pc~0; 54859#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 54347#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54348#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54701#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 54702#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54840#L726-15 assume 1 == ~t7_pc~0; 55315#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54739#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54780#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54909#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 54910#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55108#L745-15 assume 1 == ~t8_pc~0; 55340#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53788#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53789#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53751#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 53752#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53933#L764-15 assume 1 == ~t9_pc~0; 53934#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55054#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55273#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55274#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 55285#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53566#L783-15 assume 1 == ~t10_pc~0; 53567#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 54854#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54086#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54087#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 54607#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 53631#L802-15 assume 1 == ~t11_pc~0; 53632#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 53886#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55082#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55289#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 55287#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54864#L821-15 assume 1 == ~t12_pc~0; 54865#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 54994#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54485#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53592#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 53593#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54413#L1339-1 assume !(1 == ~M_E~0); 55264#L1344-1 assume !(1 == ~T1_E~0); 55265#L1349-1 assume !(1 == ~T2_E~0); 54628#L1354-1 assume !(1 == ~T3_E~0); 54629#L1359-1 assume !(1 == ~T4_E~0); 55006#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53991#L1369-1 assume !(1 == ~T6_E~0); 53992#L1374-1 assume !(1 == ~T7_E~0); 54634#L1379-1 assume !(1 == ~T8_E~0); 54635#L1384-1 assume !(1 == ~T9_E~0); 54709#L1389-1 assume !(1 == ~T10_E~0); 55197#L1394-1 assume !(1 == ~T11_E~0); 55198#L1399-1 assume !(1 == ~T12_E~0); 55324#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 54107#L1409-1 assume !(1 == ~E_1~0); 54108#L1414-1 assume !(1 == ~E_2~0); 54874#L1419-1 assume !(1 == ~E_3~0); 53729#L1424-1 assume !(1 == ~E_4~0); 53730#L1429-1 assume !(1 == ~E_5~0); 54642#L1434-1 assume !(1 == ~E_6~0); 55223#L1439-1 assume !(1 == ~E_7~0); 53765#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 53766#L1449-1 assume !(1 == ~E_9~0); 54173#L1454-1 assume !(1 == ~E_10~0); 54174#L1459-1 assume !(1 == ~E_11~0); 54741#L1464-1 assume !(1 == ~E_12~0); 54552#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 53913#L1810 [2024-11-17 08:53:08,336 INFO L747 eck$LassoCheckResult]: Loop: 53913#L1810 assume true; 53651#L1810-1 assume !false; 53652#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53826#L998 assume true; 53827#L998-1 assume !false; 55316#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 55049#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 54537#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54763#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 55227#L1003 assume !(0 != eval_~tmp~0#1); 55228#L1006 assume true; 55174#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53848#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53849#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 54284#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 54836#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 54876#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 54877#L1221 assume !(0 == ~T4_E~0); 53576#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 53577#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54596#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53521#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53522#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54719#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 55063#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 55138#L1261 assume !(0 == ~T12_E~0); 54934#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 54935#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 54769#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 54337#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 54338#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 55415#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 55375#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 54632#L1301 assume !(0 == ~E_7~0); 53868#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 53869#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 54781#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 54804#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 55100#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 55101#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54985#L593-1 assume !(1 == ~m_pc~0); 54986#L603-1 is_master_triggered_~__retres1~0#1 := 0; 56463#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56462#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56461#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56460#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56459#L612-1 assume !(1 == ~t1_pc~0); 56457#L622-1 is_transmit1_triggered_~__retres1~1#1 := 0; 56456#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56455#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56454#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56453#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56452#L631-1 assume !(1 == ~t2_pc~0); 56450#L641-1 is_transmit2_triggered_~__retres1~2#1 := 0; 56449#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56448#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56447#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 56446#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56445#L650-1 assume !(1 == ~t3_pc~0); 56443#L660-1 is_transmit3_triggered_~__retres1~3#1 := 0; 56442#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56441#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56440#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56439#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56438#L669-1 assume !(1 == ~t4_pc~0); 56436#L679-1 is_transmit4_triggered_~__retres1~4#1 := 0; 56435#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56434#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56433#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56432#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56431#L688-1 assume !(1 == ~t5_pc~0); 56429#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 56428#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56427#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56426#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 56425#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56424#L707-1 assume !(1 == ~t6_pc~0); 56422#L717-1 is_transmit6_triggered_~__retres1~6#1 := 0; 56421#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56420#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 56419#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56418#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56417#L726-1 assume 1 == ~t7_pc~0; 56416#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54406#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 54407#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54556#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 54557#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53535#L745-1 assume 1 == ~t8_pc~0; 53536#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 54040#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55212#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 53954#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53955#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54135#L764-1 assume 1 == ~t9_pc~0; 54305#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55260#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55025#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55026#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 55149#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55321#L783-1 assume 1 == ~t10_pc~0; 55322#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53964#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54890#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55298#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 55080#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55081#L802-1 assume 1 == ~t11_pc~0; 54961#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54621#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54622#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54253#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54254#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54683#L821-1 assume 1 == ~t12_pc~0; 54684#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 56134#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 56131#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 56130#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 56129#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56128#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 56112#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55176#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53603#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53604#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54136#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54137#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 54733#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56084#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56083#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 56082#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 56081#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56080#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56079#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 56078#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 55074#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 55075#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 55003#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 55004#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 55309#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 55310#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 56007#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 56006#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 56003#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 56001#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 55937#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 55936#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 55927#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 55916#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 55914#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 55338#L1829 assume !(0 == start_simulation_~tmp~3#1); 54299#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 54300#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 53590#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 54185#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 54186#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54770#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54448#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53912#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 53913#L1810 [2024-11-17 08:53:08,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:08,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1901032878, now seen corresponding path program 1 times [2024-11-17 08:53:08,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:08,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012126417] [2024-11-17 08:53:08,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:08,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:08,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:08,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:08,390 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:08,390 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1012126417] [2024-11-17 08:53:08,390 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1012126417] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:08,390 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:08,390 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:08,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1640775581] [2024-11-17 08:53:08,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:08,391 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:08,391 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:08,391 INFO L85 PathProgramCache]: Analyzing trace with hash -2076063773, now seen corresponding path program 1 times [2024-11-17 08:53:08,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:08,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [18788432] [2024-11-17 08:53:08,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:08,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:08,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:08,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:08,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:08,464 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [18788432] [2024-11-17 08:53:08,464 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [18788432] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:08,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:08,465 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:08,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498291770] [2024-11-17 08:53:08,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:08,465 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:08,465 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:08,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:08,466 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:08,466 INFO L87 Difference]: Start difference. First operand 3412 states and 4949 transitions. cyclomatic complexity: 1539 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:08,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:08,583 INFO L93 Difference]: Finished difference Result 6445 states and 9296 transitions. [2024-11-17 08:53:08,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6445 states and 9296 transitions. [2024-11-17 08:53:08,612 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6276 [2024-11-17 08:53:08,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6445 states to 6445 states and 9296 transitions. [2024-11-17 08:53:08,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6445 [2024-11-17 08:53:08,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6445 [2024-11-17 08:53:08,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6445 states and 9296 transitions. [2024-11-17 08:53:08,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:08,641 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6445 states and 9296 transitions. [2024-11-17 08:53:08,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6445 states and 9296 transitions. [2024-11-17 08:53:08,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6445 to 6437. [2024-11-17 08:53:08,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6437 states, 6437 states have (on average 1.442908187043654) internal successors, (9288), 6436 states have internal predecessors, (9288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:08,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6437 states to 6437 states and 9288 transitions. [2024-11-17 08:53:08,726 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6437 states and 9288 transitions. [2024-11-17 08:53:08,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:08,728 INFO L425 stractBuchiCegarLoop]: Abstraction has 6437 states and 9288 transitions. [2024-11-17 08:53:08,729 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:53:08,729 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6437 states and 9288 transitions. [2024-11-17 08:53:08,741 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6268 [2024-11-17 08:53:08,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:08,741 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:08,742 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:08,742 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:08,743 INFO L745 eck$LassoCheckResult]: Stem: 64204#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 64205#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 63638#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63639#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65146#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 65006#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65007#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65069#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65070#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65219#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63654#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63655#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 64709#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64800#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64333#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63752#L903 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63753#L908 assume 1 == ~t12_i~0;~t12_st~0 := 0; 64113#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65198#L1201-1 assume !(0 == ~M_E~0); 65199#L1206-1 assume !(0 == ~T1_E~0); 65000#L1211-1 assume !(0 == ~T2_E~0); 65001#L1216-1 assume !(0 == ~T3_E~0); 63924#L1221-1 assume !(0 == ~T4_E~0); 63925#L1226-1 assume !(0 == ~T5_E~0); 63546#L1231-1 assume !(0 == ~T6_E~0); 63547#L1236-1 assume !(0 == ~T7_E~0); 65051#L1241-1 assume !(0 == ~T8_E~0); 63972#L1246-1 assume !(0 == ~T9_E~0); 63973#L1251-1 assume !(0 == ~T10_E~0); 64152#L1256-1 assume !(0 == ~T11_E~0); 63319#L1261-1 assume !(0 == ~T12_E~0); 63320#L1266-1 assume !(0 == ~E_M~0); 65203#L1271-1 assume !(0 == ~E_1~0); 64721#L1276-1 assume !(0 == ~E_2~0); 64722#L1281-1 assume !(0 == ~E_3~0); 64684#L1286-1 assume !(0 == ~E_4~0); 63814#L1291-1 assume !(0 == ~E_5~0); 63815#L1296-1 assume !(0 == ~E_6~0); 64487#L1301-1 assume !(0 == ~E_7~0); 64488#L1306-1 assume !(0 == ~E_8~0); 64930#L1311-1 assume !(0 == ~E_9~0); 63767#L1316-1 assume !(0 == ~E_10~0); 63768#L1321-1 assume !(0 == ~E_11~0); 64502#L1326-1 assume !(0 == ~E_12~0); 64503#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64610#L593-15 assume !(1 == ~m_pc~0); 64771#L603-15 is_master_triggered_~__retres1~0#1 := 0; 63804#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63805#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64429#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 64430#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64465#L612-15 assume !(1 == ~t1_pc~0); 63844#L622-15 is_transmit1_triggered_~__retres1~1#1 := 0; 63845#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64592#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65209#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 63444#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63445#L631-15 assume 1 == ~t2_pc~0; 64539#L632-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64636#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64637#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 63611#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 63612#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64929#L650-15 assume 1 == ~t3_pc~0; 63792#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 63793#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64968#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 63806#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 63807#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 64583#L669-15 assume 1 == ~t4_pc~0; 64584#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64174#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 64175#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64874#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 64481#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64482#L688-15 assume 1 == ~t5_pc~0; 64334#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64335#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64300#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64162#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 64163#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64731#L707-15 assume 1 == ~t6_pc~0; 64732#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 64216#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64217#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64563#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 64564#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64713#L726-15 assume 1 == ~t7_pc~0; 65159#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64609#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64652#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64781#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 64782#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64978#L745-15 assume 1 == ~t8_pc~0; 65180#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 63656#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 63657#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63618#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 63619#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 63801#L764-15 assume 1 == ~t9_pc~0; 63802#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64919#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65120#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65121#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 65131#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 63432#L783-15 assume 1 == ~t10_pc~0; 63433#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 64727#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63955#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 63956#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 64474#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 63496#L802-15 assume 1 == ~t11_pc~0; 63497#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 63754#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64946#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65134#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 65133#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 64737#L821-15 assume 1 == ~t12_pc~0; 64738#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 64862#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64353#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 63458#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 63459#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64279#L1339-1 assume !(1 == ~M_E~0); 65110#L1344-1 assume !(1 == ~T1_E~0); 65111#L1349-1 assume !(1 == ~T2_E~0); 64495#L1354-1 assume !(1 == ~T3_E~0); 64496#L1359-1 assume !(1 == ~T4_E~0); 64872#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 63863#L1369-1 assume !(1 == ~T6_E~0); 63864#L1374-1 assume !(1 == ~T7_E~0); 64500#L1379-1 assume !(1 == ~T8_E~0); 64501#L1384-1 assume !(1 == ~T9_E~0); 64576#L1389-1 assume !(1 == ~T10_E~0); 65055#L1394-1 assume !(1 == ~T11_E~0); 65056#L1399-1 assume !(1 == ~T12_E~0); 65167#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 63976#L1409-1 assume !(1 == ~E_1~0); 63977#L1414-1 assume !(1 == ~E_2~0); 64745#L1419-1 assume !(1 == ~E_3~0); 63596#L1424-1 assume !(1 == ~E_4~0); 63597#L1429-1 assume !(1 == ~E_5~0); 64508#L1434-1 assume !(1 == ~E_6~0); 65076#L1439-1 assume !(1 == ~E_7~0); 63633#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 63634#L1449-1 assume !(1 == ~E_9~0); 64042#L1454-1 assume !(1 == ~E_10~0); 64043#L1459-1 assume !(1 == ~E_11~0); 64611#L1464-1 assume !(1 == ~E_12~0); 64419#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 63781#L1810 [2024-11-17 08:53:08,743 INFO L747 eck$LassoCheckResult]: Loop: 63781#L1810 assume true; 63516#L1810-1 assume !false; 63517#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 63694#L998 assume true; 63695#L998-1 assume !false; 64990#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64914#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 64404#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64634#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 64823#L1003 assume !(0 != eval_~tmp~0#1); 65080#L1006 assume true; 65038#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 63716#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63717#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 64156#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64710#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64747#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 64748#L1221 assume !(0 == ~T4_E~0); 63442#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 63443#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64463#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 66684#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 66681#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 66678#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 66676#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 66673#L1261 assume !(0 == ~T12_E~0); 66671#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 66670#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 66668#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 66665#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 66648#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 66641#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 65208#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 64498#L1301 assume !(0 == ~E_7~0); 63736#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 63737#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 64677#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 64678#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 64969#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 64970#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64853#L593-1 assume !(1 == ~m_pc~0); 64854#L603-1 is_master_triggered_~__retres1~0#1 := 0; 64483#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64484#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 63812#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 63813#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 64180#L612-1 assume !(1 == ~t1_pc~0); 64181#L622-1 is_transmit1_triggered_~__retres1~1#1 := 0; 64999#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65189#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65177#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64235#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64236#L631-1 assume 1 == ~t2_pc~0; 63827#L632-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 63411#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 63412#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65078#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 64976#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64896#L650-1 assume 1 == ~t3_pc~0; 64897#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65079#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64126#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64127#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 64194#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63384#L669-1 assume 1 == ~t4_pc~0; 63385#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 63934#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63978#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 63979#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64790#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 64690#L688-1 assume 1 == ~t5_pc~0; 63728#L689-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63487#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63902#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 63903#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 63535#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 63536#L707-1 assume 1 == ~t6_pc~0; 64245#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 63878#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64107#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69604#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69603#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69602#L726-1 assume 1 == ~t7_pc~0; 69601#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69599#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69598#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69597#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69596#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69595#L745-1 assume !(1 == ~t8_pc~0); 69593#L755-1 is_transmit8_triggered_~__retres1~8#1 := 0; 69592#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69591#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69590#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 69589#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69588#L764-1 assume 1 == ~t9_pc~0; 69587#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 69585#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69584#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69583#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69582#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69581#L783-1 assume !(1 == ~t10_pc~0); 69579#L793-1 is_transmit10_triggered_~__retres1~10#1 := 0; 69578#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69577#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69576#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69575#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69574#L802-1 assume 1 == ~t11_pc~0; 69573#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 69571#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69570#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69569#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 69568#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69567#L821-1 assume !(1 == ~t12_pc~0); 69565#L831-1 is_transmit12_triggered_~__retres1~12#1 := 0; 69564#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69563#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69562#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69561#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69560#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 64187#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 64188#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63468#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 63469#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64005#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64006#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64603#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 63531#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 63532#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 63436#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63437#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 63938#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 63939#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 63440#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 63441#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 64510#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 64511#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 64870#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 65063#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 65155#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 64016#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 64017#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 63709#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 63710#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 68701#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 68700#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 67300#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 67289#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 67085#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 67079#L1829 assume !(0 == start_simulation_~tmp~3#1); 64170#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 64171#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 63456#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 64054#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 64055#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64641#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64316#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 63780#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 63781#L1810 [2024-11-17 08:53:08,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:08,743 INFO L85 PathProgramCache]: Analyzing trace with hash 520890837, now seen corresponding path program 1 times [2024-11-17 08:53:08,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:08,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2104721510] [2024-11-17 08:53:08,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:08,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:08,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:08,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:08,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:08,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2104721510] [2024-11-17 08:53:08,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2104721510] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:08,780 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:08,780 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:08,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972395027] [2024-11-17 08:53:08,781 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:08,781 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:08,781 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:08,781 INFO L85 PathProgramCache]: Analyzing trace with hash 1146948829, now seen corresponding path program 1 times [2024-11-17 08:53:08,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:08,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514268524] [2024-11-17 08:53:08,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:08,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:08,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:08,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:08,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:08,835 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514268524] [2024-11-17 08:53:08,835 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514268524] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:08,835 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:08,835 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:08,835 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1503260156] [2024-11-17 08:53:08,835 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:08,835 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:08,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:08,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:08,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:08,836 INFO L87 Difference]: Start difference. First operand 6437 states and 9288 transitions. cyclomatic complexity: 2855 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:08,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:08,941 INFO L93 Difference]: Finished difference Result 12284 states and 17641 transitions. [2024-11-17 08:53:08,941 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12284 states and 17641 transitions. [2024-11-17 08:53:08,987 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12100 [2024-11-17 08:53:09,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12284 states to 12284 states and 17641 transitions. [2024-11-17 08:53:09,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12284 [2024-11-17 08:53:09,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12284 [2024-11-17 08:53:09,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12284 states and 17641 transitions. [2024-11-17 08:53:09,038 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:09,038 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12284 states and 17641 transitions. [2024-11-17 08:53:09,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12284 states and 17641 transitions. [2024-11-17 08:53:09,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12284 to 12268. [2024-11-17 08:53:09,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12268 states, 12268 states have (on average 1.4366644929898924) internal successors, (17625), 12267 states have internal predecessors, (17625), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:09,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12268 states to 12268 states and 17625 transitions. [2024-11-17 08:53:09,248 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12268 states and 17625 transitions. [2024-11-17 08:53:09,249 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:09,249 INFO L425 stractBuchiCegarLoop]: Abstraction has 12268 states and 17625 transitions. [2024-11-17 08:53:09,249 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:53:09,249 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12268 states and 17625 transitions. [2024-11-17 08:53:09,279 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 12084 [2024-11-17 08:53:09,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:09,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:09,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:09,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:09,281 INFO L745 eck$LassoCheckResult]: Stem: 82938#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 82939#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 82366#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82367#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 83922#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 83773#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 83774#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 83840#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83841#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84035#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82383#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82384#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83455#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 83554#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 83072#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 82482#L903 assume 1 == ~t11_i~0;~t11_st~0 := 0; 82483#L908 assume 1 == ~t12_i~0;~t12_st~0 := 0; 82848#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84007#L1201-1 assume !(0 == ~M_E~0); 84008#L1206-1 assume !(0 == ~T1_E~0); 83764#L1211-1 assume !(0 == ~T2_E~0); 83765#L1216-1 assume !(0 == ~T3_E~0); 82660#L1221-1 assume !(0 == ~T4_E~0); 82661#L1226-1 assume !(0 == ~T5_E~0); 82275#L1231-1 assume !(0 == ~T6_E~0); 82276#L1236-1 assume !(0 == ~T7_E~0); 83820#L1241-1 assume !(0 == ~T8_E~0); 82706#L1246-1 assume !(0 == ~T9_E~0); 82707#L1251-1 assume !(0 == ~T10_E~0); 82886#L1256-1 assume !(0 == ~T11_E~0); 82049#L1261-1 assume !(0 == ~T12_E~0); 82050#L1266-1 assume !(0 == ~E_M~0); 84012#L1271-1 assume !(0 == ~E_1~0); 83470#L1276-1 assume !(0 == ~E_2~0); 83471#L1281-1 assume !(0 == ~E_3~0); 83427#L1286-1 assume !(0 == ~E_4~0); 82544#L1291-1 assume !(0 == ~E_5~0); 82545#L1296-1 assume !(0 == ~E_6~0); 83230#L1301-1 assume !(0 == ~E_7~0); 83231#L1306-1 assume !(0 == ~E_8~0); 83691#L1311-1 assume !(0 == ~E_9~0); 82497#L1316-1 assume !(0 == ~E_10~0); 82498#L1321-1 assume !(0 == ~E_11~0); 83245#L1326-1 assume !(0 == ~E_12~0); 83246#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83354#L593-15 assume !(1 == ~m_pc~0); 83525#L603-15 is_master_triggered_~__retres1~0#1 := 0; 82534#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82535#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83169#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 83170#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83207#L612-15 assume !(1 == ~t1_pc~0); 82573#L622-15 is_transmit1_triggered_~__retres1~1#1 := 0; 82574#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83335#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 84024#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 82174#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82175#L631-15 assume !(1 == ~t2_pc~0); 83280#L641-15 is_transmit2_triggered_~__retres1~2#1 := 0; 83379#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83380#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82340#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 82341#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83690#L650-15 assume 1 == ~t3_pc~0; 82522#L651-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 82523#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83729#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82536#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 82537#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83329#L669-15 assume 1 == ~t4_pc~0; 83330#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82908#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82909#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83634#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 83225#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83226#L688-15 assume 1 == ~t5_pc~0; 83073#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83074#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83037#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82896#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 82897#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83482#L707-15 assume 1 == ~t6_pc~0; 83483#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 82952#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82953#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 83307#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 83308#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83461#L726-15 assume 1 == ~t7_pc~0; 83943#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83353#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 83396#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 83535#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 83536#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83738#L745-15 assume 1 == ~t8_pc~0; 83983#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 82385#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82386#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82347#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 82348#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82531#L764-15 assume 1 == ~t9_pc~0; 82532#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 83678#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83897#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83898#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 83906#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 82162#L783-15 assume 1 == ~t10_pc~0; 82163#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 83478#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82689#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82690#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 83218#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82226#L802-15 assume 1 == ~t11_pc~0; 82227#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 82484#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 83708#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 83910#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 83908#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 83488#L821-15 assume 1 == ~t12_pc~0; 83489#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 83621#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83091#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 82188#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 82189#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83016#L1339-1 assume !(1 == ~M_E~0); 83890#L1344-1 assume !(1 == ~T1_E~0); 83891#L1349-1 assume !(1 == ~T2_E~0); 83238#L1354-1 assume !(1 == ~T3_E~0); 83239#L1359-1 assume !(1 == ~T4_E~0); 83632#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 82597#L1369-1 assume !(1 == ~T6_E~0); 82598#L1374-1 assume !(1 == ~T7_E~0); 83243#L1379-1 assume !(1 == ~T8_E~0); 83244#L1384-1 assume !(1 == ~T9_E~0); 83320#L1389-1 assume !(1 == ~T10_E~0); 83824#L1394-1 assume !(1 == ~T11_E~0); 83825#L1399-1 assume !(1 == ~T12_E~0); 83961#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 82710#L1409-1 assume !(1 == ~E_1~0); 82711#L1414-1 assume !(1 == ~E_2~0); 83498#L1419-1 assume !(1 == ~E_3~0); 82325#L1424-1 assume !(1 == ~E_4~0); 82326#L1429-1 assume !(1 == ~E_5~0); 83251#L1434-1 assume !(1 == ~E_6~0); 83847#L1439-1 assume !(1 == ~E_7~0); 82361#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 82362#L1449-1 assume !(1 == ~E_9~0); 82776#L1454-1 assume !(1 == ~E_10~0); 82777#L1459-1 assume !(1 == ~E_11~0); 83355#L1464-1 assume !(1 == ~E_12~0); 83158#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 83159#L1810 [2024-11-17 08:53:09,281 INFO L747 eck$LassoCheckResult]: Loop: 83159#L1810 assume true; 93229#L1810-1 assume !false; 91812#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82422#L998 assume true; 82423#L998-1 assume !false; 91805#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83673#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 83143#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 83378#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 83576#L1003 assume !(0 != eval_~tmp~0#1); 83854#L1006 assume true; 94132#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94130#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94128#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 94127#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 94124#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 94123#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 94122#L1221 assume !(0 == ~T4_E~0); 94121#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94120#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 94119#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 94118#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 94117#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 94116#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 94115#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 94114#L1261 assume !(0 == ~T12_E~0); 94113#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 93612#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 93611#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 82940#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 82941#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 84079#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 84020#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 83241#L1301 assume !(0 == ~E_7~0); 82466#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 82467#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 83397#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 83422#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 83730#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 83731#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83611#L593-1 assume !(1 == ~m_pc~0); 83612#L603-1 is_master_triggered_~__retres1~0#1 := 0; 83883#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 93950#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 93948#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 83301#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82914#L612-1 assume !(1 == ~t1_pc~0); 82915#L622-1 is_transmit1_triggered_~__retres1~1#1 := 0; 83763#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84000#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 83976#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82971#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82972#L631-1 assume !(1 == ~t2_pc~0); 83351#L641-1 is_transmit2_triggered_~__retres1~2#1 := 0; 82141#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82142#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83851#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 83736#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83656#L650-1 assume 1 == ~t3_pc~0; 83657#L651-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83853#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82861#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82862#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82928#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82114#L669-1 assume 1 == ~t4_pc~0; 82115#L670-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82668#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82712#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82713#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83545#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83435#L688-1 assume 1 == ~t5_pc~0; 82457#L689-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82217#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82637#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82638#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82264#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82265#L707-1 assume 1 == ~t6_pc~0; 82981#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 82613#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82599#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82600#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 84004#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84001#L726-1 assume 1 == ~t7_pc~0; 84002#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83009#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 83010#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 83163#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 83164#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82131#L745-1 assume !(1 == ~t8_pc~0); 82133#L755-1 is_transmit8_triggered_~__retres1~8#1 := 0; 82644#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 94185#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 94184#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 94183#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94182#L764-1 assume 1 == ~t9_pc~0; 94181#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 94179#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94112#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 94111#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 94109#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 94107#L783-1 assume 1 == ~t10_pc~0; 94105#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 94094#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 94093#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 94092#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 94091#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 94090#L802-1 assume 1 == ~t11_pc~0; 94089#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 94081#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 94080#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 94078#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 94076#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 94074#L821-1 assume !(1 == ~t12_pc~0); 94071#L831-1 is_transmit12_triggered_~__retres1~12#1 := 0; 94062#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 94061#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 94060#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 94059#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94058#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 94057#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 94055#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94053#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94049#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94048#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94047#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 94046#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 94045#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 94043#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 94040#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 94038#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94036#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 94034#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 94032#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 94030#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 94027#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 94016#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 94013#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 94012#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 94011#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 94010#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 94009#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 94008#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 94007#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 93583#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 93582#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 83080#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 82254#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 82529#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 82530#L1829 assume !(0 == start_simulation_~tmp~3#1); 83981#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 93243#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 93235#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 93234#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 93233#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 93232#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 93231#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 93230#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 83159#L1810 [2024-11-17 08:53:09,281 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:09,281 INFO L85 PathProgramCache]: Analyzing trace with hash 107636632, now seen corresponding path program 1 times [2024-11-17 08:53:09,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:09,281 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628046768] [2024-11-17 08:53:09,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:09,281 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:09,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:09,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:09,315 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:09,315 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [628046768] [2024-11-17 08:53:09,315 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [628046768] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:09,315 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:09,315 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:09,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045694909] [2024-11-17 08:53:09,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:09,315 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:09,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:09,316 INFO L85 PathProgramCache]: Analyzing trace with hash -772908323, now seen corresponding path program 1 times [2024-11-17 08:53:09,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:09,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414344706] [2024-11-17 08:53:09,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:09,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:09,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:09,362 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:09,362 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:09,362 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414344706] [2024-11-17 08:53:09,362 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1414344706] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:09,362 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:09,363 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:09,363 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1114894775] [2024-11-17 08:53:09,363 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:09,363 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:09,363 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:09,363 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:09,363 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:09,363 INFO L87 Difference]: Start difference. First operand 12268 states and 17625 transitions. cyclomatic complexity: 5365 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:09,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:09,506 INFO L93 Difference]: Finished difference Result 23527 states and 33658 transitions. [2024-11-17 08:53:09,506 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23527 states and 33658 transitions. [2024-11-17 08:53:09,595 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23304 [2024-11-17 08:53:09,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23527 states to 23527 states and 33658 transitions. [2024-11-17 08:53:09,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23527 [2024-11-17 08:53:09,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23527 [2024-11-17 08:53:09,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23527 states and 33658 transitions. [2024-11-17 08:53:09,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:09,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23527 states and 33658 transitions. [2024-11-17 08:53:09,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23527 states and 33658 transitions. [2024-11-17 08:53:10,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23527 to 23495. [2024-11-17 08:53:10,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23495 states, 23495 states have (on average 1.4311981272611194) internal successors, (33626), 23494 states have internal predecessors, (33626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:10,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23495 states to 23495 states and 33626 transitions. [2024-11-17 08:53:10,093 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23495 states and 33626 transitions. [2024-11-17 08:53:10,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:10,094 INFO L425 stractBuchiCegarLoop]: Abstraction has 23495 states and 33626 transitions. [2024-11-17 08:53:10,094 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:53:10,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23495 states and 33626 transitions. [2024-11-17 08:53:10,262 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 23272 [2024-11-17 08:53:10,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:10,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:10,263 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:10,263 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:10,264 INFO L745 eck$LassoCheckResult]: Stem: 118729#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 118730#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 118170#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118171#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 119706#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 119554#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119555#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119628#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 119629#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 119787#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 118186#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 118187#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 119247#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 119346#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 118868#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 118282#L903 assume 1 == ~t11_i~0;~t11_st~0 := 0; 118283#L908 assume 1 == ~t12_i~0;~t12_st~0 := 0; 118640#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119763#L1201-1 assume !(0 == ~M_E~0); 119764#L1206-1 assume !(0 == ~T1_E~0); 119548#L1211-1 assume !(0 == ~T2_E~0); 119549#L1216-1 assume !(0 == ~T3_E~0); 118454#L1221-1 assume !(0 == ~T4_E~0); 118455#L1226-1 assume !(0 == ~T5_E~0); 118080#L1231-1 assume !(0 == ~T6_E~0); 118081#L1236-1 assume !(0 == ~T7_E~0); 119608#L1241-1 assume !(0 == ~T8_E~0); 118500#L1246-1 assume !(0 == ~T9_E~0); 118501#L1251-1 assume !(0 == ~T10_E~0); 118677#L1256-1 assume !(0 == ~T11_E~0); 117855#L1261-1 assume !(0 == ~T12_E~0); 117856#L1266-1 assume !(0 == ~E_M~0); 119770#L1271-1 assume !(0 == ~E_1~0); 119263#L1276-1 assume !(0 == ~E_2~0); 119264#L1281-1 assume !(0 == ~E_3~0); 119222#L1286-1 assume !(0 == ~E_4~0); 118342#L1291-1 assume !(0 == ~E_5~0); 118343#L1296-1 assume !(0 == ~E_6~0); 119027#L1301-1 assume !(0 == ~E_7~0); 119028#L1306-1 assume !(0 == ~E_8~0); 119480#L1311-1 assume !(0 == ~E_9~0); 118297#L1316-1 assume !(0 == ~E_10~0); 118298#L1321-1 assume !(0 == ~E_11~0); 119044#L1326-1 assume !(0 == ~E_12~0); 119045#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119150#L593-15 assume !(1 == ~m_pc~0); 119318#L603-15 is_master_triggered_~__retres1~0#1 := 0; 118331#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118332#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 118969#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 118970#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119004#L612-15 assume !(1 == ~t1_pc~0); 118368#L622-15 is_transmit1_triggered_~__retres1~1#1 := 0; 118369#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119132#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 119779#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 117978#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117979#L631-15 assume !(1 == ~t2_pc~0); 119088#L641-15 is_transmit2_triggered_~__retres1~2#1 := 0; 119176#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119177#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 118144#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 118145#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119477#L650-15 assume !(1 == ~t3_pc~0); 119478#L660-15 is_transmit3_triggered_~__retres1~3#1 := 0; 119512#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119513#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 118333#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 118334#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119126#L669-15 assume 1 == ~t4_pc~0; 119127#L670-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 118698#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118699#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 119420#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 119022#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119023#L688-15 assume 1 == ~t5_pc~0; 118872#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 118873#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118832#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 118686#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 118687#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 119274#L707-15 assume 1 == ~t6_pc~0; 119275#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 118744#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 118745#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 119109#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 119110#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119254#L726-15 assume 1 == ~t7_pc~0; 119720#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 119149#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 119191#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 119327#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 119328#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 119525#L745-15 assume 1 == ~t8_pc~0; 119745#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 118190#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 118191#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 118154#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 118155#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 118328#L764-15 assume 1 == ~t9_pc~0; 118329#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 119465#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 119681#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 119682#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 119690#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117966#L783-15 assume 1 == ~t10_pc~0; 117967#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 119270#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 118482#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 118483#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 119014#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 118031#L802-15 assume 1 == ~t11_pc~0; 118032#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 118286#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 119495#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 119693#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 119692#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 119280#L821-15 assume 1 == ~t12_pc~0; 119281#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 119406#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 118890#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 117994#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 117995#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118811#L1339-1 assume !(1 == ~M_E~0); 119672#L1344-1 assume !(1 == ~T1_E~0); 119673#L1349-1 assume !(1 == ~T2_E~0); 119037#L1354-1 assume !(1 == ~T3_E~0); 119038#L1359-1 assume !(1 == ~T4_E~0); 119419#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 118388#L1369-1 assume !(1 == ~T6_E~0); 118389#L1374-1 assume !(1 == ~T7_E~0); 119042#L1379-1 assume !(1 == ~T8_E~0); 119043#L1384-1 assume !(1 == ~T9_E~0); 119120#L1389-1 assume !(1 == ~T10_E~0); 119613#L1394-1 assume !(1 == ~T11_E~0); 119614#L1399-1 assume !(1 == ~T12_E~0); 119731#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 118504#L1409-1 assume !(1 == ~E_1~0); 118505#L1414-1 assume !(1 == ~E_2~0); 119290#L1419-1 assume !(1 == ~E_3~0); 118129#L1424-1 assume !(1 == ~E_4~0); 118130#L1429-1 assume !(1 == ~E_5~0); 119051#L1434-1 assume !(1 == ~E_6~0); 119635#L1439-1 assume !(1 == ~E_7~0); 118165#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 118166#L1449-1 assume !(1 == ~E_9~0); 118567#L1454-1 assume !(1 == ~E_10~0); 118568#L1459-1 assume !(1 == ~E_11~0); 119152#L1464-1 assume !(1 == ~E_12~0); 118958#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 118959#L1810 [2024-11-17 08:53:10,265 INFO L747 eck$LassoCheckResult]: Loop: 118959#L1810 assume true; 126352#L1810-1 assume !false; 125504#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 125502#L998 assume true; 125500#L998-1 assume !false; 125498#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 125466#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 125464#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 125462#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 125459#L1003 assume !(0 != eval_~tmp~0#1); 125460#L1006 assume true; 132361#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 132358#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132356#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 132354#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 132352#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 132350#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132348#L1221 assume !(0 == ~T4_E~0); 132346#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 132344#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 132342#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 132340#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 132338#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 132336#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 132334#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 132332#L1261 assume !(0 == ~T12_E~0); 132330#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 132328#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 132326#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 132324#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 132321#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 132319#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 132317#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 132315#L1301 assume !(0 == ~E_7~0); 132313#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 132311#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 132308#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 132306#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 132304#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 132302#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132300#L593-1 assume !(1 == ~m_pc~0); 132298#L603-1 is_master_triggered_~__retres1~0#1 := 0; 132295#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132293#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 132291#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 132289#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132287#L612-1 assume !(1 == ~t1_pc~0); 132285#L622-1 is_transmit1_triggered_~__retres1~1#1 := 0; 132282#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132280#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 132278#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 132276#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132274#L631-1 assume !(1 == ~t2_pc~0); 132272#L641-1 is_transmit2_triggered_~__retres1~2#1 := 0; 132271#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132270#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 132269#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 132268#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132267#L650-1 assume !(1 == ~t3_pc~0); 132266#L660-1 is_transmit3_triggered_~__retres1~3#1 := 0; 132265#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132264#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 132263#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 132262#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132261#L669-1 assume !(1 == ~t4_pc~0); 132258#L679-1 is_transmit4_triggered_~__retres1~4#1 := 0; 132256#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132254#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 132252#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132250#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132248#L688-1 assume 1 == ~t5_pc~0; 132246#L689-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 132242#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132240#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 132238#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 132236#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 132234#L707-1 assume !(1 == ~t6_pc~0); 132231#L717-1 is_transmit6_triggered_~__retres1~6#1 := 0; 132229#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 132227#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 132225#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 132223#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 132221#L726-1 assume !(1 == ~t7_pc~0); 132218#L736-1 is_transmit7_triggered_~__retres1~7#1 := 0; 132216#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 132214#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 132212#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 132210#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 132208#L745-1 assume 1 == ~t8_pc~0; 132206#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 132202#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 132200#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 132198#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 132196#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 132194#L764-1 assume 1 == ~t9_pc~0; 132192#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 132188#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 126509#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 126506#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 126504#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 126502#L783-1 assume !(1 == ~t10_pc~0); 126499#L793-1 is_transmit10_triggered_~__retres1~10#1 := 0; 126497#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 126495#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 126492#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 126490#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 126488#L802-1 assume 1 == ~t11_pc~0; 126485#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 126482#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 126479#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 126477#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 126475#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 126473#L821-1 assume 1 == ~t12_pc~0; 126471#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 126468#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 126465#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 126463#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 126461#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126459#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 126457#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 126455#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 126452#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 126450#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 126448#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 126446#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 126444#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 126442#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 126440#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 126438#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 126436#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 126434#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 126432#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 126430#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 126428#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 126426#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 126424#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 126422#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 126420#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 126418#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 126416#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 126414#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 126412#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 126410#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 126408#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 126406#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 126398#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 126387#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 126385#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 126381#L1829 assume !(0 == start_simulation_~tmp~3#1); 126380#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 126374#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 126366#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 126363#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 126360#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 126358#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 126356#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 126354#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 118959#L1810 [2024-11-17 08:53:10,267 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:10,267 INFO L85 PathProgramCache]: Analyzing trace with hash -374410341, now seen corresponding path program 1 times [2024-11-17 08:53:10,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:10,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422115838] [2024-11-17 08:53:10,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:10,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:10,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:10,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:10,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:10,301 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1422115838] [2024-11-17 08:53:10,301 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1422115838] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:10,301 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:10,301 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:10,301 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053422328] [2024-11-17 08:53:10,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:10,302 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:10,302 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:10,302 INFO L85 PathProgramCache]: Analyzing trace with hash -1024403546, now seen corresponding path program 1 times [2024-11-17 08:53:10,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:10,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [215176231] [2024-11-17 08:53:10,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:10,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:10,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:10,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:10,347 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:10,347 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [215176231] [2024-11-17 08:53:10,347 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [215176231] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:10,347 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:10,347 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:10,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1447543651] [2024-11-17 08:53:10,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:10,348 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:10,348 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:10,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:10,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:10,348 INFO L87 Difference]: Start difference. First operand 23495 states and 33626 transitions. cyclomatic complexity: 10147 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:10,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:10,536 INFO L93 Difference]: Finished difference Result 45150 states and 64367 transitions. [2024-11-17 08:53:10,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45150 states and 64367 transitions. [2024-11-17 08:53:10,815 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44832 [2024-11-17 08:53:10,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45150 states to 45150 states and 64367 transitions. [2024-11-17 08:53:10,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45150 [2024-11-17 08:53:10,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45150 [2024-11-17 08:53:10,986 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45150 states and 64367 transitions. [2024-11-17 08:53:11,026 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:11,026 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45150 states and 64367 transitions. [2024-11-17 08:53:11,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45150 states and 64367 transitions. [2024-11-17 08:53:11,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45150 to 45086. [2024-11-17 08:53:11,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45086 states, 45086 states have (on average 1.4262298718005588) internal successors, (64303), 45085 states have internal predecessors, (64303), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:11,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45086 states to 45086 states and 64303 transitions. [2024-11-17 08:53:11,661 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45086 states and 64303 transitions. [2024-11-17 08:53:11,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:11,662 INFO L425 stractBuchiCegarLoop]: Abstraction has 45086 states and 64303 transitions. [2024-11-17 08:53:11,662 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:53:11,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45086 states and 64303 transitions. [2024-11-17 08:53:11,972 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44768 [2024-11-17 08:53:11,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:11,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:11,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:11,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:11,975 INFO L745 eck$LassoCheckResult]: Stem: 187394#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 187395#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 186824#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 186825#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 188382#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 188218#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 188219#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 188297#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 188298#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 188475#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 186843#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 186844#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 187908#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 187999#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 187525#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 186948#L903 assume 1 == ~t11_i~0;~t11_st~0 := 0; 186949#L908 assume 1 == ~t12_i~0;~t12_st~0 := 0; 187303#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 188457#L1201-1 assume !(0 == ~M_E~0); 188458#L1206-1 assume !(0 == ~T1_E~0); 188212#L1211-1 assume !(0 == ~T2_E~0); 188213#L1216-1 assume !(0 == ~T3_E~0); 187115#L1221-1 assume !(0 == ~T4_E~0); 187116#L1226-1 assume !(0 == ~T5_E~0); 186733#L1231-1 assume !(0 == ~T6_E~0); 186734#L1236-1 assume !(0 == ~T7_E~0); 188276#L1241-1 assume !(0 == ~T8_E~0); 187164#L1246-1 assume !(0 == ~T9_E~0); 187165#L1251-1 assume !(0 == ~T10_E~0); 187341#L1256-1 assume !(0 == ~T11_E~0); 186507#L1261-1 assume !(0 == ~T12_E~0); 186508#L1266-1 assume !(0 == ~E_M~0); 188463#L1271-1 assume !(0 == ~E_1~0); 187923#L1276-1 assume !(0 == ~E_2~0); 187924#L1281-1 assume !(0 == ~E_3~0); 187883#L1286-1 assume !(0 == ~E_4~0); 187007#L1291-1 assume !(0 == ~E_5~0); 187008#L1296-1 assume !(0 == ~E_6~0); 187685#L1301-1 assume !(0 == ~E_7~0); 187686#L1306-1 assume !(0 == ~E_8~0); 188129#L1311-1 assume !(0 == ~E_9~0); 186963#L1316-1 assume !(0 == ~E_10~0); 186964#L1321-1 assume !(0 == ~E_11~0); 187701#L1326-1 assume !(0 == ~E_12~0); 187702#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 187808#L593-15 assume !(1 == ~m_pc~0); 187972#L603-15 is_master_triggered_~__retres1~0#1 := 0; 186997#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 186998#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 187626#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 187627#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 187660#L612-15 assume !(1 == ~t1_pc~0); 187034#L622-15 is_transmit1_triggered_~__retres1~1#1 := 0; 187035#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 187789#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 188468#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 186628#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186629#L631-15 assume !(1 == ~t2_pc~0); 187739#L641-15 is_transmit2_triggered_~__retres1~2#1 := 0; 187837#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 187838#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 186797#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 186798#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 188127#L650-15 assume !(1 == ~t3_pc~0); 188128#L660-15 is_transmit3_triggered_~__retres1~3#1 := 0; 188169#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 188170#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 186999#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 187000#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 187784#L669-15 assume !(1 == ~t4_pc~0); 187785#L679-15 is_transmit4_triggered_~__retres1~4#1 := 0; 187364#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 187365#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 188072#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 187679#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 187680#L688-15 assume 1 == ~t5_pc~0; 187526#L689-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 187527#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 187491#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 187352#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 187353#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 187933#L707-15 assume 1 == ~t6_pc~0; 187934#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 187406#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 187407#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 187762#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 187763#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 187914#L726-15 assume 1 == ~t7_pc~0; 188403#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 187807#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 187851#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 187981#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 187982#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 188179#L745-15 assume 1 == ~t8_pc~0; 188432#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 186845#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 186846#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 186804#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 186805#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 186994#L764-15 assume 1 == ~t9_pc~0; 186995#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 188115#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 188360#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 188361#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 188369#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 186616#L783-15 assume 1 == ~t10_pc~0; 186617#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 187929#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 187146#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 187147#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 187672#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 186682#L802-15 assume 1 == ~t11_pc~0; 186683#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 186950#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 188145#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 188372#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 188371#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 187939#L821-15 assume 1 == ~t12_pc~0; 187940#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 188060#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 187547#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 186644#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 186645#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 187470#L1339-1 assume !(1 == ~M_E~0); 188353#L1344-1 assume !(1 == ~T1_E~0); 188354#L1349-1 assume !(1 == ~T2_E~0); 187693#L1354-1 assume !(1 == ~T3_E~0); 187694#L1359-1 assume !(1 == ~T4_E~0); 188070#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 187054#L1369-1 assume !(1 == ~T6_E~0); 187055#L1374-1 assume !(1 == ~T7_E~0); 187699#L1379-1 assume !(1 == ~T8_E~0); 187700#L1384-1 assume !(1 == ~T9_E~0); 187777#L1389-1 assume !(1 == ~T10_E~0); 188281#L1394-1 assume !(1 == ~T11_E~0); 188282#L1399-1 assume !(1 == ~T12_E~0); 188418#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 187168#L1409-1 assume !(1 == ~E_1~0); 187169#L1414-1 assume !(1 == ~E_2~0); 187947#L1419-1 assume !(1 == ~E_3~0); 186782#L1424-1 assume !(1 == ~E_4~0); 186783#L1429-1 assume !(1 == ~E_5~0); 187707#L1434-1 assume !(1 == ~E_6~0); 188305#L1439-1 assume !(1 == ~E_7~0); 186819#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 186820#L1449-1 assume !(1 == ~E_9~0); 187234#L1454-1 assume !(1 == ~E_10~0); 187235#L1459-1 assume !(1 == ~E_11~0); 187809#L1464-1 assume !(1 == ~E_12~0); 187614#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 187615#L1810 [2024-11-17 08:53:11,978 INFO L747 eck$LassoCheckResult]: Loop: 187615#L1810 assume true; 210625#L1810-1 assume !false; 210617#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 210615#L998 assume true; 210613#L998-1 assume !false; 210611#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 210564#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 210557#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 210551#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 210542#L1003 assume !(0 != eval_~tmp~0#1); 210543#L1006 assume true; 214778#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 214776#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 214774#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 214773#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 214720#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 214709#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 214699#L1221 assume !(0 == ~T4_E~0); 214693#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 213722#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 213721#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 213720#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 213719#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 213718#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 213717#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 213716#L1261 assume !(0 == ~T12_E~0); 213714#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 213712#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 213710#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 213708#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 213706#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 213704#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 213702#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 213700#L1301 assume !(0 == ~E_7~0); 213698#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 213696#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 213694#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 213692#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 213690#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 213688#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 213686#L593-1 assume !(1 == ~m_pc~0); 213684#L603-1 is_master_triggered_~__retres1~0#1 := 0; 213682#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 213680#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 213678#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 213676#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 213674#L612-1 assume !(1 == ~t1_pc~0); 213672#L622-1 is_transmit1_triggered_~__retres1~1#1 := 0; 213670#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 213668#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 213666#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 213664#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213662#L631-1 assume !(1 == ~t2_pc~0); 213660#L641-1 is_transmit2_triggered_~__retres1~2#1 := 0; 213658#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213656#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 213654#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 213651#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213649#L650-1 assume !(1 == ~t3_pc~0); 213647#L660-1 is_transmit3_triggered_~__retres1~3#1 := 0; 213645#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 213643#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 213641#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 213638#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 213636#L669-1 assume !(1 == ~t4_pc~0); 213634#L679-1 is_transmit4_triggered_~__retres1~4#1 := 0; 213632#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 213615#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 213608#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 213534#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 213526#L688-1 assume 1 == ~t5_pc~0; 213519#L689-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 213516#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 213514#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 213512#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 213510#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 213508#L707-1 assume 1 == ~t6_pc~0; 213506#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 213503#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213501#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 213499#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 213497#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 213495#L726-1 assume 1 == ~t7_pc~0; 213493#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 213490#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 213488#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 213486#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 213484#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 213481#L745-1 assume 1 == ~t8_pc~0; 213479#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 213476#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 213474#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 213472#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 213470#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 213468#L764-1 assume 1 == ~t9_pc~0; 213466#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 213463#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 213461#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 213459#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 213457#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 213454#L783-1 assume !(1 == ~t10_pc~0); 213451#L793-1 is_transmit10_triggered_~__retres1~10#1 := 0; 213449#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 213434#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 213431#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 213429#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 213427#L802-1 assume 1 == ~t11_pc~0; 213425#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 213422#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 213420#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 213417#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 213415#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 213413#L821-1 assume 1 == ~t12_pc~0; 213411#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 213408#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 213406#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 213403#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 213401#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 213399#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 213397#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 213395#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 213393#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 213390#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 213388#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 213386#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 213384#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 213382#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 213380#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 213377#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 213365#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 213359#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 213352#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 213345#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 213338#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 213330#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 213324#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 213318#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 213311#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 213302#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 213294#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 213288#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 213281#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 213273#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 213264#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 213255#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 212947#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 212936#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 212934#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 211564#L1829 assume !(0 == start_simulation_~tmp~3#1); 211560#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 210648#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 210639#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 210637#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 210635#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 210633#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 210632#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 210629#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 187615#L1810 [2024-11-17 08:53:11,979 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:11,979 INFO L85 PathProgramCache]: Analyzing trace with hash 239173086, now seen corresponding path program 1 times [2024-11-17 08:53:11,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:11,979 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2056384518] [2024-11-17 08:53:11,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:11,979 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:11,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:12,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:12,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:12,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2056384518] [2024-11-17 08:53:12,013 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2056384518] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:12,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:12,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:12,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [82438618] [2024-11-17 08:53:12,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:12,013 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:12,013 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:12,014 INFO L85 PathProgramCache]: Analyzing trace with hash -1617816352, now seen corresponding path program 1 times [2024-11-17 08:53:12,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:12,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274034023] [2024-11-17 08:53:12,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:12,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:12,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:12,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:12,055 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:12,055 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274034023] [2024-11-17 08:53:12,056 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274034023] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:12,056 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:12,056 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:12,056 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [604460410] [2024-11-17 08:53:12,056 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:12,056 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:12,056 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:12,057 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:12,057 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:12,057 INFO L87 Difference]: Start difference. First operand 45086 states and 64303 transitions. cyclomatic complexity: 19249 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:12,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:12,453 INFO L93 Difference]: Finished difference Result 86685 states and 123180 transitions. [2024-11-17 08:53:12,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86685 states and 123180 transitions. [2024-11-17 08:53:12,995 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 86144 [2024-11-17 08:53:13,354 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86685 states to 86685 states and 123180 transitions. [2024-11-17 08:53:13,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86685 [2024-11-17 08:53:13,401 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86685 [2024-11-17 08:53:13,401 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86685 states and 123180 transitions. [2024-11-17 08:53:13,474 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:13,475 INFO L218 hiAutomatonCegarLoop]: Abstraction has 86685 states and 123180 transitions. [2024-11-17 08:53:13,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86685 states and 123180 transitions. [2024-11-17 08:53:14,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86685 to 86557. [2024-11-17 08:53:14,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86557 states, 86557 states have (on average 1.4216296775535195) internal successors, (123052), 86556 states have internal predecessors, (123052), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:14,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86557 states to 86557 states and 123052 transitions. [2024-11-17 08:53:14,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 86557 states and 123052 transitions. [2024-11-17 08:53:14,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:14,539 INFO L425 stractBuchiCegarLoop]: Abstraction has 86557 states and 123052 transitions. [2024-11-17 08:53:14,539 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:53:14,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86557 states and 123052 transitions. [2024-11-17 08:53:14,776 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 86016 [2024-11-17 08:53:14,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:14,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:14,778 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:14,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:14,778 INFO L745 eck$LassoCheckResult]: Stem: 319183#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 319184#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 318603#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 318604#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 320217#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 320048#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 320049#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 320131#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 320132#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 320311#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 318620#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 318621#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 319705#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 319811#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 319315#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 318722#L903 assume 1 == ~t11_i~0;~t11_st~0 := 0; 318723#L908 assume 1 == ~t12_i~0;~t12_st~0 := 0; 319088#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 320280#L1201-1 assume !(0 == ~M_E~0); 320281#L1206-1 assume !(0 == ~T1_E~0); 320042#L1211-1 assume !(0 == ~T2_E~0); 320043#L1216-1 assume !(0 == ~T3_E~0); 318898#L1221-1 assume !(0 == ~T4_E~0); 318899#L1226-1 assume !(0 == ~T5_E~0); 318514#L1231-1 assume !(0 == ~T6_E~0); 318515#L1236-1 assume !(0 == ~T7_E~0); 320106#L1241-1 assume !(0 == ~T8_E~0); 318945#L1246-1 assume !(0 == ~T9_E~0); 318946#L1251-1 assume !(0 == ~T10_E~0); 319127#L1256-1 assume !(0 == ~T11_E~0); 318289#L1261-1 assume !(0 == ~T12_E~0); 318290#L1266-1 assume !(0 == ~E_M~0); 320288#L1271-1 assume !(0 == ~E_1~0); 319724#L1276-1 assume !(0 == ~E_2~0); 319725#L1281-1 assume !(0 == ~E_3~0); 319679#L1286-1 assume !(0 == ~E_4~0); 318787#L1291-1 assume !(0 == ~E_5~0); 318788#L1296-1 assume !(0 == ~E_6~0); 319475#L1301-1 assume !(0 == ~E_7~0); 319476#L1306-1 assume !(0 == ~E_8~0); 319957#L1311-1 assume !(0 == ~E_9~0); 318741#L1316-1 assume !(0 == ~E_10~0); 318742#L1321-1 assume !(0 == ~E_11~0); 319491#L1326-1 assume !(0 == ~E_12~0); 319492#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 319599#L593-15 assume !(1 == ~m_pc~0); 319783#L603-15 is_master_triggered_~__retres1~0#1 := 0; 318776#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 318777#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 319414#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 319415#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 319452#L612-15 assume !(1 == ~t1_pc~0); 318813#L622-15 is_transmit1_triggered_~__retres1~1#1 := 0; 318814#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 319578#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 320295#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 318410#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 318411#L631-15 assume !(1 == ~t2_pc~0); 319530#L641-15 is_transmit2_triggered_~__retres1~2#1 := 0; 319635#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 319636#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 318577#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 318578#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 319953#L650-15 assume !(1 == ~t3_pc~0); 319954#L660-15 is_transmit3_triggered_~__retres1~3#1 := 0; 320000#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 320001#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 318778#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 318779#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 319572#L669-15 assume !(1 == ~t4_pc~0); 319573#L679-15 is_transmit4_triggered_~__retres1~4#1 := 0; 319149#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 319150#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 319893#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 319470#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 319471#L688-15 assume !(1 == ~t5_pc~0); 319579#L698-15 is_transmit5_triggered_~__retres1~5#1 := 0; 319580#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 319283#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 319136#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 319137#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 319738#L707-15 assume 1 == ~t6_pc~0; 319739#L708-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 319194#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 319195#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 319553#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 319554#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 319712#L726-15 assume 1 == ~t7_pc~0; 320232#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 319598#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 319649#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 319793#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 319794#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 320011#L745-15 assume 1 == ~t8_pc~0; 320261#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 318624#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 318625#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 318587#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 318588#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 318773#L764-15 assume 1 == ~t9_pc~0; 318774#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 319942#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 320190#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 320191#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 320199#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 318398#L783-15 assume 1 == ~t10_pc~0; 318399#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 319730#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 318926#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 318927#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 319463#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 318464#L802-15 assume 1 == ~t11_pc~0; 318465#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 318726#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 319974#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 320203#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 320202#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 319745#L821-15 assume 1 == ~t12_pc~0; 319746#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 319881#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 319333#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 318427#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 318428#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 319263#L1339-1 assume !(1 == ~M_E~0); 320178#L1344-1 assume !(1 == ~T1_E~0); 320179#L1349-1 assume !(1 == ~T2_E~0); 319484#L1354-1 assume !(1 == ~T3_E~0); 319485#L1359-1 assume !(1 == ~T4_E~0); 319892#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 318834#L1369-1 assume !(1 == ~T6_E~0); 318835#L1374-1 assume !(1 == ~T7_E~0); 319489#L1379-1 assume !(1 == ~T8_E~0); 319490#L1384-1 assume !(1 == ~T9_E~0); 319566#L1389-1 assume !(1 == ~T10_E~0); 320112#L1394-1 assume !(1 == ~T11_E~0); 320113#L1399-1 assume !(1 == ~T12_E~0); 320247#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 318949#L1409-1 assume !(1 == ~E_1~0); 318950#L1414-1 assume !(1 == ~E_2~0); 319755#L1419-1 assume !(1 == ~E_3~0); 318563#L1424-1 assume !(1 == ~E_4~0); 318564#L1429-1 assume !(1 == ~E_5~0); 319497#L1434-1 assume !(1 == ~E_6~0); 320137#L1439-1 assume !(1 == ~E_7~0); 318598#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 318599#L1449-1 assume !(1 == ~E_9~0); 319013#L1454-1 assume !(1 == ~E_10~0); 319014#L1459-1 assume !(1 == ~E_11~0); 319601#L1464-1 assume !(1 == ~E_12~0); 319402#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 319403#L1810 [2024-11-17 08:53:14,779 INFO L747 eck$LassoCheckResult]: Loop: 319403#L1810 assume true; 361943#L1810-1 assume !false; 361939#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 361938#L998 assume true; 361937#L998-1 assume !false; 361936#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 361923#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 361922#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 361921#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 361919#L1003 assume !(0 != eval_~tmp~0#1); 361920#L1006 assume true; 362915#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 362914#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 362913#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 362912#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 362911#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 362910#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 362909#L1221 assume !(0 == ~T4_E~0); 362908#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 362907#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 362906#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 362905#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 362904#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 362903#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 362902#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 362901#L1261 assume !(0 == ~T12_E~0); 362900#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 362899#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 362898#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 362897#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 362896#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 362895#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 362894#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 362893#L1301 assume !(0 == ~E_7~0); 362892#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 362891#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 362890#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 362889#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 362888#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 362887#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 362886#L593-1 assume !(1 == ~m_pc~0); 362885#L603-1 is_master_triggered_~__retres1~0#1 := 0; 362884#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 362883#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 362882#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 362881#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 362880#L612-1 assume !(1 == ~t1_pc~0); 362879#L622-1 is_transmit1_triggered_~__retres1~1#1 := 0; 362878#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 362877#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 362876#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 362875#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 362874#L631-1 assume !(1 == ~t2_pc~0); 362873#L641-1 is_transmit2_triggered_~__retres1~2#1 := 0; 362872#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 362871#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 362870#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 362869#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 362868#L650-1 assume !(1 == ~t3_pc~0); 362867#L660-1 is_transmit3_triggered_~__retres1~3#1 := 0; 362866#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 362865#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 362864#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 362863#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 362862#L669-1 assume !(1 == ~t4_pc~0); 362861#L679-1 is_transmit4_triggered_~__retres1~4#1 := 0; 362860#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 362859#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 362858#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 362857#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 362856#L688-1 assume !(1 == ~t5_pc~0); 362855#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 362854#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 362853#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 362852#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 362851#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 362850#L707-1 assume 1 == ~t6_pc~0; 362849#L708-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 362847#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 362845#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 362843#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 362841#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 362839#L726-1 assume 1 == ~t7_pc~0; 362837#L727-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 362834#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 362832#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 362830#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 362828#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 362826#L745-1 assume !(1 == ~t8_pc~0); 362823#L755-1 is_transmit8_triggered_~__retres1~8#1 := 0; 362821#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 362819#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 362817#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 362815#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 362813#L764-1 assume 1 == ~t9_pc~0; 362811#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 362808#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 362806#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 362804#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 362802#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 362800#L783-1 assume 1 == ~t10_pc~0; 362797#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 362793#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 362790#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 362787#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 362784#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 362781#L802-1 assume !(1 == ~t11_pc~0); 362777#L812-1 is_transmit11_triggered_~__retres1~11#1 := 0; 362774#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 362771#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 362767#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 362763#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 362759#L821-1 assume 1 == ~t12_pc~0; 362755#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 362750#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 362746#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 362741#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 362737#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 362733#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 362729#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 362724#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 362719#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 362713#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 362708#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 362703#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 362698#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 362693#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 362688#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 362682#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 362677#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 362672#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 362667#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 362661#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 362655#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 362648#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 362641#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 362634#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 362627#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 362619#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 362613#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 362607#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 362602#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 362598#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 362595#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 362592#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 362298#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 362283#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 362275#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 362269#L1829 assume !(0 == start_simulation_~tmp~3#1); 362264#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 362040#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 362006#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 361993#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 361982#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 361972#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 361963#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 361955#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 319403#L1810 [2024-11-17 08:53:14,779 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:14,780 INFO L85 PathProgramCache]: Analyzing trace with hash 219002465, now seen corresponding path program 1 times [2024-11-17 08:53:14,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:14,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363072022] [2024-11-17 08:53:14,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:14,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:14,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:14,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:14,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:14,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [363072022] [2024-11-17 08:53:14,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [363072022] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:14,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:14,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:14,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1774452471] [2024-11-17 08:53:14,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:14,838 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:14,838 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:14,838 INFO L85 PathProgramCache]: Analyzing trace with hash 2019337702, now seen corresponding path program 1 times [2024-11-17 08:53:14,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:14,838 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718525633] [2024-11-17 08:53:14,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:14,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:14,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:14,892 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:14,892 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:14,892 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718525633] [2024-11-17 08:53:14,892 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1718525633] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:14,892 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:14,893 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:14,893 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [761285595] [2024-11-17 08:53:14,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:14,893 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:14,893 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:14,894 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:14,894 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:14,894 INFO L87 Difference]: Start difference. First operand 86557 states and 123052 transitions. cyclomatic complexity: 36559 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:15,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:15,614 INFO L93 Difference]: Finished difference Result 166300 states and 235561 transitions. [2024-11-17 08:53:15,614 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 166300 states and 235561 transitions. [2024-11-17 08:53:16,897 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 165312 [2024-11-17 08:53:17,650 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 166300 states to 166300 states and 235561 transitions. [2024-11-17 08:53:17,650 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 166300 [2024-11-17 08:53:17,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 166300 [2024-11-17 08:53:17,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 166300 states and 235561 transitions. [2024-11-17 08:53:17,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:17,727 INFO L218 hiAutomatonCegarLoop]: Abstraction has 166300 states and 235561 transitions. [2024-11-17 08:53:17,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166300 states and 235561 transitions. [2024-11-17 08:53:19,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166300 to 166044. [2024-11-17 08:53:19,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 166044 states, 166044 states have (on average 1.4171243766712438) internal successors, (235305), 166043 states have internal predecessors, (235305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:20,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 166044 states to 166044 states and 235305 transitions. [2024-11-17 08:53:20,149 INFO L240 hiAutomatonCegarLoop]: Abstraction has 166044 states and 235305 transitions. [2024-11-17 08:53:20,149 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:20,150 INFO L425 stractBuchiCegarLoop]: Abstraction has 166044 states and 235305 transitions. [2024-11-17 08:53:20,150 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:53:20,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 166044 states and 235305 transitions. [2024-11-17 08:53:20,568 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 165056 [2024-11-17 08:53:20,569 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:20,569 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:20,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:20,571 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:20,572 INFO L745 eck$LassoCheckResult]: Stem: 572043#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 572044#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 571469#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 571470#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 573077#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 572902#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 572903#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 572990#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 572991#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 573197#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 571485#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 571486#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 572564#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 572668#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 572175#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 571589#L903 assume 1 == ~t11_i~0;~t11_st~0 := 0; 571590#L908 assume 1 == ~t12_i~0;~t12_st~0 := 0; 571952#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 573168#L1201-1 assume !(0 == ~M_E~0); 573169#L1206-1 assume !(0 == ~T1_E~0); 572896#L1211-1 assume !(0 == ~T2_E~0); 572897#L1216-1 assume !(0 == ~T3_E~0); 571759#L1221-1 assume !(0 == ~T4_E~0); 571760#L1226-1 assume !(0 == ~T5_E~0); 571379#L1231-1 assume !(0 == ~T6_E~0); 571380#L1236-1 assume !(0 == ~T7_E~0); 572965#L1241-1 assume !(0 == ~T8_E~0); 571807#L1246-1 assume !(0 == ~T9_E~0); 571808#L1251-1 assume !(0 == ~T10_E~0); 571989#L1256-1 assume !(0 == ~T11_E~0); 571153#L1261-1 assume !(0 == ~T12_E~0); 571154#L1266-1 assume !(0 == ~E_M~0); 573176#L1271-1 assume !(0 == ~E_1~0); 572583#L1276-1 assume !(0 == ~E_2~0); 572584#L1281-1 assume !(0 == ~E_3~0); 572540#L1286-1 assume !(0 == ~E_4~0); 571649#L1291-1 assume !(0 == ~E_5~0); 571650#L1296-1 assume !(0 == ~E_6~0); 572334#L1301-1 assume !(0 == ~E_7~0); 572335#L1306-1 assume !(0 == ~E_8~0); 572820#L1311-1 assume !(0 == ~E_9~0); 571604#L1316-1 assume !(0 == ~E_10~0); 571605#L1321-1 assume !(0 == ~E_11~0); 572351#L1326-1 assume !(0 == ~E_12~0); 572352#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 572461#L593-15 assume !(1 == ~m_pc~0); 572638#L603-15 is_master_triggered_~__retres1~0#1 := 0; 571639#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 571640#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 572271#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 572272#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 572308#L612-15 assume !(1 == ~t1_pc~0); 571676#L622-15 is_transmit1_triggered_~__retres1~1#1 := 0; 571677#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 572439#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 573189#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 571277#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 571278#L631-15 assume !(1 == ~t2_pc~0); 572386#L641-15 is_transmit2_triggered_~__retres1~2#1 := 0; 572492#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 572493#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 571443#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 571444#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 572816#L650-15 assume !(1 == ~t3_pc~0); 572817#L660-15 is_transmit3_triggered_~__retres1~3#1 := 0; 572859#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 572860#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 571641#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 571642#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 572434#L669-15 assume !(1 == ~t4_pc~0); 572435#L679-15 is_transmit4_triggered_~__retres1~4#1 := 0; 572012#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 572013#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 572750#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 572329#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 572330#L688-15 assume !(1 == ~t5_pc~0); 572440#L698-15 is_transmit5_triggered_~__retres1~5#1 := 0; 572441#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 572141#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 572000#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 572001#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 572596#L707-15 assume !(1 == ~t6_pc~0); 572241#L717-15 is_transmit6_triggered_~__retres1~6#1 := 0; 572056#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 572057#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 572413#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 572414#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 572572#L726-15 assume 1 == ~t7_pc~0; 573104#L727-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 572460#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 572508#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 572649#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 572650#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 572870#L745-15 assume 1 == ~t8_pc~0; 573138#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 571489#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 571490#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 571452#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 571453#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 571636#L764-15 assume 1 == ~t9_pc~0; 571637#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 572801#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 573052#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 573053#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 573062#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 571264#L783-15 assume 1 == ~t10_pc~0; 571265#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 572590#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 571789#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 571790#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 572321#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 571329#L802-15 assume 1 == ~t11_pc~0; 571330#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 571593#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 572835#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 573065#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 573064#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 572602#L821-15 assume 1 == ~t12_pc~0; 572603#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 572740#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 572191#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 571291#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 571292#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 572119#L1339-1 assume !(1 == ~M_E~0); 573044#L1344-1 assume !(1 == ~T1_E~0); 573045#L1349-1 assume !(1 == ~T2_E~0); 572342#L1354-1 assume !(1 == ~T3_E~0); 572343#L1359-1 assume !(1 == ~T4_E~0); 572749#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 571696#L1369-1 assume !(1 == ~T6_E~0); 571697#L1374-1 assume !(1 == ~T7_E~0); 572349#L1379-1 assume !(1 == ~T8_E~0); 572350#L1384-1 assume !(1 == ~T9_E~0); 572427#L1389-1 assume !(1 == ~T10_E~0); 572970#L1394-1 assume !(1 == ~T11_E~0); 572971#L1399-1 assume !(1 == ~T12_E~0); 573122#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 571811#L1409-1 assume !(1 == ~E_1~0); 571812#L1414-1 assume !(1 == ~E_2~0); 572610#L1419-1 assume !(1 == ~E_3~0); 571427#L1424-1 assume !(1 == ~E_4~0); 571428#L1429-1 assume !(1 == ~E_5~0); 572357#L1434-1 assume !(1 == ~E_6~0); 572997#L1439-1 assume !(1 == ~E_7~0); 571464#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 571465#L1449-1 assume !(1 == ~E_9~0); 571876#L1454-1 assume !(1 == ~E_10~0); 571877#L1459-1 assume !(1 == ~E_11~0); 572463#L1464-1 assume !(1 == ~E_12~0); 572259#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 572260#L1810 [2024-11-17 08:53:20,574 INFO L747 eck$LassoCheckResult]: Loop: 572260#L1810 assume true; 642556#L1810-1 assume !false; 641959#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 641957#L998 assume true; 641955#L998-1 assume !false; 641953#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 641925#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 641922#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 641920#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 641917#L1003 assume !(0 != eval_~tmp~0#1); 641918#L1006 assume true; 643060#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 643059#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 643058#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 643057#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 643056#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 643055#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 643054#L1221 assume !(0 == ~T4_E~0); 643053#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 643052#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 643051#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 643050#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 643049#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 643048#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 643047#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 643046#L1261 assume !(0 == ~T12_E~0); 643044#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 643041#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 643039#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 643037#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 643035#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 643033#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 643031#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 643029#L1301 assume !(0 == ~E_7~0); 643027#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 643025#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 643023#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 643021#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 643019#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 643016#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 643014#L593-1 assume !(1 == ~m_pc~0); 643012#L603-1 is_master_triggered_~__retres1~0#1 := 0; 643010#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 643008#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 643006#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 643004#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 643002#L612-1 assume !(1 == ~t1_pc~0); 643000#L622-1 is_transmit1_triggered_~__retres1~1#1 := 0; 642998#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 642996#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 642994#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 642991#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 642989#L631-1 assume !(1 == ~t2_pc~0); 642987#L641-1 is_transmit2_triggered_~__retres1~2#1 := 0; 642985#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 642983#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 642981#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 642979#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 642977#L650-1 assume !(1 == ~t3_pc~0); 642975#L660-1 is_transmit3_triggered_~__retres1~3#1 := 0; 642973#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 642971#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 642969#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 642967#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 642965#L669-1 assume !(1 == ~t4_pc~0); 642963#L679-1 is_transmit4_triggered_~__retres1~4#1 := 0; 642961#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 642959#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 642957#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 642954#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 642952#L688-1 assume !(1 == ~t5_pc~0); 642950#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 642948#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 642946#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 642944#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 642941#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 642939#L707-1 assume !(1 == ~t6_pc~0); 642937#L717-1 is_transmit6_triggered_~__retres1~6#1 := 0; 642935#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 642933#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 642931#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 642928#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 642926#L726-1 assume !(1 == ~t7_pc~0); 642923#L736-1 is_transmit7_triggered_~__retres1~7#1 := 0; 642921#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 642919#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 642917#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 642914#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 642912#L745-1 assume !(1 == ~t8_pc~0); 642909#L755-1 is_transmit8_triggered_~__retres1~8#1 := 0; 642907#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 642905#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 642903#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 642900#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 642898#L764-1 assume !(1 == ~t9_pc~0); 642895#L774-1 is_transmit9_triggered_~__retres1~9#1 := 0; 642893#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 642891#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 642889#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 642886#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 642884#L783-1 assume !(1 == ~t10_pc~0); 642881#L793-1 is_transmit10_triggered_~__retres1~10#1 := 0; 642879#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 642877#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 642876#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 642875#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 642872#L802-1 assume 1 == ~t11_pc~0; 642869#L803-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 642866#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 642864#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 642862#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 642860#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 642859#L821-1 assume 1 == ~t12_pc~0; 642856#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 642852#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 642848#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 642844#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 642840#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 642836#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 642835#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 642834#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 642833#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 642832#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 642831#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 642830#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 642829#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 642828#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 642827#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 642826#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 642825#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 642824#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 642823#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 642822#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 642821#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 642820#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 642819#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 642818#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 642817#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 642815#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 642813#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 642811#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 642809#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 642807#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 642805#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 642803#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 642795#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 642784#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 642782#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 642599#L1829 assume !(0 == start_simulation_~tmp~3#1); 642597#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 642580#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 642570#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 642565#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 642563#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 642561#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 642559#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 642558#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 572260#L1810 [2024-11-17 08:53:20,578 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:20,579 INFO L85 PathProgramCache]: Analyzing trace with hash -981250780, now seen corresponding path program 1 times [2024-11-17 08:53:20,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:20,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688714628] [2024-11-17 08:53:20,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:20,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:20,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:20,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:20,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:20,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688714628] [2024-11-17 08:53:20,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688714628] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:20,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:20,705 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:20,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [405420890] [2024-11-17 08:53:20,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:20,705 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:20,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:20,705 INFO L85 PathProgramCache]: Analyzing trace with hash 700292975, now seen corresponding path program 1 times [2024-11-17 08:53:20,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:20,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654954770] [2024-11-17 08:53:20,706 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:20,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:20,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:20,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:20,749 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:20,749 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654954770] [2024-11-17 08:53:20,749 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654954770] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:20,749 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:20,749 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:20,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132634248] [2024-11-17 08:53:20,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:20,750 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:20,751 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:20,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:20,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:20,751 INFO L87 Difference]: Start difference. First operand 166044 states and 235305 transitions. cyclomatic complexity: 69389 Second operand has 4 states, 4 states have (on average 37.5) internal successors, (150), 3 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:22,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:22,904 INFO L93 Difference]: Finished difference Result 397275 states and 560294 transitions. [2024-11-17 08:53:22,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 397275 states and 560294 transitions. [2024-11-17 08:53:25,066 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 394368 [2024-11-17 08:53:26,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 397275 states to 397275 states and 560294 transitions. [2024-11-17 08:53:26,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 397275 [2024-11-17 08:53:26,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 397275 [2024-11-17 08:53:26,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 397275 states and 560294 transitions. [2024-11-17 08:53:27,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:27,073 INFO L218 hiAutomatonCegarLoop]: Abstraction has 397275 states and 560294 transitions. [2024-11-17 08:53:27,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 397275 states and 560294 transitions. [2024-11-17 08:53:30,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 397275 to 318363. [2024-11-17 08:53:30,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 318363 states, 318363 states have (on average 1.4131478846473993) internal successors, (449894), 318362 states have internal predecessors, (449894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:32,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318363 states to 318363 states and 449894 transitions. [2024-11-17 08:53:32,210 INFO L240 hiAutomatonCegarLoop]: Abstraction has 318363 states and 449894 transitions. [2024-11-17 08:53:32,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:32,219 INFO L425 stractBuchiCegarLoop]: Abstraction has 318363 states and 449894 transitions. [2024-11-17 08:53:32,219 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:53:32,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318363 states and 449894 transitions. [2024-11-17 08:53:33,311 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 316544 [2024-11-17 08:53:33,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:33,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:33,316 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:33,316 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:33,316 INFO L745 eck$LassoCheckResult]: Stem: 1135373#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(20, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~token~0 := 0;~local~0 := 0; 1135374#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1; 1134801#L1773 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1134802#L841-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1136322#L848 assume 1 == ~m_i~0;~m_st~0 := 0; 1136172#L853 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1136173#L858 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1136246#L863 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1136247#L868 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1136405#L873 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1134818#L878 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1134819#L883 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1135867#L888 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1135963#L893 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1135499#L898 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1134921#L903 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1134922#L908 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1135285#L914 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1136384#L1201-1 assume !(0 == ~M_E~0); 1136385#L1206-1 assume !(0 == ~T1_E~0); 1136166#L1211-1 assume !(0 == ~T2_E~0); 1136167#L1216-1 assume !(0 == ~T3_E~0); 1135094#L1221-1 assume !(0 == ~T4_E~0); 1135095#L1226-1 assume !(0 == ~T5_E~0); 1134709#L1231-1 assume !(0 == ~T6_E~0); 1134710#L1236-1 assume !(0 == ~T7_E~0); 1136224#L1241-1 assume !(0 == ~T8_E~0); 1135144#L1246-1 assume !(0 == ~T9_E~0); 1135145#L1251-1 assume !(0 == ~T10_E~0); 1135320#L1256-1 assume !(0 == ~T11_E~0); 1134484#L1261-1 assume !(0 == ~T12_E~0); 1134485#L1266-1 assume !(0 == ~E_M~0); 1136389#L1271-1 assume !(0 == ~E_1~0); 1135884#L1276-1 assume !(0 == ~E_2~0); 1135885#L1281-1 assume !(0 == ~E_3~0); 1135843#L1286-1 assume !(0 == ~E_4~0); 1134985#L1291-1 assume !(0 == ~E_5~0); 1134986#L1296-1 assume !(0 == ~E_6~0); 1135651#L1301-1 assume !(0 == ~E_7~0); 1135652#L1306-1 assume !(0 == ~E_8~0); 1136102#L1311-1 assume !(0 == ~E_9~0); 1134938#L1316-1 assume !(0 == ~E_10~0); 1134939#L1321-1 assume !(0 == ~E_11~0); 1135666#L1326-1 assume !(0 == ~E_12~0); 1135667#L1332-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1135771#L593-15 assume !(1 == ~m_pc~0); 1135933#L603-15 is_master_triggered_~__retres1~0#1 := 0; 1134973#L596-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1134974#L605-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1135592#L1492-15 assume !(0 != activate_threads_~tmp~1#1); 1135593#L1498-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1135629#L612-15 assume !(1 == ~t1_pc~0); 1135012#L622-15 is_transmit1_triggered_~__retres1~1#1 := 0; 1135013#L615-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1135750#L624-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1136396#L1500-15 assume !(0 != activate_threads_~tmp___0~0#1); 1134604#L1506-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1134605#L631-15 assume !(1 == ~t2_pc~0); 1135705#L641-15 is_transmit2_triggered_~__retres1~2#1 := 0; 1135800#L634-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1135801#L643-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1134774#L1508-15 assume !(0 != activate_threads_~tmp___1~0#1); 1134775#L1514-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1136098#L650-15 assume !(1 == ~t3_pc~0); 1136099#L660-15 is_transmit3_triggered_~__retres1~3#1 := 0; 1136135#L653-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1136136#L662-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1134975#L1516-15 assume !(0 != activate_threads_~tmp___2~0#1); 1134976#L1522-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1135745#L669-15 assume !(1 == ~t4_pc~0); 1135746#L679-15 is_transmit4_triggered_~__retres1~4#1 := 0; 1135342#L672-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1135343#L681-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1136042#L1524-15 assume !(0 != activate_threads_~tmp___3~0#1); 1135645#L1530-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1135646#L688-15 assume !(1 == ~t5_pc~0); 1135751#L698-15 is_transmit5_triggered_~__retres1~5#1 := 0; 1135752#L691-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1135467#L700-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1135329#L1532-15 assume !(0 != activate_threads_~tmp___4~0#1); 1135330#L1538-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1135892#L707-15 assume !(1 == ~t6_pc~0); 1135562#L717-15 is_transmit6_triggered_~__retres1~6#1 := 0; 1135385#L710-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1135386#L719-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1135729#L1540-15 assume !(0 != activate_threads_~tmp___5~0#1); 1135730#L1546-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1135875#L726-15 assume !(1 == ~t7_pc~0); 1135769#L736-15 is_transmit7_triggered_~__retres1~7#1 := 0; 1135770#L729-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1135814#L738-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1135942#L1548-15 assume !(0 != activate_threads_~tmp___6~0#1); 1135943#L1554-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1136145#L745-15 assume 1 == ~t8_pc~0; 1136364#L746-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1134822#L748-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1134823#L757-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1134783#L1556-15 assume !(0 != activate_threads_~tmp___7~0#1); 1134784#L1562-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1134970#L764-15 assume 1 == ~t9_pc~0; 1134971#L765-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1136088#L767-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1136297#L776-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1136298#L1564-15 assume !(0 != activate_threads_~tmp___8~0#1); 1136310#L1570-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1134592#L783-15 assume 1 == ~t10_pc~0; 1134593#L784-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1135888#L786-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1135125#L795-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1135126#L1572-15 assume !(0 != activate_threads_~tmp___9~0#1); 1135638#L1578-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1134658#L802-15 assume 1 == ~t11_pc~0; 1134659#L803-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1134925#L805-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1136116#L814-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1136313#L1580-15 assume !(0 != activate_threads_~tmp___10~0#1); 1136312#L1586-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1135898#L821-15 assume 1 == ~t12_pc~0; 1135899#L822-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1136030#L824-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1135515#L833-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1134620#L1588-15 assume !(0 != activate_threads_~tmp___11~0#1); 1134621#L1594-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1135448#L1339-1 assume !(1 == ~M_E~0); 1136290#L1344-1 assume !(1 == ~T1_E~0); 1136291#L1349-1 assume !(1 == ~T2_E~0); 1135659#L1354-1 assume !(1 == ~T3_E~0); 1135660#L1359-1 assume !(1 == ~T4_E~0); 1136040#L1364-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1135031#L1369-1 assume !(1 == ~T6_E~0); 1135032#L1374-1 assume !(1 == ~T7_E~0); 1135664#L1379-1 assume !(1 == ~T8_E~0); 1135665#L1384-1 assume !(1 == ~T9_E~0); 1135738#L1389-1 assume !(1 == ~T10_E~0); 1136230#L1394-1 assume !(1 == ~T11_E~0); 1136231#L1399-1 assume !(1 == ~T12_E~0); 1136350#L1404-1 assume 1 == ~E_M~0;~E_M~0 := 2; 1135148#L1409-1 assume !(1 == ~E_1~0); 1135149#L1414-1 assume !(1 == ~E_2~0); 1135906#L1419-1 assume !(1 == ~E_3~0); 1134759#L1424-1 assume !(1 == ~E_4~0); 1134760#L1429-1 assume !(1 == ~E_5~0); 1135672#L1434-1 assume !(1 == ~E_6~0); 1136252#L1439-1 assume !(1 == ~E_7~0); 1134796#L1444-1 assume 1 == ~E_8~0;~E_8~0 := 2; 1134797#L1449-1 assume !(1 == ~E_9~0); 1135213#L1454-1 assume !(1 == ~E_10~0); 1135214#L1459-1 assume !(1 == ~E_11~0); 1135773#L1464-1 assume !(1 == ~E_12~0); 1135581#L1470-1 assume true;assume { :end_inline_reset_delta_events } true; 1135582#L1810 [2024-11-17 08:53:33,317 INFO L747 eck$LassoCheckResult]: Loop: 1135582#L1810 assume true; 1268202#L1810-1 assume !false; 1267783#start_simulation_while_14_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1267782#L998 assume true; 1267780#L998-1 assume !false; 1267777#eval_while_13_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1267751#L921-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1267749#L971-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1267747#L989-2 assume true;eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1267744#L1003 assume !(0 != eval_~tmp~0#1); 1267745#L1006 assume true; 1268648#L1194 assume true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1268646#L841 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1268645#L1201 assume 0 == ~M_E~0;~M_E~0 := 1; 1268643#L1206 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1268641#L1211 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1268639#L1216 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1268637#L1221 assume !(0 == ~T4_E~0); 1268635#L1226 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1268632#L1231 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1268630#L1236 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1268628#L1241 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1268626#L1246 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1268624#L1251 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1268622#L1256 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1268619#L1261 assume !(0 == ~T12_E~0); 1268617#L1266 assume 0 == ~E_M~0;~E_M~0 := 1; 1268615#L1271 assume 0 == ~E_1~0;~E_1~0 := 1; 1268613#L1276 assume 0 == ~E_2~0;~E_2~0 := 1; 1268611#L1281 assume 0 == ~E_3~0;~E_3~0 := 1; 1268609#L1286 assume 0 == ~E_4~0;~E_4~0 := 1; 1268606#L1291 assume 0 == ~E_5~0;~E_5~0 := 1; 1268604#L1296 assume 0 == ~E_6~0;~E_6~0 := 1; 1268602#L1301 assume !(0 == ~E_7~0); 1268600#L1306 assume 0 == ~E_8~0;~E_8~0 := 1; 1268598#L1311 assume 0 == ~E_9~0;~E_9~0 := 1; 1268596#L1316 assume 0 == ~E_10~0;~E_10~0 := 1; 1268593#L1321 assume 0 == ~E_11~0;~E_11~0 := 1; 1268591#L1326 assume 0 == ~E_12~0;~E_12~0 := 1; 1268589#L1332 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1268587#L593-1 assume !(1 == ~m_pc~0); 1268585#L603-1 is_master_triggered_~__retres1~0#1 := 0; 1268583#L596-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1268580#L605-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1268578#L1492-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1268576#L1498-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1268574#L612-1 assume !(1 == ~t1_pc~0); 1268572#L622-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1268570#L615-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1268568#L624-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1268566#L1500-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1268564#L1506-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1268562#L631-1 assume !(1 == ~t2_pc~0); 1268560#L641-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1268558#L634-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1268556#L643-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1268554#L1508-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1268552#L1514-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1268550#L650-1 assume !(1 == ~t3_pc~0); 1268548#L660-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1268546#L653-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1268544#L662-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1268542#L1516-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1268540#L1522-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1268538#L669-1 assume !(1 == ~t4_pc~0); 1268536#L679-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1268534#L672-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1268532#L681-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1268530#L1524-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1268528#L1530-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1268526#L688-1 assume !(1 == ~t5_pc~0); 1268524#L698-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1268522#L691-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1268520#L700-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1268518#L1532-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1268517#L1538-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1268516#L707-1 assume !(1 == ~t6_pc~0); 1268515#L717-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1268501#L710-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1268499#L719-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1268497#L1540-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1268496#L1546-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1268495#L726-1 assume !(1 == ~t7_pc~0); 1176258#L736-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1268494#L729-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1268493#L738-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1268492#L1548-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1268491#L1554-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1268490#L745-1 assume 1 == ~t8_pc~0; 1268489#L746-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1268487#L748-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1268486#L757-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1268485#L1556-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1268484#L1562-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1268483#L764-1 assume 1 == ~t9_pc~0; 1268482#L765-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1268480#L767-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1268479#L776-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1268478#L1564-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1268477#L1570-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1268476#L783-1 assume 1 == ~t10_pc~0; 1268475#L784-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1268473#L786-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1268472#L795-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1268471#L1572-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1268470#L1578-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1268469#L802-1 assume !(1 == ~t11_pc~0); 1268467#L812-1 is_transmit11_triggered_~__retres1~11#1 := 0; 1268466#L805-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1268465#L814-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1268464#L1580-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1268463#L1586-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1268462#L821-1 assume 1 == ~t12_pc~0; 1268461#L822-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1268459#L824-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1268458#L833-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1268456#L1588-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1268454#L1594-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1268452#L1339 assume 1 == ~M_E~0;~M_E~0 := 2; 1268450#L1344 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1268448#L1349 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1268446#L1354 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1268444#L1359 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1268442#L1364 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1268440#L1369 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1268438#L1374 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1268436#L1379 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1268434#L1384 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1268432#L1389 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1268430#L1394 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1268428#L1399 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1268426#L1404 assume 1 == ~E_M~0;~E_M~0 := 2; 1268424#L1409 assume 1 == ~E_1~0;~E_1~0 := 2; 1268422#L1414 assume 1 == ~E_2~0;~E_2~0 := 2; 1268420#L1419 assume 1 == ~E_3~0;~E_3~0 := 2; 1268418#L1424 assume 1 == ~E_4~0;~E_4~0 := 2; 1268416#L1429 assume 1 == ~E_5~0;~E_5~0 := 2; 1268414#L1434 assume 1 == ~E_6~0;~E_6~0 := 2; 1268412#L1439 assume 1 == ~E_7~0;~E_7~0 := 2; 1268410#L1444 assume 1 == ~E_8~0;~E_8~0 := 2; 1268408#L1449 assume 1 == ~E_9~0;~E_9~0 := 2; 1268406#L1454 assume 1 == ~E_10~0;~E_10~0 := 2; 1268404#L1459 assume 1 == ~E_11~0;~E_11~0 := 2; 1268402#L1464 assume 1 == ~E_12~0;~E_12~0 := 2; 1268400#L1470 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1268392#L921-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1268381#L971-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1268379#L989-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1268242#L1829 assume !(0 == start_simulation_~tmp~3#1); 1268240#L1840 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1; 1268225#L921 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1; 1268216#L971 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1; 1268214#L989 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1268212#L1784 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1268210#L1786 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1268208#L1792 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1268205#L1842 assume !(0 != start_simulation_~tmp___0~1#1); 1135582#L1810 [2024-11-17 08:53:33,320 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:33,320 INFO L85 PathProgramCache]: Analyzing trace with hash -1869221337, now seen corresponding path program 1 times [2024-11-17 08:53:33,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:33,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1733399717] [2024-11-17 08:53:33,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:33,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:33,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:33,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:33,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:33,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1733399717] [2024-11-17 08:53:33,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1733399717] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:33,379 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:33,379 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:33,379 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1497112057] [2024-11-17 08:53:33,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:33,379 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:33,380 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:33,380 INFO L85 PathProgramCache]: Analyzing trace with hash -481963543, now seen corresponding path program 1 times [2024-11-17 08:53:33,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:33,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436771109] [2024-11-17 08:53:33,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:33,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:33,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:33,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:33,444 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:33,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [436771109] [2024-11-17 08:53:33,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [436771109] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:33,444 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:33,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:33,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [754984026] [2024-11-17 08:53:33,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:33,445 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:33,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:33,445 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:33,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:33,446 INFO L87 Difference]: Start difference. First operand 318363 states and 449894 transitions. cyclomatic complexity: 131659 Second operand has 3 states, 3 states have (on average 50.0) internal successors, (150), 2 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:35,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:35,838 INFO L93 Difference]: Finished difference Result 610714 states and 860387 transitions. [2024-11-17 08:53:35,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 610714 states and 860387 transitions. [2024-11-17 08:53:39,407 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 606720 [2024-11-17 08:53:41,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 610714 states to 610714 states and 860387 transitions. [2024-11-17 08:53:41,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 610714 [2024-11-17 08:53:41,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 610714 [2024-11-17 08:53:41,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 610714 states and 860387 transitions. [2024-11-17 08:53:41,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:41,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 610714 states and 860387 transitions. [2024-11-17 08:53:42,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 610714 states and 860387 transitions.