./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:53:33,389 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:53:33,467 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:53:33,475 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:53:33,476 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:53:33,476 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:53:33,512 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:53:33,514 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:53:33,515 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:53:33,516 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:53:33,517 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:53:33,518 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:53:33,518 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:53:33,519 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:53:33,520 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:53:33,520 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:53:33,520 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:53:33,520 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:53:33,521 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:53:33,521 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:53:33,521 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:53:33,524 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:53:33,524 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:53:33,524 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:53:33,525 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:53:33,525 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:53:33,525 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:53:33,526 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:53:33,526 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:53:33,526 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:53:33,526 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:53:33,527 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:53:33,527 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:53:33,527 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:53:33,528 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:53:33,528 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:53:33,528 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:53:33,528 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:53:33,528 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:53:33,529 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:53:33,529 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2024-11-17 08:53:33,790 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:53:33,820 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:53:33,823 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:53:33,825 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:53:33,826 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:53:33,827 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.02.cil.c [2024-11-17 08:53:35,313 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:53:35,516 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:53:35,518 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.02.cil.c [2024-11-17 08:53:35,528 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/af0b492de/1e6237f9ed7143c3b7b66a3155740f75/FLAG15cf24916 [2024-11-17 08:53:35,883 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/af0b492de/1e6237f9ed7143c3b7b66a3155740f75 [2024-11-17 08:53:35,886 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:53:35,887 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:53:35,888 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:35,888 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:53:35,894 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:53:35,895 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:35" (1/1) ... [2024-11-17 08:53:35,896 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@23d7e0f3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:35, skipping insertion in model container [2024-11-17 08:53:35,896 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:35" (1/1) ... [2024-11-17 08:53:35,937 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:53:36,154 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:36,171 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:53:36,211 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:36,246 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:53:36,246 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36 WrapperNode [2024-11-17 08:53:36,247 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:36,248 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:36,248 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:53:36,248 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:53:36,255 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,269 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,324 INFO L138 Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 45, statements flattened = 530 [2024-11-17 08:53:36,324 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:36,325 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:53:36,325 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:53:36,325 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:53:36,337 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,338 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,341 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,360 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:53:36,361 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,362 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,370 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,371 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,373 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,375 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,379 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:53:36,380 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:53:36,380 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:53:36,380 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:53:36,381 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (1/1) ... [2024-11-17 08:53:36,390 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:53:36,407 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:53:36,426 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:53:36,433 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:53:36,482 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:53:36,483 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:53:36,483 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:53:36,483 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:53:36,566 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:53:36,569 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:53:37,178 INFO L? ?]: Removed 90 outVars from TransFormulas that were not future-live. [2024-11-17 08:53:37,178 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:53:37,198 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:53:37,198 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:53:37,199 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:37 BoogieIcfgContainer [2024-11-17 08:53:37,199 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:53:37,200 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:53:37,200 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:53:37,204 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:53:37,205 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:37,206 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:53:35" (1/3) ... [2024-11-17 08:53:37,207 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4fdc68e0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:37, skipping insertion in model container [2024-11-17 08:53:37,207 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:37,207 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:36" (2/3) ... [2024-11-17 08:53:37,207 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4fdc68e0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:37, skipping insertion in model container [2024-11-17 08:53:37,208 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:37,208 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:37" (3/3) ... [2024-11-17 08:53:37,209 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2024-11-17 08:53:37,277 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:53:37,277 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:53:37,277 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:53:37,278 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:53:37,278 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:53:37,279 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:53:37,279 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:53:37,279 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:53:37,285 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 228 states, 227 states have (on average 1.4845814977973568) internal successors, (337), 227 states have internal predecessors, (337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:37,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2024-11-17 08:53:37,320 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:37,320 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:37,329 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:37,329 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:37,330 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:53:37,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 228 states, 227 states have (on average 1.4845814977973568) internal successors, (337), 227 states have internal predecessors, (337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:37,342 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 182 [2024-11-17 08:53:37,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:37,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:37,344 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:37,345 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:37,353 INFO L745 eck$LassoCheckResult]: Stem: 216#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 27#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3#L491true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71#L214-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 188#L221true assume 1 == ~m_i~0;~m_st~0 := 0; 11#L226true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 70#L231true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 204#L237true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 152#L334-1true assume !(0 == ~M_E~0); 101#L339-1true assume !(0 == ~T1_E~0); 98#L344-1true assume !(0 == ~T2_E~0); 138#L349-1true assume !(0 == ~E_1~0); 42#L354-1true assume 0 == ~E_2~0;~E_2~0 := 1; 198#L360-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 192#L156-4true assume 1 == ~m_pc~0; 213#L157-4true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 167#L159-4true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 183#L168-4true assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 127#L405-4true assume !(0 != activate_threads_~tmp~1#1); 20#L411-4true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 228#L175-4true assume !(1 == ~t1_pc~0); 180#L185-4true is_transmit1_triggered_~__retres1~1#1 := 0; 74#L178-4true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 207#L187-4true assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 122#L413-4true assume !(0 != activate_threads_~tmp___0~0#1); 87#L419-4true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132#L194-4true assume 1 == ~t2_pc~0; 226#L195-4true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 200#L197-4true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81#L206-4true assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 190#L421-4true assume !(0 != activate_threads_~tmp___1~0#1); 25#L427-4true assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 203#L367-1true assume !(1 == ~M_E~0); 125#L372-1true assume !(1 == ~T1_E~0); 129#L377-1true assume !(1 == ~T2_E~0); 24#L382-1true assume !(1 == ~E_1~0); 75#L387-1true assume !(1 == ~E_2~0); 111#L393-1true assume true;assume { :end_inline_reset_delta_events } true; 156#L528true [2024-11-17 08:53:37,355 INFO L747 eck$LassoCheckResult]: Loop: 156#L528true assume true; 51#L528-1true assume !false; 34#start_simulation_while_5_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 144#L271true assume !true; 55#L279true assume true; 131#L327true assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 222#L214true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35#L334true assume 0 == ~M_E~0;~M_E~0 := 1; 112#L339true assume 0 == ~T1_E~0;~T1_E~0 := 1; 32#L344true assume 0 == ~T2_E~0;~T2_E~0 := 1; 77#L349true assume 0 == ~E_1~0;~E_1~0 := 1; 163#L354true assume 0 == ~E_2~0;~E_2~0 := 1; 17#L360true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91#L156-1true assume !(1 == ~m_pc~0); 179#L166-1true is_master_triggered_~__retres1~0#1 := 0; 208#L159-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107#L168-1true assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 72#L405-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 147#L411-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 220#L175-1true assume !(1 == ~t1_pc~0); 214#L185-1true is_transmit1_triggered_~__retres1~1#1 := 0; 210#L178-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 202#L187-1true assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 135#L413-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 108#L419-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7#L194-1true assume !(1 == ~t2_pc~0); 164#L204-1true is_transmit2_triggered_~__retres1~2#1 := 0; 13#L197-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 184#L206-1true assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 195#L421-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 63#L427-1true assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15#L367true assume 1 == ~M_E~0;~M_E~0 := 2; 146#L372true assume 1 == ~T1_E~0;~T1_E~0 := 2; 116#L377true assume 1 == ~T2_E~0;~T2_E~0 := 2; 102#L382true assume 1 == ~E_1~0;~E_1~0 := 2; 160#L387true assume 1 == ~E_2~0;~E_2~0 := 2; 130#L393true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 139#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10#L254-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 26#L262-1true assume true;start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 151#L547true assume !(0 == start_simulation_~tmp~3#1); 115#L558true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 9#L244true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 54#L254true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 165#L262true assume true;stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 41#L502true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 177#L504true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 185#L510true assume true;start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 21#L560true assume !(0 != start_simulation_~tmp___0~1#1); 156#L528true [2024-11-17 08:53:37,361 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:37,362 INFO L85 PathProgramCache]: Analyzing trace with hash -193741385, now seen corresponding path program 1 times [2024-11-17 08:53:37,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:37,370 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764315733] [2024-11-17 08:53:37,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:37,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:37,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:37,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:37,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:37,603 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764315733] [2024-11-17 08:53:37,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764315733] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:37,604 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:37,604 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:37,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769497523] [2024-11-17 08:53:37,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:37,611 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:37,613 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:37,613 INFO L85 PathProgramCache]: Analyzing trace with hash -133971478, now seen corresponding path program 1 times [2024-11-17 08:53:37,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:37,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815505607] [2024-11-17 08:53:37,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:37,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:37,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:37,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:37,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:37,656 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815505607] [2024-11-17 08:53:37,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815505607] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:37,656 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:37,657 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:37,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [716355943] [2024-11-17 08:53:37,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:37,658 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:37,659 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:37,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:37,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:37,690 INFO L87 Difference]: Start difference. First operand has 228 states, 227 states have (on average 1.4845814977973568) internal successors, (337), 227 states have internal predecessors, (337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:37,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:37,727 INFO L93 Difference]: Finished difference Result 222 states and 317 transitions. [2024-11-17 08:53:37,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 222 states and 317 transitions. [2024-11-17 08:53:37,732 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2024-11-17 08:53:37,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 222 states to 215 states and 310 transitions. [2024-11-17 08:53:37,739 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 215 [2024-11-17 08:53:37,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 215 [2024-11-17 08:53:37,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 215 states and 310 transitions. [2024-11-17 08:53:37,741 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:37,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 215 states and 310 transitions. [2024-11-17 08:53:37,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states and 310 transitions. [2024-11-17 08:53:37,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 215. [2024-11-17 08:53:37,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 215 states, 215 states have (on average 1.441860465116279) internal successors, (310), 214 states have internal predecessors, (310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:37,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 310 transitions. [2024-11-17 08:53:37,774 INFO L240 hiAutomatonCegarLoop]: Abstraction has 215 states and 310 transitions. [2024-11-17 08:53:37,776 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:37,779 INFO L425 stractBuchiCegarLoop]: Abstraction has 215 states and 310 transitions. [2024-11-17 08:53:37,779 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:53:37,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 215 states and 310 transitions. [2024-11-17 08:53:37,781 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2024-11-17 08:53:37,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:37,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:37,783 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:37,783 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:37,784 INFO L745 eck$LassoCheckResult]: Stem: 673#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 514#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 462#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 463#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 583#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 480#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 481#L231 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 582#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 658#L334-1 assume !(0 == ~M_E~0); 619#L339-1 assume !(0 == ~T1_E~0); 613#L344-1 assume !(0 == ~T2_E~0); 614#L349-1 assume !(0 == ~E_1~0); 541#L354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 542#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 668#L156-4 assume 1 == ~m_pc~0; 669#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 526#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 661#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 643#L405-4 assume !(0 != activate_threads_~tmp~1#1); 500#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 501#L175-4 assume !(1 == ~t1_pc~0); 664#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 588#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 589#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 636#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 602#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 603#L194-4 assume 1 == ~t2_pc~0; 647#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 609#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 593#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 594#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 511#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 512#L367-1 assume !(1 == ~M_E~0); 639#L372-1 assume !(1 == ~T1_E~0); 640#L377-1 assume !(1 == ~T2_E~0); 509#L382-1 assume !(1 == ~E_1~0); 510#L387-1 assume !(1 == ~E_2~0); 590#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 503#L528 [2024-11-17 08:53:37,785 INFO L747 eck$LassoCheckResult]: Loop: 503#L528 assume true; 559#L528-1 assume !false; 527#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 497#L271 assume true; 504#L271-1 assume !false; 505#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 655#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 515#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 516#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 459#L276 assume !(0 != eval_~tmp~0#1); 461#L279 assume true; 563#L327 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 646#L214 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 528#L334 assume 0 == ~M_E~0;~M_E~0 := 1; 529#L339 assume 0 == ~T1_E~0;~T1_E~0 := 1; 523#L344 assume 0 == ~T2_E~0;~T2_E~0 := 1; 524#L349 assume 0 == ~E_1~0;~E_1~0 := 1; 591#L354 assume 0 == ~E_2~0;~E_2~0 := 1; 493#L360 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 494#L156-1 assume 1 == ~m_pc~0; 490#L157-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 492#L159-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 624#L168-1 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 584#L405-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 585#L411-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 654#L175-1 assume 1 == ~t1_pc~0; 506#L176-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 507#L178-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 670#L187-1 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 650#L413-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 625#L419-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 471#L194-1 assume 1 == ~t2_pc~0; 472#L195-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 484#L197-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 485#L206-1 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 667#L421-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 571#L427-1 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 488#L367 assume 1 == ~M_E~0;~M_E~0 := 2; 489#L372 assume 1 == ~T1_E~0;~T1_E~0 := 2; 630#L377 assume 1 == ~T2_E~0;~T2_E~0 := 2; 620#L382 assume 1 == ~E_1~0;~E_1~0 := 2; 621#L387 assume 1 == ~E_2~0;~E_2~0 := 2; 644#L393 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 645#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 478#L254-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 479#L262-1 assume true;start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 513#L547 assume !(0 == start_simulation_~tmp~3#1); 556#L558 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 475#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 476#L254 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 562#L262 assume true;stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 539#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 540#L504 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 663#L510 assume true;start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 502#L560 assume !(0 != start_simulation_~tmp___0~1#1); 503#L528 [2024-11-17 08:53:37,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:37,786 INFO L85 PathProgramCache]: Analyzing trace with hash 1989935542, now seen corresponding path program 1 times [2024-11-17 08:53:37,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:37,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290334735] [2024-11-17 08:53:37,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:37,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:37,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:37,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:37,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:37,861 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290334735] [2024-11-17 08:53:37,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290334735] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:37,861 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:37,862 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:37,862 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [692471656] [2024-11-17 08:53:37,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:37,863 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:37,864 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:37,865 INFO L85 PathProgramCache]: Analyzing trace with hash -1439888550, now seen corresponding path program 1 times [2024-11-17 08:53:37,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:37,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36295669] [2024-11-17 08:53:37,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:37,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:37,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:38,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:38,002 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:38,002 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36295669] [2024-11-17 08:53:38,002 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [36295669] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:38,003 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:38,003 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:38,003 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481698077] [2024-11-17 08:53:38,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:38,004 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:38,005 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:38,005 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:38,005 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:38,006 INFO L87 Difference]: Start difference. First operand 215 states and 310 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:38,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:38,028 INFO L93 Difference]: Finished difference Result 215 states and 309 transitions. [2024-11-17 08:53:38,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 215 states and 309 transitions. [2024-11-17 08:53:38,030 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2024-11-17 08:53:38,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 215 states to 215 states and 309 transitions. [2024-11-17 08:53:38,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 215 [2024-11-17 08:53:38,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 215 [2024-11-17 08:53:38,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 215 states and 309 transitions. [2024-11-17 08:53:38,034 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:38,034 INFO L218 hiAutomatonCegarLoop]: Abstraction has 215 states and 309 transitions. [2024-11-17 08:53:38,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215 states and 309 transitions. [2024-11-17 08:53:38,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215 to 215. [2024-11-17 08:53:38,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 215 states, 215 states have (on average 1.4372093023255814) internal successors, (309), 214 states have internal predecessors, (309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:38,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 309 transitions. [2024-11-17 08:53:38,046 INFO L240 hiAutomatonCegarLoop]: Abstraction has 215 states and 309 transitions. [2024-11-17 08:53:38,046 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:38,048 INFO L425 stractBuchiCegarLoop]: Abstraction has 215 states and 309 transitions. [2024-11-17 08:53:38,048 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:53:38,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 215 states and 309 transitions. [2024-11-17 08:53:38,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 174 [2024-11-17 08:53:38,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:38,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:38,051 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:38,051 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:38,054 INFO L745 eck$LassoCheckResult]: Stem: 1112#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 953#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 901#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 902#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1022#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 919#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 920#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1021#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1097#L334-1 assume !(0 == ~M_E~0); 1058#L339-1 assume !(0 == ~T1_E~0); 1052#L344-1 assume !(0 == ~T2_E~0); 1053#L349-1 assume !(0 == ~E_1~0); 980#L354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 981#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1107#L156-4 assume 1 == ~m_pc~0; 1108#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 965#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1100#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1082#L405-4 assume !(0 != activate_threads_~tmp~1#1); 939#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 940#L175-4 assume !(1 == ~t1_pc~0); 1103#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 1027#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1028#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1075#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 1041#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1042#L194-4 assume 1 == ~t2_pc~0; 1086#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1048#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1032#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1033#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 950#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 951#L367-1 assume !(1 == ~M_E~0); 1078#L372-1 assume !(1 == ~T1_E~0); 1079#L377-1 assume !(1 == ~T2_E~0); 948#L382-1 assume !(1 == ~E_1~0); 949#L387-1 assume !(1 == ~E_2~0); 1029#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 942#L528 [2024-11-17 08:53:38,054 INFO L747 eck$LassoCheckResult]: Loop: 942#L528 assume true; 998#L528-1 assume !false; 966#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 936#L271 assume true; 943#L271-1 assume !false; 944#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1094#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 954#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 955#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 898#L276 assume !(0 != eval_~tmp~0#1); 900#L279 assume true; 1002#L327 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1085#L214 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 967#L334 assume 0 == ~M_E~0;~M_E~0 := 1; 968#L339 assume 0 == ~T1_E~0;~T1_E~0 := 1; 962#L344 assume 0 == ~T2_E~0;~T2_E~0 := 1; 963#L349 assume 0 == ~E_1~0;~E_1~0 := 1; 1030#L354 assume 0 == ~E_2~0;~E_2~0 := 1; 932#L360 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 933#L156-1 assume 1 == ~m_pc~0; 929#L157-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 931#L159-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1063#L168-1 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1023#L405-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1024#L411-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1093#L175-1 assume 1 == ~t1_pc~0; 945#L176-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 946#L178-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1109#L187-1 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1089#L413-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1064#L419-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 910#L194-1 assume !(1 == ~t2_pc~0); 912#L204-1 is_transmit2_triggered_~__retres1~2#1 := 0; 923#L197-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 924#L206-1 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1106#L421-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1010#L427-1 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 927#L367 assume 1 == ~M_E~0;~M_E~0 := 2; 928#L372 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1069#L377 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1059#L382 assume 1 == ~E_1~0;~E_1~0 := 2; 1060#L387 assume 1 == ~E_2~0;~E_2~0 := 2; 1083#L393 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1084#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 917#L254-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 918#L262-1 assume true;start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 952#L547 assume !(0 == start_simulation_~tmp~3#1); 995#L558 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 914#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 915#L254 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1001#L262 assume true;stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 978#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 979#L504 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1102#L510 assume true;start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 941#L560 assume !(0 != start_simulation_~tmp___0~1#1); 942#L528 [2024-11-17 08:53:38,056 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:38,056 INFO L85 PathProgramCache]: Analyzing trace with hash -294927913, now seen corresponding path program 1 times [2024-11-17 08:53:38,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:38,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085885844] [2024-11-17 08:53:38,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:38,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:38,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:38,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:38,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:38,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085885844] [2024-11-17 08:53:38,154 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085885844] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:38,155 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:38,155 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:38,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [533563647] [2024-11-17 08:53:38,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:38,155 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:38,156 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:38,158 INFO L85 PathProgramCache]: Analyzing trace with hash 298543031, now seen corresponding path program 1 times [2024-11-17 08:53:38,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:38,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678329147] [2024-11-17 08:53:38,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:38,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:38,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:38,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:38,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:38,293 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678329147] [2024-11-17 08:53:38,293 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [678329147] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:38,293 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:38,293 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:38,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599620344] [2024-11-17 08:53:38,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:38,294 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:38,294 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:38,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:38,295 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:38,295 INFO L87 Difference]: Start difference. First operand 215 states and 309 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 9.5) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:38,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:38,468 INFO L93 Difference]: Finished difference Result 344 states and 488 transitions. [2024-11-17 08:53:38,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 344 states and 488 transitions. [2024-11-17 08:53:38,471 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 297 [2024-11-17 08:53:38,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 344 states to 344 states and 488 transitions. [2024-11-17 08:53:38,475 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 344 [2024-11-17 08:53:38,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 344 [2024-11-17 08:53:38,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 344 states and 488 transitions. [2024-11-17 08:53:38,478 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:38,481 INFO L218 hiAutomatonCegarLoop]: Abstraction has 344 states and 488 transitions. [2024-11-17 08:53:38,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 344 states and 488 transitions. [2024-11-17 08:53:38,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 344 to 343. [2024-11-17 08:53:38,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 343 states, 343 states have (on average 1.4198250728862973) internal successors, (487), 342 states have internal predecessors, (487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:38,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 343 states to 343 states and 487 transitions. [2024-11-17 08:53:38,498 INFO L240 hiAutomatonCegarLoop]: Abstraction has 343 states and 487 transitions. [2024-11-17 08:53:38,498 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:38,499 INFO L425 stractBuchiCegarLoop]: Abstraction has 343 states and 487 transitions. [2024-11-17 08:53:38,499 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:53:38,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 343 states and 487 transitions. [2024-11-17 08:53:38,501 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 297 [2024-11-17 08:53:38,501 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:38,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:38,503 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:38,503 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:38,503 INFO L745 eck$LassoCheckResult]: Stem: 1706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1525#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1472#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1473#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1595#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 1490#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1491#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1594#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1682#L334-1 assume !(0 == ~M_E~0); 1634#L339-1 assume !(0 == ~T1_E~0); 1628#L344-1 assume !(0 == ~T2_E~0); 1629#L349-1 assume !(0 == ~E_1~0); 1552#L354-1 assume !(0 == ~E_2~0); 1553#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1697#L156-4 assume 1 == ~m_pc~0; 1698#L157-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1537#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1686#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1660#L405-4 assume !(0 != activate_threads_~tmp~1#1); 1511#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1512#L175-4 assume !(1 == ~t1_pc~0); 1691#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 1600#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1601#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1653#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 1616#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1617#L194-4 assume 1 == ~t2_pc~0; 1665#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1624#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1605#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1606#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 1522#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1523#L367-1 assume 1 == ~M_E~0;~M_E~0 := 2; 1656#L372-1 assume !(1 == ~T1_E~0); 1657#L377-1 assume !(1 == ~T2_E~0); 1520#L382-1 assume !(1 == ~E_1~0); 1521#L387-1 assume !(1 == ~E_2~0); 1602#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 1514#L528 [2024-11-17 08:53:38,504 INFO L747 eck$LassoCheckResult]: Loop: 1514#L528 assume true; 1570#L528-1 assume !false; 1538#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1508#L271 assume true; 1676#L271-1 assume !false; 1703#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1704#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1526#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1527#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1469#L276 assume !(0 != eval_~tmp~0#1); 1471#L279 assume true; 1663#L327 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1664#L214 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1709#L334 assume 0 == ~M_E~0;~M_E~0 := 1; 1710#L339 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1811#L344 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1810#L349 assume 0 == ~E_1~0;~E_1~0 := 1; 1809#L354 assume !(0 == ~E_2~0); 1808#L360 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1807#L156-1 assume !(1 == ~m_pc~0); 1805#L166-1 is_master_triggered_~__retres1~0#1 := 0; 1804#L159-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1803#L168-1 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1802#L405-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1801#L411-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1800#L175-1 assume !(1 == ~t1_pc~0); 1798#L185-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1797#L178-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1796#L187-1 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1795#L413-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1794#L419-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1793#L194-1 assume 1 == ~t2_pc~0; 1792#L195-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1790#L197-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1789#L206-1 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1788#L421-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1787#L427-1 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1786#L367 assume 1 == ~M_E~0;~M_E~0 := 2; 1499#L372 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1785#L377 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1784#L382 assume 1 == ~E_1~0;~E_1~0 := 2; 1783#L387 assume 1 == ~E_2~0;~E_2~0 := 2; 1685#L393 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1781#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1779#L254-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1778#L262-1 assume true;start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 1777#L547 assume !(0 == start_simulation_~tmp~3#1); 1567#L558 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1774#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1773#L254 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1771#L262 assume true;stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 1769#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1768#L504 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1766#L510 assume true;start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1513#L560 assume !(0 != start_simulation_~tmp___0~1#1); 1514#L528 [2024-11-17 08:53:38,504 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:38,504 INFO L85 PathProgramCache]: Analyzing trace with hash -292537257, now seen corresponding path program 1 times [2024-11-17 08:53:38,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:38,505 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788569100] [2024-11-17 08:53:38,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:38,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:38,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:38,557 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:38,557 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:38,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788569100] [2024-11-17 08:53:38,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788569100] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:38,558 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:38,558 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:38,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2023489579] [2024-11-17 08:53:38,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:38,559 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:38,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:38,559 INFO L85 PathProgramCache]: Analyzing trace with hash 1612333939, now seen corresponding path program 1 times [2024-11-17 08:53:38,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:38,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794157470] [2024-11-17 08:53:38,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:38,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:38,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:38,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:38,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:38,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794157470] [2024-11-17 08:53:38,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1794157470] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:38,648 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:38,648 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:38,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2051907798] [2024-11-17 08:53:38,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:38,649 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:38,649 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:38,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:38,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:38,650 INFO L87 Difference]: Start difference. First operand 343 states and 487 transitions. cyclomatic complexity: 146 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:38,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:38,688 INFO L93 Difference]: Finished difference Result 625 states and 873 transitions. [2024-11-17 08:53:38,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 625 states and 873 transitions. [2024-11-17 08:53:38,693 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 578 [2024-11-17 08:53:38,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 625 states to 625 states and 873 transitions. [2024-11-17 08:53:38,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 625 [2024-11-17 08:53:38,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 625 [2024-11-17 08:53:38,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 625 states and 873 transitions. [2024-11-17 08:53:38,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:38,701 INFO L218 hiAutomatonCegarLoop]: Abstraction has 625 states and 873 transitions. [2024-11-17 08:53:38,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 625 states and 873 transitions. [2024-11-17 08:53:38,719 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 625 to 579. [2024-11-17 08:53:38,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 579 states, 579 states have (on average 1.4041450777202074) internal successors, (813), 578 states have internal predecessors, (813), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:38,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 579 states to 579 states and 813 transitions. [2024-11-17 08:53:38,722 INFO L240 hiAutomatonCegarLoop]: Abstraction has 579 states and 813 transitions. [2024-11-17 08:53:38,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:38,723 INFO L425 stractBuchiCegarLoop]: Abstraction has 579 states and 813 transitions. [2024-11-17 08:53:38,723 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:53:38,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 579 states and 813 transitions. [2024-11-17 08:53:38,726 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 532 [2024-11-17 08:53:38,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:38,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:38,729 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:38,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:38,730 INFO L745 eck$LassoCheckResult]: Stem: 2712#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2501#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2451#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2452#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2576#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 2469#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2470#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2571#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2673#L334-1 assume !(0 == ~M_E~0); 2616#L339-1 assume !(0 == ~T1_E~0); 2610#L344-1 assume !(0 == ~T2_E~0); 2611#L349-1 assume !(0 == ~E_1~0); 2527#L354-1 assume !(0 == ~E_2~0); 2528#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2702#L156-4 assume !(1 == ~m_pc~0); 2512#L166-4 is_master_triggered_~__retres1~0#1 := 0; 2513#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2685#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2647#L405-4 assume !(0 != activate_threads_~tmp~1#1); 2487#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2488#L175-4 assume !(1 == ~t1_pc~0); 2694#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 2577#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2578#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2640#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 2595#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2596#L194-4 assume 1 == ~t2_pc~0; 2655#L195-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2605#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2584#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2585#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 2498#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2499#L367-1 assume 1 == ~M_E~0;~M_E~0 := 2; 2705#L372-1 assume !(1 == ~T1_E~0); 2650#L377-1 assume !(1 == ~T2_E~0); 2651#L382-1 assume !(1 == ~E_1~0); 2954#L387-1 assume !(1 == ~E_2~0); 2579#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 2952#L528 [2024-11-17 08:53:38,730 INFO L747 eck$LassoCheckResult]: Loop: 2952#L528 assume true; 2950#L528-1 assume !false; 2514#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2484#L271 assume true; 2946#L271-1 assume !false; 2710#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2666#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2668#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2935#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2934#L276 assume !(0 != eval_~tmp~0#1); 2933#L279 assume true; 2932#L327 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2931#L214 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2930#L334 assume 0 == ~M_E~0;~M_E~0 := 1; 2629#L339 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2510#L344 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2511#L349 assume 0 == ~E_1~0;~E_1~0 := 1; 2581#L354 assume !(0 == ~E_2~0); 2480#L360 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2481#L156-1 assume !(1 == ~m_pc~0); 2598#L166-1 is_master_triggered_~__retres1~0#1 := 0; 2691#L159-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2623#L168-1 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2574#L405-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2575#L411-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2665#L175-1 assume 1 == ~t1_pc~0; 2493#L176-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2494#L178-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2704#L187-1 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2658#L413-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2624#L419-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2458#L194-1 assume 1 == ~t2_pc~0; 2459#L195-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2471#L197-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2472#L206-1 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2696#L421-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2559#L427-1 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2475#L367 assume 1 == ~M_E~0;~M_E~0 := 2; 2476#L372 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2632#L377 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2617#L382 assume 1 == ~E_1~0;~E_1~0 := 2; 2618#L387 assume 1 == ~E_2~0;~E_2~0 := 2; 2652#L393 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2653#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2465#L254-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2466#L262-1 assume true;start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 2500#L547 assume !(0 == start_simulation_~tmp~3#1); 2542#L558 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2462#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2463#L254 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2547#L262 assume true;stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 2525#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2526#L504 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2697#L510 assume true;start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2698#L560 assume !(0 != start_simulation_~tmp___0~1#1); 2952#L528 [2024-11-17 08:53:38,733 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:38,733 INFO L85 PathProgramCache]: Analyzing trace with hash 1445894324, now seen corresponding path program 1 times [2024-11-17 08:53:38,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:38,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015768081] [2024-11-17 08:53:38,734 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:38,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:38,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:38,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:38,792 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:38,792 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015768081] [2024-11-17 08:53:38,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015768081] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:38,794 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:38,794 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:38,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336783561] [2024-11-17 08:53:38,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:38,795 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:38,795 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:38,795 INFO L85 PathProgramCache]: Analyzing trace with hash -1307746090, now seen corresponding path program 1 times [2024-11-17 08:53:38,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:38,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1777293314] [2024-11-17 08:53:38,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:38,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:38,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:38,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:38,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:38,848 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1777293314] [2024-11-17 08:53:38,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1777293314] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:38,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:38,849 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:38,849 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131728037] [2024-11-17 08:53:38,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:38,849 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:38,849 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:38,850 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:38,850 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:38,850 INFO L87 Difference]: Start difference. First operand 579 states and 813 transitions. cyclomatic complexity: 238 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:38,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:38,889 INFO L93 Difference]: Finished difference Result 1094 states and 1520 transitions. [2024-11-17 08:53:38,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1094 states and 1520 transitions. [2024-11-17 08:53:38,896 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1038 [2024-11-17 08:53:38,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1094 states to 1094 states and 1520 transitions. [2024-11-17 08:53:38,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1094 [2024-11-17 08:53:38,903 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1094 [2024-11-17 08:53:38,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1094 states and 1520 transitions. [2024-11-17 08:53:38,905 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:38,905 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1094 states and 1520 transitions. [2024-11-17 08:53:38,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1094 states and 1520 transitions. [2024-11-17 08:53:38,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1094 to 1070. [2024-11-17 08:53:38,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1070 states, 1070 states have (on average 1.394392523364486) internal successors, (1492), 1069 states have internal predecessors, (1492), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:38,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1070 states to 1070 states and 1492 transitions. [2024-11-17 08:53:38,927 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1070 states and 1492 transitions. [2024-11-17 08:53:38,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:38,930 INFO L425 stractBuchiCegarLoop]: Abstraction has 1070 states and 1492 transitions. [2024-11-17 08:53:38,930 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:53:38,930 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1070 states and 1492 transitions. [2024-11-17 08:53:38,935 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1022 [2024-11-17 08:53:38,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:38,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:38,936 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:38,936 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:38,936 INFO L745 eck$LassoCheckResult]: Stem: 4391#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4183#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4133#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4134#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4256#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 4149#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4150#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4255#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4356#L334-1 assume !(0 == ~M_E~0); 4301#L339-1 assume !(0 == ~T1_E~0); 4295#L344-1 assume !(0 == ~T2_E~0); 4296#L349-1 assume !(0 == ~E_1~0); 4209#L354-1 assume !(0 == ~E_2~0); 4210#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4381#L156-4 assume !(1 == ~m_pc~0); 4194#L166-4 is_master_triggered_~__retres1~0#1 := 0; 4195#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4366#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 4334#L405-4 assume !(0 != activate_threads_~tmp~1#1); 4169#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4170#L175-4 assume !(1 == ~t1_pc~0); 4374#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 4261#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4262#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 4327#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 4281#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4282#L194-4 assume !(1 == ~t2_pc~0); 4288#L204-4 is_transmit2_triggered_~__retres1~2#1 := 0; 4289#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4270#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4271#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 4180#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4181#L367-1 assume 1 == ~M_E~0;~M_E~0 := 2; 4330#L372-1 assume !(1 == ~T1_E~0); 4331#L377-1 assume !(1 == ~T2_E~0); 4178#L382-1 assume !(1 == ~E_1~0); 4179#L387-1 assume !(1 == ~E_2~0); 4264#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 4313#L528 [2024-11-17 08:53:38,936 INFO L747 eck$LassoCheckResult]: Loop: 4313#L528 assume true; 4861#L528-1 assume !false; 4544#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4541#L271 assume true; 4539#L271-1 assume !false; 4536#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4537#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4525#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4526#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4519#L276 assume !(0 != eval_~tmp~0#1); 4520#L279 assume true; 5062#L327 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5061#L214 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5060#L334 assume 0 == ~M_E~0;~M_E~0 := 1; 5059#L339 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5058#L344 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5057#L349 assume 0 == ~E_1~0;~E_1~0 := 1; 5056#L354 assume !(0 == ~E_2~0); 5055#L360 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5054#L156-1 assume !(1 == ~m_pc~0); 5053#L166-1 is_master_triggered_~__retres1~0#1 := 0; 5052#L159-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5051#L168-1 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 5050#L405-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5049#L411-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5048#L175-1 assume !(1 == ~t1_pc~0); 5046#L185-1 is_transmit1_triggered_~__retres1~1#1 := 0; 5045#L178-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5044#L187-1 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 5043#L413-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5042#L419-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5041#L194-1 assume !(1 == ~t2_pc~0); 5040#L204-1 is_transmit2_triggered_~__retres1~2#1 := 0; 5039#L197-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5038#L206-1 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 5037#L421-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5036#L427-1 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5035#L367 assume 1 == ~M_E~0;~M_E~0 := 2; 4971#L372 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5034#L377 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5030#L382 assume 1 == ~E_1~0;~E_1~0 := 2; 5028#L387 assume 1 == ~E_2~0;~E_2~0 := 2; 4965#L393 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4997#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4993#L254-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4991#L262-1 assume true;start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 4353#L547 assume !(0 == start_simulation_~tmp~3#1); 4355#L558 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4879#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 4878#L254 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 4876#L262 assume true;stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 4874#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4872#L504 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4870#L510 assume true;start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 4866#L560 assume !(0 != start_simulation_~tmp___0~1#1); 4313#L528 [2024-11-17 08:53:38,939 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:38,939 INFO L85 PathProgramCache]: Analyzing trace with hash 873912465, now seen corresponding path program 1 times [2024-11-17 08:53:38,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:38,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550948594] [2024-11-17 08:53:38,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:38,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:38,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:38,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:38,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:38,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550948594] [2024-11-17 08:53:38,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1550948594] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:38,990 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:38,990 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:38,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1378553135] [2024-11-17 08:53:38,991 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:38,991 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:38,991 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:38,992 INFO L85 PathProgramCache]: Analyzing trace with hash -944201776, now seen corresponding path program 1 times [2024-11-17 08:53:38,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:38,992 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20256241] [2024-11-17 08:53:38,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:38,992 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:39,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:39,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:39,048 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20256241] [2024-11-17 08:53:39,048 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [20256241] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:39,048 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:39,048 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:39,048 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898691244] [2024-11-17 08:53:39,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:39,049 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:39,049 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:39,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:39,050 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:39,050 INFO L87 Difference]: Start difference. First operand 1070 states and 1492 transitions. cyclomatic complexity: 430 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 2 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:39,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:39,097 INFO L93 Difference]: Finished difference Result 1589 states and 2194 transitions. [2024-11-17 08:53:39,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1589 states and 2194 transitions. [2024-11-17 08:53:39,106 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1543 [2024-11-17 08:53:39,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1589 states to 1589 states and 2194 transitions. [2024-11-17 08:53:39,115 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1589 [2024-11-17 08:53:39,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1589 [2024-11-17 08:53:39,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1589 states and 2194 transitions. [2024-11-17 08:53:39,118 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:39,119 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1589 states and 2194 transitions. [2024-11-17 08:53:39,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1589 states and 2194 transitions. [2024-11-17 08:53:39,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1589 to 1173. [2024-11-17 08:53:39,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1173 states, 1173 states have (on average 1.3844842284739982) internal successors, (1624), 1172 states have internal predecessors, (1624), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:39,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1173 states to 1173 states and 1624 transitions. [2024-11-17 08:53:39,140 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1173 states and 1624 transitions. [2024-11-17 08:53:39,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:39,141 INFO L425 stractBuchiCegarLoop]: Abstraction has 1173 states and 1624 transitions. [2024-11-17 08:53:39,141 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:53:39,141 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1173 states and 1624 transitions. [2024-11-17 08:53:39,146 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1130 [2024-11-17 08:53:39,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:39,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:39,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:39,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:39,148 INFO L745 eck$LassoCheckResult]: Stem: 7057#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6851#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6799#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6800#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6926#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 6818#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6819#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6925#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7025#L334-1 assume !(0 == ~M_E~0); 6972#L339-1 assume !(0 == ~T1_E~0); 6966#L344-1 assume !(0 == ~T2_E~0); 6967#L349-1 assume !(0 == ~E_1~0); 6878#L354-1 assume !(0 == ~E_2~0); 6879#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7047#L156-4 assume !(1 == ~m_pc~0); 6862#L166-4 is_master_triggered_~__retres1~0#1 := 0; 6863#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7032#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 7004#L405-4 assume !(0 != activate_threads_~tmp~1#1); 6837#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6838#L175-4 assume !(1 == ~t1_pc~0); 7038#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 6931#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6932#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6997#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 6951#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6952#L194-4 assume !(1 == ~t2_pc~0); 6959#L204-4 is_transmit2_triggered_~__retres1~2#1 := 0; 6960#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6939#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6940#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 6848#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6849#L367-1 assume !(1 == ~M_E~0); 7000#L372-1 assume !(1 == ~T1_E~0); 7001#L377-1 assume !(1 == ~T2_E~0); 6846#L382-1 assume !(1 == ~E_1~0); 6847#L387-1 assume !(1 == ~E_2~0); 6933#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 6985#L528 [2024-11-17 08:53:39,148 INFO L747 eck$LassoCheckResult]: Loop: 6985#L528 assume true; 7455#L528-1 assume !false; 7448#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7442#L271 assume true; 7440#L271-1 assume !false; 7438#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7435#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7430#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7428#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7425#L276 assume !(0 != eval_~tmp~0#1); 7426#L279 assume true; 7966#L327 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7058#L214 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6865#L334 assume !(0 == ~M_E~0); 6866#L339 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6860#L344 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6861#L349 assume 0 == ~E_1~0;~E_1~0 := 1; 6935#L354 assume !(0 == ~E_2~0); 6830#L360 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6831#L156-1 assume !(1 == ~m_pc~0); 6954#L166-1 is_master_triggered_~__retres1~0#1 := 0; 7037#L159-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6981#L168-1 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6927#L405-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6928#L411-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7018#L175-1 assume 1 == ~t1_pc~0; 6843#L176-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6844#L178-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7050#L187-1 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 7011#L413-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6982#L419-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6809#L194-1 assume !(1 == ~t2_pc~0); 6810#L204-1 is_transmit2_triggered_~__retres1~2#1 := 0; 7921#L197-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7920#L206-1 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7919#L421-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7915#L427-1 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7913#L367 assume !(1 == ~M_E~0); 7366#L372 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7910#L377 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7908#L382 assume 1 == ~E_1~0;~E_1~0 := 2; 7906#L387 assume 1 == ~E_2~0;~E_2~0 := 2; 7904#L393 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7902#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7894#L254-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7893#L262-1 assume true;start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 7022#L547 assume !(0 == start_simulation_~tmp~3#1); 7024#L558 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7515#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7512#L254 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7508#L262 assume true;stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 7503#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7501#L504 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7499#L510 assume true;start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7463#L560 assume !(0 != start_simulation_~tmp___0~1#1); 6985#L528 [2024-11-17 08:53:39,148 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,149 INFO L85 PathProgramCache]: Analyzing trace with hash 902541616, now seen corresponding path program 1 times [2024-11-17 08:53:39,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205520136] [2024-11-17 08:53:39,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:39,180 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:39,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:39,211 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:39,212 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,212 INFO L85 PathProgramCache]: Analyzing trace with hash -442313615, now seen corresponding path program 1 times [2024-11-17 08:53:39,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2008878434] [2024-11-17 08:53:39,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:39,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:39,256 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:39,256 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2008878434] [2024-11-17 08:53:39,256 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2008878434] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:39,256 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:39,256 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:39,257 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [862733132] [2024-11-17 08:53:39,257 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:39,257 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:39,258 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:39,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:53:39,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:53:39,259 INFO L87 Difference]: Start difference. First operand 1173 states and 1624 transitions. cyclomatic complexity: 455 Second operand has 5 states, 5 states have (on average 11.0) internal successors, (55), 5 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:39,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:39,314 INFO L93 Difference]: Finished difference Result 1229 states and 1680 transitions. [2024-11-17 08:53:39,314 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1229 states and 1680 transitions. [2024-11-17 08:53:39,320 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1186 [2024-11-17 08:53:39,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1229 states to 1229 states and 1680 transitions. [2024-11-17 08:53:39,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1229 [2024-11-17 08:53:39,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1229 [2024-11-17 08:53:39,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1229 states and 1680 transitions. [2024-11-17 08:53:39,328 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:39,328 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1229 states and 1680 transitions. [2024-11-17 08:53:39,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1229 states and 1680 transitions. [2024-11-17 08:53:39,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1229 to 1197. [2024-11-17 08:53:39,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1197 states, 1197 states have (on average 1.3767752715121135) internal successors, (1648), 1196 states have internal predecessors, (1648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:39,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1197 states to 1197 states and 1648 transitions. [2024-11-17 08:53:39,347 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1197 states and 1648 transitions. [2024-11-17 08:53:39,348 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:53:39,348 INFO L425 stractBuchiCegarLoop]: Abstraction has 1197 states and 1648 transitions. [2024-11-17 08:53:39,348 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:53:39,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1197 states and 1648 transitions. [2024-11-17 08:53:39,354 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1154 [2024-11-17 08:53:39,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:39,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:39,355 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:39,355 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:39,356 INFO L745 eck$LassoCheckResult]: Stem: 9484#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 9261#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9210#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9211#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9339#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 9229#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9230#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9334#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9439#L334-1 assume !(0 == ~M_E~0); 9380#L339-1 assume !(0 == ~T1_E~0); 9374#L344-1 assume !(0 == ~T2_E~0); 9375#L349-1 assume !(0 == ~E_1~0); 9287#L354-1 assume !(0 == ~E_2~0); 9288#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9474#L156-4 assume !(1 == ~m_pc~0); 9272#L166-4 is_master_triggered_~__retres1~0#1 := 0; 9273#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9454#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 9412#L405-4 assume !(0 != activate_threads_~tmp~1#1); 9246#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9247#L175-4 assume !(1 == ~t1_pc~0); 9468#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 9340#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9341#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 9405#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 9357#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9358#L194-4 assume !(1 == ~t2_pc~0); 9367#L204-4 is_transmit2_triggered_~__retres1~2#1 := 0; 9368#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9347#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9348#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 9257#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9258#L367-1 assume !(1 == ~M_E~0); 9408#L372-1 assume !(1 == ~T1_E~0); 9409#L377-1 assume !(1 == ~T2_E~0); 9255#L382-1 assume !(1 == ~E_1~0); 9256#L387-1 assume !(1 == ~E_2~0); 9342#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 9391#L528 [2024-11-17 08:53:39,356 INFO L747 eck$LassoCheckResult]: Loop: 9391#L528 assume true; 10166#L528-1 assume !false; 10164#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9895#L271 assume true; 10161#L271-1 assume !false; 10158#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10152#L244-2 assume !(0 == ~m_st~0); 10153#L248-2 assume !(0 == ~t1_st~0); 10150#L252-2 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 10151#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10298#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10296#L276 assume !(0 != eval_~tmp~0#1); 10294#L279 assume true; 10292#L327 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10290#L214 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10288#L334 assume !(0 == ~M_E~0); 10285#L339 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10283#L344 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10281#L349 assume 0 == ~E_1~0;~E_1~0 := 1; 10279#L354 assume !(0 == ~E_2~0); 10277#L360 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10275#L156-1 assume !(1 == ~m_pc~0); 10273#L166-1 is_master_triggered_~__retres1~0#1 := 0; 10271#L159-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10269#L168-1 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10267#L405-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10265#L411-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10264#L175-1 assume !(1 == ~t1_pc~0); 10243#L185-1 is_transmit1_triggered_~__retres1~1#1 := 0; 10241#L178-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10239#L187-1 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10237#L413-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10235#L419-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10233#L194-1 assume !(1 == ~t2_pc~0); 10231#L204-1 is_transmit2_triggered_~__retres1~2#1 := 0; 10229#L197-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10226#L206-1 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10224#L421-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10222#L427-1 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10220#L367 assume !(1 == ~M_E~0); 10216#L372 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10214#L377 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10211#L382 assume 1 == ~E_1~0;~E_1~0 := 2; 10209#L387 assume 1 == ~E_2~0;~E_2~0 := 2; 10207#L393 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10203#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10199#L254-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10197#L262-1 assume true;start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 10183#L547 assume !(0 == start_simulation_~tmp~3#1); 10182#L558 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10179#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10178#L254 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10177#L262 assume true;stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 10176#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10174#L504 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10172#L510 assume true;start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10170#L560 assume !(0 != start_simulation_~tmp___0~1#1); 9391#L528 [2024-11-17 08:53:39,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,357 INFO L85 PathProgramCache]: Analyzing trace with hash 902541616, now seen corresponding path program 2 times [2024-11-17 08:53:39,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961839616] [2024-11-17 08:53:39,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:39,368 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:39,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:39,380 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:39,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,381 INFO L85 PathProgramCache]: Analyzing trace with hash -1892753929, now seen corresponding path program 1 times [2024-11-17 08:53:39,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877002672] [2024-11-17 08:53:39,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:39,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:39,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:39,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1877002672] [2024-11-17 08:53:39,456 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1877002672] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:39,456 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:39,456 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:39,456 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [90806901] [2024-11-17 08:53:39,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:39,457 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:39,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:39,457 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:53:39,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:53:39,458 INFO L87 Difference]: Start difference. First operand 1197 states and 1648 transitions. cyclomatic complexity: 455 Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:39,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:39,553 INFO L93 Difference]: Finished difference Result 1221 states and 1655 transitions. [2024-11-17 08:53:39,553 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1221 states and 1655 transitions. [2024-11-17 08:53:39,560 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1178 [2024-11-17 08:53:39,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1221 states to 1221 states and 1655 transitions. [2024-11-17 08:53:39,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1221 [2024-11-17 08:53:39,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1221 [2024-11-17 08:53:39,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1221 states and 1655 transitions. [2024-11-17 08:53:39,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:39,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1221 states and 1655 transitions. [2024-11-17 08:53:39,569 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1221 states and 1655 transitions. [2024-11-17 08:53:39,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1221 to 1221. [2024-11-17 08:53:39,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1221 states, 1221 states have (on average 1.3554463554463554) internal successors, (1655), 1220 states have internal predecessors, (1655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:39,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1221 states to 1221 states and 1655 transitions. [2024-11-17 08:53:39,589 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1221 states and 1655 transitions. [2024-11-17 08:53:39,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:53:39,591 INFO L425 stractBuchiCegarLoop]: Abstraction has 1221 states and 1655 transitions. [2024-11-17 08:53:39,591 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:53:39,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1221 states and 1655 transitions. [2024-11-17 08:53:39,597 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1178 [2024-11-17 08:53:39,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:39,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:39,598 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:39,598 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:39,599 INFO L745 eck$LassoCheckResult]: Stem: 11900#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 11686#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 11634#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11635#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11756#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 11653#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11654#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11755#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11860#L334-1 assume !(0 == ~M_E~0); 11805#L339-1 assume !(0 == ~T1_E~0); 11799#L344-1 assume !(0 == ~T2_E~0); 11800#L349-1 assume !(0 == ~E_1~0); 11712#L354-1 assume !(0 == ~E_2~0); 11713#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11891#L156-4 assume !(1 == ~m_pc~0); 11697#L166-4 is_master_triggered_~__retres1~0#1 := 0; 11698#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11872#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11835#L405-4 assume !(0 != activate_threads_~tmp~1#1); 11672#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11673#L175-4 assume !(1 == ~t1_pc~0); 11882#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 11761#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11762#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 11828#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 11784#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11785#L194-4 assume !(1 == ~t2_pc~0); 11792#L204-4 is_transmit2_triggered_~__retres1~2#1 := 0; 11793#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11770#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 11771#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 11683#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11684#L367-1 assume !(1 == ~M_E~0); 11831#L372-1 assume !(1 == ~T1_E~0); 11832#L377-1 assume !(1 == ~T2_E~0); 11681#L382-1 assume !(1 == ~E_1~0); 11682#L387-1 assume !(1 == ~E_2~0); 11763#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 11675#L528 [2024-11-17 08:53:39,599 INFO L747 eck$LassoCheckResult]: Loop: 11675#L528 assume true; 11729#L528-1 assume !false; 11699#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11669#L271 assume true; 12605#L271-1 assume !false; 12604#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12602#L244-2 assume !(0 == ~m_st~0); 12603#L248-2 assume !(0 == ~t1_st~0); 12600#L252-2 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 12598#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12599#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12771#L276 assume !(0 != eval_~tmp~0#1); 12770#L279 assume true; 12769#L327 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12767#L214 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12765#L334 assume !(0 == ~M_E~0); 12763#L339 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12762#L344 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12761#L349 assume 0 == ~E_1~0;~E_1~0 := 1; 12759#L354 assume !(0 == ~E_2~0); 12757#L360 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12755#L156-1 assume !(1 == ~m_pc~0); 12753#L166-1 is_master_triggered_~__retres1~0#1 := 0; 12751#L159-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12748#L168-1 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12746#L405-1 assume !(0 != activate_threads_~tmp~1#1); 12745#L411-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12744#L175-1 assume !(1 == ~t1_pc~0); 12739#L185-1 is_transmit1_triggered_~__retres1~1#1 := 0; 12737#L178-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12735#L187-1 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 12733#L413-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12731#L419-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12729#L194-1 assume !(1 == ~t2_pc~0); 12727#L204-1 is_transmit2_triggered_~__retres1~2#1 := 0; 12725#L197-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12723#L206-1 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12721#L421-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12720#L427-1 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12718#L367 assume !(1 == ~M_E~0); 12714#L372 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12713#L377 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12708#L382 assume 1 == ~E_1~0;~E_1~0 := 2; 12705#L387 assume 1 == ~E_2~0;~E_2~0 := 2; 12702#L393 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 12617#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 12615#L254-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 12607#L262-1 assume true;start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 11971#L547 assume !(0 == start_simulation_~tmp~3#1); 11726#L558 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11648#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11649#L254 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11734#L262 assume true;stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 11710#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11711#L504 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11880#L510 assume true;start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 11674#L560 assume !(0 != start_simulation_~tmp___0~1#1); 11675#L528 [2024-11-17 08:53:39,599 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,600 INFO L85 PathProgramCache]: Analyzing trace with hash 902541616, now seen corresponding path program 3 times [2024-11-17 08:53:39,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372957166] [2024-11-17 08:53:39,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:39,610 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:39,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:39,621 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:39,622 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,622 INFO L85 PathProgramCache]: Analyzing trace with hash 392109526, now seen corresponding path program 1 times [2024-11-17 08:53:39,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390108146] [2024-11-17 08:53:39,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:39,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:39,651 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:39,651 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390108146] [2024-11-17 08:53:39,652 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390108146] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:39,652 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:39,652 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:39,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [67104464] [2024-11-17 08:53:39,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:39,652 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:39,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:39,653 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:39,653 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:39,653 INFO L87 Difference]: Start difference. First operand 1221 states and 1655 transitions. cyclomatic complexity: 438 Second operand has 3 states, 3 states have (on average 19.0) internal successors, (57), 3 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:39,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:39,693 INFO L93 Difference]: Finished difference Result 1770 states and 2358 transitions. [2024-11-17 08:53:39,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1770 states and 2358 transitions. [2024-11-17 08:53:39,703 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1692 [2024-11-17 08:53:39,710 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1770 states to 1770 states and 2358 transitions. [2024-11-17 08:53:39,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1770 [2024-11-17 08:53:39,712 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1770 [2024-11-17 08:53:39,712 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1770 states and 2358 transitions. [2024-11-17 08:53:39,714 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:39,714 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1770 states and 2358 transitions. [2024-11-17 08:53:39,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1770 states and 2358 transitions. [2024-11-17 08:53:39,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1770 to 1733. [2024-11-17 08:53:39,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1733 states, 1733 states have (on average 1.3335256780150029) internal successors, (2311), 1732 states have internal predecessors, (2311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:39,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1733 states to 1733 states and 2311 transitions. [2024-11-17 08:53:39,742 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1733 states and 2311 transitions. [2024-11-17 08:53:39,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:39,743 INFO L425 stractBuchiCegarLoop]: Abstraction has 1733 states and 2311 transitions. [2024-11-17 08:53:39,743 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:53:39,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1733 states and 2311 transitions. [2024-11-17 08:53:39,752 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1655 [2024-11-17 08:53:39,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:39,752 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:39,755 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:39,755 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:39,755 INFO L745 eck$LassoCheckResult]: Stem: 14885#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 14681#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 14631#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14632#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14754#L221 assume !(1 == ~m_i~0);~m_st~0 := 2; 14648#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14649#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14753#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14852#L334-1 assume !(0 == ~M_E~0); 14798#L339-1 assume !(0 == ~T1_E~0); 14792#L344-1 assume !(0 == ~T2_E~0); 14793#L349-1 assume !(0 == ~E_1~0); 14707#L354-1 assume !(0 == ~E_2~0); 14708#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14873#L156-4 assume !(1 == ~m_pc~0); 14692#L166-4 is_master_triggered_~__retres1~0#1 := 0; 14693#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14856#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 14825#L405-4 assume !(0 != activate_threads_~tmp~1#1); 14667#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14668#L175-4 assume !(1 == ~t1_pc~0); 14863#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 14759#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14760#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14818#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 14779#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14780#L194-4 assume !(1 == ~t2_pc~0); 14787#L204-4 is_transmit2_triggered_~__retres1~2#1 := 0; 14788#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14767#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14768#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 15871#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15869#L367-1 assume !(1 == ~M_E~0); 14821#L372-1 assume !(1 == ~T1_E~0); 14822#L377-1 assume !(1 == ~T2_E~0); 14676#L382-1 assume !(1 == ~E_1~0); 14677#L387-1 assume !(1 == ~E_2~0); 14761#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 14806#L528 [2024-11-17 08:53:39,755 INFO L747 eck$LassoCheckResult]: Loop: 14806#L528 assume true; 16130#L528-1 assume !false; 16123#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16117#L271 assume true; 16115#L271-1 assume !false; 16113#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16111#L244-2 assume !(0 == ~m_st~0); 15821#L248-2 assume !(0 == ~t1_st~0); 16107#L252-2 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 16104#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16102#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16099#L276 assume !(0 != eval_~tmp~0#1); 16096#L279 assume true; 16094#L327 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16092#L214 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16090#L334 assume !(0 == ~M_E~0); 16086#L339 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16087#L344 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16082#L349 assume 0 == ~E_1~0;~E_1~0 := 1; 16083#L354 assume !(0 == ~E_2~0); 14908#L360 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14909#L156-1 assume !(1 == ~m_pc~0); 16247#L166-1 is_master_triggered_~__retres1~0#1 := 0; 16246#L159-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14803#L168-1 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 14755#L405-1 assume !(0 != activate_threads_~tmp~1#1); 14756#L411-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16244#L175-1 assume !(1 == ~t1_pc~0); 16242#L185-1 is_transmit1_triggered_~__retres1~1#1 := 0; 16241#L178-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16240#L187-1 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14834#L413-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14804#L419-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14641#L194-1 assume !(1 == ~t2_pc~0); 14642#L204-1 is_transmit2_triggered_~__retres1~2#1 := 0; 16236#L197-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16233#L206-1 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16230#L421-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16227#L427-1 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16223#L367 assume !(1 == ~M_E~0); 16219#L372 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16215#L377 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16211#L382 assume 1 == ~E_1~0;~E_1~0 := 2; 16207#L387 assume 1 == ~E_2~0;~E_2~0 := 2; 16202#L393 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16197#L244-1 assume !(0 == ~m_st~0); 16079#L248-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16074#L254-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16075#L262-1 assume true;start_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1; 14849#L547 assume !(0 == start_simulation_~tmp~3#1); 14851#L558 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 16182#L244 assume !(0 == ~m_st~0); 16177#L248 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 16173#L254 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 16164#L262 assume true;stop_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret11#1;havoc stop_simulation_#t~ret11#1; 16158#L502 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16154#L504 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16149#L510 assume true;start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret11#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 16143#L560 assume !(0 != start_simulation_~tmp___0~1#1); 14806#L528 [2024-11-17 08:53:39,756 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,756 INFO L85 PathProgramCache]: Analyzing trace with hash 1928033615, now seen corresponding path program 1 times [2024-11-17 08:53:39,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [652152203] [2024-11-17 08:53:39,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:39,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:39,778 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:39,778 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [652152203] [2024-11-17 08:53:39,778 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [652152203] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:39,778 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:39,778 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:39,779 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830393149] [2024-11-17 08:53:39,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:39,779 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:39,779 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1987482142, now seen corresponding path program 1 times [2024-11-17 08:53:39,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960189159] [2024-11-17 08:53:39,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:39,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:39,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:39,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960189159] [2024-11-17 08:53:39,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1960189159] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:39,858 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:39,858 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:39,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1215184443] [2024-11-17 08:53:39,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:39,859 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:39,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:39,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:39,860 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:39,860 INFO L87 Difference]: Start difference. First operand 1733 states and 2311 transitions. cyclomatic complexity: 584 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:39,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:39,873 INFO L93 Difference]: Finished difference Result 1699 states and 2265 transitions. [2024-11-17 08:53:39,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1699 states and 2265 transitions. [2024-11-17 08:53:39,880 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1655 [2024-11-17 08:53:39,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1699 states to 1699 states and 2265 transitions. [2024-11-17 08:53:39,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1699 [2024-11-17 08:53:39,888 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1699 [2024-11-17 08:53:39,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1699 states and 2265 transitions. [2024-11-17 08:53:39,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:39,891 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1699 states and 2265 transitions. [2024-11-17 08:53:39,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1699 states and 2265 transitions. [2024-11-17 08:53:39,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1699 to 1699. [2024-11-17 08:53:39,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1699 states, 1699 states have (on average 1.3331371394938198) internal successors, (2265), 1698 states have internal predecessors, (2265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:39,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1699 states to 1699 states and 2265 transitions. [2024-11-17 08:53:39,918 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1699 states and 2265 transitions. [2024-11-17 08:53:39,918 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:39,919 INFO L425 stractBuchiCegarLoop]: Abstraction has 1699 states and 2265 transitions. [2024-11-17 08:53:39,919 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:53:39,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1699 states and 2265 transitions. [2024-11-17 08:53:39,926 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 1655 [2024-11-17 08:53:39,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:39,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:39,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:39,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:39,928 INFO L745 eck$LassoCheckResult]: Stem: 18338#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 18122#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 18074#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18075#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18203#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 18091#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18092#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18198#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18299#L334-1 assume !(0 == ~M_E~0); 18244#L339-1 assume !(0 == ~T1_E~0); 18238#L344-1 assume !(0 == ~T2_E~0); 18239#L349-1 assume !(0 == ~E_1~0); 18150#L354-1 assume !(0 == ~E_2~0); 18151#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18328#L156-4 assume !(1 == ~m_pc~0); 18133#L166-4 is_master_triggered_~__retres1~0#1 := 0; 18134#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18309#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 18275#L405-4 assume !(0 != activate_threads_~tmp~1#1); 18108#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18109#L175-4 assume !(1 == ~t1_pc~0); 18316#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 18204#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18205#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 18268#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 18222#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18223#L194-4 assume !(1 == ~t2_pc~0); 18232#L204-4 is_transmit2_triggered_~__retres1~2#1 := 0; 18233#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18211#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 18212#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 18119#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18120#L367-1 assume !(1 == ~M_E~0); 18271#L372-1 assume !(1 == ~T1_E~0); 18272#L377-1 assume !(1 == ~T2_E~0); 18117#L382-1 assume !(1 == ~E_1~0); 18118#L387-1 assume !(1 == ~E_2~0); 18206#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 18256#L528 assume true; 18790#L528-1 assume !false; 18746#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18701#L271 [2024-11-17 08:53:39,928 INFO L747 eck$LassoCheckResult]: Loop: 18701#L271 assume true; 18697#L271-1 assume !false; 18693#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 18688#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 18683#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 18678#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18673#L276 assume 0 != eval_~tmp~0#1; 18668#L281-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 18661#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 18662#L281 havoc eval_~tmp_ndt_1~0#1; 18797#L295-1 assume !(0 == ~t1_st~0); 18747#L309-1 assume !(0 == ~t2_st~0); 18701#L271 [2024-11-17 08:53:39,928 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,928 INFO L85 PathProgramCache]: Analyzing trace with hash 1122352840, now seen corresponding path program 1 times [2024-11-17 08:53:39,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877185756] [2024-11-17 08:53:39,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:39,936 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:39,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:39,946 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:39,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1988755603, now seen corresponding path program 1 times [2024-11-17 08:53:39,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464627600] [2024-11-17 08:53:39,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:39,953 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:39,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:39,958 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:39,959 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:39,959 INFO L85 PathProgramCache]: Analyzing trace with hash 815582426, now seen corresponding path program 1 times [2024-11-17 08:53:39,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:39,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735908944] [2024-11-17 08:53:39,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:39,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:39,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:39,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:39,995 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:39,995 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735908944] [2024-11-17 08:53:39,995 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1735908944] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:39,995 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:39,995 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:39,995 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1217325786] [2024-11-17 08:53:39,995 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:40,058 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:40,059 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:40,059 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:40,059 INFO L87 Difference]: Start difference. First operand 1699 states and 2265 transitions. cyclomatic complexity: 572 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:40,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:40,103 INFO L93 Difference]: Finished difference Result 2830 states and 3715 transitions. [2024-11-17 08:53:40,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2830 states and 3715 transitions. [2024-11-17 08:53:40,115 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2784 [2024-11-17 08:53:40,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2830 states to 2830 states and 3715 transitions. [2024-11-17 08:53:40,128 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2830 [2024-11-17 08:53:40,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2830 [2024-11-17 08:53:40,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2830 states and 3715 transitions. [2024-11-17 08:53:40,135 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:40,135 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2830 states and 3715 transitions. [2024-11-17 08:53:40,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2830 states and 3715 transitions. [2024-11-17 08:53:40,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2830 to 2669. [2024-11-17 08:53:40,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2669 states, 2669 states have (on average 1.3210940427126265) internal successors, (3526), 2668 states have internal predecessors, (3526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:40,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2669 states to 2669 states and 3526 transitions. [2024-11-17 08:53:40,180 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2669 states and 3526 transitions. [2024-11-17 08:53:40,180 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:40,181 INFO L425 stractBuchiCegarLoop]: Abstraction has 2669 states and 3526 transitions. [2024-11-17 08:53:40,181 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:53:40,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2669 states and 3526 transitions. [2024-11-17 08:53:40,189 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2623 [2024-11-17 08:53:40,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:40,189 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:40,190 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:40,190 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:40,190 INFO L745 eck$LassoCheckResult]: Stem: 22877#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 22659#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 22611#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22612#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22736#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 22628#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22629#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22731#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22839#L334-1 assume !(0 == ~M_E~0); 22782#L339-1 assume !(0 == ~T1_E~0); 22776#L344-1 assume !(0 == ~T2_E~0); 22777#L349-1 assume !(0 == ~E_1~0); 22686#L354-1 assume !(0 == ~E_2~0); 22687#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22869#L156-4 assume !(1 == ~m_pc~0); 22670#L166-4 is_master_triggered_~__retres1~0#1 := 0; 22671#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22854#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 22813#L405-4 assume !(0 != activate_threads_~tmp~1#1); 22645#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22646#L175-4 assume !(1 == ~t1_pc~0); 22863#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 22737#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22738#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 22805#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 22758#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22759#L194-4 assume !(1 == ~t2_pc~0); 22769#L204-4 is_transmit2_triggered_~__retres1~2#1 := 0; 22770#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22746#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22747#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 22656#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22657#L367-1 assume !(1 == ~M_E~0); 22809#L372-1 assume !(1 == ~T1_E~0); 22810#L377-1 assume !(1 == ~T2_E~0); 22654#L382-1 assume !(1 == ~E_1~0); 22655#L387-1 assume !(1 == ~E_2~0); 22739#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 22793#L528 assume true; 24789#L528-1 assume !false; 24788#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24561#L271 [2024-11-17 08:53:40,191 INFO L747 eck$LassoCheckResult]: Loop: 24561#L271 assume true; 24787#L271-1 assume !false; 24786#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24784#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 24783#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24781#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24779#L276 assume 0 != eval_~tmp~0#1; 24776#L281-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 22716#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 22717#L281 havoc eval_~tmp_ndt_1~0#1; 22814#L295-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 24448#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 24563#L295 havoc eval_~tmp_ndt_2~0#1; 24560#L309-1 assume !(0 == ~t2_st~0); 24561#L271 [2024-11-17 08:53:40,191 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:40,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1122352840, now seen corresponding path program 2 times [2024-11-17 08:53:40,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:40,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23936662] [2024-11-17 08:53:40,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:40,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:40,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:40,198 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:40,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:40,206 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:40,206 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:40,207 INFO L85 PathProgramCache]: Analyzing trace with hash -66278257, now seen corresponding path program 1 times [2024-11-17 08:53:40,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:40,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958116859] [2024-11-17 08:53:40,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:40,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:40,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:40,210 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:40,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:40,213 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:40,214 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:40,214 INFO L85 PathProgramCache]: Analyzing trace with hash 2090697494, now seen corresponding path program 1 times [2024-11-17 08:53:40,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:40,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099504552] [2024-11-17 08:53:40,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:40,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:40,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:40,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:40,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:40,241 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099504552] [2024-11-17 08:53:40,241 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099504552] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:40,241 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:40,241 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:40,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698859961] [2024-11-17 08:53:40,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:40,287 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:40,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:40,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:40,288 INFO L87 Difference]: Start difference. First operand 2669 states and 3526 transitions. cyclomatic complexity: 863 Second operand has 3 states, 2 states have (on average 27.5) internal successors, (55), 3 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:40,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:40,331 INFO L93 Difference]: Finished difference Result 2733 states and 3584 transitions. [2024-11-17 08:53:40,331 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2733 states and 3584 transitions. [2024-11-17 08:53:40,343 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2625 [2024-11-17 08:53:40,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2733 states to 2733 states and 3584 transitions. [2024-11-17 08:53:40,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2733 [2024-11-17 08:53:40,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2733 [2024-11-17 08:53:40,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2733 states and 3584 transitions. [2024-11-17 08:53:40,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:40,363 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2733 states and 3584 transitions. [2024-11-17 08:53:40,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2733 states and 3584 transitions. [2024-11-17 08:53:40,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2733 to 2733. [2024-11-17 08:53:40,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2733 states, 2733 states have (on average 1.3113794365166485) internal successors, (3584), 2732 states have internal predecessors, (3584), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:40,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2733 states to 2733 states and 3584 transitions. [2024-11-17 08:53:40,453 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2733 states and 3584 transitions. [2024-11-17 08:53:40,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:40,454 INFO L425 stractBuchiCegarLoop]: Abstraction has 2733 states and 3584 transitions. [2024-11-17 08:53:40,454 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:53:40,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2733 states and 3584 transitions. [2024-11-17 08:53:40,466 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2625 [2024-11-17 08:53:40,466 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:40,466 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:40,467 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:40,467 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:40,467 INFO L745 eck$LassoCheckResult]: Stem: 28299#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 28069#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~4#1;havoc main_~__retres1~4#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 28019#L491 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12#1, start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28020#L214-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28144#L221 assume 1 == ~m_i~0;~m_st~0 := 0; 28037#L226 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28038#L231 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28143#L237 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28257#L334-1 assume !(0 == ~M_E~0); 28191#L339-1 assume !(0 == ~T1_E~0); 28185#L344-1 assume !(0 == ~T2_E~0); 28186#L349-1 assume !(0 == ~E_1~0); 28097#L354-1 assume !(0 == ~E_2~0); 28098#L360-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28285#L156-4 assume !(1 == ~m_pc~0); 28080#L166-4 is_master_triggered_~__retres1~0#1 := 0; 28081#L159-4 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28270#L168-4 assume true;activate_threads_#t~ret8#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 28223#L405-4 assume !(0 != activate_threads_~tmp~1#1); 28055#L411-4 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28056#L175-4 assume !(1 == ~t1_pc~0); 28275#L185-4 is_transmit1_triggered_~__retres1~1#1 := 0; 28149#L178-4 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28150#L187-4 assume true;activate_threads_#t~ret9#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28214#L413-4 assume !(0 != activate_threads_~tmp___0~0#1); 28168#L419-4 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28169#L194-4 assume !(1 == ~t2_pc~0); 28179#L204-4 is_transmit2_triggered_~__retres1~2#1 := 0; 28180#L197-4 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28156#L206-4 assume true;activate_threads_#t~ret10#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28157#L421-4 assume !(0 != activate_threads_~tmp___1~0#1); 28066#L427-4 assume true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28067#L367-1 assume !(1 == ~M_E~0); 28219#L372-1 assume !(1 == ~T1_E~0); 28220#L377-1 assume !(1 == ~T2_E~0); 28064#L382-1 assume !(1 == ~E_1~0); 28065#L387-1 assume !(1 == ~E_2~0); 28151#L393-1 assume true;assume { :end_inline_reset_delta_events } true; 28203#L528 assume true; 29050#L528-1 assume !false; 29048#start_simulation_while_5_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29049#L271 [2024-11-17 08:53:40,468 INFO L747 eck$LassoCheckResult]: Loop: 29049#L271 assume true; 29125#L271-1 assume !false; 29124#eval_while_4_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 29123#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 29122#L254-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 29032#L262-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 29033#L276 assume 0 != eval_~tmp~0#1; 29025#L281-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 29026#L284 assume !(0 != eval_~tmp_ndt_1~0#1); 29136#L281 havoc eval_~tmp_ndt_1~0#1; 29131#L295-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 29130#L298 assume !(0 != eval_~tmp_ndt_2~0#1); 29129#L295 havoc eval_~tmp_ndt_2~0#1; 29128#L309-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 29127#L312 assume !(0 != eval_~tmp_ndt_3~0#1); 29126#L309 havoc eval_~tmp_ndt_3~0#1; 29049#L271 [2024-11-17 08:53:40,468 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:40,468 INFO L85 PathProgramCache]: Analyzing trace with hash 1122352840, now seen corresponding path program 3 times [2024-11-17 08:53:40,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:40,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653689519] [2024-11-17 08:53:40,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:40,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:40,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:40,478 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:40,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:40,487 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:40,488 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:40,488 INFO L85 PathProgramCache]: Analyzing trace with hash 731109494, now seen corresponding path program 1 times [2024-11-17 08:53:40,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:40,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1855541094] [2024-11-17 08:53:40,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:40,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:40,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:40,493 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:40,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:40,496 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:40,497 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:40,497 INFO L85 PathProgramCache]: Analyzing trace with hash -884397763, now seen corresponding path program 1 times [2024-11-17 08:53:40,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:40,497 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966175721] [2024-11-17 08:53:40,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:40,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:40,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:40,507 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:40,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:40,518 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:41,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:41,143 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:41,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:41,273 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.11 08:53:41 BoogieIcfgContainer [2024-11-17 08:53:41,273 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-17 08:53:41,274 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-17 08:53:41,274 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-17 08:53:41,277 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-17 08:53:41,278 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:37" (3/4) ... [2024-11-17 08:53:41,280 INFO L140 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-17 08:53:41,348 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-17 08:53:41,348 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-17 08:53:41,351 INFO L158 Benchmark]: Toolchain (without parser) took 5464.08ms. Allocated memory was 159.4MB in the beginning and 245.4MB in the end (delta: 86.0MB). Free memory was 101.5MB in the beginning and 85.4MB in the end (delta: 16.1MB). Peak memory consumption was 105.5MB. Max. memory is 16.1GB. [2024-11-17 08:53:41,352 INFO L158 Benchmark]: CDTParser took 0.25ms. Allocated memory is still 159.4MB. Free memory is still 119.5MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-17 08:53:41,353 INFO L158 Benchmark]: CACSL2BoogieTranslator took 358.87ms. Allocated memory is still 159.4MB. Free memory was 101.5MB in the beginning and 86.0MB in the end (delta: 15.5MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2024-11-17 08:53:41,353 INFO L158 Benchmark]: Boogie Procedure Inliner took 76.82ms. Allocated memory is still 159.4MB. Free memory was 86.0MB in the beginning and 83.1MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-17 08:53:41,353 INFO L158 Benchmark]: Boogie Preprocessor took 53.84ms. Allocated memory is still 159.4MB. Free memory was 83.1MB in the beginning and 80.6MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2024-11-17 08:53:41,353 INFO L158 Benchmark]: IcfgBuilder took 819.20ms. Allocated memory was 159.4MB in the beginning and 203.4MB in the end (delta: 44.0MB). Free memory was 80.6MB in the beginning and 158.9MB in the end (delta: -78.4MB). Peak memory consumption was 27.7MB. Max. memory is 16.1GB. [2024-11-17 08:53:41,354 INFO L158 Benchmark]: BuchiAutomizer took 4072.89ms. Allocated memory was 203.4MB in the beginning and 245.4MB in the end (delta: 41.9MB). Free memory was 158.9MB in the beginning and 90.6MB in the end (delta: 68.3MB). Peak memory consumption was 111.3MB. Max. memory is 16.1GB. [2024-11-17 08:53:41,355 INFO L158 Benchmark]: Witness Printer took 74.39ms. Allocated memory is still 245.4MB. Free memory was 90.6MB in the beginning and 85.4MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-17 08:53:41,356 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25ms. Allocated memory is still 159.4MB. Free memory is still 119.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 358.87ms. Allocated memory is still 159.4MB. Free memory was 101.5MB in the beginning and 86.0MB in the end (delta: 15.5MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 76.82ms. Allocated memory is still 159.4MB. Free memory was 86.0MB in the beginning and 83.1MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 53.84ms. Allocated memory is still 159.4MB. Free memory was 83.1MB in the beginning and 80.6MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * IcfgBuilder took 819.20ms. Allocated memory was 159.4MB in the beginning and 203.4MB in the end (delta: 44.0MB). Free memory was 80.6MB in the beginning and 158.9MB in the end (delta: -78.4MB). Peak memory consumption was 27.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 4072.89ms. Allocated memory was 203.4MB in the beginning and 245.4MB in the end (delta: 41.9MB). Free memory was 158.9MB in the beginning and 90.6MB in the end (delta: 68.3MB). Peak memory consumption was 111.3MB. Max. memory is 16.1GB. * Witness Printer took 74.39ms. Allocated memory is still 245.4MB. Free memory was 90.6MB in the beginning and 85.4MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 12 terminating modules (12 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.12 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2733 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.9s and 13 iterations. TraceHistogramMax:1. Analysis of lassos took 2.4s. Construction of modules took 0.3s. Büchi inclusion checks took 0.9s. Highest rank in rank-based complementation 0. Minimization of det autom 12. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 12 MinimizatonAttempts, 717 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2782 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2782 mSDsluCounter, 7007 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3288 mSDsCounter, 94 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 301 IncrementalHoareTripleChecker+Invalid, 395 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 94 mSolverCounterUnsat, 3719 mSDtfsCounter, 301 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN0 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0] [L573] int __retres1 ; [L577] CALL init_model() [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L577] RET init_model() [L578] CALL start_simulation() [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L521] FCALL update_channels() [L522] CALL init_threads() [L221] COND TRUE m_i == 1 [L222] m_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L522] RET init_threads() [L523] CALL fire_delta_events() [L334] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L339] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L344] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L349] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L354] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L523] RET fire_delta_events() [L524] CALL activate_threads() [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L403] CALL, EXPR is_master_triggered() [L153] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L156] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L166] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L168] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L403] RET, EXPR is_master_triggered() [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] CALL, EXPR is_transmit1_triggered() [L172] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L175] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L185] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L187] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L411] RET, EXPR is_transmit1_triggered() [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] CALL, EXPR is_transmit2_triggered() [L191] int __retres1 ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L194] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L204] __retres1 = 0 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L206] return (__retres1); VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L419] RET, EXPR is_transmit2_triggered() [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L524] RET activate_threads() [L525] CALL reset_delta_events() [L367] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L372] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L377] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L382] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L387] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L525] RET reset_delta_events() [L528] COND TRUE 1 VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] [L531] kernel_st = 1 [L532] CALL eval() [L267] int tmp ; VAL [E_1=2, E_2=2, M_E=2, T1_E=2, T2_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0] Loop: [L271] COND TRUE 1 [L274] CALL, EXPR exists_runnable_thread() [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] RET, EXPR exists_runnable_thread() [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-17 08:53:41,394 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)