./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.06.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.06.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:53:38,679 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:53:38,730 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:53:38,734 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:53:38,735 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:53:38,735 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:53:38,757 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:53:38,758 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:53:38,758 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:53:38,761 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:53:38,761 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:53:38,762 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:53:38,762 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:53:38,763 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:53:38,763 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:53:38,763 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:53:38,764 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:53:38,764 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:53:38,764 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:53:38,764 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:53:38,764 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:53:38,765 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:53:38,765 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:53:38,765 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:53:38,765 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:53:38,765 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:53:38,765 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:53:38,765 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:53:38,766 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:53:38,766 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:53:38,766 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:53:38,766 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:53:38,766 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:53:38,766 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:53:38,767 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:53:38,767 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:53:38,767 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:53:38,767 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:53:38,767 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:53:38,767 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:53:38,768 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df [2024-11-17 08:53:38,966 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:53:38,985 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:53:38,987 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:53:38,988 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:53:38,988 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:53:38,989 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.06.cil.c [2024-11-17 08:53:40,180 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:53:40,345 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:53:40,348 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.06.cil.c [2024-11-17 08:53:40,357 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3d03026e/70a407d8d9d947bb9c81fcd839075bfa/FLAG8fc89b692 [2024-11-17 08:53:40,372 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a3d03026e/70a407d8d9d947bb9c81fcd839075bfa [2024-11-17 08:53:40,374 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:53:40,375 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:53:40,377 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:40,377 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:53:40,381 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:53:40,382 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,382 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@380fb382 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40, skipping insertion in model container [2024-11-17 08:53:40,382 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,419 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:53:40,668 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:40,679 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:53:40,720 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:40,735 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:53:40,735 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40 WrapperNode [2024-11-17 08:53:40,735 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:40,736 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:40,736 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:53:40,736 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:53:40,743 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,752 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,797 INFO L138 Inliner]: procedures = 40, calls = 49, calls flagged for inlining = 44, calls inlined = 105, statements flattened = 1526 [2024-11-17 08:53:40,798 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:40,798 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:53:40,798 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:53:40,798 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:53:40,809 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,809 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,821 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,843 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:53:40,844 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,844 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,861 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,862 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,867 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,869 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,876 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:53:40,876 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:53:40,877 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:53:40,877 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:53:40,877 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (1/1) ... [2024-11-17 08:53:40,884 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:53:40,895 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:53:40,908 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:53:40,910 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:53:40,947 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:53:40,948 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:53:40,948 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:53:40,948 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:53:41,027 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:53:41,029 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:53:41,963 INFO L? ?]: Removed 290 outVars from TransFormulas that were not future-live. [2024-11-17 08:53:41,963 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:53:41,997 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:53:41,997 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:53:41,998 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:41 BoogieIcfgContainer [2024-11-17 08:53:41,998 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:53:42,002 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:53:42,003 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:53:42,006 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:53:42,007 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:42,007 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:53:40" (1/3) ... [2024-11-17 08:53:42,008 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e864db0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:42, skipping insertion in model container [2024-11-17 08:53:42,008 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:42,008 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:40" (2/3) ... [2024-11-17 08:53:42,010 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e864db0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:42, skipping insertion in model container [2024-11-17 08:53:42,010 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:42,010 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:41" (3/3) ... [2024-11-17 08:53:42,011 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.06.cil.c [2024-11-17 08:53:42,058 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:53:42,058 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:53:42,058 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:53:42,058 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:53:42,058 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:53:42,058 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:53:42,058 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:53:42,058 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:53:42,063 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 676 states, 675 states have (on average 1.4948148148148148) internal successors, (1009), 675 states have internal predecessors, (1009), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:42,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 582 [2024-11-17 08:53:42,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:42,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:42,109 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:42,109 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:42,110 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:53:42,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 676 states, 675 states have (on average 1.4948148148148148) internal successors, (1009), 675 states have internal predecessors, (1009), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:42,117 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 582 [2024-11-17 08:53:42,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:42,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:42,119 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:42,119 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:42,125 INFO L745 eck$LassoCheckResult]: Stem: 664#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 45#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 450#L987true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 398#L454-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3#L461true assume !(1 == ~m_i~0);~m_st~0 := 2; 320#L466true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 43#L471true assume 1 == ~t2_i~0;~t2_st~0 := 0; 389#L476true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 543#L481true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 123#L486true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 333#L491true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 666#L497true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 438#L670-1true assume !(0 == ~M_E~0); 277#L675-1true assume !(0 == ~T1_E~0); 367#L680-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 474#L685-1true assume !(0 == ~T3_E~0); 336#L690-1true assume !(0 == ~T4_E~0); 653#L695-1true assume !(0 == ~T5_E~0); 416#L700-1true assume !(0 == ~T6_E~0); 406#L705-1true assume !(0 == ~E_1~0); 594#L710-1true assume !(0 == ~E_2~0); 276#L715-1true assume !(0 == ~E_3~0); 225#L720-1true assume 0 == ~E_4~0;~E_4~0 := 1; 261#L725-1true assume !(0 == ~E_5~0); 308#L730-1true assume !(0 == ~E_6~0); 249#L736-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 240#L320-8true assume 1 == ~m_pc~0; 658#L321-8true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 168#L323-8true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 446#L332-8true assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 116#L825-8true assume !(0 != activate_threads_~tmp~1#1); 480#L831-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 462#L339-8true assume 1 == ~t1_pc~0; 8#L340-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 231#L342-8true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62#L351-8true assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 476#L833-8true assume !(0 != activate_threads_~tmp___0~0#1); 306#L839-8true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 545#L358-8true assume !(1 == ~t2_pc~0); 151#L368-8true is_transmit2_triggered_~__retres1~2#1 := 0; 330#L361-8true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 535#L370-8true assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 319#L841-8true assume !(0 != activate_threads_~tmp___1~0#1); 522#L847-8true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 228#L377-8true assume 1 == ~t3_pc~0; 550#L378-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 79#L380-8true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52#L389-8true assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 451#L849-8true assume !(0 != activate_threads_~tmp___2~0#1); 485#L855-8true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 498#L396-8true assume 1 == ~t4_pc~0; 207#L397-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 670#L399-8true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158#L408-8true assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95#L857-8true assume !(0 != activate_threads_~tmp___3~0#1); 316#L863-8true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 630#L415-8true assume 1 == ~t5_pc~0; 426#L416-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 237#L418-8true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 283#L427-8true assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 179#L865-8true assume !(0 != activate_threads_~tmp___4~0#1); 659#L871-8true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 608#L434-8true assume !(1 == ~t6_pc~0); 309#L444-8true is_transmit6_triggered_~__retres1~6#1 := 0; 467#L437-8true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 589#L446-8true assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 478#L873-8true assume !(0 != activate_threads_~tmp___5~0#1); 555#L879-8true assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 668#L743-1true assume !(1 == ~M_E~0); 530#L748-1true assume !(1 == ~T1_E~0); 300#L753-1true assume !(1 == ~T2_E~0); 424#L758-1true assume !(1 == ~T3_E~0); 502#L763-1true assume !(1 == ~T4_E~0); 600#L768-1true assume !(1 == ~T5_E~0); 167#L773-1true assume !(1 == ~T6_E~0); 662#L778-1true assume !(1 == ~E_1~0); 153#L783-1true assume !(1 == ~E_2~0); 642#L788-1true assume !(1 == ~E_3~0); 366#L793-1true assume !(1 == ~E_4~0); 332#L798-1true assume !(1 == ~E_5~0); 75#L803-1true assume !(1 == ~E_6~0); 646#L809-1true assume true;assume { :end_inline_reset_delta_events } true; 185#L1024true [2024-11-17 08:53:42,127 INFO L747 eck$LassoCheckResult]: Loop: 185#L1024true assume true; 381#L1024-1true assume !false; 663#start_simulation_while_9_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 209#L551true assume !true; 226#L559true assume true; 31#L663true assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6#L454true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 576#L670true assume 0 == ~M_E~0;~M_E~0 := 1; 89#L675true assume 0 == ~T1_E~0;~T1_E~0 := 1; 667#L680true assume 0 == ~T2_E~0;~T2_E~0 := 1; 440#L685true assume !(0 == ~T3_E~0); 581#L690true assume 0 == ~T4_E~0;~T4_E~0 := 1; 492#L695true assume 0 == ~T5_E~0;~T5_E~0 := 1; 408#L700true assume 0 == ~T6_E~0;~T6_E~0 := 1; 303#L705true assume 0 == ~E_1~0;~E_1~0 := 1; 93#L710true assume 0 == ~E_2~0;~E_2~0 := 1; 343#L715true assume 0 == ~E_3~0;~E_3~0 := 1; 375#L720true assume 0 == ~E_4~0;~E_4~0 := 1; 15#L725true assume !(0 == ~E_5~0); 404#L730true assume 0 == ~E_6~0;~E_6~0 := 1; 218#L736true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 368#L320-1true assume 1 == ~m_pc~0; 625#L321-1true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 447#L323-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 382#L332-1true assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 528#L825-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 562#L831-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 149#L339-1true assume 1 == ~t1_pc~0; 221#L340-1true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16#L342-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 204#L351-1true assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 586#L833-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 140#L839-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 577#L358-1true assume 1 == ~t2_pc~0; 626#L359-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 192#L361-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 338#L370-1true assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 126#L841-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 380#L847-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 526#L377-1true assume 1 == ~t3_pc~0; 183#L378-1true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 511#L380-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 592#L389-1true assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 564#L849-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 517#L855-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 363#L396-1true assume 1 == ~t4_pc~0; 137#L397-1true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 482#L399-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 281#L408-1true assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 675#L857-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2#L863-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 536#L415-1true assume !(1 == ~t5_pc~0); 109#L425-1true is_transmit5_triggered_~__retres1~5#1 := 0; 509#L418-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88#L427-1true assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 622#L865-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 612#L871-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 479#L434-1true assume 1 == ~t6_pc~0; 494#L435-1true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 557#L437-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 613#L446-1true assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 607#L873-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 411#L879-1true assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 584#L743true assume 1 == ~M_E~0;~M_E~0 := 2; 61#L748true assume 1 == ~T1_E~0;~T1_E~0 := 2; 496#L753true assume 1 == ~T2_E~0;~T2_E~0 := 2; 454#L758true assume 1 == ~T3_E~0;~T3_E~0 := 2; 604#L763true assume 1 == ~T4_E~0;~T4_E~0 := 2; 14#L768true assume 1 == ~T5_E~0;~T5_E~0 := 2; 573#L773true assume 1 == ~T6_E~0;~T6_E~0 := 2; 184#L778true assume 1 == ~E_1~0;~E_1~0 := 2; 103#L783true assume 1 == ~E_2~0;~E_2~0 := 2; 172#L788true assume 1 == ~E_3~0;~E_3~0 := 2; 565#L793true assume 1 == ~E_4~0;~E_4~0 := 2; 227#L798true assume 1 == ~E_5~0;~E_5~0 := 2; 360#L803true assume 1 == ~E_6~0;~E_6~0 := 2; 315#L809true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 120#L504-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 436#L530-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 238#L542-1true assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 475#L1043true assume !(0 == start_simulation_~tmp~3#1); 464#L1054true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 615#L504true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 385#L530true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 512#L542true assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 253#L998true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 459#L1000true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 171#L1006true assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 248#L1056true assume !(0 != start_simulation_~tmp___0~1#1); 185#L1024true [2024-11-17 08:53:42,132 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:42,132 INFO L85 PathProgramCache]: Analyzing trace with hash -2112068791, now seen corresponding path program 1 times [2024-11-17 08:53:42,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:42,138 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827845894] [2024-11-17 08:53:42,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:42,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:42,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:42,331 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:42,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:42,332 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827845894] [2024-11-17 08:53:42,332 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [827845894] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:42,332 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:42,332 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:42,333 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [482822911] [2024-11-17 08:53:42,334 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:42,337 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:42,337 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:42,337 INFO L85 PathProgramCache]: Analyzing trace with hash -1043835734, now seen corresponding path program 1 times [2024-11-17 08:53:42,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:42,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337693007] [2024-11-17 08:53:42,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:42,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:42,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:42,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:42,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:42,374 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1337693007] [2024-11-17 08:53:42,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1337693007] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:42,374 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:42,375 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:42,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1973639898] [2024-11-17 08:53:42,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:42,376 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:42,376 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:42,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:42,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:42,401 INFO L87 Difference]: Start difference. First operand has 676 states, 675 states have (on average 1.4948148148148148) internal successors, (1009), 675 states have internal predecessors, (1009), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:42,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:42,448 INFO L93 Difference]: Finished difference Result 666 states and 977 transitions. [2024-11-17 08:53:42,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 666 states and 977 transitions. [2024-11-17 08:53:42,457 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:42,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 666 states to 659 states and 970 transitions. [2024-11-17 08:53:42,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 659 [2024-11-17 08:53:42,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 659 [2024-11-17 08:53:42,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 659 states and 970 transitions. [2024-11-17 08:53:42,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:42,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 659 states and 970 transitions. [2024-11-17 08:53:42,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states and 970 transitions. [2024-11-17 08:53:42,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 659. [2024-11-17 08:53:42,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 659 states, 659 states have (on average 1.471927162367223) internal successors, (970), 658 states have internal predecessors, (970), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:42,511 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 970 transitions. [2024-11-17 08:53:42,512 INFO L240 hiAutomatonCegarLoop]: Abstraction has 659 states and 970 transitions. [2024-11-17 08:53:42,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:42,517 INFO L425 stractBuchiCegarLoop]: Abstraction has 659 states and 970 transitions. [2024-11-17 08:53:42,517 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:53:42,517 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 659 states and 970 transitions. [2024-11-17 08:53:42,519 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:42,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:42,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:42,523 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:42,523 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:42,523 INFO L745 eck$LassoCheckResult]: Stem: 2009#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1440#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1441#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1907#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1353#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1354#L466 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1438#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1439#L476 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1904#L481 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1574#L486 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1575#L491 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1862#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1940#L670-1 assume !(0 == ~M_E~0); 1795#L675-1 assume !(0 == ~T1_E~0); 1796#L680-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1889#L685-1 assume !(0 == ~T3_E~0); 1863#L690-1 assume !(0 == ~T4_E~0); 1864#L695-1 assume !(0 == ~T5_E~0); 1924#L700-1 assume !(0 == ~T6_E~0); 1912#L705-1 assume !(0 == ~E_1~0); 1913#L710-1 assume !(0 == ~E_2~0); 1794#L715-1 assume !(0 == ~E_3~0); 1737#L720-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1738#L725-1 assume !(0 == ~E_5~0); 1779#L730-1 assume !(0 == ~E_6~0); 1765#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1754#L320-8 assume 1 == ~m_pc~0; 1755#L321-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1656#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1657#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1565#L825-8 assume !(0 != activate_threads_~tmp~1#1); 1566#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1953#L339-8 assume 1 == ~t1_pc~0; 1363#L340-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1364#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1473#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1474#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 1833#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1834#L358-8 assume !(1 == ~t2_pc~0); 1629#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 1630#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1857#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1845#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 1846#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1741#L377-8 assume 1 == ~t3_pc~0; 1742#L378-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1388#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1455#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1456#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 1948#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1968#L396-8 assume 1 == ~t4_pc~0; 1708#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1709#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1643#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1531#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 1532#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1842#L415-8 assume 1 == ~t5_pc~0; 1932#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1514#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1752#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1676#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 1677#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2006#L434-8 assume !(1 == ~t6_pc~0); 1835#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 1836#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1957#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1963#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 1964#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1994#L743-1 assume !(1 == ~M_E~0); 1985#L748-1 assume !(1 == ~T1_E~0); 1827#L753-1 assume !(1 == ~T2_E~0); 1828#L758-1 assume !(1 == ~T3_E~0); 1931#L763-1 assume !(1 == ~T4_E~0); 1974#L768-1 assume !(1 == ~T5_E~0); 1654#L773-1 assume !(1 == ~T6_E~0); 1655#L778-1 assume !(1 == ~E_1~0); 1634#L783-1 assume !(1 == ~E_2~0); 1635#L788-1 assume !(1 == ~E_3~0); 1887#L793-1 assume !(1 == ~E_4~0); 1860#L798-1 assume !(1 == ~E_5~0); 1495#L803-1 assume !(1 == ~E_6~0); 1496#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 1685#L1024 [2024-11-17 08:53:42,524 INFO L747 eck$LassoCheckResult]: Loop: 1685#L1024 assume true; 1686#L1024-1 assume !false; 1895#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1622#L551 assume true; 1713#L551-1 assume !false; 1882#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1810#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1584#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1668#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1780#L556 assume !(0 != eval_~tmp~0#1); 1739#L559 assume true; 1417#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1361#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1362#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 1521#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1522#L680 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1942#L685 assume !(0 == ~T3_E~0); 1943#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1970#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1916#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1831#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 1528#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 1529#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 1870#L720 assume 0 == ~E_4~0;~E_4~0 := 1; 1379#L725 assume !(0 == ~E_5~0); 1380#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 1725#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1726#L320-1 assume 1 == ~m_pc~0; 1890#L321-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1390#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1896#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1897#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1983#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1625#L339-1 assume 1 == ~t1_pc~0; 1626#L340-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1381#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1382#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1706#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1610#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1611#L358-1 assume 1 == ~t2_pc~0; 1997#L359-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1695#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1696#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1581#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1582#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1894#L377-1 assume 1 == ~t3_pc~0; 1681#L378-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1682#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1977#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1995#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1978#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1881#L396-1 assume 1 == ~t4_pc~0; 1603#L397-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1604#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1803#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1804#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1351#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1352#L415-1 assume 1 == ~t5_pc~0; 1981#L416-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1552#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1517#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1518#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2008#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1961#L434-1 assume 1 == ~t6_pc~0; 1962#L435-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1675#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1993#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2005#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1917#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1918#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 1469#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1470#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1950#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1951#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1377#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1378#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1684#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 1542#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 1543#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 1663#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 1735#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 1736#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 1841#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1569#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1479#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1750#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1751#L1043 assume !(0 == start_simulation_~tmp~3#1); 1872#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1954#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1451#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1900#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1768#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1769#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1661#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1662#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 1685#L1024 [2024-11-17 08:53:42,524 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:42,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1763381674, now seen corresponding path program 1 times [2024-11-17 08:53:42,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:42,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [920581483] [2024-11-17 08:53:42,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:42,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:42,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:42,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:42,607 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:42,607 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [920581483] [2024-11-17 08:53:42,607 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [920581483] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:42,607 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:42,607 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:42,607 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006257988] [2024-11-17 08:53:42,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:42,608 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:42,608 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:42,608 INFO L85 PathProgramCache]: Analyzing trace with hash 2126476244, now seen corresponding path program 1 times [2024-11-17 08:53:42,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:42,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555121183] [2024-11-17 08:53:42,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:42,609 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:42,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:42,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:42,757 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:42,757 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555121183] [2024-11-17 08:53:42,757 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555121183] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:42,760 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:42,760 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:42,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40901561] [2024-11-17 08:53:42,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:42,761 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:42,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:42,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:42,762 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:42,762 INFO L87 Difference]: Start difference. First operand 659 states and 970 transitions. cyclomatic complexity: 312 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:42,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:42,779 INFO L93 Difference]: Finished difference Result 659 states and 969 transitions. [2024-11-17 08:53:42,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 659 states and 969 transitions. [2024-11-17 08:53:42,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:42,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 659 states to 659 states and 969 transitions. [2024-11-17 08:53:42,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 659 [2024-11-17 08:53:42,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 659 [2024-11-17 08:53:42,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 659 states and 969 transitions. [2024-11-17 08:53:42,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:42,789 INFO L218 hiAutomatonCegarLoop]: Abstraction has 659 states and 969 transitions. [2024-11-17 08:53:42,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states and 969 transitions. [2024-11-17 08:53:42,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 659. [2024-11-17 08:53:42,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 659 states, 659 states have (on average 1.4704097116843702) internal successors, (969), 658 states have internal predecessors, (969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:42,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 969 transitions. [2024-11-17 08:53:42,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 659 states and 969 transitions. [2024-11-17 08:53:42,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:42,810 INFO L425 stractBuchiCegarLoop]: Abstraction has 659 states and 969 transitions. [2024-11-17 08:53:42,810 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:53:42,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 659 states and 969 transitions. [2024-11-17 08:53:42,812 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:42,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:42,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:42,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:42,816 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:42,817 INFO L745 eck$LassoCheckResult]: Stem: 3336#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 2770#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 2771#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3234#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2680#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 2681#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2765#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2766#L476 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3231#L481 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2904#L486 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2905#L491 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3189#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3267#L670-1 assume !(0 == ~M_E~0); 3122#L675-1 assume !(0 == ~T1_E~0); 3123#L680-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3217#L685-1 assume !(0 == ~T3_E~0); 3190#L690-1 assume !(0 == ~T4_E~0); 3191#L695-1 assume !(0 == ~T5_E~0); 3251#L700-1 assume !(0 == ~T6_E~0); 3239#L705-1 assume !(0 == ~E_1~0); 3240#L710-1 assume !(0 == ~E_2~0); 3121#L715-1 assume !(0 == ~E_3~0); 3065#L720-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3066#L725-1 assume !(0 == ~E_5~0); 3106#L730-1 assume !(0 == ~E_6~0); 3092#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3082#L320-8 assume 1 == ~m_pc~0; 3083#L321-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2983#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2984#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2889#L825-8 assume !(0 != activate_threads_~tmp~1#1); 2890#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3279#L339-8 assume 1 == ~t1_pc~0; 2690#L340-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2691#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2798#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2799#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 3160#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3161#L358-8 assume !(1 == ~t2_pc~0); 2955#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 2956#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3184#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3172#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 3173#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3067#L377-8 assume 1 == ~t3_pc~0; 3068#L378-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2713#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2782#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2783#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 3275#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3295#L396-8 assume 1 == ~t4_pc~0; 3035#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3036#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2969#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2858#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 2859#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3169#L415-8 assume 1 == ~t5_pc~0; 3259#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2841#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3077#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3003#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 3004#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3333#L434-8 assume !(1 == ~t6_pc~0); 3162#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 3163#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3284#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3288#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 3289#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3320#L743-1 assume !(1 == ~M_E~0); 3311#L748-1 assume !(1 == ~T1_E~0); 3154#L753-1 assume !(1 == ~T2_E~0); 3155#L758-1 assume !(1 == ~T3_E~0); 3257#L763-1 assume !(1 == ~T4_E~0); 3301#L768-1 assume !(1 == ~T5_E~0); 2981#L773-1 assume !(1 == ~T6_E~0); 2982#L778-1 assume !(1 == ~E_1~0); 2958#L783-1 assume !(1 == ~E_2~0); 2959#L788-1 assume !(1 == ~E_3~0); 3214#L793-1 assume !(1 == ~E_4~0); 3187#L798-1 assume !(1 == ~E_5~0); 2822#L803-1 assume !(1 == ~E_6~0); 2823#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 3012#L1024 [2024-11-17 08:53:42,818 INFO L747 eck$LassoCheckResult]: Loop: 3012#L1024 assume true; 3013#L1024-1 assume !false; 3222#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2948#L551 assume true; 3040#L551-1 assume !false; 3208#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3137#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2911#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2995#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3107#L556 assume !(0 != eval_~tmp~0#1); 3062#L559 assume true; 2742#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2686#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2687#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 2848#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2849#L680 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3269#L685 assume !(0 == ~T3_E~0); 3270#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3297#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3243#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3158#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 2855#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 2856#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 3197#L720 assume 0 == ~E_4~0;~E_4~0 := 1; 2706#L725 assume !(0 == ~E_5~0); 2707#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 3052#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3053#L320-1 assume !(1 == ~m_pc~0); 2714#L330-1 is_master_triggered_~__retres1~0#1 := 0; 2715#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3223#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3224#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3310#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2952#L339-1 assume 1 == ~t1_pc~0; 2953#L340-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2708#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2709#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3033#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2937#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2938#L358-1 assume 1 == ~t2_pc~0; 3324#L359-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3022#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3023#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2908#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2909#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3221#L377-1 assume 1 == ~t3_pc~0; 3008#L378-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3009#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3304#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3322#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3305#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3209#L396-1 assume 1 == ~t4_pc~0; 2931#L397-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2932#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3130#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3131#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2678#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2679#L415-1 assume 1 == ~t5_pc~0; 3308#L416-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2880#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2846#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2847#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3335#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3290#L434-1 assume !(1 == ~t6_pc~0); 3001#L444-1 is_transmit6_triggered_~__retres1~6#1 := 0; 3002#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3321#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3332#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3245#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3246#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 2796#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2797#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3277#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3278#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2704#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2705#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3011#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 2870#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 2871#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 2990#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 3063#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 3064#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 3168#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2896#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2806#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3078#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3079#L1043 assume !(0 == start_simulation_~tmp~3#1); 3199#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3281#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2778#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3227#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3095#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3096#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2988#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2989#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 3012#L1024 [2024-11-17 08:53:42,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:42,818 INFO L85 PathProgramCache]: Analyzing trace with hash 1749848873, now seen corresponding path program 1 times [2024-11-17 08:53:42,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:42,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079444341] [2024-11-17 08:53:42,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:42,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:42,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:42,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:42,855 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:42,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079444341] [2024-11-17 08:53:42,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079444341] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:42,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:42,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:42,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339117396] [2024-11-17 08:53:42,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:42,857 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:42,857 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:42,857 INFO L85 PathProgramCache]: Analyzing trace with hash -1039587314, now seen corresponding path program 1 times [2024-11-17 08:53:42,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:42,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1086419493] [2024-11-17 08:53:42,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:42,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:42,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:42,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:42,922 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:42,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1086419493] [2024-11-17 08:53:42,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1086419493] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:42,923 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:42,923 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:42,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414589803] [2024-11-17 08:53:42,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:42,923 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:42,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:42,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:42,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:42,924 INFO L87 Difference]: Start difference. First operand 659 states and 969 transitions. cyclomatic complexity: 311 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:42,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:42,934 INFO L93 Difference]: Finished difference Result 659 states and 968 transitions. [2024-11-17 08:53:42,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 659 states and 968 transitions. [2024-11-17 08:53:42,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:42,940 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 659 states to 659 states and 968 transitions. [2024-11-17 08:53:42,940 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 659 [2024-11-17 08:53:42,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 659 [2024-11-17 08:53:42,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 659 states and 968 transitions. [2024-11-17 08:53:42,942 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:42,942 INFO L218 hiAutomatonCegarLoop]: Abstraction has 659 states and 968 transitions. [2024-11-17 08:53:42,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states and 968 transitions. [2024-11-17 08:53:42,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 659. [2024-11-17 08:53:42,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 659 states, 659 states have (on average 1.4688922610015174) internal successors, (968), 658 states have internal predecessors, (968), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:42,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 968 transitions. [2024-11-17 08:53:42,949 INFO L240 hiAutomatonCegarLoop]: Abstraction has 659 states and 968 transitions. [2024-11-17 08:53:42,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:42,951 INFO L425 stractBuchiCegarLoop]: Abstraction has 659 states and 968 transitions. [2024-11-17 08:53:42,951 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:53:42,951 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 659 states and 968 transitions. [2024-11-17 08:53:42,953 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:42,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:42,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:42,954 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:42,955 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:42,955 INFO L745 eck$LassoCheckResult]: Stem: 4663#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4094#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4095#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4561#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4007#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 4008#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4090#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4091#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4558#L481 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4228#L486 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4229#L491 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4515#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4594#L670-1 assume !(0 == ~M_E~0); 4449#L675-1 assume !(0 == ~T1_E~0); 4450#L680-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4542#L685-1 assume !(0 == ~T3_E~0); 4517#L690-1 assume !(0 == ~T4_E~0); 4518#L695-1 assume !(0 == ~T5_E~0); 4578#L700-1 assume !(0 == ~T6_E~0); 4566#L705-1 assume !(0 == ~E_1~0); 4567#L710-1 assume !(0 == ~E_2~0); 4448#L715-1 assume !(0 == ~E_3~0); 4389#L720-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4390#L725-1 assume !(0 == ~E_5~0); 4433#L730-1 assume !(0 == ~E_6~0); 4419#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4408#L320-8 assume 1 == ~m_pc~0; 4409#L321-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4310#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4311#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4216#L825-8 assume !(0 != activate_threads_~tmp~1#1); 4217#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4606#L339-8 assume 1 == ~t1_pc~0; 4017#L340-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4018#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4125#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4126#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 4487#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4488#L358-8 assume !(1 == ~t2_pc~0); 4282#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 4283#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4511#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4499#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 4500#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4394#L377-8 assume 1 == ~t3_pc~0; 4395#L378-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4040#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4109#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4110#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 4602#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4622#L396-8 assume 1 == ~t4_pc~0; 4362#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4363#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4296#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4185#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 4186#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4496#L415-8 assume 1 == ~t5_pc~0; 4586#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4168#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4404#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4330#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 4331#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4660#L434-8 assume !(1 == ~t6_pc~0); 4489#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 4490#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4611#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4615#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 4616#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4647#L743-1 assume !(1 == ~M_E~0); 4638#L748-1 assume !(1 == ~T1_E~0); 4481#L753-1 assume !(1 == ~T2_E~0); 4482#L758-1 assume !(1 == ~T3_E~0); 4584#L763-1 assume !(1 == ~T4_E~0); 4628#L768-1 assume !(1 == ~T5_E~0); 4308#L773-1 assume !(1 == ~T6_E~0); 4309#L778-1 assume !(1 == ~E_1~0); 4285#L783-1 assume !(1 == ~E_2~0); 4286#L788-1 assume !(1 == ~E_3~0); 4541#L793-1 assume !(1 == ~E_4~0); 4514#L798-1 assume !(1 == ~E_5~0); 4149#L803-1 assume !(1 == ~E_6~0); 4150#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 4339#L1024 [2024-11-17 08:53:42,955 INFO L747 eck$LassoCheckResult]: Loop: 4339#L1024 assume true; 4340#L1024-1 assume !false; 4549#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4275#L551 assume true; 4367#L551-1 assume !false; 4535#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4464#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4238#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4322#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4434#L556 assume !(0 != eval_~tmp~0#1); 4391#L559 assume true; 4069#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4013#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4014#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 4175#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4176#L680 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4596#L685 assume !(0 == ~T3_E~0); 4597#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4624#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4570#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4485#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 4182#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 4183#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 4524#L720 assume 0 == ~E_4~0;~E_4~0 := 1; 4033#L725 assume !(0 == ~E_5~0); 4034#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 4379#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4380#L320-1 assume !(1 == ~m_pc~0); 4041#L330-1 is_master_triggered_~__retres1~0#1 := 0; 4042#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4550#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4551#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4637#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4279#L339-1 assume 1 == ~t1_pc~0; 4280#L340-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4035#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4036#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4360#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4264#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4265#L358-1 assume 1 == ~t2_pc~0; 4651#L359-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4349#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4350#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4235#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4236#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4548#L377-1 assume !(1 == ~t3_pc~0); 4337#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 4336#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4631#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4649#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4632#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4536#L396-1 assume 1 == ~t4_pc~0; 4258#L397-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4259#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4457#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4458#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4005#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4006#L415-1 assume 1 == ~t5_pc~0; 4635#L416-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4207#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4173#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4174#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4662#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4617#L434-1 assume !(1 == ~t6_pc~0); 4328#L444-1 is_transmit6_triggered_~__retres1~6#1 := 0; 4329#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4648#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4659#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4572#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4573#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 4123#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4124#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4604#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4605#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4031#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4032#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4338#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 4197#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 4198#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 4317#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 4392#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 4393#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 4495#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4223#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4133#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4405#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4406#L1043 assume !(0 == start_simulation_~tmp~3#1); 4526#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4608#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4105#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4554#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 4422#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4423#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4315#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4316#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 4339#L1024 [2024-11-17 08:53:42,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:42,956 INFO L85 PathProgramCache]: Analyzing trace with hash 882796648, now seen corresponding path program 1 times [2024-11-17 08:53:42,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:42,956 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040616200] [2024-11-17 08:53:42,956 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:42,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:42,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:42,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:42,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:42,993 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040616200] [2024-11-17 08:53:42,993 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040616200] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:42,993 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:42,993 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:42,993 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1713722899] [2024-11-17 08:53:42,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:42,993 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:42,993 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:42,994 INFO L85 PathProgramCache]: Analyzing trace with hash -1264608725, now seen corresponding path program 1 times [2024-11-17 08:53:42,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:42,994 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1098402187] [2024-11-17 08:53:42,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:42,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,046 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1098402187] [2024-11-17 08:53:43,047 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1098402187] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,047 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,047 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:43,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190427874] [2024-11-17 08:53:43,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,048 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:43,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:43,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:43,048 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:43,048 INFO L87 Difference]: Start difference. First operand 659 states and 968 transitions. cyclomatic complexity: 310 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:43,058 INFO L93 Difference]: Finished difference Result 659 states and 967 transitions. [2024-11-17 08:53:43,058 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 659 states and 967 transitions. [2024-11-17 08:53:43,061 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:43,063 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 659 states to 659 states and 967 transitions. [2024-11-17 08:53:43,063 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 659 [2024-11-17 08:53:43,064 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 659 [2024-11-17 08:53:43,064 INFO L73 IsDeterministic]: Start isDeterministic. Operand 659 states and 967 transitions. [2024-11-17 08:53:43,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:43,065 INFO L218 hiAutomatonCegarLoop]: Abstraction has 659 states and 967 transitions. [2024-11-17 08:53:43,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states and 967 transitions. [2024-11-17 08:53:43,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 659. [2024-11-17 08:53:43,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 659 states, 659 states have (on average 1.4673748103186646) internal successors, (967), 658 states have internal predecessors, (967), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 967 transitions. [2024-11-17 08:53:43,094 INFO L240 hiAutomatonCegarLoop]: Abstraction has 659 states and 967 transitions. [2024-11-17 08:53:43,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:43,096 INFO L425 stractBuchiCegarLoop]: Abstraction has 659 states and 967 transitions. [2024-11-17 08:53:43,096 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:53:43,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 659 states and 967 transitions. [2024-11-17 08:53:43,098 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:43,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:43,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:43,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:43,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:43,099 INFO L745 eck$LassoCheckResult]: Stem: 5990#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 5421#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5422#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5888#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5334#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 5335#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5417#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5418#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5885#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5555#L486 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5556#L491 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5842#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5921#L670-1 assume !(0 == ~M_E~0); 5776#L675-1 assume !(0 == ~T1_E~0); 5777#L680-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5870#L685-1 assume !(0 == ~T3_E~0); 5844#L690-1 assume !(0 == ~T4_E~0); 5845#L695-1 assume !(0 == ~T5_E~0); 5905#L700-1 assume !(0 == ~T6_E~0); 5893#L705-1 assume !(0 == ~E_1~0); 5894#L710-1 assume !(0 == ~E_2~0); 5775#L715-1 assume !(0 == ~E_3~0); 5718#L720-1 assume 0 == ~E_4~0;~E_4~0 := 1; 5719#L725-1 assume !(0 == ~E_5~0); 5760#L730-1 assume !(0 == ~E_6~0); 5746#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5735#L320-8 assume 1 == ~m_pc~0; 5736#L321-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5637#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5638#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5546#L825-8 assume !(0 != activate_threads_~tmp~1#1); 5547#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5933#L339-8 assume 1 == ~t1_pc~0; 5344#L340-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5345#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5454#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5455#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 5814#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5815#L358-8 assume !(1 == ~t2_pc~0); 5609#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 5610#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5838#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5826#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 5827#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5722#L377-8 assume 1 == ~t3_pc~0; 5723#L378-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5367#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5436#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5437#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 5929#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5949#L396-8 assume 1 == ~t4_pc~0; 5689#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5690#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5623#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5512#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 5513#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5823#L415-8 assume 1 == ~t5_pc~0; 5913#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5495#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5733#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5657#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 5658#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5987#L434-8 assume !(1 == ~t6_pc~0); 5816#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 5817#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5938#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5944#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 5945#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5975#L743-1 assume !(1 == ~M_E~0); 5965#L748-1 assume !(1 == ~T1_E~0); 5808#L753-1 assume !(1 == ~T2_E~0); 5809#L758-1 assume !(1 == ~T3_E~0); 5911#L763-1 assume !(1 == ~T4_E~0); 5955#L768-1 assume !(1 == ~T5_E~0); 5635#L773-1 assume !(1 == ~T6_E~0); 5636#L778-1 assume !(1 == ~E_1~0); 5615#L783-1 assume !(1 == ~E_2~0); 5616#L788-1 assume !(1 == ~E_3~0); 5868#L793-1 assume !(1 == ~E_4~0); 5841#L798-1 assume !(1 == ~E_5~0); 5476#L803-1 assume !(1 == ~E_6~0); 5477#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 5666#L1024 [2024-11-17 08:53:43,104 INFO L747 eck$LassoCheckResult]: Loop: 5666#L1024 assume true; 5667#L1024-1 assume !false; 5876#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5603#L551 assume true; 5694#L551-1 assume !false; 5863#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5791#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5565#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5649#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5761#L556 assume !(0 != eval_~tmp~0#1); 5720#L559 assume true; 5398#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5342#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5343#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 5502#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5503#L680 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5923#L685 assume !(0 == ~T3_E~0); 5924#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5951#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5897#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5812#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 5509#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 5510#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 5851#L720 assume 0 == ~E_4~0;~E_4~0 := 1; 5360#L725 assume !(0 == ~E_5~0); 5361#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 5706#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5707#L320-1 assume !(1 == ~m_pc~0); 5368#L330-1 is_master_triggered_~__retres1~0#1 := 0; 5369#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5877#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5878#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5964#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5606#L339-1 assume 1 == ~t1_pc~0; 5607#L340-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5362#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5363#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5687#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5591#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5592#L358-1 assume 1 == ~t2_pc~0; 5978#L359-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5676#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5677#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5562#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5563#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5875#L377-1 assume !(1 == ~t3_pc~0); 5664#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 5663#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5958#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5976#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5959#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5862#L396-1 assume 1 == ~t4_pc~0; 5584#L397-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5585#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5783#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5784#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5332#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5333#L415-1 assume 1 == ~t5_pc~0; 5962#L416-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5533#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5498#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5499#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5989#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5942#L434-1 assume 1 == ~t6_pc~0; 5943#L435-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5656#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5974#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5986#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5898#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5899#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 5448#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5449#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5931#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5932#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5356#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5357#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5665#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 5523#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 5524#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 5644#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 5716#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 5717#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 5820#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5550#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5460#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5731#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5732#L1043 assume !(0 == start_simulation_~tmp~3#1); 5853#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5935#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5432#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5881#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5749#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5750#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5642#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5643#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 5666#L1024 [2024-11-17 08:53:43,105 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:43,105 INFO L85 PathProgramCache]: Analyzing trace with hash 439185225, now seen corresponding path program 1 times [2024-11-17 08:53:43,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:43,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956935656] [2024-11-17 08:53:43,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:43,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,132 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,132 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956935656] [2024-11-17 08:53:43,132 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956935656] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,132 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,132 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:43,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1653057037] [2024-11-17 08:53:43,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,133 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:43,133 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:43,133 INFO L85 PathProgramCache]: Analyzing trace with hash 1447094990, now seen corresponding path program 1 times [2024-11-17 08:53:43,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:43,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837708143] [2024-11-17 08:53:43,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:43,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,173 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,173 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1837708143] [2024-11-17 08:53:43,173 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1837708143] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,173 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,173 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:43,173 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1650235693] [2024-11-17 08:53:43,173 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,174 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:43,174 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:43,174 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:43,174 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:43,175 INFO L87 Difference]: Start difference. First operand 659 states and 967 transitions. cyclomatic complexity: 309 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:43,184 INFO L93 Difference]: Finished difference Result 659 states and 966 transitions. [2024-11-17 08:53:43,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 659 states and 966 transitions. [2024-11-17 08:53:43,187 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:43,189 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 659 states to 659 states and 966 transitions. [2024-11-17 08:53:43,189 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 659 [2024-11-17 08:53:43,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 659 [2024-11-17 08:53:43,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 659 states and 966 transitions. [2024-11-17 08:53:43,190 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:43,190 INFO L218 hiAutomatonCegarLoop]: Abstraction has 659 states and 966 transitions. [2024-11-17 08:53:43,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states and 966 transitions. [2024-11-17 08:53:43,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 659. [2024-11-17 08:53:43,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 659 states, 659 states have (on average 1.4658573596358118) internal successors, (966), 658 states have internal predecessors, (966), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 966 transitions. [2024-11-17 08:53:43,197 INFO L240 hiAutomatonCegarLoop]: Abstraction has 659 states and 966 transitions. [2024-11-17 08:53:43,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:43,198 INFO L425 stractBuchiCegarLoop]: Abstraction has 659 states and 966 transitions. [2024-11-17 08:53:43,199 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:53:43,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 659 states and 966 transitions. [2024-11-17 08:53:43,201 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:43,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:43,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:43,202 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:43,202 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:43,202 INFO L745 eck$LassoCheckResult]: Stem: 7317#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6751#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6752#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7215#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6661#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 6662#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6746#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6747#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7212#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6882#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6883#L491 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7170#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7248#L670-1 assume !(0 == ~M_E~0); 7103#L675-1 assume !(0 == ~T1_E~0); 7104#L680-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7198#L685-1 assume !(0 == ~T3_E~0); 7171#L690-1 assume !(0 == ~T4_E~0); 7172#L695-1 assume !(0 == ~T5_E~0); 7232#L700-1 assume !(0 == ~T6_E~0); 7220#L705-1 assume !(0 == ~E_1~0); 7221#L710-1 assume !(0 == ~E_2~0); 7102#L715-1 assume !(0 == ~E_3~0); 7045#L720-1 assume 0 == ~E_4~0;~E_4~0 := 1; 7046#L725-1 assume !(0 == ~E_5~0); 7087#L730-1 assume !(0 == ~E_6~0); 7073#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7063#L320-8 assume 1 == ~m_pc~0; 7064#L321-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6964#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6965#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6873#L825-8 assume !(0 != activate_threads_~tmp~1#1); 6874#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7261#L339-8 assume 1 == ~t1_pc~0; 6671#L340-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6672#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6781#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6782#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 7141#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7142#L358-8 assume !(1 == ~t2_pc~0); 6937#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 6938#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7167#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7153#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 7154#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7049#L377-8 assume 1 == ~t3_pc~0; 7050#L378-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6698#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6766#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6767#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 7256#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7276#L396-8 assume 1 == ~t4_pc~0; 7018#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7019#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6951#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6839#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 6840#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7150#L415-8 assume 1 == ~t5_pc~0; 7240#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6822#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7060#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6984#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 6985#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7314#L434-8 assume !(1 == ~t6_pc~0); 7143#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 7144#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7265#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7271#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 7272#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7302#L743-1 assume !(1 == ~M_E~0); 7293#L748-1 assume !(1 == ~T1_E~0); 7136#L753-1 assume !(1 == ~T2_E~0); 7137#L758-1 assume !(1 == ~T3_E~0); 7239#L763-1 assume !(1 == ~T4_E~0); 7282#L768-1 assume !(1 == ~T5_E~0); 6962#L773-1 assume !(1 == ~T6_E~0); 6963#L778-1 assume !(1 == ~E_1~0); 6942#L783-1 assume !(1 == ~E_2~0); 6943#L788-1 assume !(1 == ~E_3~0); 7195#L793-1 assume !(1 == ~E_4~0); 7168#L798-1 assume !(1 == ~E_5~0); 6803#L803-1 assume !(1 == ~E_6~0); 6804#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 6993#L1024 [2024-11-17 08:53:43,202 INFO L747 eck$LassoCheckResult]: Loop: 6993#L1024 assume true; 6994#L1024-1 assume !false; 7205#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6929#L551 assume true; 7021#L551-1 assume !false; 7190#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7118#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6895#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6978#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7088#L556 assume !(0 != eval_~tmp~0#1); 7047#L559 assume true; 6725#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6669#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6670#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 6829#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6830#L680 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7250#L685 assume !(0 == ~T3_E~0); 7251#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7278#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7224#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7139#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 6836#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 6837#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 7178#L720 assume 0 == ~E_4~0;~E_4~0 := 1; 6687#L725 assume !(0 == ~E_5~0); 6688#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 7033#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7034#L320-1 assume !(1 == ~m_pc~0); 6693#L330-1 is_master_triggered_~__retres1~0#1 := 0; 6694#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7203#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7204#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7291#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6933#L339-1 assume 1 == ~t1_pc~0; 6934#L340-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6689#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6690#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7014#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6918#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6919#L358-1 assume 1 == ~t2_pc~0; 7305#L359-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7003#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7004#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6889#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6890#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7202#L377-1 assume 1 == ~t3_pc~0; 6989#L378-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6990#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7285#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7303#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7286#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7189#L396-1 assume 1 == ~t4_pc~0; 6912#L397-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6913#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7111#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7112#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6659#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6660#L415-1 assume 1 == ~t5_pc~0; 7289#L416-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6861#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6827#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6828#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7316#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7269#L434-1 assume 1 == ~t6_pc~0; 7270#L435-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6983#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7301#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7313#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7225#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7226#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 6777#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6778#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7258#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7259#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6685#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6686#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6992#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 6851#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 6852#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 6971#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 7043#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 7044#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 7149#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6877#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6787#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7058#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7059#L1043 assume !(0 == start_simulation_~tmp~3#1); 7180#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7262#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6759#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7208#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7076#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7077#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6969#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6970#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 6993#L1024 [2024-11-17 08:53:43,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:43,203 INFO L85 PathProgramCache]: Analyzing trace with hash 1394706504, now seen corresponding path program 1 times [2024-11-17 08:53:43,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:43,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743638975] [2024-11-17 08:53:43,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:43,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,228 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1743638975] [2024-11-17 08:53:43,228 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1743638975] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,228 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:43,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579436512] [2024-11-17 08:53:43,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,229 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:43,229 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:43,230 INFO L85 PathProgramCache]: Analyzing trace with hash 1672116401, now seen corresponding path program 1 times [2024-11-17 08:53:43,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:43,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1865852056] [2024-11-17 08:53:43,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:43,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1865852056] [2024-11-17 08:53:43,277 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1865852056] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,277 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,277 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:43,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115309328] [2024-11-17 08:53:43,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,278 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:43,278 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:43,278 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:43,279 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:43,279 INFO L87 Difference]: Start difference. First operand 659 states and 966 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,288 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:43,288 INFO L93 Difference]: Finished difference Result 659 states and 965 transitions. [2024-11-17 08:53:43,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 659 states and 965 transitions. [2024-11-17 08:53:43,291 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:43,293 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 659 states to 659 states and 965 transitions. [2024-11-17 08:53:43,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 659 [2024-11-17 08:53:43,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 659 [2024-11-17 08:53:43,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 659 states and 965 transitions. [2024-11-17 08:53:43,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:43,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 659 states and 965 transitions. [2024-11-17 08:53:43,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 659 states and 965 transitions. [2024-11-17 08:53:43,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 659 to 659. [2024-11-17 08:53:43,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 659 states, 659 states have (on average 1.464339908952959) internal successors, (965), 658 states have internal predecessors, (965), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 659 states to 659 states and 965 transitions. [2024-11-17 08:53:43,301 INFO L240 hiAutomatonCegarLoop]: Abstraction has 659 states and 965 transitions. [2024-11-17 08:53:43,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:43,303 INFO L425 stractBuchiCegarLoop]: Abstraction has 659 states and 965 transitions. [2024-11-17 08:53:43,303 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:53:43,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 659 states and 965 transitions. [2024-11-17 08:53:43,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 570 [2024-11-17 08:53:43,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:43,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:43,306 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:43,306 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:43,307 INFO L745 eck$LassoCheckResult]: Stem: 8644#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 8075#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8076#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8542#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7988#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 7989#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8071#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8072#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8539#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8209#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8210#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8496#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8575#L670-1 assume !(0 == ~M_E~0); 8430#L675-1 assume !(0 == ~T1_E~0); 8431#L680-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8523#L685-1 assume !(0 == ~T3_E~0); 8498#L690-1 assume !(0 == ~T4_E~0); 8499#L695-1 assume !(0 == ~T5_E~0); 8559#L700-1 assume !(0 == ~T6_E~0); 8547#L705-1 assume !(0 == ~E_1~0); 8548#L710-1 assume !(0 == ~E_2~0); 8429#L715-1 assume !(0 == ~E_3~0); 8370#L720-1 assume 0 == ~E_4~0;~E_4~0 := 1; 8371#L725-1 assume !(0 == ~E_5~0); 8414#L730-1 assume !(0 == ~E_6~0); 8400#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8389#L320-8 assume 1 == ~m_pc~0; 8390#L321-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8291#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8292#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8197#L825-8 assume !(0 != activate_threads_~tmp~1#1); 8198#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8587#L339-8 assume 1 == ~t1_pc~0; 7998#L340-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7999#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8106#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8107#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 8468#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8469#L358-8 assume !(1 == ~t2_pc~0); 8263#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 8264#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8492#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8480#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 8481#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8375#L377-8 assume 1 == ~t3_pc~0; 8376#L378-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8021#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8090#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8091#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 8583#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8603#L396-8 assume 1 == ~t4_pc~0; 8343#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8344#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8277#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8166#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 8167#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8477#L415-8 assume 1 == ~t5_pc~0; 8567#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8149#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8385#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8311#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 8312#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8641#L434-8 assume !(1 == ~t6_pc~0); 8470#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 8471#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8592#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8596#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 8597#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8628#L743-1 assume !(1 == ~M_E~0); 8619#L748-1 assume !(1 == ~T1_E~0); 8462#L753-1 assume !(1 == ~T2_E~0); 8463#L758-1 assume !(1 == ~T3_E~0); 8565#L763-1 assume !(1 == ~T4_E~0); 8609#L768-1 assume !(1 == ~T5_E~0); 8289#L773-1 assume !(1 == ~T6_E~0); 8290#L778-1 assume !(1 == ~E_1~0); 8266#L783-1 assume !(1 == ~E_2~0); 8267#L788-1 assume !(1 == ~E_3~0); 8522#L793-1 assume !(1 == ~E_4~0); 8495#L798-1 assume !(1 == ~E_5~0); 8130#L803-1 assume !(1 == ~E_6~0); 8131#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 8320#L1024 [2024-11-17 08:53:43,308 INFO L747 eck$LassoCheckResult]: Loop: 8320#L1024 assume true; 8321#L1024-1 assume !false; 8530#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8256#L551 assume true; 8348#L551-1 assume !false; 8516#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8445#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8219#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8303#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8415#L556 assume !(0 != eval_~tmp~0#1); 8372#L559 assume true; 8050#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7994#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7995#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 8156#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8157#L680 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8577#L685 assume !(0 == ~T3_E~0); 8578#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8605#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8551#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8466#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 8163#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 8164#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 8505#L720 assume 0 == ~E_4~0;~E_4~0 := 1; 8014#L725 assume !(0 == ~E_5~0); 8015#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 8360#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8361#L320-1 assume !(1 == ~m_pc~0); 8022#L330-1 is_master_triggered_~__retres1~0#1 := 0; 8023#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8531#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8532#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8618#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8260#L339-1 assume 1 == ~t1_pc~0; 8261#L340-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8016#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8017#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8341#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8245#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8246#L358-1 assume 1 == ~t2_pc~0; 8632#L359-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8330#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8331#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8216#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8217#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8529#L377-1 assume 1 == ~t3_pc~0; 8316#L378-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8317#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8612#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8630#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8613#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8517#L396-1 assume !(1 == ~t4_pc~0); 8241#L406-1 is_transmit4_triggered_~__retres1~4#1 := 0; 8240#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8438#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8439#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7986#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7987#L415-1 assume 1 == ~t5_pc~0; 8616#L416-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8188#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8154#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8155#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8643#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8598#L434-1 assume !(1 == ~t6_pc~0); 8309#L444-1 is_transmit6_triggered_~__retres1~6#1 := 0; 8310#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8629#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8640#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8553#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8554#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 8104#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8105#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8585#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8586#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8012#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8013#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8319#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 8178#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 8179#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 8298#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 8373#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 8374#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 8476#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8204#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8114#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8386#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 8387#L1043 assume !(0 == start_simulation_~tmp~3#1); 8507#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8589#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8086#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8535#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 8403#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8404#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8296#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8297#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 8320#L1024 [2024-11-17 08:53:43,309 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:43,309 INFO L85 PathProgramCache]: Analyzing trace with hash -791227543, now seen corresponding path program 1 times [2024-11-17 08:53:43,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:43,309 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368656791] [2024-11-17 08:53:43,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:43,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368656791] [2024-11-17 08:53:43,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368656791] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,357 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:43,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556995095] [2024-11-17 08:53:43,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,357 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:43,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:43,358 INFO L85 PathProgramCache]: Analyzing trace with hash -1166887957, now seen corresponding path program 1 times [2024-11-17 08:53:43,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:43,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201340287] [2024-11-17 08:53:43,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:43,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,416 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,416 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201340287] [2024-11-17 08:53:43,416 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201340287] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,417 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,417 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:43,417 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [968514066] [2024-11-17 08:53:43,417 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,417 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:43,417 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:43,418 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:43,418 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:43,418 INFO L87 Difference]: Start difference. First operand 659 states and 965 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:43,502 INFO L93 Difference]: Finished difference Result 1241 states and 1811 transitions. [2024-11-17 08:53:43,502 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1241 states and 1811 transitions. [2024-11-17 08:53:43,509 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1140 [2024-11-17 08:53:43,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1241 states to 1241 states and 1811 transitions. [2024-11-17 08:53:43,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1241 [2024-11-17 08:53:43,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1241 [2024-11-17 08:53:43,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1241 states and 1811 transitions. [2024-11-17 08:53:43,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:43,516 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1241 states and 1811 transitions. [2024-11-17 08:53:43,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1241 states and 1811 transitions. [2024-11-17 08:53:43,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1241 to 1241. [2024-11-17 08:53:43,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1241 states, 1241 states have (on average 1.459307010475423) internal successors, (1811), 1240 states have internal predecessors, (1811), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1241 states to 1241 states and 1811 transitions. [2024-11-17 08:53:43,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1241 states and 1811 transitions. [2024-11-17 08:53:43,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:43,540 INFO L425 stractBuchiCegarLoop]: Abstraction has 1241 states and 1811 transitions. [2024-11-17 08:53:43,540 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:53:43,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1241 states and 1811 transitions. [2024-11-17 08:53:43,545 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1140 [2024-11-17 08:53:43,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:43,545 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:43,546 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:43,546 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:43,546 INFO L745 eck$LassoCheckResult]: Stem: 10591#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 9988#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9989#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10476#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9900#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 9901#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9984#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9985#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10473#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10126#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10127#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10428#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10510#L670-1 assume !(0 == ~M_E~0); 10359#L675-1 assume !(0 == ~T1_E~0); 10360#L680-1 assume !(0 == ~T2_E~0); 10456#L685-1 assume !(0 == ~T3_E~0); 10430#L690-1 assume !(0 == ~T4_E~0); 10431#L695-1 assume !(0 == ~T5_E~0); 10494#L700-1 assume !(0 == ~T6_E~0); 10481#L705-1 assume !(0 == ~E_1~0); 10482#L710-1 assume !(0 == ~E_2~0); 10358#L715-1 assume !(0 == ~E_3~0); 10291#L720-1 assume 0 == ~E_4~0;~E_4~0 := 1; 10292#L725-1 assume !(0 == ~E_5~0); 10341#L730-1 assume !(0 == ~E_6~0); 10325#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10311#L320-8 assume 1 == ~m_pc~0; 10312#L321-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10210#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10211#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10112#L825-8 assume !(0 != activate_threads_~tmp~1#1); 10113#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10522#L339-8 assume 1 == ~t1_pc~0; 9910#L340-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9911#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10020#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10021#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 10399#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10400#L358-8 assume !(1 == ~t2_pc~0); 10182#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 10183#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10424#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10411#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 10412#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10297#L377-8 assume 1 == ~t3_pc~0; 10298#L378-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9933#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10003#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10004#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 10518#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10538#L396-8 assume 1 == ~t4_pc~0; 10264#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10265#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10196#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10080#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 10081#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10408#L415-8 assume 1 == ~t5_pc~0; 10502#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10063#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10307#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10231#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 10232#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10585#L434-8 assume !(1 == ~t6_pc~0); 10401#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 10402#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10527#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10531#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 10532#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10567#L743-1 assume !(1 == ~M_E~0); 10556#L748-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10557#L753-1 assume !(1 == ~T2_E~0); 10393#L758-1 assume !(1 == ~T3_E~0); 10981#L763-1 assume !(1 == ~T4_E~0); 10980#L768-1 assume !(1 == ~T5_E~0); 10979#L773-1 assume !(1 == ~T6_E~0); 10978#L778-1 assume !(1 == ~E_1~0); 10977#L783-1 assume !(1 == ~E_2~0); 10976#L788-1 assume !(1 == ~E_3~0); 10975#L793-1 assume !(1 == ~E_4~0); 10974#L798-1 assume !(1 == ~E_5~0); 10973#L803-1 assume !(1 == ~E_6~0); 10972#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 10970#L1024 [2024-11-17 08:53:43,547 INFO L747 eck$LassoCheckResult]: Loop: 10970#L1024 assume true; 10969#L1024-1 assume !false; 10607#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10606#L551 assume true; 10605#L551-1 assume !false; 10604#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10600#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10222#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10223#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10592#L556 assume !(0 != eval_~tmp~0#1); 10593#L559 assume true; 9962#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9963#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10573#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 10574#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10595#L680 assume !(0 == ~T2_E~0); 11091#L685 assume !(0 == ~T3_E~0); 11089#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11087#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11085#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11083#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 11081#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 11079#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 11077#L720 assume 0 == ~E_4~0;~E_4~0 := 1; 11075#L725 assume !(0 == ~E_5~0); 11073#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 11071#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11069#L320-1 assume !(1 == ~m_pc~0); 11066#L330-1 is_master_triggered_~__retres1~0#1 := 0; 11064#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11062#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11060#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11059#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11058#L339-1 assume !(1 == ~t1_pc~0); 11056#L349-1 is_transmit1_triggered_~__retres1~1#1 := 0; 11055#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11054#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11053#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11052#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11051#L358-1 assume !(1 == ~t2_pc~0); 11049#L368-1 is_transmit2_triggered_~__retres1~2#1 := 0; 11048#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11047#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11046#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11045#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11044#L377-1 assume !(1 == ~t3_pc~0); 11042#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 11041#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11040#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11039#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11038#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11037#L396-1 assume !(1 == ~t4_pc~0); 11035#L406-1 is_transmit4_triggered_~__retres1~4#1 := 0; 11034#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11033#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11032#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11031#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11030#L415-1 assume !(1 == ~t5_pc~0); 11028#L425-1 is_transmit5_triggered_~__retres1~5#1 := 0; 11027#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11026#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11025#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11024#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11023#L434-1 assume !(1 == ~t6_pc~0); 11021#L444-1 is_transmit6_triggered_~__retres1~6#1 := 0; 11020#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11019#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11018#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11017#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11016#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 11015#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10018#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10542#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11014#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11013#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11012#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11011#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 11010#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 11009#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 11008#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 11007#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 11006#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 11005#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10999#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10997#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10996#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 10995#L1043 assume !(0 == start_simulation_~tmp~3#1); 10994#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10988#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10986#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10985#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 10984#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10983#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10982#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 10971#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 10970#L1024 [2024-11-17 08:53:43,547 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:43,547 INFO L85 PathProgramCache]: Analyzing trace with hash 2126629191, now seen corresponding path program 1 times [2024-11-17 08:53:43,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:43,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906878355] [2024-11-17 08:53:43,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:43,548 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906878355] [2024-11-17 08:53:43,597 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906878355] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,597 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,597 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:43,597 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760425808] [2024-11-17 08:53:43,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,598 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:43,598 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:43,598 INFO L85 PathProgramCache]: Analyzing trace with hash -1830791042, now seen corresponding path program 1 times [2024-11-17 08:53:43,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:43,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583982301] [2024-11-17 08:53:43,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:43,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583982301] [2024-11-17 08:53:43,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583982301] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,648 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,648 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:43,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714729426] [2024-11-17 08:53:43,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,648 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:43,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:43,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:43,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:43,649 INFO L87 Difference]: Start difference. First operand 1241 states and 1811 transitions. cyclomatic complexity: 572 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:43,761 INFO L93 Difference]: Finished difference Result 2295 states and 3342 transitions. [2024-11-17 08:53:43,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2295 states and 3342 transitions. [2024-11-17 08:53:43,770 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2178 [2024-11-17 08:53:43,778 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2295 states to 2295 states and 3342 transitions. [2024-11-17 08:53:43,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2295 [2024-11-17 08:53:43,779 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2295 [2024-11-17 08:53:43,779 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2295 states and 3342 transitions. [2024-11-17 08:53:43,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:43,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2295 states and 3342 transitions. [2024-11-17 08:53:43,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2295 states and 3342 transitions. [2024-11-17 08:53:43,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2295 to 2293. [2024-11-17 08:53:43,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2293 states, 2293 states have (on average 1.456607064980375) internal successors, (3340), 2292 states have internal predecessors, (3340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2293 states to 2293 states and 3340 transitions. [2024-11-17 08:53:43,813 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2293 states and 3340 transitions. [2024-11-17 08:53:43,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:43,814 INFO L425 stractBuchiCegarLoop]: Abstraction has 2293 states and 3340 transitions. [2024-11-17 08:53:43,814 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:53:43,814 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2293 states and 3340 transitions. [2024-11-17 08:53:43,820 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2178 [2024-11-17 08:53:43,821 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:43,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:43,821 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:43,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:43,822 INFO L745 eck$LassoCheckResult]: Stem: 14243#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 13536#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 13537#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14053#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13448#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 13449#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13534#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13535#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14050#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13675#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13676#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13992#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14099#L670-1 assume !(0 == ~M_E~0); 13913#L675-1 assume !(0 == ~T1_E~0); 13914#L680-1 assume !(0 == ~T2_E~0); 14031#L685-1 assume !(0 == ~T3_E~0); 13993#L690-1 assume !(0 == ~T4_E~0); 13994#L695-1 assume !(0 == ~T5_E~0); 14074#L700-1 assume !(0 == ~T6_E~0); 14060#L705-1 assume !(0 == ~E_1~0); 14061#L710-1 assume !(0 == ~E_2~0); 13912#L715-1 assume !(0 == ~E_3~0); 13848#L720-1 assume !(0 == ~E_4~0); 13849#L725-1 assume !(0 == ~E_5~0); 13897#L730-1 assume !(0 == ~E_6~0); 13882#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13867#L320-8 assume 1 == ~m_pc~0; 13868#L321-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13761#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13762#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13665#L825-8 assume !(0 != activate_threads_~tmp~1#1); 13666#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14117#L339-8 assume 1 == ~t1_pc~0; 13458#L340-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13459#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13571#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13572#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 13955#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13956#L358-8 assume !(1 == ~t2_pc~0); 13732#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 13733#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13986#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13972#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 13973#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13854#L377-8 assume 1 == ~t3_pc~0; 13855#L378-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13483#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13552#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13553#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 14110#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14135#L396-8 assume 1 == ~t4_pc~0; 13819#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13820#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13745#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13629#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 13630#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13968#L415-8 assume 1 == ~t5_pc~0; 14087#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13612#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13865#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13782#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 13783#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14226#L434-8 assume !(1 == ~t6_pc~0); 13958#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 13959#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14124#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14130#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 14131#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14181#L743-1 assume !(1 == ~M_E~0); 14164#L748-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13948#L753-1 assume !(1 == ~T2_E~0); 13949#L758-1 assume !(1 == ~T3_E~0); 14086#L763-1 assume !(1 == ~T4_E~0); 14216#L768-1 assume !(1 == ~T5_E~0); 14217#L773-1 assume !(1 == ~T6_E~0); 14241#L778-1 assume !(1 == ~E_1~0); 14242#L783-1 assume !(1 == ~E_2~0); 14238#L788-1 assume !(1 == ~E_3~0); 14239#L793-1 assume !(1 == ~E_4~0); 14347#L798-1 assume !(1 == ~E_5~0); 14340#L803-1 assume !(1 == ~E_6~0); 14335#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 14275#L1024 [2024-11-17 08:53:43,822 INFO L747 eck$LassoCheckResult]: Loop: 14275#L1024 assume true; 14269#L1024-1 assume !false; 14265#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14264#L551 assume true; 14263#L551-1 assume !false; 14262#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14258#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14254#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14253#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14251#L556 assume !(0 != eval_~tmp~0#1); 14250#L559 assume true; 14249#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14248#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14247#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 14245#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14246#L680 assume !(0 == ~T2_E~0); 15311#L685 assume !(0 == ~T3_E~0); 15307#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15304#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15302#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15300#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 15298#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 15296#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 15295#L720 assume !(0 == ~E_4~0); 15294#L725 assume !(0 == ~E_5~0); 15231#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 15229#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15230#L320-1 assume !(1 == ~m_pc~0); 15289#L330-1 is_master_triggered_~__retres1~0#1 := 0; 15287#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15285#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15284#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15283#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15282#L339-1 assume !(1 == ~t1_pc~0); 15280#L349-1 is_transmit1_triggered_~__retres1~1#1 := 0; 15166#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15165#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15164#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13711#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13712#L358-1 assume !(1 == ~t2_pc~0); 14925#L368-1 is_transmit2_triggered_~__retres1~2#1 := 0; 14917#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14915#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14913#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14911#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14908#L377-1 assume !(1 == ~t3_pc~0); 14905#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 14903#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14901#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14900#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14155#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14021#L396-1 assume 1 == ~t4_pc~0; 13704#L397-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13705#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13922#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13923#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13446#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13447#L415-1 assume !(1 == ~t5_pc~0); 13650#L425-1 is_transmit5_triggered_~__retres1~5#1 := 0; 13651#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14153#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14693#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14691#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14689#L434-1 assume !(1 == ~t6_pc~0); 14670#L444-1 is_transmit6_triggered_~__retres1~6#1 := 0; 14667#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14665#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14663#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14661#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14659#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 14657#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13567#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14141#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14653#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14651#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14649#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14629#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 14480#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 14466#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 14453#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 14439#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 14437#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 14419#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14400#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14395#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14392#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 14388#L1043 assume !(0 == start_simulation_~tmp~3#1); 14386#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 14379#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14376#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14373#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 14371#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14341#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14339#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 14334#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 14275#L1024 [2024-11-17 08:53:43,822 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:43,823 INFO L85 PathProgramCache]: Analyzing trace with hash -2067426138, now seen corresponding path program 1 times [2024-11-17 08:53:43,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:43,823 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1033420579] [2024-11-17 08:53:43,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:43,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,848 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1033420579] [2024-11-17 08:53:43,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1033420579] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,848 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,849 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:43,849 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [893663681] [2024-11-17 08:53:43,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,849 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:43,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:43,849 INFO L85 PathProgramCache]: Analyzing trace with hash 482443648, now seen corresponding path program 1 times [2024-11-17 08:53:43,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:43,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113066624] [2024-11-17 08:53:43,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:43,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:43,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:43,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:43,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:43,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113066624] [2024-11-17 08:53:43,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113066624] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:43,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:43,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:43,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782057248] [2024-11-17 08:53:43,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:43,885 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:43,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:43,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:43,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:43,886 INFO L87 Difference]: Start difference. First operand 2293 states and 3340 transitions. cyclomatic complexity: 1051 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:43,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:43,945 INFO L93 Difference]: Finished difference Result 4428 states and 6388 transitions. [2024-11-17 08:53:43,945 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4428 states and 6388 transitions. [2024-11-17 08:53:43,980 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4306 [2024-11-17 08:53:43,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4428 states to 4428 states and 6388 transitions. [2024-11-17 08:53:43,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4428 [2024-11-17 08:53:43,997 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4428 [2024-11-17 08:53:43,997 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4428 states and 6388 transitions. [2024-11-17 08:53:44,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:44,000 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4428 states and 6388 transitions. [2024-11-17 08:53:44,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4428 states and 6388 transitions. [2024-11-17 08:53:44,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4428 to 4224. [2024-11-17 08:53:44,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4224 states, 4224 states have (on average 1.4460227272727273) internal successors, (6108), 4223 states have internal predecessors, (6108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:44,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4224 states to 4224 states and 6108 transitions. [2024-11-17 08:53:44,046 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4224 states and 6108 transitions. [2024-11-17 08:53:44,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:44,048 INFO L425 stractBuchiCegarLoop]: Abstraction has 4224 states and 6108 transitions. [2024-11-17 08:53:44,048 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:53:44,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4224 states and 6108 transitions. [2024-11-17 08:53:44,057 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4102 [2024-11-17 08:53:44,057 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:44,057 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:44,058 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:44,058 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:44,058 INFO L745 eck$LassoCheckResult]: Stem: 20879#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 20267#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 20268#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20739#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20178#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 20179#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20262#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20263#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20735#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20402#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20403#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20688#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20780#L670-1 assume !(0 == ~M_E~0); 20620#L675-1 assume !(0 == ~T1_E~0); 20621#L680-1 assume !(0 == ~T2_E~0); 20720#L685-1 assume !(0 == ~T3_E~0); 20689#L690-1 assume !(0 == ~T4_E~0); 20690#L695-1 assume !(0 == ~T5_E~0); 20756#L700-1 assume !(0 == ~T6_E~0); 20744#L705-1 assume !(0 == ~E_1~0); 20745#L710-1 assume !(0 == ~E_2~0); 20619#L715-1 assume !(0 == ~E_3~0); 20562#L720-1 assume !(0 == ~E_4~0); 20563#L725-1 assume !(0 == ~E_5~0); 20604#L730-1 assume !(0 == ~E_6~0); 20589#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20579#L320-8 assume !(1 == ~m_pc~0); 20580#L330-8 is_master_triggered_~__retres1~0#1 := 0; 20480#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20481#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20391#L825-8 assume !(0 != activate_threads_~tmp~1#1); 20392#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20793#L339-8 assume 1 == ~t1_pc~0; 20188#L340-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20189#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20298#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20299#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 20659#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20660#L358-8 assume !(1 == ~t2_pc~0); 20453#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 20454#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20685#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20672#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 20673#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20565#L377-8 assume 1 == ~t3_pc~0; 20566#L378-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20215#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20282#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20283#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 20788#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20812#L396-8 assume 1 == ~t4_pc~0; 20534#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20535#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20467#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20356#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 20357#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20669#L415-8 assume 1 == ~t5_pc~0; 20766#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20339#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20576#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20500#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 20501#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20868#L434-8 assume !(1 == ~t6_pc~0); 20661#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 20662#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20797#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20805#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 20806#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20844#L743-1 assume !(1 == ~M_E~0); 20830#L748-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20654#L753-1 assume !(1 == ~T2_E~0); 20655#L758-1 assume !(1 == ~T3_E~0); 23631#L763-1 assume !(1 == ~T4_E~0); 23629#L768-1 assume !(1 == ~T5_E~0); 20478#L773-1 assume !(1 == ~T6_E~0); 20479#L778-1 assume !(1 == ~E_1~0); 20878#L783-1 assume !(1 == ~E_2~0); 23517#L788-1 assume !(1 == ~E_3~0); 23515#L793-1 assume !(1 == ~E_4~0); 20717#L798-1 assume !(1 == ~E_5~0); 23493#L803-1 assume !(1 == ~E_6~0); 23484#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 23476#L1024 [2024-11-17 08:53:44,058 INFO L747 eck$LassoCheckResult]: Loop: 23476#L1024 assume true; 23470#L1024-1 assume !false; 23466#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23465#L551 assume true; 23464#L551-1 assume !false; 23463#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23459#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 23455#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 23454#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23452#L556 assume !(0 != eval_~tmp~0#1); 23453#L559 assume true; 24386#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24351#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23992#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 23989#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23987#L680 assume !(0 == ~T2_E~0); 23985#L685 assume !(0 == ~T3_E~0); 23983#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23981#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23979#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23976#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 23974#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 23972#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 23964#L720 assume !(0 == ~E_4~0); 23962#L725 assume !(0 == ~E_5~0); 23960#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 23958#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23957#L320-1 assume !(1 == ~m_pc~0); 23956#L330-1 is_master_triggered_~__retres1~0#1 := 0; 23952#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23951#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23950#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23949#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23946#L339-1 assume !(1 == ~t1_pc~0); 23944#L349-1 is_transmit1_triggered_~__retres1~1#1 := 0; 23942#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23940#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23937#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23935#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23933#L358-1 assume !(1 == ~t2_pc~0); 23930#L368-1 is_transmit2_triggered_~__retres1~2#1 := 0; 23928#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23927#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23924#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23920#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23916#L377-1 assume !(1 == ~t3_pc~0); 23912#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 23909#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23907#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23904#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23903#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23901#L396-1 assume !(1 == ~t4_pc~0); 23898#L406-1 is_transmit4_triggered_~__retres1~4#1 := 0; 23896#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23894#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23892#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23890#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23888#L415-1 assume !(1 == ~t5_pc~0); 23884#L425-1 is_transmit5_triggered_~__retres1~5#1 := 0; 23882#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23880#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23878#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23876#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23874#L434-1 assume !(1 == ~t6_pc~0); 23870#L444-1 is_transmit6_triggered_~__retres1~6#1 := 0; 23868#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23866#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23864#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23862#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23860#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 23859#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20294#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23735#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23856#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23854#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23852#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23850#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 23849#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 23846#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 23844#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 20846#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 23841#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 23839#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23814#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 23809#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 23806#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 23564#L1043 assume !(0 == start_simulation_~tmp~3#1); 23561#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 23551#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 23549#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 23547#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 23514#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23502#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23492#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 23483#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 23476#L1024 [2024-11-17 08:53:44,059 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:44,059 INFO L85 PathProgramCache]: Analyzing trace with hash 861093123, now seen corresponding path program 1 times [2024-11-17 08:53:44,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:44,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1824429487] [2024-11-17 08:53:44,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:44,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:44,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:44,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:44,095 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:44,095 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1824429487] [2024-11-17 08:53:44,096 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1824429487] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:44,096 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:44,096 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:44,096 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890722675] [2024-11-17 08:53:44,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:44,096 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:44,097 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:44,097 INFO L85 PathProgramCache]: Analyzing trace with hash 355143005, now seen corresponding path program 1 times [2024-11-17 08:53:44,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:44,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547021256] [2024-11-17 08:53:44,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:44,097 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:44,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:44,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:44,138 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:44,138 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547021256] [2024-11-17 08:53:44,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [547021256] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:44,138 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:44,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:44,138 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1457325241] [2024-11-17 08:53:44,138 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:44,139 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:44,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:44,139 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:44,139 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:44,139 INFO L87 Difference]: Start difference. First operand 4224 states and 6108 transitions. cyclomatic complexity: 1892 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:44,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:44,199 INFO L93 Difference]: Finished difference Result 7865 states and 11301 transitions. [2024-11-17 08:53:44,199 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7865 states and 11301 transitions. [2024-11-17 08:53:44,223 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7720 [2024-11-17 08:53:44,249 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7865 states to 7865 states and 11301 transitions. [2024-11-17 08:53:44,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7865 [2024-11-17 08:53:44,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7865 [2024-11-17 08:53:44,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7865 states and 11301 transitions. [2024-11-17 08:53:44,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:44,262 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7865 states and 11301 transitions. [2024-11-17 08:53:44,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7865 states and 11301 transitions. [2024-11-17 08:53:44,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7865 to 7833. [2024-11-17 08:53:44,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7833 states, 7833 states have (on average 1.438656964126133) internal successors, (11269), 7832 states have internal predecessors, (11269), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:44,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7833 states to 7833 states and 11269 transitions. [2024-11-17 08:53:44,395 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7833 states and 11269 transitions. [2024-11-17 08:53:44,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:44,396 INFO L425 stractBuchiCegarLoop]: Abstraction has 7833 states and 11269 transitions. [2024-11-17 08:53:44,396 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:53:44,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7833 states and 11269 transitions. [2024-11-17 08:53:44,412 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7688 [2024-11-17 08:53:44,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:44,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:44,413 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:44,413 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:44,414 INFO L745 eck$LassoCheckResult]: Stem: 33031#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 32359#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 32360#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32854#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32276#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 32277#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32355#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32356#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32851#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32496#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32497#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32799#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32899#L670-1 assume !(0 == ~M_E~0); 32728#L675-1 assume !(0 == ~T1_E~0); 32729#L680-1 assume !(0 == ~T2_E~0); 32831#L685-1 assume !(0 == ~T3_E~0); 32802#L690-1 assume !(0 == ~T4_E~0); 32803#L695-1 assume !(0 == ~T5_E~0); 32874#L700-1 assume !(0 == ~T6_E~0); 32862#L705-1 assume !(0 == ~E_1~0); 32863#L710-1 assume !(0 == ~E_2~0); 32727#L715-1 assume !(0 == ~E_3~0); 32666#L720-1 assume !(0 == ~E_4~0); 32667#L725-1 assume !(0 == ~E_5~0); 32712#L730-1 assume !(0 == ~E_6~0); 32698#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32685#L320-8 assume !(1 == ~m_pc~0); 32686#L330-8 is_master_triggered_~__retres1~0#1 := 0; 32579#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32580#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32484#L825-8 assume !(0 != activate_threads_~tmp~1#1); 32485#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32913#L339-8 assume !(1 == ~t1_pc~0); 32452#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 32453#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32391#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32392#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 32768#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32769#L358-8 assume !(1 == ~t2_pc~0); 32551#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 32552#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32796#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 32784#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 32785#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32671#L377-8 assume 1 == ~t3_pc~0; 32672#L378-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 32306#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32374#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32375#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 32908#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32936#L396-8 assume 1 == ~t4_pc~0; 32638#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32639#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32565#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32450#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 32451#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32780#L415-8 assume 1 == ~t5_pc~0; 32884#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32433#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32681#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32600#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 32601#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33013#L434-8 assume !(1 == ~t6_pc~0); 32771#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 32772#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32922#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32928#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 32929#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32978#L743-1 assume !(1 == ~M_E~0); 32963#L748-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32762#L753-1 assume !(1 == ~T2_E~0); 32763#L758-1 assume !(1 == ~T3_E~0); 34940#L763-1 assume !(1 == ~T4_E~0); 34938#L768-1 assume !(1 == ~T5_E~0); 34936#L773-1 assume !(1 == ~T6_E~0); 34935#L778-1 assume !(1 == ~E_1~0); 34934#L783-1 assume !(1 == ~E_2~0); 33026#L788-1 assume !(1 == ~E_3~0); 33027#L793-1 assume !(1 == ~E_4~0); 34675#L798-1 assume !(1 == ~E_5~0); 34673#L803-1 assume !(1 == ~E_6~0); 34624#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 34621#L1024 [2024-11-17 08:53:44,414 INFO L747 eck$LassoCheckResult]: Loop: 34621#L1024 assume true; 34619#L1024-1 assume !false; 34615#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34612#L551 assume true; 34610#L551-1 assume !false; 34608#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 34575#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 34570#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 34568#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 34566#L556 assume !(0 != eval_~tmp~0#1); 34567#L559 assume true; 36710#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36709#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36708#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 36707#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36706#L680 assume !(0 == ~T2_E~0); 36705#L685 assume !(0 == ~T3_E~0); 36704#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36703#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36702#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36701#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 36700#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 36699#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 36698#L720 assume !(0 == ~E_4~0); 36697#L725 assume !(0 == ~E_5~0); 36696#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 36695#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36694#L320-1 assume !(1 == ~m_pc~0); 36693#L330-1 is_master_triggered_~__retres1~0#1 := 0; 36692#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36691#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 36690#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36689#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36688#L339-1 assume !(1 == ~t1_pc~0); 36687#L349-1 is_transmit1_triggered_~__retres1~1#1 := 0; 36686#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36685#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 36684#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36683#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36682#L358-1 assume !(1 == ~t2_pc~0); 36680#L368-1 is_transmit2_triggered_~__retres1~2#1 := 0; 36679#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36678#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 36677#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36676#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36675#L377-1 assume !(1 == ~t3_pc~0); 36673#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 36672#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36671#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36670#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36669#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36668#L396-1 assume !(1 == ~t4_pc~0); 36666#L406-1 is_transmit4_triggered_~__retres1~4#1 := 0; 36665#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36664#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36663#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36662#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36660#L415-1 assume !(1 == ~t5_pc~0); 36657#L425-1 is_transmit5_triggered_~__retres1~5#1 := 0; 36655#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36653#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36651#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36649#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36647#L434-1 assume !(1 == ~t6_pc~0); 36643#L444-1 is_transmit6_triggered_~__retres1~6#1 := 0; 36641#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36639#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36637#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36635#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36633#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 36631#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35492#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36182#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36627#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36625#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36623#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36621#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 36552#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 36309#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 35469#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 35465#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 35463#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 35461#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 34900#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 34897#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 34896#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 34796#L1043 assume !(0 == start_simulation_~tmp~3#1); 34724#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 34663#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 34660#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 34657#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 34653#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34652#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34650#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 34623#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 34621#L1024 [2024-11-17 08:53:44,415 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:44,415 INFO L85 PathProgramCache]: Analyzing trace with hash 636071712, now seen corresponding path program 1 times [2024-11-17 08:53:44,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:44,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149621371] [2024-11-17 08:53:44,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:44,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:44,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:44,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:44,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:44,454 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [149621371] [2024-11-17 08:53:44,454 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [149621371] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:44,455 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:44,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:44,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596328519] [2024-11-17 08:53:44,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:44,455 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:44,455 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:44,455 INFO L85 PathProgramCache]: Analyzing trace with hash 355143005, now seen corresponding path program 2 times [2024-11-17 08:53:44,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:44,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811392384] [2024-11-17 08:53:44,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:44,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:44,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:44,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:44,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:44,496 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [811392384] [2024-11-17 08:53:44,496 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [811392384] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:44,496 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:44,496 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:44,497 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1866034364] [2024-11-17 08:53:44,497 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:44,497 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:44,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:44,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:44,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:44,498 INFO L87 Difference]: Start difference. First operand 7833 states and 11269 transitions. cyclomatic complexity: 3452 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:44,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:44,580 INFO L93 Difference]: Finished difference Result 15024 states and 21470 transitions. [2024-11-17 08:53:44,580 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15024 states and 21470 transitions. [2024-11-17 08:53:44,628 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14816 [2024-11-17 08:53:44,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15024 states to 15024 states and 21470 transitions. [2024-11-17 08:53:44,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15024 [2024-11-17 08:53:44,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15024 [2024-11-17 08:53:44,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15024 states and 21470 transitions. [2024-11-17 08:53:44,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:44,695 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15024 states and 21470 transitions. [2024-11-17 08:53:44,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15024 states and 21470 transitions. [2024-11-17 08:53:44,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15024 to 14960. [2024-11-17 08:53:44,907 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14960 states, 14960 states have (on average 1.4308823529411765) internal successors, (21406), 14959 states have internal predecessors, (21406), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:45,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14960 states to 14960 states and 21406 transitions. [2024-11-17 08:53:45,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14960 states and 21406 transitions. [2024-11-17 08:53:45,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:45,012 INFO L425 stractBuchiCegarLoop]: Abstraction has 14960 states and 21406 transitions. [2024-11-17 08:53:45,012 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:53:45,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14960 states and 21406 transitions. [2024-11-17 08:53:45,052 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14752 [2024-11-17 08:53:45,053 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:45,053 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:45,053 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:45,054 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:45,054 INFO L745 eck$LassoCheckResult]: Stem: 55879#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 55223#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 55224#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55722#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55142#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 55143#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55219#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55220#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55716#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55364#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55365#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55668#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55760#L670-1 assume !(0 == ~M_E~0); 55594#L675-1 assume !(0 == ~T1_E~0); 55595#L680-1 assume !(0 == ~T2_E~0); 55700#L685-1 assume !(0 == ~T3_E~0); 55670#L690-1 assume !(0 == ~T4_E~0); 55671#L695-1 assume !(0 == ~T5_E~0); 55741#L700-1 assume !(0 == ~T6_E~0); 55728#L705-1 assume !(0 == ~E_1~0); 55729#L710-1 assume !(0 == ~E_2~0); 55593#L715-1 assume !(0 == ~E_3~0); 55533#L720-1 assume !(0 == ~E_4~0); 55534#L725-1 assume !(0 == ~E_5~0); 55577#L730-1 assume !(0 == ~E_6~0); 55563#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55552#L320-8 assume !(1 == ~m_pc~0); 55553#L330-8 is_master_triggered_~__retres1~0#1 := 0; 55445#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55446#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55352#L825-8 assume !(0 != activate_threads_~tmp~1#1); 55353#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55777#L339-8 assume !(1 == ~t1_pc~0); 55318#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 55319#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55255#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55256#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 55637#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55638#L358-8 assume !(1 == ~t2_pc~0); 55416#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 55417#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55665#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55651#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 55652#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55538#L377-8 assume !(1 == ~t3_pc~0); 55171#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 55172#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55239#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55240#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 55770#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55796#L396-8 assume 1 == ~t4_pc~0; 55502#L397-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 55503#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55430#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55316#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 55317#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55648#L415-8 assume 1 == ~t5_pc~0; 55750#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55299#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55548#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55466#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 55467#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55863#L434-8 assume !(1 == ~t6_pc~0); 55639#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 55640#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55784#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55788#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 55789#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55839#L743-1 assume !(1 == ~M_E~0); 55827#L748-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55828#L753-1 assume !(1 == ~T2_E~0); 57593#L758-1 assume !(1 == ~T3_E~0); 58087#L763-1 assume !(1 == ~T4_E~0); 55857#L768-1 assume !(1 == ~T5_E~0); 55443#L773-1 assume !(1 == ~T6_E~0); 55444#L778-1 assume !(1 == ~E_1~0); 55419#L783-1 assume !(1 == ~E_2~0); 55420#L788-1 assume !(1 == ~E_3~0); 55698#L793-1 assume !(1 == ~E_4~0); 55699#L798-1 assume !(1 == ~E_5~0); 58515#L803-1 assume !(1 == ~E_6~0); 58514#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 58512#L1024 [2024-11-17 08:53:45,054 INFO L747 eck$LassoCheckResult]: Loop: 58512#L1024 assume true; 58511#L1024-1 assume !false; 57253#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57251#L551 assume true; 57249#L551-1 assume !false; 57247#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 57237#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 57232#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 57230#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57226#L556 assume !(0 != eval_~tmp~0#1); 57227#L559 assume true; 58696#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 58694#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58692#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 58690#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 58687#L680 assume !(0 == ~T2_E~0); 58685#L685 assume !(0 == ~T3_E~0); 58683#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58681#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 58679#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 58677#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 58674#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 58672#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 58670#L720 assume !(0 == ~E_4~0); 58668#L725 assume !(0 == ~E_5~0); 58666#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 58664#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 58663#L320-1 assume !(1 == ~m_pc~0); 58662#L330-1 is_master_triggered_~__retres1~0#1 := 0; 58661#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 58660#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 58659#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 58658#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 58657#L339-1 assume !(1 == ~t1_pc~0); 58656#L349-1 is_transmit1_triggered_~__retres1~1#1 := 0; 58655#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 58653#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 58651#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 58649#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 58647#L358-1 assume !(1 == ~t2_pc~0); 58644#L368-1 is_transmit2_triggered_~__retres1~2#1 := 0; 58642#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 58640#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 58638#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58636#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 58634#L377-1 assume !(1 == ~t3_pc~0); 58632#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 58630#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 58628#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 58625#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 58623#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 58621#L396-1 assume !(1 == ~t4_pc~0); 58618#L406-1 is_transmit4_triggered_~__retres1~4#1 := 0; 58616#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58614#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 58612#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 58610#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 58608#L415-1 assume !(1 == ~t5_pc~0); 58605#L425-1 is_transmit5_triggered_~__retres1~5#1 := 0; 58603#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 58601#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 58598#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 58596#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58594#L434-1 assume 1 == ~t6_pc~0; 58592#L435-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 58589#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58587#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 58584#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 58582#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58580#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 58578#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57679#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 58572#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 58569#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 58567#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58565#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58563#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 58561#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 58559#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 58556#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 57657#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 58552#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 58550#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 58538#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 58536#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 58534#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 58532#L1043 assume !(0 == start_simulation_~tmp~3#1); 58530#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 58524#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 58522#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 58521#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 58520#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 58517#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 58516#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 58513#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 58512#L1024 [2024-11-17 08:53:45,055 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:45,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1609344189, now seen corresponding path program 1 times [2024-11-17 08:53:45,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:45,055 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154869757] [2024-11-17 08:53:45,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:45,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:45,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:45,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:45,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:45,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1154869757] [2024-11-17 08:53:45,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1154869757] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:45,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:45,091 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:45,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2125192677] [2024-11-17 08:53:45,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:45,091 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:45,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:45,092 INFO L85 PathProgramCache]: Analyzing trace with hash -1228120576, now seen corresponding path program 1 times [2024-11-17 08:53:45,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:45,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2010607098] [2024-11-17 08:53:45,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:45,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:45,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:45,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:45,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:45,131 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2010607098] [2024-11-17 08:53:45,131 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2010607098] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:45,131 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:45,131 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:45,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174876841] [2024-11-17 08:53:45,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:45,132 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:45,132 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:45,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:45,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:45,133 INFO L87 Difference]: Start difference. First operand 14960 states and 21406 transitions. cyclomatic complexity: 6478 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:45,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:45,317 INFO L93 Difference]: Finished difference Result 27959 states and 39811 transitions. [2024-11-17 08:53:45,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27959 states and 39811 transitions. [2024-11-17 08:53:45,403 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 27624 [2024-11-17 08:53:45,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27959 states to 27959 states and 39811 transitions. [2024-11-17 08:53:45,467 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27959 [2024-11-17 08:53:45,486 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27959 [2024-11-17 08:53:45,487 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27959 states and 39811 transitions. [2024-11-17 08:53:45,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:45,515 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27959 states and 39811 transitions. [2024-11-17 08:53:45,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27959 states and 39811 transitions. [2024-11-17 08:53:45,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27959 to 27831. [2024-11-17 08:53:45,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27831 states, 27831 states have (on average 1.4258560597894434) internal successors, (39683), 27830 states have internal predecessors, (39683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:45,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27831 states to 27831 states and 39683 transitions. [2024-11-17 08:53:45,945 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27831 states and 39683 transitions. [2024-11-17 08:53:45,945 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:45,946 INFO L425 stractBuchiCegarLoop]: Abstraction has 27831 states and 39683 transitions. [2024-11-17 08:53:45,946 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:53:45,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27831 states and 39683 transitions. [2024-11-17 08:53:46,005 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 27496 [2024-11-17 08:53:46,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:46,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:46,006 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,006 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,007 INFO L745 eck$LassoCheckResult]: Stem: 98842#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 98155#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 98156#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 98655#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98070#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 98071#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 98151#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 98152#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 98651#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98293#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98294#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 98599#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 98704#L670-1 assume !(0 == ~M_E~0); 98524#L675-1 assume !(0 == ~T1_E~0); 98525#L680-1 assume !(0 == ~T2_E~0); 98629#L685-1 assume !(0 == ~T3_E~0); 98602#L690-1 assume !(0 == ~T4_E~0); 98603#L695-1 assume !(0 == ~T5_E~0); 98676#L700-1 assume !(0 == ~T6_E~0); 98663#L705-1 assume !(0 == ~E_1~0); 98664#L710-1 assume !(0 == ~E_2~0); 98523#L715-1 assume !(0 == ~E_3~0); 98462#L720-1 assume !(0 == ~E_4~0); 98463#L725-1 assume !(0 == ~E_5~0); 98508#L730-1 assume !(0 == ~E_6~0); 98493#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 98482#L320-8 assume !(1 == ~m_pc~0); 98483#L330-8 is_master_triggered_~__retres1~0#1 := 0; 98379#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98380#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 98281#L825-8 assume !(0 != activate_threads_~tmp~1#1); 98282#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98720#L339-8 assume !(1 == ~t1_pc~0); 98249#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 98250#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98188#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 98189#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 98566#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98567#L358-8 assume !(1 == ~t2_pc~0); 98351#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 98352#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 98596#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98582#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 98583#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98467#L377-8 assume !(1 == ~t3_pc~0); 98099#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 98100#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 98171#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 98172#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 98713#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98742#L396-8 assume !(1 == ~t4_pc~0); 98753#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 98831#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 98365#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 98247#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 98248#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 98579#L415-8 assume 1 == ~t5_pc~0; 98692#L416-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 98229#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 98477#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 98400#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 98401#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 98826#L434-8 assume !(1 == ~t6_pc~0); 98568#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 98569#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 98728#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 98735#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 98736#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98791#L743-1 assume !(1 == ~M_E~0); 98778#L748-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98560#L753-1 assume !(1 == ~T2_E~0); 98561#L758-1 assume !(1 == ~T3_E~0); 98758#L763-1 assume !(1 == ~T4_E~0); 98759#L768-1 assume !(1 == ~T5_E~0); 98377#L773-1 assume !(1 == ~T6_E~0); 98378#L778-1 assume !(1 == ~E_1~0); 98354#L783-1 assume !(1 == ~E_2~0); 98355#L788-1 assume !(1 == ~E_3~0); 98628#L793-1 assume !(1 == ~E_4~0); 98598#L798-1 assume !(1 == ~E_5~0); 98211#L803-1 assume !(1 == ~E_6~0); 98212#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 98839#L1024 [2024-11-17 08:53:46,007 INFO L747 eck$LassoCheckResult]: Loop: 98839#L1024 assume true; 108469#L1024-1 assume !false; 108425#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 108424#L551 assume true; 108423#L551-1 assume !false; 108422#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 108339#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 108334#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 108332#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 108328#L556 assume !(0 != eval_~tmp~0#1); 108329#L559 assume true; 108651#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 108650#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 108649#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 108648#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 108647#L680 assume !(0 == ~T2_E~0); 108646#L685 assume !(0 == ~T3_E~0); 108645#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 108644#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 108643#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 108642#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 108640#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 108638#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 108636#L720 assume !(0 == ~E_4~0); 108634#L725 assume !(0 == ~E_5~0); 108632#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 108630#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108628#L320-1 assume !(1 == ~m_pc~0); 108626#L330-1 is_master_triggered_~__retres1~0#1 := 0; 108624#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108622#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 108620#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 108618#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108616#L339-1 assume !(1 == ~t1_pc~0); 108613#L349-1 is_transmit1_triggered_~__retres1~1#1 := 0; 108611#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108609#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 108607#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 108605#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108603#L358-1 assume 1 == ~t2_pc~0; 108601#L359-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 108598#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 108596#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 108594#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 108592#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108590#L377-1 assume !(1 == ~t3_pc~0); 108588#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 108586#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108584#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 108582#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 108580#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108578#L396-1 assume !(1 == ~t4_pc~0); 108575#L406-1 is_transmit4_triggered_~__retres1~4#1 := 0; 108573#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108571#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 108569#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 108567#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 108565#L415-1 assume !(1 == ~t5_pc~0); 108561#L425-1 is_transmit5_triggered_~__retres1~5#1 := 0; 108559#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 108557#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 108555#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 108553#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 108551#L434-1 assume 1 == ~t6_pc~0; 108549#L435-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 108547#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 108546#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 108544#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 108542#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 108540#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 108538#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 106259#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 106593#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 108534#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 108533#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 108531#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 108530#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 108529#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 108528#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 108526#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 107573#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 108523#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 108521#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 108509#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 108506#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 108504#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 108501#L1043 assume !(0 == start_simulation_~tmp~3#1); 108497#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 108485#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 108482#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 108480#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 108478#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 108476#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 108474#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 108472#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 98839#L1024 [2024-11-17 08:53:46,007 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,007 INFO L85 PathProgramCache]: Analyzing trace with hash -1102359526, now seen corresponding path program 1 times [2024-11-17 08:53:46,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,008 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64891152] [2024-11-17 08:53:46,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [64891152] [2024-11-17 08:53:46,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [64891152] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:46,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [31892770] [2024-11-17 08:53:46,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,114 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:46,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,114 INFO L85 PathProgramCache]: Analyzing trace with hash 138327459, now seen corresponding path program 1 times [2024-11-17 08:53:46,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856129435] [2024-11-17 08:53:46,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856129435] [2024-11-17 08:53:46,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856129435] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,211 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,211 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:46,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2014920217] [2024-11-17 08:53:46,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,211 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:46,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:46,211 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:46,211 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:46,212 INFO L87 Difference]: Start difference. First operand 27831 states and 39683 transitions. cyclomatic complexity: 11916 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:46,557 INFO L93 Difference]: Finished difference Result 51982 states and 73864 transitions. [2024-11-17 08:53:46,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51982 states and 73864 transitions. [2024-11-17 08:53:46,916 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 51296 [2024-11-17 08:53:47,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51982 states to 51982 states and 73864 transitions. [2024-11-17 08:53:47,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51982 [2024-11-17 08:53:47,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51982 [2024-11-17 08:53:47,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51982 states and 73864 transitions. [2024-11-17 08:53:47,113 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:47,113 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51982 states and 73864 transitions. [2024-11-17 08:53:47,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51982 states and 73864 transitions. [2024-11-17 08:53:47,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51982 to 51726. [2024-11-17 08:53:47,626 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51726 states, 51726 states have (on average 1.4230367706762557) internal successors, (73608), 51725 states have internal predecessors, (73608), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:47,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51726 states to 51726 states and 73608 transitions. [2024-11-17 08:53:47,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51726 states and 73608 transitions. [2024-11-17 08:53:47,706 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:47,706 INFO L425 stractBuchiCegarLoop]: Abstraction has 51726 states and 73608 transitions. [2024-11-17 08:53:47,706 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:53:47,706 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51726 states and 73608 transitions. [2024-11-17 08:53:47,954 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 51040 [2024-11-17 08:53:47,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:47,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:47,955 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,955 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,956 INFO L745 eck$LassoCheckResult]: Stem: 178715#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 177979#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 177980#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 178505#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 177892#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 177893#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 177974#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 177975#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 178500#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 178121#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 178122#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 178438#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 178553#L670-1 assume !(0 == ~M_E~0); 178358#L675-1 assume !(0 == ~T1_E~0); 178359#L680-1 assume !(0 == ~T2_E~0); 178477#L685-1 assume !(0 == ~T3_E~0); 178441#L690-1 assume !(0 == ~T4_E~0); 178442#L695-1 assume !(0 == ~T5_E~0); 178528#L700-1 assume !(0 == ~T6_E~0); 178513#L705-1 assume !(0 == ~E_1~0); 178514#L710-1 assume !(0 == ~E_2~0); 178357#L715-1 assume !(0 == ~E_3~0); 178290#L720-1 assume !(0 == ~E_4~0); 178291#L725-1 assume !(0 == ~E_5~0); 178340#L730-1 assume !(0 == ~E_6~0); 178322#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 178309#L320-8 assume !(1 == ~m_pc~0); 178310#L330-8 is_master_triggered_~__retres1~0#1 := 0; 178202#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 178203#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 178108#L825-8 assume !(0 != activate_threads_~tmp~1#1); 178109#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 178570#L339-8 assume !(1 == ~t1_pc~0); 178073#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 178074#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 178012#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 178013#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 178404#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 178405#L358-8 assume !(1 == ~t2_pc~0); 178174#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 178175#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 178435#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 178420#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 178421#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 178294#L377-8 assume !(1 == ~t3_pc~0); 177925#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 177926#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 177995#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 177996#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 178563#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 178594#L396-8 assume !(1 == ~t4_pc~0); 178612#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 178699#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 178188#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 178070#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 178071#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 178416#L415-8 assume !(1 == ~t5_pc~0); 178051#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 178052#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 178304#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 178222#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 178223#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 178687#L434-8 assume !(1 == ~t6_pc~0); 178406#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 178407#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 178577#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 178588#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 178589#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178649#L743-1 assume !(1 == ~M_E~0); 178635#L748-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 178398#L753-1 assume !(1 == ~T2_E~0); 178399#L758-1 assume !(1 == ~T3_E~0); 223630#L763-1 assume !(1 == ~T4_E~0); 223628#L768-1 assume !(1 == ~T5_E~0); 223626#L773-1 assume !(1 == ~T6_E~0); 223624#L778-1 assume !(1 == ~E_1~0); 223622#L783-1 assume !(1 == ~E_2~0); 223619#L788-1 assume !(1 == ~E_3~0); 223617#L793-1 assume !(1 == ~E_4~0); 178474#L798-1 assume !(1 == ~E_5~0); 223614#L803-1 assume !(1 == ~E_6~0); 223612#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 223610#L1024 [2024-11-17 08:53:47,956 INFO L747 eck$LassoCheckResult]: Loop: 223610#L1024 assume true; 223609#L1024-1 assume !false; 223594#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 223591#L551 assume true; 223588#L551-1 assume !false; 223587#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 200098#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 200093#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 200091#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 200088#L556 assume !(0 != eval_~tmp~0#1); 200089#L559 assume true; 223867#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 223865#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 223863#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 223861#L675 assume 0 == ~T1_E~0;~T1_E~0 := 1; 223859#L680 assume !(0 == ~T2_E~0); 223857#L685 assume !(0 == ~T3_E~0); 223855#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 223853#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 223851#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 223849#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 223847#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 223845#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 223843#L720 assume !(0 == ~E_4~0); 223841#L725 assume !(0 == ~E_5~0); 223839#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 223837#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 223835#L320-1 assume !(1 == ~m_pc~0); 223833#L330-1 is_master_triggered_~__retres1~0#1 := 0; 223831#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223829#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 223827#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 223825#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 223823#L339-1 assume !(1 == ~t1_pc~0); 223821#L349-1 is_transmit1_triggered_~__retres1~1#1 := 0; 223819#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 223816#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 223814#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 223812#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223810#L358-1 assume 1 == ~t2_pc~0; 223808#L359-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 223805#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223803#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 223801#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 223799#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223797#L377-1 assume !(1 == ~t3_pc~0); 223795#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 223793#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 223791#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 223789#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 223787#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223785#L396-1 assume !(1 == ~t4_pc~0); 223783#L406-1 is_transmit4_triggered_~__retres1~4#1 := 0; 223781#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223779#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 223777#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 223775#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 223773#L415-1 assume !(1 == ~t5_pc~0); 223771#L425-1 is_transmit5_triggered_~__retres1~5#1 := 0; 223769#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223766#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 223764#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 223762#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 223760#L434-1 assume 1 == ~t6_pc~0; 223758#L435-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 223755#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223754#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 223753#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 223752#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 223750#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 223748#L748 assume 1 == ~T1_E~0;~T1_E~0 := 2; 202367#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 205322#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 223742#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 223740#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 223739#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 223738#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 223736#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 223734#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 223732#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 223728#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 223725#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 223723#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 223711#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 223708#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 223706#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 223703#L1043 assume !(0 == start_simulation_~tmp~3#1); 223700#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 223680#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 223677#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 223675#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 223673#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 223670#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 223668#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 223611#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 223610#L1024 [2024-11-17 08:53:47,956 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:47,956 INFO L85 PathProgramCache]: Analyzing trace with hash -1211888329, now seen corresponding path program 1 times [2024-11-17 08:53:47,956 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:47,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961051663] [2024-11-17 08:53:47,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:47,957 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:47,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:48,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:48,009 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:48,009 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961051663] [2024-11-17 08:53:48,010 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961051663] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:48,010 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:48,010 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:48,010 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [949093435] [2024-11-17 08:53:48,010 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:48,012 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:48,012 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:48,012 INFO L85 PathProgramCache]: Analyzing trace with hash 138327459, now seen corresponding path program 2 times [2024-11-17 08:53:48,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:48,012 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921928] [2024-11-17 08:53:48,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:48,013 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:48,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:48,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:48,058 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:48,058 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [921928] [2024-11-17 08:53:48,058 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [921928] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:48,058 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:48,058 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:48,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275524756] [2024-11-17 08:53:48,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:48,059 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:48,059 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:48,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:48,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:48,060 INFO L87 Difference]: Start difference. First operand 51726 states and 73608 transitions. cyclomatic complexity: 22010 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:48,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:48,281 INFO L93 Difference]: Finished difference Result 51717 states and 73301 transitions. [2024-11-17 08:53:48,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51717 states and 73301 transitions. [2024-11-17 08:53:48,462 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 51040 [2024-11-17 08:53:48,627 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51717 states to 51717 states and 73301 transitions. [2024-11-17 08:53:48,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51717 [2024-11-17 08:53:48,666 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51717 [2024-11-17 08:53:48,666 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51717 states and 73301 transitions. [2024-11-17 08:53:48,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:48,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51717 states and 73301 transitions. [2024-11-17 08:53:48,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51717 states and 73301 transitions. [2024-11-17 08:53:49,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51717 to 13380. [2024-11-17 08:53:49,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13380 states, 13380 states have (on average 1.4150971599402093) internal successors, (18934), 13379 states have internal predecessors, (18934), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13380 states to 13380 states and 18934 transitions. [2024-11-17 08:53:49,057 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13380 states and 18934 transitions. [2024-11-17 08:53:49,057 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:49,058 INFO L425 stractBuchiCegarLoop]: Abstraction has 13380 states and 18934 transitions. [2024-11-17 08:53:49,058 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:53:49,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13380 states and 18934 transitions. [2024-11-17 08:53:49,087 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 13152 [2024-11-17 08:53:49,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:49,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:49,088 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,088 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,089 INFO L745 eck$LassoCheckResult]: Stem: 282107#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 281425#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 281426#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 281929#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 281344#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 281345#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 281423#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 281424#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 281924#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 281563#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 281564#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 281871#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 281975#L670-1 assume !(0 == ~M_E~0); 281795#L675-1 assume !(0 == ~T1_E~0); 281796#L680-1 assume !(0 == ~T2_E~0); 281907#L685-1 assume !(0 == ~T3_E~0); 281873#L690-1 assume !(0 == ~T4_E~0); 281874#L695-1 assume !(0 == ~T5_E~0); 281951#L700-1 assume !(0 == ~T6_E~0); 281937#L705-1 assume !(0 == ~E_1~0); 281938#L710-1 assume !(0 == ~E_2~0); 281794#L715-1 assume !(0 == ~E_3~0); 281732#L720-1 assume !(0 == ~E_4~0); 281733#L725-1 assume !(0 == ~E_5~0); 281778#L730-1 assume !(0 == ~E_6~0); 281761#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281751#L320-8 assume !(1 == ~m_pc~0); 281752#L330-8 is_master_triggered_~__retres1~0#1 := 0; 281645#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 281646#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 281552#L825-8 assume !(0 != activate_threads_~tmp~1#1); 281553#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 281993#L339-8 assume !(1 == ~t1_pc~0); 281517#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 281518#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 281458#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 281459#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 281840#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 281841#L358-8 assume !(1 == ~t2_pc~0); 281619#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 281620#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281868#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 281853#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 281854#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 281737#L377-8 assume !(1 == ~t3_pc~0); 281375#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 281376#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 281443#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 281444#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 281986#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 282012#L396-8 assume !(1 == ~t4_pc~0); 282022#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 282098#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 281633#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 281515#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 281516#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 281850#L415-8 assume !(1 == ~t5_pc~0); 281497#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 281498#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 281748#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 281666#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 281667#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 282092#L434-8 assume !(1 == ~t6_pc~0); 281842#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 281843#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 282000#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 282006#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 282007#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 282058#L743-1 assume !(1 == ~M_E~0); 282046#L748-1 assume !(1 == ~T1_E~0); 281834#L753-1 assume !(1 == ~T2_E~0); 281835#L758-1 assume !(1 == ~T3_E~0); 281963#L763-1 assume !(1 == ~T4_E~0); 282025#L768-1 assume !(1 == ~T5_E~0); 281643#L773-1 assume !(1 == ~T6_E~0); 281644#L778-1 assume !(1 == ~E_1~0); 281624#L783-1 assume !(1 == ~E_2~0); 281625#L788-1 assume !(1 == ~E_3~0); 281903#L793-1 assume !(1 == ~E_4~0); 281869#L798-1 assume !(1 == ~E_5~0); 281480#L803-1 assume !(1 == ~E_6~0); 281481#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 282102#L1024 [2024-11-17 08:53:49,089 INFO L747 eck$LassoCheckResult]: Loop: 282102#L1024 assume true; 285877#L1024-1 assume !false; 285847#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 285845#L551 assume true; 285843#L551-1 assume !false; 285841#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 285831#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 285826#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 285824#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 285820#L556 assume !(0 != eval_~tmp~0#1); 285821#L559 assume true; 286060#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 286058#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 286054#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 286050#L675 assume !(0 == ~T1_E~0); 286049#L680 assume !(0 == ~T2_E~0); 286048#L685 assume !(0 == ~T3_E~0); 286047#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 286046#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 286045#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 286044#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 286043#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 286042#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 286041#L720 assume !(0 == ~E_4~0); 286040#L725 assume !(0 == ~E_5~0); 286039#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 286038#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 286036#L320-1 assume !(1 == ~m_pc~0); 286034#L330-1 is_master_triggered_~__retres1~0#1 := 0; 286032#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 286030#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 286028#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 286026#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 286024#L339-1 assume !(1 == ~t1_pc~0); 286022#L349-1 is_transmit1_triggered_~__retres1~1#1 := 0; 286020#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 286018#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 286016#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 286014#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 286012#L358-1 assume !(1 == ~t2_pc~0); 286008#L368-1 is_transmit2_triggered_~__retres1~2#1 := 0; 286006#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 286004#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 286002#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 286000#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 285998#L377-1 assume !(1 == ~t3_pc~0); 285996#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 285994#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 285992#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 285990#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 285988#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 285986#L396-1 assume !(1 == ~t4_pc~0); 285984#L406-1 is_transmit4_triggered_~__retres1~4#1 := 0; 285982#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 285980#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 285978#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 285976#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 285974#L415-1 assume !(1 == ~t5_pc~0); 285972#L425-1 is_transmit5_triggered_~__retres1~5#1 := 0; 285970#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 285968#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 285966#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 285964#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 285962#L434-1 assume !(1 == ~t6_pc~0); 285958#L444-1 is_transmit6_triggered_~__retres1~6#1 := 0; 285956#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 285954#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 285952#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 285950#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 285948#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 285946#L748 assume !(1 == ~T1_E~0); 285944#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 285942#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 285940#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 285938#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 285936#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 285934#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 285932#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 285930#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 285928#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 285926#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 285924#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 285923#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 285917#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 285914#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 285912#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 285909#L1043 assume !(0 == start_simulation_~tmp~3#1); 285906#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 285894#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 285891#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 285889#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 285887#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 285885#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 285883#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 285880#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 282102#L1024 [2024-11-17 08:53:49,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,090 INFO L85 PathProgramCache]: Analyzing trace with hash -1505291336, now seen corresponding path program 1 times [2024-11-17 08:53:49,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1871136650] [2024-11-17 08:53:49,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:49,098 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:49,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:49,138 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:49,139 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,139 INFO L85 PathProgramCache]: Analyzing trace with hash 2043981919, now seen corresponding path program 1 times [2024-11-17 08:53:49,139 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,139 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366361376] [2024-11-17 08:53:49,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,139 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,176 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1366361376] [2024-11-17 08:53:49,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1366361376] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,176 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:49,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765060966] [2024-11-17 08:53:49,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,177 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:49,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:49,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:53:49,177 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:53:49,178 INFO L87 Difference]: Start difference. First operand 13380 states and 18934 transitions. cyclomatic complexity: 5586 Second operand has 5 states, 5 states have (on average 19.0) internal successors, (95), 5 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:49,256 INFO L93 Difference]: Finished difference Result 13604 states and 19158 transitions. [2024-11-17 08:53:49,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13604 states and 19158 transitions. [2024-11-17 08:53:49,382 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 13376 [2024-11-17 08:53:49,404 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13604 states to 13604 states and 19158 transitions. [2024-11-17 08:53:49,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13604 [2024-11-17 08:53:49,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13604 [2024-11-17 08:53:49,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13604 states and 19158 transitions. [2024-11-17 08:53:49,415 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:49,416 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13604 states and 19158 transitions. [2024-11-17 08:53:49,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13604 states and 19158 transitions. [2024-11-17 08:53:49,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13604 to 13476. [2024-11-17 08:53:49,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13476 states, 13476 states have (on average 1.4121401009201544) internal successors, (19030), 13475 states have internal predecessors, (19030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13476 states to 13476 states and 19030 transitions. [2024-11-17 08:53:49,518 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13476 states and 19030 transitions. [2024-11-17 08:53:49,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:53:49,518 INFO L425 stractBuchiCegarLoop]: Abstraction has 13476 states and 19030 transitions. [2024-11-17 08:53:49,518 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:53:49,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13476 states and 19030 transitions. [2024-11-17 08:53:49,549 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 13248 [2024-11-17 08:53:49,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:49,549 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:49,550 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,550 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,550 INFO L745 eck$LassoCheckResult]: Stem: 309091#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 308421#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 308422#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 308918#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 308336#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 308337#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 308416#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 308417#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 308911#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 308556#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 308557#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 308859#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 308964#L670-1 assume !(0 == ~M_E~0); 308780#L675-1 assume !(0 == ~T1_E~0); 308781#L680-1 assume !(0 == ~T2_E~0); 308894#L685-1 assume !(0 == ~T3_E~0); 308862#L690-1 assume !(0 == ~T4_E~0); 308863#L695-1 assume !(0 == ~T5_E~0); 308938#L700-1 assume !(0 == ~T6_E~0); 308925#L705-1 assume !(0 == ~E_1~0); 308926#L710-1 assume !(0 == ~E_2~0); 308779#L715-1 assume !(0 == ~E_3~0); 308721#L720-1 assume !(0 == ~E_4~0); 308722#L725-1 assume !(0 == ~E_5~0); 308764#L730-1 assume !(0 == ~E_6~0); 308749#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 308739#L320-8 assume !(1 == ~m_pc~0); 308740#L330-8 is_master_triggered_~__retres1~0#1 := 0; 308633#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 308634#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 308545#L825-8 assume !(0 != activate_threads_~tmp~1#1); 308546#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 308980#L339-8 assume !(1 == ~t1_pc~0); 308511#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 308512#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 308451#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 308452#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 308824#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 308825#L358-8 assume !(1 == ~t2_pc~0); 308606#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 308607#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 308856#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 308841#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 308842#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 308725#L377-8 assume !(1 == ~t3_pc~0); 308369#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 308370#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 308436#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 308437#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 308974#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 308999#L396-8 assume !(1 == ~t4_pc~0); 309008#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 309081#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 308620#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 308508#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 308509#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 308837#L415-8 assume !(1 == ~t5_pc~0); 308489#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 308490#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 308736#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 308654#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 308655#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 309068#L434-8 assume !(1 == ~t6_pc~0); 308826#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 308827#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 308984#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 308993#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 308994#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 309039#L743-1 assume !(1 == ~M_E~0); 309029#L748-1 assume !(1 == ~T1_E~0); 308819#L753-1 assume !(1 == ~T2_E~0); 308820#L758-1 assume !(1 == ~T3_E~0); 308951#L763-1 assume !(1 == ~T4_E~0); 309010#L768-1 assume !(1 == ~T5_E~0); 308631#L773-1 assume !(1 == ~T6_E~0); 308632#L778-1 assume !(1 == ~E_1~0); 308611#L783-1 assume !(1 == ~E_2~0); 308612#L788-1 assume !(1 == ~E_3~0); 308892#L793-1 assume !(1 == ~E_4~0); 308857#L798-1 assume !(1 == ~E_5~0); 308472#L803-1 assume !(1 == ~E_6~0); 308473#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 309090#L1024 [2024-11-17 08:53:49,551 INFO L747 eck$LassoCheckResult]: Loop: 309090#L1024 assume true; 312599#L1024-1 assume !false; 312595#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 312594#L551 assume true; 312593#L551-1 assume !false; 312592#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 312588#L504-2 assume !(0 == ~m_st~0); 312589#L508-2 assume !(0 == ~t1_st~0); 312590#L512-2 assume !(0 == ~t2_st~0); 312591#L516-2 assume !(0 == ~t3_st~0); 312584#L520-2 assume !(0 == ~t4_st~0); 312585#L524-2 assume !(0 == ~t5_st~0); 312586#L528-2 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 312587#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 312578#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 312579#L556 assume !(0 != eval_~tmp~0#1); 313254#L559 assume true; 313253#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 313252#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 313251#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 313250#L675 assume !(0 == ~T1_E~0); 313249#L680 assume !(0 == ~T2_E~0); 313248#L685 assume !(0 == ~T3_E~0); 313247#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 313246#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 313245#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 313244#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 313243#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 313242#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 313241#L720 assume !(0 == ~E_4~0); 313240#L725 assume !(0 == ~E_5~0); 313239#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 313238#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 313237#L320-1 assume !(1 == ~m_pc~0); 313236#L330-1 is_master_triggered_~__retres1~0#1 := 0; 313235#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 313234#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 313233#L825-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 313232#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 313231#L339-1 assume !(1 == ~t1_pc~0); 313230#L349-1 is_transmit1_triggered_~__retres1~1#1 := 0; 313229#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 313228#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 313227#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 313226#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 313225#L358-1 assume !(1 == ~t2_pc~0); 313223#L368-1 is_transmit2_triggered_~__retres1~2#1 := 0; 313222#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 313221#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 313220#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 313219#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 313218#L377-1 assume !(1 == ~t3_pc~0); 313217#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 313216#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 313215#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 313214#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 313213#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 313212#L396-1 assume !(1 == ~t4_pc~0); 313211#L406-1 is_transmit4_triggered_~__retres1~4#1 := 0; 313210#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 313209#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 313208#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 313207#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 313206#L415-1 assume !(1 == ~t5_pc~0); 313205#L425-1 is_transmit5_triggered_~__retres1~5#1 := 0; 313204#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 313203#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 313202#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 313201#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 313200#L434-1 assume !(1 == ~t6_pc~0); 313198#L444-1 is_transmit6_triggered_~__retres1~6#1 := 0; 313197#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 313196#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 313195#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 313194#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 313193#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 313192#L748 assume !(1 == ~T1_E~0); 313191#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 313190#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 313189#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 313188#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 313187#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 313186#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 313185#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 313184#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 313183#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 313182#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 313181#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 313180#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 313174#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 313168#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 313107#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 313104#L1043 assume !(0 == start_simulation_~tmp~3#1); 313102#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 313096#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 312626#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 312614#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 312612#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 312610#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 312608#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 312606#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 309090#L1024 [2024-11-17 08:53:49,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1505291336, now seen corresponding path program 2 times [2024-11-17 08:53:49,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,552 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754341645] [2024-11-17 08:53:49,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:49,559 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:49,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:49,578 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:49,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,579 INFO L85 PathProgramCache]: Analyzing trace with hash 365218198, now seen corresponding path program 1 times [2024-11-17 08:53:49,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243148777] [2024-11-17 08:53:49,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,638 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [243148777] [2024-11-17 08:53:49,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [243148777] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,638 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,638 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:49,638 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687547422] [2024-11-17 08:53:49,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,638 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:49,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:49,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:53:49,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:53:49,639 INFO L87 Difference]: Start difference. First operand 13476 states and 19030 transitions. cyclomatic complexity: 5586 Second operand has 5 states, 5 states have (on average 20.2) internal successors, (101), 5 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:49,777 INFO L93 Difference]: Finished difference Result 13764 states and 19237 transitions. [2024-11-17 08:53:49,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13764 states and 19237 transitions. [2024-11-17 08:53:49,819 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 13536 [2024-11-17 08:53:49,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13764 states to 13764 states and 19237 transitions. [2024-11-17 08:53:49,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13764 [2024-11-17 08:53:49,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13764 [2024-11-17 08:53:49,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13764 states and 19237 transitions. [2024-11-17 08:53:49,992 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:49,992 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13764 states and 19237 transitions. [2024-11-17 08:53:49,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13764 states and 19237 transitions. [2024-11-17 08:53:50,101 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13764 to 13764. [2024-11-17 08:53:50,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13764 states, 13764 states have (on average 1.3976315024702122) internal successors, (19237), 13763 states have internal predecessors, (19237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13764 states to 13764 states and 19237 transitions. [2024-11-17 08:53:50,136 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13764 states and 19237 transitions. [2024-11-17 08:53:50,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:53:50,137 INFO L425 stractBuchiCegarLoop]: Abstraction has 13764 states and 19237 transitions. [2024-11-17 08:53:50,137 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:53:50,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13764 states and 19237 transitions. [2024-11-17 08:53:50,173 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 13536 [2024-11-17 08:53:50,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:50,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:50,175 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,175 INFO L745 eck$LassoCheckResult]: Stem: 336328#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 335664#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 335665#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 336157#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 335584#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 335585#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 335662#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 335663#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 336151#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 335803#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 335804#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 336097#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 336201#L670-1 assume !(0 == ~M_E~0); 336026#L675-1 assume !(0 == ~T1_E~0); 336027#L680-1 assume !(0 == ~T2_E~0); 336133#L685-1 assume !(0 == ~T3_E~0); 336099#L690-1 assume !(0 == ~T4_E~0); 336100#L695-1 assume !(0 == ~T5_E~0); 336179#L700-1 assume !(0 == ~T6_E~0); 336166#L705-1 assume !(0 == ~E_1~0); 336167#L710-1 assume !(0 == ~E_2~0); 336025#L715-1 assume !(0 == ~E_3~0); 335965#L720-1 assume !(0 == ~E_4~0); 335966#L725-1 assume !(0 == ~E_5~0); 336010#L730-1 assume !(0 == ~E_6~0); 335992#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 335981#L320-8 assume !(1 == ~m_pc~0); 335982#L330-8 is_master_triggered_~__retres1~0#1 := 0; 335882#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 335883#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 335792#L825-8 assume !(0 != activate_threads_~tmp~1#1); 335793#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 336216#L339-8 assume !(1 == ~t1_pc~0); 335759#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 335760#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 335699#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 335700#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 336067#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 336068#L358-8 assume !(1 == ~t2_pc~0); 335855#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 335856#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 336094#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 336080#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 336081#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 335968#L377-8 assume !(1 == ~t3_pc~0); 335615#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 335616#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 335682#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 335683#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 336211#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 336233#L396-8 assume !(1 == ~t4_pc~0); 336242#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 336321#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 335869#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 335756#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 335757#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336077#L415-8 assume !(1 == ~t5_pc~0); 335737#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 335738#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 335978#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 335902#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 335903#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 336307#L434-8 assume !(1 == ~t6_pc~0); 336069#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 336070#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 336220#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 336228#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 336229#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336279#L743-1 assume !(1 == ~M_E~0); 336267#L748-1 assume !(1 == ~T1_E~0); 336062#L753-1 assume !(1 == ~T2_E~0); 336063#L758-1 assume !(1 == ~T3_E~0); 336189#L763-1 assume !(1 == ~T4_E~0); 336248#L768-1 assume !(1 == ~T5_E~0); 335880#L773-1 assume !(1 == ~T6_E~0); 335881#L778-1 assume !(1 == ~E_1~0); 335860#L783-1 assume !(1 == ~E_2~0); 335861#L788-1 assume !(1 == ~E_3~0); 336131#L793-1 assume !(1 == ~E_4~0); 336095#L798-1 assume !(1 == ~E_5~0); 335720#L803-1 assume !(1 == ~E_6~0); 335721#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 336327#L1024 [2024-11-17 08:53:50,175 INFO L747 eck$LassoCheckResult]: Loop: 336327#L1024 assume true; 346450#L1024-1 assume !false; 346427#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 346425#L551 assume true; 346423#L551-1 assume !false; 346365#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 344959#L504-2 assume !(0 == ~m_st~0); 344960#L508-2 assume !(0 == ~t1_st~0); 344961#L512-2 assume !(0 == ~t2_st~0); 344962#L516-2 assume !(0 == ~t3_st~0); 344955#L520-2 assume !(0 == ~t4_st~0); 344956#L524-2 assume !(0 == ~t5_st~0); 344957#L528-2 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 344958#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 346923#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 346922#L556 assume !(0 != eval_~tmp~0#1); 346921#L559 assume true; 346920#L663 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 346919#L454 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 346917#L670 assume 0 == ~M_E~0;~M_E~0 := 1; 346915#L675 assume !(0 == ~T1_E~0); 346913#L680 assume !(0 == ~T2_E~0); 346911#L685 assume !(0 == ~T3_E~0); 346909#L690 assume 0 == ~T4_E~0;~T4_E~0 := 1; 346908#L695 assume 0 == ~T5_E~0;~T5_E~0 := 1; 346907#L700 assume 0 == ~T6_E~0;~T6_E~0 := 1; 346906#L705 assume 0 == ~E_1~0;~E_1~0 := 1; 346905#L710 assume 0 == ~E_2~0;~E_2~0 := 1; 346904#L715 assume 0 == ~E_3~0;~E_3~0 := 1; 346903#L720 assume !(0 == ~E_4~0); 346902#L725 assume !(0 == ~E_5~0); 346901#L730 assume 0 == ~E_6~0;~E_6~0 := 1; 346899#L736 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 346897#L320-1 assume !(1 == ~m_pc~0); 346895#L330-1 is_master_triggered_~__retres1~0#1 := 0; 346893#L323-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 346891#L332-1 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 346889#L825-1 assume !(0 != activate_threads_~tmp~1#1); 346887#L831-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 346885#L339-1 assume !(1 == ~t1_pc~0); 346883#L349-1 is_transmit1_triggered_~__retres1~1#1 := 0; 346881#L342-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 346879#L351-1 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 346877#L833-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 346875#L839-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 346872#L358-1 assume !(1 == ~t2_pc~0); 346869#L368-1 is_transmit2_triggered_~__retres1~2#1 := 0; 346867#L361-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 346865#L370-1 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 346863#L841-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 346861#L847-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 346859#L377-1 assume !(1 == ~t3_pc~0); 346857#L387-1 is_transmit3_triggered_~__retres1~3#1 := 0; 346855#L380-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 346853#L389-1 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 346851#L849-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 346849#L855-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 346847#L396-1 assume !(1 == ~t4_pc~0); 346845#L406-1 is_transmit4_triggered_~__retres1~4#1 := 0; 346843#L399-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 346841#L408-1 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 346839#L857-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 346837#L863-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 346835#L415-1 assume !(1 == ~t5_pc~0); 346833#L425-1 is_transmit5_triggered_~__retres1~5#1 := 0; 346831#L418-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 346829#L427-1 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 346827#L865-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 346825#L871-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 346822#L434-1 assume 1 == ~t6_pc~0; 346820#L435-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 346817#L437-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 346815#L446-1 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 346813#L873-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 346811#L879-1 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 346809#L743 assume 1 == ~M_E~0;~M_E~0 := 2; 346807#L748 assume !(1 == ~T1_E~0); 346805#L753 assume 1 == ~T2_E~0;~T2_E~0 := 2; 346803#L758 assume 1 == ~T3_E~0;~T3_E~0 := 2; 346801#L763 assume 1 == ~T4_E~0;~T4_E~0 := 2; 346799#L768 assume 1 == ~T5_E~0;~T5_E~0 := 2; 346797#L773 assume 1 == ~T6_E~0;~T6_E~0 := 2; 346795#L778 assume 1 == ~E_1~0;~E_1~0 := 2; 346793#L783 assume 1 == ~E_2~0;~E_2~0 := 2; 346791#L788 assume 1 == ~E_3~0;~E_3~0 := 2; 346789#L793 assume 1 == ~E_4~0;~E_4~0 := 2; 346787#L798 assume 1 == ~E_5~0;~E_5~0 := 2; 346786#L803 assume 1 == ~E_6~0;~E_6~0 := 2; 346785#L809 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 346778#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 346775#L530-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 346772#L542-1 assume true;start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 346769#L1043 assume !(0 == start_simulation_~tmp~3#1); 346766#L1054 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 346752#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 346749#L530 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 346747#L542 assume true;stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 346745#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 346728#L1000 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 346548#L1006 assume true;start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 346475#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 336327#L1024 [2024-11-17 08:53:50,176 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,176 INFO L85 PathProgramCache]: Analyzing trace with hash -1505291336, now seen corresponding path program 3 times [2024-11-17 08:53:50,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369769953] [2024-11-17 08:53:50,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:50,186 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:50,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:50,207 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:50,207 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,207 INFO L85 PathProgramCache]: Analyzing trace with hash 902241816, now seen corresponding path program 1 times [2024-11-17 08:53:50,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384423234] [2024-11-17 08:53:50,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:50,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:50,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:50,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384423234] [2024-11-17 08:53:50,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1384423234] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:50,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:50,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:50,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1440416617] [2024-11-17 08:53:50,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:50,248 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:50,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:50,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:50,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:50,249 INFO L87 Difference]: Start difference. First operand 13764 states and 19237 transitions. cyclomatic complexity: 5505 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:50,335 INFO L93 Difference]: Finished difference Result 23463 states and 32248 transitions. [2024-11-17 08:53:50,335 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23463 states and 32248 transitions. [2024-11-17 08:53:50,430 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 23120 [2024-11-17 08:53:50,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23463 states to 23463 states and 32248 transitions. [2024-11-17 08:53:50,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23463 [2024-11-17 08:53:50,509 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23463 [2024-11-17 08:53:50,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23463 states and 32248 transitions. [2024-11-17 08:53:50,527 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:50,527 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23463 states and 32248 transitions. [2024-11-17 08:53:50,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23463 states and 32248 transitions. [2024-11-17 08:53:50,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23463 to 22743. [2024-11-17 08:53:50,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22743 states, 22743 states have (on average 1.37642351492767) internal successors, (31304), 22742 states have internal predecessors, (31304), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22743 states to 22743 states and 31304 transitions. [2024-11-17 08:53:50,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22743 states and 31304 transitions. [2024-11-17 08:53:50,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:50,882 INFO L425 stractBuchiCegarLoop]: Abstraction has 22743 states and 31304 transitions. [2024-11-17 08:53:50,882 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:53:50,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22743 states and 31304 transitions. [2024-11-17 08:53:50,925 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 22400 [2024-11-17 08:53:50,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:50,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:50,926 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,926 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,926 INFO L745 eck$LassoCheckResult]: Stem: 373577#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 372901#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 372902#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 373395#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 372817#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 372818#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 372896#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 372897#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 373388#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 373036#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 373037#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 373338#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 373439#L670-1 assume !(0 == ~M_E~0); 373264#L675-1 assume !(0 == ~T1_E~0); 373265#L680-1 assume !(0 == ~T2_E~0); 373372#L685-1 assume !(0 == ~T3_E~0); 373339#L690-1 assume !(0 == ~T4_E~0); 373340#L695-1 assume !(0 == ~T5_E~0); 373416#L700-1 assume !(0 == ~T6_E~0); 373401#L705-1 assume !(0 == ~E_1~0); 373402#L710-1 assume !(0 == ~E_2~0); 373263#L715-1 assume !(0 == ~E_3~0); 373200#L720-1 assume !(0 == ~E_4~0); 373201#L725-1 assume !(0 == ~E_5~0); 373245#L730-1 assume !(0 == ~E_6~0); 373226#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 373216#L320-8 assume !(1 == ~m_pc~0); 373217#L330-8 is_master_triggered_~__retres1~0#1 := 0; 373115#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 373116#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 373025#L825-8 assume !(0 != activate_threads_~tmp~1#1); 373026#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 373459#L339-8 assume !(1 == ~t1_pc~0); 372992#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 372993#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 372933#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 372934#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 373306#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 373307#L358-8 assume !(1 == ~t2_pc~0); 373088#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 373089#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 373335#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 373319#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 373320#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 373203#L377-8 assume !(1 == ~t3_pc~0); 372850#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 372851#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 372916#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 372917#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 373451#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 373480#L396-8 assume !(1 == ~t4_pc~0); 373497#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 373571#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 373102#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 372989#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 372990#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 373315#L415-8 assume !(1 == ~t5_pc~0); 372971#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 372972#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 373213#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 373136#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 373137#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 373562#L434-8 assume !(1 == ~t6_pc~0); 373308#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 373309#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 373467#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 373475#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 373476#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 373534#L743-1 assume !(1 == ~M_E~0); 373521#L748-1 assume !(1 == ~T1_E~0); 373301#L753-1 assume !(1 == ~T2_E~0); 373302#L758-1 assume !(1 == ~T3_E~0); 373426#L763-1 assume !(1 == ~T4_E~0); 373501#L768-1 assume !(1 == ~T5_E~0); 373113#L773-1 assume !(1 == ~T6_E~0); 373114#L778-1 assume !(1 == ~E_1~0); 373093#L783-1 assume !(1 == ~E_2~0); 373094#L788-1 assume !(1 == ~E_3~0); 373370#L793-1 assume !(1 == ~E_4~0); 373336#L798-1 assume !(1 == ~E_5~0); 372954#L803-1 assume !(1 == ~E_6~0); 372955#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 373575#L1024 assume true; 377411#L1024-1 assume !false; 377379#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 377377#L551 [2024-11-17 08:53:50,926 INFO L747 eck$LassoCheckResult]: Loop: 377377#L551 assume true; 377375#L551-1 assume !false; 377374#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 377370#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 377369#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 377368#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 377367#L556 assume 0 != eval_~tmp~0#1; 377365#L561-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 377362#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 377360#L561 havoc eval_~tmp_ndt_1~0#1; 377353#L575-1 assume !(0 == ~t1_st~0); 377349#L589-1 assume !(0 == ~t2_st~0); 377339#L603-1 assume !(0 == ~t3_st~0); 377331#L617-1 assume !(0 == ~t4_st~0); 377328#L631-1 assume !(0 == ~t5_st~0); 377329#L645-1 assume !(0 == ~t6_st~0); 377377#L551 [2024-11-17 08:53:50,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,927 INFO L85 PathProgramCache]: Analyzing trace with hash -379598708, now seen corresponding path program 1 times [2024-11-17 08:53:50,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321366060] [2024-11-17 08:53:50,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:50,935 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:50,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:50,947 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:50,948 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,948 INFO L85 PathProgramCache]: Analyzing trace with hash -556053301, now seen corresponding path program 1 times [2024-11-17 08:53:50,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028487508] [2024-11-17 08:53:50,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:50,951 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:50,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:50,954 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:50,954 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,954 INFO L85 PathProgramCache]: Analyzing trace with hash -1410949290, now seen corresponding path program 1 times [2024-11-17 08:53:50,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666677058] [2024-11-17 08:53:50,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:50,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:50,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:50,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666677058] [2024-11-17 08:53:50,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [666677058] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:50,986 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:50,986 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:50,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501607499] [2024-11-17 08:53:50,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:51,061 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:51,062 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:51,062 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:51,062 INFO L87 Difference]: Start difference. First operand 22743 states and 31304 transitions. cyclomatic complexity: 8609 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:51,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:51,155 INFO L93 Difference]: Finished difference Result 29643 states and 40220 transitions. [2024-11-17 08:53:51,155 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29643 states and 40220 transitions. [2024-11-17 08:53:51,243 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 29204 [2024-11-17 08:53:51,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29643 states to 29643 states and 40220 transitions. [2024-11-17 08:53:51,294 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29643 [2024-11-17 08:53:51,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29643 [2024-11-17 08:53:51,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29643 states and 40220 transitions. [2024-11-17 08:53:51,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:51,320 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29643 states and 40220 transitions. [2024-11-17 08:53:51,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29643 states and 40220 transitions. [2024-11-17 08:53:51,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29643 to 28411. [2024-11-17 08:53:51,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28411 states, 28411 states have (on average 1.3587694906902257) internal successors, (38604), 28410 states have internal predecessors, (38604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:51,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28411 states to 28411 states and 38604 transitions. [2024-11-17 08:53:51,696 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28411 states and 38604 transitions. [2024-11-17 08:53:51,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:51,697 INFO L425 stractBuchiCegarLoop]: Abstraction has 28411 states and 38604 transitions. [2024-11-17 08:53:51,697 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:53:51,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28411 states and 38604 transitions. [2024-11-17 08:53:51,753 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 27972 [2024-11-17 08:53:51,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:51,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:51,754 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:51,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:51,754 INFO L745 eck$LassoCheckResult]: Stem: 425984#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 425294#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 425295#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 425802#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 425211#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 425212#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 425290#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 425291#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 425795#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 425433#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 425434#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 425739#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 425850#L670-1 assume !(0 == ~M_E~0); 425669#L675-1 assume !(0 == ~T1_E~0); 425670#L680-1 assume !(0 == ~T2_E~0); 425775#L685-1 assume !(0 == ~T3_E~0); 425741#L690-1 assume !(0 == ~T4_E~0); 425742#L695-1 assume !(0 == ~T5_E~0); 425824#L700-1 assume !(0 == ~T6_E~0); 425810#L705-1 assume !(0 == ~E_1~0); 425811#L710-1 assume !(0 == ~E_2~0); 425668#L715-1 assume !(0 == ~E_3~0); 425600#L720-1 assume !(0 == ~E_4~0); 425601#L725-1 assume !(0 == ~E_5~0); 425652#L730-1 assume !(0 == ~E_6~0); 425633#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 425620#L320-8 assume !(1 == ~m_pc~0); 425621#L330-8 is_master_triggered_~__retres1~0#1 := 0; 425513#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 425514#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 425421#L825-8 assume !(0 != activate_threads_~tmp~1#1); 425422#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 425868#L339-8 assume !(1 == ~t1_pc~0); 425387#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 425388#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 425324#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 425325#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 425712#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 425713#L358-8 assume !(1 == ~t2_pc~0); 425485#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 425486#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 425736#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 425724#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 425725#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 425606#L377-8 assume !(1 == ~t3_pc~0); 425240#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 425241#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 425308#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 425309#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 425861#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 425889#L396-8 assume !(1 == ~t4_pc~0); 425902#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 425976#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 425499#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 425385#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 425386#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 425721#L415-8 assume !(1 == ~t5_pc~0); 425366#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 425367#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 425615#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 425535#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 425536#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 425965#L434-8 assume !(1 == ~t6_pc~0); 425714#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 425715#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 425876#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 425881#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 425882#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425932#L743-1 assume !(1 == ~M_E~0); 425920#L748-1 assume !(1 == ~T1_E~0); 425705#L753-1 assume !(1 == ~T2_E~0); 425706#L758-1 assume !(1 == ~T3_E~0); 425833#L763-1 assume !(1 == ~T4_E~0); 425905#L768-1 assume !(1 == ~T5_E~0); 425511#L773-1 assume !(1 == ~T6_E~0); 425512#L778-1 assume !(1 == ~E_1~0); 425488#L783-1 assume !(1 == ~E_2~0); 425489#L788-1 assume !(1 == ~E_3~0); 425774#L793-1 assume !(1 == ~E_4~0); 425738#L798-1 assume !(1 == ~E_5~0); 425348#L803-1 assume !(1 == ~E_6~0); 425349#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 425982#L1024 assume true; 428784#L1024-1 assume !false; 428766#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 428764#L551 [2024-11-17 08:53:51,754 INFO L747 eck$LassoCheckResult]: Loop: 428764#L551 assume true; 428762#L551-1 assume !false; 428760#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 428757#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 428755#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 428753#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 428751#L556 assume 0 != eval_~tmp~0#1; 428748#L561-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 428745#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 428743#L561 havoc eval_~tmp_ndt_1~0#1; 428742#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 428740#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 428737#L575 havoc eval_~tmp_ndt_2~0#1; 428733#L589-1 assume !(0 == ~t2_st~0); 428723#L603-1 assume !(0 == ~t3_st~0); 428715#L617-1 assume !(0 == ~t4_st~0); 428712#L631-1 assume !(0 == ~t5_st~0); 428713#L645-1 assume !(0 == ~t6_st~0); 428764#L551 [2024-11-17 08:53:51,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:51,755 INFO L85 PathProgramCache]: Analyzing trace with hash -379598708, now seen corresponding path program 2 times [2024-11-17 08:53:51,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:51,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882276871] [2024-11-17 08:53:51,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:51,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:51,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:51,762 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:51,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:51,773 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:51,773 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:51,773 INFO L85 PathProgramCache]: Analyzing trace with hash 1214819831, now seen corresponding path program 1 times [2024-11-17 08:53:51,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:51,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926025054] [2024-11-17 08:53:51,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:51,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:51,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:51,776 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:51,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:51,778 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:51,778 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:51,778 INFO L85 PathProgramCache]: Analyzing trace with hash -1472062, now seen corresponding path program 1 times [2024-11-17 08:53:51,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:51,778 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1833929581] [2024-11-17 08:53:51,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:51,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:51,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:51,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:51,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:51,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1833929581] [2024-11-17 08:53:51,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1833929581] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:51,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:51,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:51,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [874738238] [2024-11-17 08:53:51,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:51,859 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:51,859 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:51,859 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:51,859 INFO L87 Difference]: Start difference. First operand 28411 states and 38604 transitions. cyclomatic complexity: 10241 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:51,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:51,985 INFO L93 Difference]: Finished difference Result 53031 states and 71720 transitions. [2024-11-17 08:53:51,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53031 states and 71720 transitions. [2024-11-17 08:53:52,350 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 52160 [2024-11-17 08:53:52,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53031 states to 53031 states and 71720 transitions. [2024-11-17 08:53:52,457 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53031 [2024-11-17 08:53:52,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53031 [2024-11-17 08:53:52,490 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53031 states and 71720 transitions. [2024-11-17 08:53:52,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:52,511 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53031 states and 71720 transitions. [2024-11-17 08:53:52,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53031 states and 71720 transitions. [2024-11-17 08:53:52,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53031 to 50007. [2024-11-17 08:53:53,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50007 states, 50007 states have (on average 1.356450096986422) internal successors, (67832), 50006 states have internal predecessors, (67832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:53,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50007 states to 50007 states and 67832 transitions. [2024-11-17 08:53:53,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50007 states and 67832 transitions. [2024-11-17 08:53:53,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:53,096 INFO L425 stractBuchiCegarLoop]: Abstraction has 50007 states and 67832 transitions. [2024-11-17 08:53:53,096 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:53:53,097 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50007 states and 67832 transitions. [2024-11-17 08:53:53,236 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 49136 [2024-11-17 08:53:53,236 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:53,236 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:53,237 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:53,237 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:53,237 INFO L745 eck$LassoCheckResult]: Stem: 507440#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 506745#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 506746#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 507260#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 506661#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 506662#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 506740#L471 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 506741#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 513303#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 513302#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 513301#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 513300#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 513299#L670-1 assume !(0 == ~M_E~0); 513298#L675-1 assume !(0 == ~T1_E~0); 513297#L680-1 assume !(0 == ~T2_E~0); 513296#L685-1 assume !(0 == ~T3_E~0); 513295#L690-1 assume !(0 == ~T4_E~0); 513294#L695-1 assume !(0 == ~T5_E~0); 513293#L700-1 assume !(0 == ~T6_E~0); 513292#L705-1 assume !(0 == ~E_1~0); 513291#L710-1 assume !(0 == ~E_2~0); 513290#L715-1 assume !(0 == ~E_3~0); 513289#L720-1 assume !(0 == ~E_4~0); 513288#L725-1 assume !(0 == ~E_5~0); 513287#L730-1 assume !(0 == ~E_6~0); 513286#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 513285#L320-8 assume !(1 == ~m_pc~0); 513284#L330-8 is_master_triggered_~__retres1~0#1 := 0; 513283#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 513282#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 513281#L825-8 assume !(0 != activate_threads_~tmp~1#1); 513280#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 513279#L339-8 assume !(1 == ~t1_pc~0); 513278#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 513277#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 513276#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 513275#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 513274#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 513273#L358-8 assume !(1 == ~t2_pc~0); 513271#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 513270#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 513269#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 513268#L841-8 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 507176#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 507057#L377-8 assume !(1 == ~t3_pc~0); 506690#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 506691#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 506759#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 506760#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 507311#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 507335#L396-8 assume !(1 == ~t4_pc~0); 507343#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 507426#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 506949#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 506837#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 506838#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 507172#L415-8 assume !(1 == ~t5_pc~0); 506819#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 506820#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 507068#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 506985#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 506986#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 507417#L434-8 assume !(1 == ~t6_pc~0); 507164#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 507165#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 507322#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 507328#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 507329#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 507382#L743-1 assume !(1 == ~M_E~0); 507367#L748-1 assume !(1 == ~T1_E~0); 507155#L753-1 assume !(1 == ~T2_E~0); 507156#L758-1 assume !(1 == ~T3_E~0); 513232#L763-1 assume !(1 == ~T4_E~0); 513230#L768-1 assume !(1 == ~T5_E~0); 506962#L773-1 assume !(1 == ~T6_E~0); 506963#L778-1 assume !(1 == ~E_1~0); 506938#L783-1 assume !(1 == ~E_2~0); 506939#L788-1 assume !(1 == ~E_3~0); 507229#L793-1 assume !(1 == ~E_4~0); 507192#L798-1 assume !(1 == ~E_5~0); 506801#L803-1 assume !(1 == ~E_6~0); 506802#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 507433#L1024 assume true; 527585#L1024-1 assume !false; 527563#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 527562#L551 [2024-11-17 08:53:53,237 INFO L747 eck$LassoCheckResult]: Loop: 527562#L551 assume true; 527561#L551-1 assume !false; 527558#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 527556#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 527555#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 527554#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 527553#L556 assume 0 != eval_~tmp~0#1; 527550#L561-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 527547#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 527548#L561 havoc eval_~tmp_ndt_1~0#1; 527594#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 527592#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 527591#L575 havoc eval_~tmp_ndt_2~0#1; 527590#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 513157#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 527587#L589 havoc eval_~tmp_ndt_3~0#1; 527582#L603-1 assume !(0 == ~t3_st~0); 527577#L617-1 assume !(0 == ~t4_st~0); 527571#L631-1 assume !(0 == ~t5_st~0); 527564#L645-1 assume !(0 == ~t6_st~0); 527562#L551 [2024-11-17 08:53:53,238 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:53,238 INFO L85 PathProgramCache]: Analyzing trace with hash 189217804, now seen corresponding path program 1 times [2024-11-17 08:53:53,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:53,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1182002164] [2024-11-17 08:53:53,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:53,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:53,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:53,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:53,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:53,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1182002164] [2024-11-17 08:53:53,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1182002164] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:53,260 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:53,260 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:53,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336022531] [2024-11-17 08:53:53,260 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:53,260 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:53,261 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:53,261 INFO L85 PathProgramCache]: Analyzing trace with hash 1524488843, now seen corresponding path program 1 times [2024-11-17 08:53:53,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:53,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193596654] [2024-11-17 08:53:53,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:53,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:53,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:53,264 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:53,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:53,267 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:53,335 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:53,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:53,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:53,336 INFO L87 Difference]: Start difference. First operand 50007 states and 67832 transitions. cyclomatic complexity: 17873 Second operand has 3 states, 3 states have (on average 28.333333333333332) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:53,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:53,477 INFO L93 Difference]: Finished difference Result 49927 states and 67719 transitions. [2024-11-17 08:53:53,478 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49927 states and 67719 transitions. [2024-11-17 08:53:53,678 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 49136 [2024-11-17 08:53:53,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49927 states to 49927 states and 67719 transitions. [2024-11-17 08:53:53,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49927 [2024-11-17 08:53:53,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49927 [2024-11-17 08:53:53,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49927 states and 67719 transitions. [2024-11-17 08:53:53,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:53,861 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49927 states and 67719 transitions. [2024-11-17 08:53:53,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49927 states and 67719 transitions. [2024-11-17 08:53:54,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49927 to 49927. [2024-11-17 08:53:54,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49927 states, 49927 states have (on average 1.3563602860175856) internal successors, (67719), 49926 states have internal predecessors, (67719), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:54,603 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49927 states to 49927 states and 67719 transitions. [2024-11-17 08:53:54,603 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49927 states and 67719 transitions. [2024-11-17 08:53:54,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:54,604 INFO L425 stractBuchiCegarLoop]: Abstraction has 49927 states and 67719 transitions. [2024-11-17 08:53:54,604 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:53:54,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49927 states and 67719 transitions. [2024-11-17 08:53:54,717 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 49136 [2024-11-17 08:53:54,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:54,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:54,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:54,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:54,718 INFO L745 eck$LassoCheckResult]: Stem: 607393#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 606683#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 606684#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 607187#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 606601#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 606602#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 606679#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 606680#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 607180#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 606821#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 606822#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 607122#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 607235#L670-1 assume !(0 == ~M_E~0); 607051#L675-1 assume !(0 == ~T1_E~0); 607052#L680-1 assume !(0 == ~T2_E~0); 607159#L685-1 assume !(0 == ~T3_E~0); 607124#L690-1 assume !(0 == ~T4_E~0); 607125#L695-1 assume !(0 == ~T5_E~0); 607211#L700-1 assume !(0 == ~T6_E~0); 607196#L705-1 assume !(0 == ~E_1~0); 607197#L710-1 assume !(0 == ~E_2~0); 607050#L715-1 assume !(0 == ~E_3~0); 606989#L720-1 assume !(0 == ~E_4~0); 606990#L725-1 assume !(0 == ~E_5~0); 607035#L730-1 assume !(0 == ~E_6~0); 607020#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 607009#L320-8 assume !(1 == ~m_pc~0); 607010#L330-8 is_master_triggered_~__retres1~0#1 := 0; 606903#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 606904#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 606810#L825-8 assume !(0 != activate_threads_~tmp~1#1); 606811#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 607248#L339-8 assume !(1 == ~t1_pc~0); 606777#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 606778#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 606715#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 606716#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 607092#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 607093#L358-8 assume !(1 == ~t2_pc~0); 606875#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 606876#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 607118#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 607105#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 607106#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 606995#L377-8 assume !(1 == ~t3_pc~0); 606630#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 606631#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 606697#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 606698#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 607243#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 607275#L396-8 assume !(1 == ~t4_pc~0); 607286#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 607380#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 606889#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 606775#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 606776#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607102#L415-8 assume !(1 == ~t5_pc~0); 606756#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 606757#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 607004#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 606925#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 606926#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 607362#L434-8 assume !(1 == ~t6_pc~0); 607094#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 607095#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 607257#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 607266#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 607267#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 607324#L743-1 assume !(1 == ~M_E~0); 607310#L748-1 assume !(1 == ~T1_E~0); 607085#L753-1 assume !(1 == ~T2_E~0); 607086#L758-1 assume !(1 == ~T3_E~0); 607220#L763-1 assume !(1 == ~T4_E~0); 607289#L768-1 assume !(1 == ~T5_E~0); 606901#L773-1 assume !(1 == ~T6_E~0); 606902#L778-1 assume !(1 == ~E_1~0); 606878#L783-1 assume !(1 == ~E_2~0); 606879#L788-1 assume !(1 == ~E_3~0); 607158#L793-1 assume !(1 == ~E_4~0); 607121#L798-1 assume !(1 == ~E_5~0); 606739#L803-1 assume !(1 == ~E_6~0); 606740#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 607388#L1024 assume true; 615597#L1024-1 assume !false; 615552#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 615550#L551 [2024-11-17 08:53:54,719 INFO L747 eck$LassoCheckResult]: Loop: 615550#L551 assume true; 615548#L551-1 assume !false; 615546#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 615543#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 615541#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 615538#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 615536#L556 assume 0 != eval_~tmp~0#1; 615533#L561-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 615530#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 615528#L561 havoc eval_~tmp_ndt_1~0#1; 615526#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 615522#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 615523#L575 havoc eval_~tmp_ndt_2~0#1; 615596#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 615594#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 615593#L589 havoc eval_~tmp_ndt_3~0#1; 615589#L603-1 assume !(0 == ~t3_st~0); 615585#L617-1 assume !(0 == ~t4_st~0); 615578#L631-1 assume !(0 == ~t5_st~0); 615553#L645-1 assume !(0 == ~t6_st~0); 615550#L551 [2024-11-17 08:53:54,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:54,719 INFO L85 PathProgramCache]: Analyzing trace with hash -379598708, now seen corresponding path program 3 times [2024-11-17 08:53:54,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:54,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683480910] [2024-11-17 08:53:54,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:54,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:54,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:54,726 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:54,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:54,737 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:54,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:54,738 INFO L85 PathProgramCache]: Analyzing trace with hash 1524488843, now seen corresponding path program 2 times [2024-11-17 08:53:54,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:54,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2144664580] [2024-11-17 08:53:54,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:54,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:54,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:54,741 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:54,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:54,743 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:54,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:54,743 INFO L85 PathProgramCache]: Analyzing trace with hash 899084182, now seen corresponding path program 1 times [2024-11-17 08:53:54,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:54,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187369933] [2024-11-17 08:53:54,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:54,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:54,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:54,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:54,773 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:54,773 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187369933] [2024-11-17 08:53:54,773 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [187369933] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:54,773 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:54,773 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:54,773 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1375048879] [2024-11-17 08:53:54,773 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:54,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:54,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:54,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:54,834 INFO L87 Difference]: Start difference. First operand 49927 states and 67719 transitions. cyclomatic complexity: 17840 Second operand has 3 states, 3 states have (on average 35.0) internal successors, (105), 3 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:54,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:54,990 INFO L93 Difference]: Finished difference Result 67115 states and 90283 transitions. [2024-11-17 08:53:54,990 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67115 states and 90283 transitions. [2024-11-17 08:53:55,224 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 66068 [2024-11-17 08:53:55,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67115 states to 67115 states and 90283 transitions. [2024-11-17 08:53:55,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67115 [2024-11-17 08:53:55,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67115 [2024-11-17 08:53:55,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67115 states and 90283 transitions. [2024-11-17 08:53:55,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:55,819 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67115 states and 90283 transitions. [2024-11-17 08:53:55,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67115 states and 90283 transitions. [2024-11-17 08:53:56,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67115 to 64715. [2024-11-17 08:53:56,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64715 states, 64715 states have (on average 1.3476164722243684) internal successors, (87211), 64714 states have internal predecessors, (87211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:56,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64715 states to 64715 states and 87211 transitions. [2024-11-17 08:53:56,315 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64715 states and 87211 transitions. [2024-11-17 08:53:56,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:56,315 INFO L425 stractBuchiCegarLoop]: Abstraction has 64715 states and 87211 transitions. [2024-11-17 08:53:56,315 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:53:56,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64715 states and 87211 transitions. [2024-11-17 08:53:56,711 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 63668 [2024-11-17 08:53:56,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:56,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:56,711 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:56,711 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:56,712 INFO L745 eck$LassoCheckResult]: Stem: 724470#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 723737#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 723738#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 724268#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 723651#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 723652#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 723733#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 723734#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 724262#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 723874#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 723875#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 724199#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 724318#L670-1 assume !(0 == ~M_E~0); 724121#L675-1 assume !(0 == ~T1_E~0); 724122#L680-1 assume !(0 == ~T2_E~0); 724237#L685-1 assume !(0 == ~T3_E~0); 724202#L690-1 assume !(0 == ~T4_E~0); 724203#L695-1 assume !(0 == ~T5_E~0); 724293#L700-1 assume !(0 == ~T6_E~0); 724279#L705-1 assume !(0 == ~E_1~0); 724280#L710-1 assume !(0 == ~E_2~0); 724120#L715-1 assume !(0 == ~E_3~0); 724053#L720-1 assume !(0 == ~E_4~0); 724054#L725-1 assume !(0 == ~E_5~0); 724105#L730-1 assume !(0 == ~E_6~0); 724086#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 724072#L320-8 assume !(1 == ~m_pc~0); 724073#L330-8 is_master_triggered_~__retres1~0#1 := 0; 723960#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 723961#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 723862#L825-8 assume !(0 != activate_threads_~tmp~1#1); 723863#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 724335#L339-8 assume !(1 == ~t1_pc~0); 723828#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 723829#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 723767#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 723768#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 724167#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 724168#L358-8 assume !(1 == ~t2_pc~0); 723929#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 723930#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 724195#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 724182#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 724183#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 724058#L377-8 assume !(1 == ~t3_pc~0); 723680#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 723681#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 723751#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 723752#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 724327#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 724358#L396-8 assume !(1 == ~t4_pc~0); 724371#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 724459#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 723944#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 723826#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 723827#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 724179#L415-8 assume !(1 == ~t5_pc~0); 723808#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 723809#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 724068#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 723982#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 723983#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 724445#L434-8 assume !(1 == ~t6_pc~0); 724170#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 724171#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 724343#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 724350#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 724351#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 724411#L743-1 assume !(1 == ~M_E~0); 724392#L748-1 assume !(1 == ~T1_E~0); 724160#L753-1 assume !(1 == ~T2_E~0); 724161#L758-1 assume !(1 == ~T3_E~0); 724303#L763-1 assume !(1 == ~T4_E~0); 724373#L768-1 assume !(1 == ~T5_E~0); 723958#L773-1 assume !(1 == ~T6_E~0); 723959#L778-1 assume !(1 == ~E_1~0); 723933#L783-1 assume !(1 == ~E_2~0); 723934#L788-1 assume !(1 == ~E_3~0); 724236#L793-1 assume !(1 == ~E_4~0); 724198#L798-1 assume !(1 == ~E_5~0); 723790#L803-1 assume !(1 == ~E_6~0); 723791#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 724467#L1024 assume true; 731560#L1024-1 assume !false; 731539#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 731537#L551 [2024-11-17 08:53:56,712 INFO L747 eck$LassoCheckResult]: Loop: 731537#L551 assume true; 731535#L551-1 assume !false; 731533#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 731530#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 731528#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 731526#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 731524#L556 assume 0 != eval_~tmp~0#1; 731520#L561-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 731517#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 731515#L561 havoc eval_~tmp_ndt_1~0#1; 731513#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 731511#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 731509#L575 havoc eval_~tmp_ndt_2~0#1; 731506#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 730405#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 731504#L589 havoc eval_~tmp_ndt_3~0#1; 731563#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 731561#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 731559#L603 havoc eval_~tmp_ndt_4~0#1; 731554#L617-1 assume !(0 == ~t4_st~0); 731547#L631-1 assume !(0 == ~t5_st~0); 731540#L645-1 assume !(0 == ~t6_st~0); 731537#L551 [2024-11-17 08:53:56,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:56,712 INFO L85 PathProgramCache]: Analyzing trace with hash -379598708, now seen corresponding path program 4 times [2024-11-17 08:53:56,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:56,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884840750] [2024-11-17 08:53:56,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:56,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:56,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:56,720 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:56,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:56,732 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:56,732 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:56,732 INFO L85 PathProgramCache]: Analyzing trace with hash 524574391, now seen corresponding path program 1 times [2024-11-17 08:53:56,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:56,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170625348] [2024-11-17 08:53:56,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:56,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:56,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:56,735 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:56,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:56,739 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:56,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:56,739 INFO L85 PathProgramCache]: Analyzing trace with hash 806116610, now seen corresponding path program 1 times [2024-11-17 08:53:56,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:56,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697035556] [2024-11-17 08:53:56,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:56,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:56,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:56,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:56,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:56,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697035556] [2024-11-17 08:53:56,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697035556] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:56,763 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:56,763 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:56,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [755131939] [2024-11-17 08:53:56,764 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:56,828 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:56,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:56,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:56,829 INFO L87 Difference]: Start difference. First operand 64715 states and 87211 transitions. cyclomatic complexity: 22544 Second operand has 3 states, 3 states have (on average 35.666666666666664) internal successors, (107), 3 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:57,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:57,021 INFO L93 Difference]: Finished difference Result 88663 states and 118663 transitions. [2024-11-17 08:53:57,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88663 states and 118663 transitions. [2024-11-17 08:53:57,320 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 87208 [2024-11-17 08:53:57,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88663 states to 88663 states and 118663 transitions. [2024-11-17 08:53:57,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88663 [2024-11-17 08:53:57,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88663 [2024-11-17 08:53:57,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88663 states and 118663 transitions. [2024-11-17 08:53:57,623 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:57,623 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88663 states and 118663 transitions. [2024-11-17 08:53:57,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88663 states and 118663 transitions. [2024-11-17 08:53:58,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88663 to 85999. [2024-11-17 08:53:58,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85999 states, 85999 states have (on average 1.340469075221805) internal successors, (115279), 85998 states have internal predecessors, (115279), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:58,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85999 states to 85999 states and 115279 transitions. [2024-11-17 08:53:58,895 INFO L240 hiAutomatonCegarLoop]: Abstraction has 85999 states and 115279 transitions. [2024-11-17 08:53:58,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:58,896 INFO L425 stractBuchiCegarLoop]: Abstraction has 85999 states and 115279 transitions. [2024-11-17 08:53:58,896 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-17 08:53:58,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85999 states and 115279 transitions. [2024-11-17 08:53:59,133 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 84544 [2024-11-17 08:53:59,133 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:59,134 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:59,134 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:59,134 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:59,135 INFO L745 eck$LassoCheckResult]: Stem: 877885#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 877120#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 877121#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 877654#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 877037#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 877038#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 877116#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 877117#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 877647#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 877259#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 877260#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 877577#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 877707#L670-1 assume !(0 == ~M_E~0); 877499#L675-1 assume !(0 == ~T1_E~0); 877500#L680-1 assume !(0 == ~T2_E~0); 877621#L685-1 assume !(0 == ~T3_E~0); 877579#L690-1 assume !(0 == ~T4_E~0); 877580#L695-1 assume !(0 == ~T5_E~0); 877682#L700-1 assume !(0 == ~T6_E~0); 877667#L705-1 assume !(0 == ~E_1~0); 877668#L710-1 assume !(0 == ~E_2~0); 877498#L715-1 assume !(0 == ~E_3~0); 877431#L720-1 assume !(0 == ~E_4~0); 877432#L725-1 assume !(0 == ~E_5~0); 877483#L730-1 assume !(0 == ~E_6~0); 877465#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 877454#L320-8 assume !(1 == ~m_pc~0); 877455#L330-8 is_master_triggered_~__retres1~0#1 := 0; 877340#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 877341#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 877246#L825-8 assume !(0 != activate_threads_~tmp~1#1); 877247#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 877724#L339-8 assume !(1 == ~t1_pc~0); 877213#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 877214#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 877152#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 877153#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 877543#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 877544#L358-8 assume !(1 == ~t2_pc~0); 877312#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 877313#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 877574#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 877558#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 877559#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 877437#L377-8 assume !(1 == ~t3_pc~0); 877066#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 877067#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 877134#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 877135#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 877719#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 877751#L396-8 assume !(1 == ~t4_pc~0); 877766#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 877869#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 877326#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 877211#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 877212#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 877555#L415-8 assume !(1 == ~t5_pc~0); 877192#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 877193#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 877449#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 877361#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 877362#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 877855#L434-8 assume !(1 == ~t6_pc~0); 877546#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 877547#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 877733#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 877742#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 877743#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 877813#L743-1 assume !(1 == ~M_E~0); 877793#L748-1 assume !(1 == ~T1_E~0); 877536#L753-1 assume !(1 == ~T2_E~0); 877537#L758-1 assume !(1 == ~T3_E~0); 877691#L763-1 assume !(1 == ~T4_E~0); 877769#L768-1 assume !(1 == ~T5_E~0); 877338#L773-1 assume !(1 == ~T6_E~0); 877339#L778-1 assume !(1 == ~E_1~0); 877315#L783-1 assume !(1 == ~E_2~0); 877316#L788-1 assume !(1 == ~E_3~0); 877620#L793-1 assume !(1 == ~E_4~0); 877576#L798-1 assume !(1 == ~E_5~0); 877175#L803-1 assume !(1 == ~E_6~0); 877176#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 877876#L1024 assume true; 882998#L1024-1 assume !false; 882986#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 882984#L551 [2024-11-17 08:53:59,135 INFO L747 eck$LassoCheckResult]: Loop: 882984#L551 assume true; 882982#L551-1 assume !false; 882980#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 882977#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 882975#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 882973#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 882971#L556 assume 0 != eval_~tmp~0#1; 882968#L561-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 882965#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 882963#L561 havoc eval_~tmp_ndt_1~0#1; 882960#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 882957#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 882955#L575 havoc eval_~tmp_ndt_2~0#1; 882953#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 882838#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 882949#L589 havoc eval_~tmp_ndt_3~0#1; 883554#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 883548#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 883544#L603 havoc eval_~tmp_ndt_4~0#1; 883540#L617-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 883535#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 883530#L617 havoc eval_~tmp_ndt_5~0#1; 883524#L631-1 assume !(0 == ~t5_st~0); 882987#L645-1 assume !(0 == ~t6_st~0); 882984#L551 [2024-11-17 08:53:59,135 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,135 INFO L85 PathProgramCache]: Analyzing trace with hash -379598708, now seen corresponding path program 5 times [2024-11-17 08:53:59,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971586798] [2024-11-17 08:53:59,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:59,144 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:59,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:59,157 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:59,158 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,158 INFO L85 PathProgramCache]: Analyzing trace with hash 1607231563, now seen corresponding path program 1 times [2024-11-17 08:53:59,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248899403] [2024-11-17 08:53:59,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:59,161 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:53:59,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:53:59,164 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:53:59,164 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,164 INFO L85 PathProgramCache]: Analyzing trace with hash 1586364374, now seen corresponding path program 1 times [2024-11-17 08:53:59,164 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,164 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138008048] [2024-11-17 08:53:59,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,164 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:59,193 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:59,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:59,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [138008048] [2024-11-17 08:53:59,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [138008048] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:59,193 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:59,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:59,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76663352] [2024-11-17 08:53:59,194 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:59,267 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:59,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:59,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:59,267 INFO L87 Difference]: Start difference. First operand 85999 states and 115279 transitions. cyclomatic complexity: 29328 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:59,968 INFO L93 Difference]: Finished difference Result 118602 states and 157882 transitions. [2024-11-17 08:53:59,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118602 states and 157882 transitions. [2024-11-17 08:54:00,398 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 116679 [2024-11-17 08:54:00,681 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118602 states to 118602 states and 157882 transitions. [2024-11-17 08:54:00,681 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118602 [2024-11-17 08:54:00,754 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118602 [2024-11-17 08:54:00,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118602 states and 157882 transitions. [2024-11-17 08:54:00,808 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:00,808 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118602 states and 157882 transitions. [2024-11-17 08:54:00,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118602 states and 157882 transitions. [2024-11-17 08:54:02,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118602 to 116010. [2024-11-17 08:54:02,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116010 states, 116010 states have (on average 1.3330057753641928) internal successors, (154642), 116009 states have internal predecessors, (154642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116010 states to 116010 states and 154642 transitions. [2024-11-17 08:54:02,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116010 states and 154642 transitions. [2024-11-17 08:54:02,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:02,294 INFO L425 stractBuchiCegarLoop]: Abstraction has 116010 states and 154642 transitions. [2024-11-17 08:54:02,294 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-17 08:54:02,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116010 states and 154642 transitions. [2024-11-17 08:54:03,018 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 114087 [2024-11-17 08:54:03,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:03,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:03,019 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,019 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,020 INFO L745 eck$LassoCheckResult]: Stem: 1082505#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1081730#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1081731#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1082269#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1081646#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1081647#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1081728#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1081729#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1082258#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1081873#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1081874#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1082198#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1082317#L670-1 assume !(0 == ~M_E~0); 1082118#L675-1 assume !(0 == ~T1_E~0); 1082119#L680-1 assume !(0 == ~T2_E~0); 1082237#L685-1 assume !(0 == ~T3_E~0); 1082199#L690-1 assume !(0 == ~T4_E~0); 1082200#L695-1 assume !(0 == ~T5_E~0); 1082294#L700-1 assume !(0 == ~T6_E~0); 1082278#L705-1 assume !(0 == ~E_1~0); 1082279#L710-1 assume !(0 == ~E_2~0); 1082117#L715-1 assume !(0 == ~E_3~0); 1082048#L720-1 assume !(0 == ~E_4~0); 1082049#L725-1 assume !(0 == ~E_5~0); 1082098#L730-1 assume !(0 == ~E_6~0); 1082081#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1082069#L320-8 assume !(1 == ~m_pc~0); 1082070#L330-8 is_master_triggered_~__retres1~0#1 := 0; 1081958#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1081959#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1081860#L825-8 assume !(0 != activate_threads_~tmp~1#1); 1081861#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1082338#L339-8 assume !(1 == ~t1_pc~0); 1081825#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1081826#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1081764#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1081765#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 1082166#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1082167#L358-8 assume !(1 == ~t2_pc~0); 1081930#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 1081931#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1082194#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1082180#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 1082181#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1082054#L377-8 assume !(1 == ~t3_pc~0); 1081675#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 1081676#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1081744#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1081745#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 1082328#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1082359#L396-8 assume !(1 == ~t4_pc~0); 1082374#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 1082488#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1081944#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1081822#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 1081823#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1082177#L415-8 assume !(1 == ~t5_pc~0); 1081803#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 1081804#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1082064#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1081980#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 1081981#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1082472#L434-8 assume !(1 == ~t6_pc~0); 1082168#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 1082169#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1082344#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1082354#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 1082355#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1082421#L743-1 assume !(1 == ~M_E~0); 1082403#L748-1 assume !(1 == ~T1_E~0); 1082160#L753-1 assume !(1 == ~T2_E~0); 1082161#L758-1 assume !(1 == ~T3_E~0); 1082303#L763-1 assume !(1 == ~T4_E~0); 1082380#L768-1 assume !(1 == ~T5_E~0); 1081956#L773-1 assume !(1 == ~T6_E~0); 1081957#L778-1 assume !(1 == ~E_1~0); 1081935#L783-1 assume !(1 == ~E_2~0); 1081936#L788-1 assume !(1 == ~E_3~0); 1082234#L793-1 assume !(1 == ~E_4~0); 1082195#L798-1 assume !(1 == ~E_5~0); 1081785#L803-1 assume !(1 == ~E_6~0); 1081786#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 1082500#L1024 assume true; 1139429#L1024-1 assume !false; 1139297#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1139296#L551 [2024-11-17 08:54:03,023 INFO L747 eck$LassoCheckResult]: Loop: 1139296#L551 assume true; 1139295#L551-1 assume !false; 1139294#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1139292#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1139291#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1139290#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1139288#L556 assume 0 != eval_~tmp~0#1; 1139284#L561-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1139281#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1139279#L561 havoc eval_~tmp_ndt_1~0#1; 1139277#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1139274#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1139272#L575 havoc eval_~tmp_ndt_2~0#1; 1135940#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1135938#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1135937#L589 havoc eval_~tmp_ndt_3~0#1; 1135936#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1135933#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1135934#L603 havoc eval_~tmp_ndt_4~0#1; 1139424#L617-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1139420#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1139418#L617 havoc eval_~tmp_ndt_5~0#1; 1139416#L631-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1139413#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1139411#L631 havoc eval_~tmp_ndt_6~0#1; 1139298#L645-1 assume !(0 == ~t6_st~0); 1139296#L551 [2024-11-17 08:54:03,023 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,024 INFO L85 PathProgramCache]: Analyzing trace with hash -379598708, now seen corresponding path program 6 times [2024-11-17 08:54:03,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [341321550] [2024-11-17 08:54:03,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:03,031 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:54:03,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:03,044 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:54:03,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,045 INFO L85 PathProgramCache]: Analyzing trace with hash -1638609033, now seen corresponding path program 1 times [2024-11-17 08:54:03,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511456989] [2024-11-17 08:54:03,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,045 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:03,048 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:54:03,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:03,050 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:54:03,051 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,051 INFO L85 PathProgramCache]: Analyzing trace with hash -217141182, now seen corresponding path program 1 times [2024-11-17 08:54:03,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426604129] [2024-11-17 08:54:03,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,074 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [426604129] [2024-11-17 08:54:03,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [426604129] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,074 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,074 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:03,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855368358] [2024-11-17 08:54:03,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,143 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:03,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:03,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:03,144 INFO L87 Difference]: Start difference. First operand 116010 states and 154642 transitions. cyclomatic complexity: 38680 Second operand has 3 states, 2 states have (on average 55.5) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:03,689 INFO L93 Difference]: Finished difference Result 224718 states and 299408 transitions. [2024-11-17 08:54:03,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 224718 states and 299408 transitions. [2024-11-17 08:54:05,115 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 220959 [2024-11-17 08:54:05,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 224718 states to 224718 states and 299408 transitions. [2024-11-17 08:54:05,722 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 224718 [2024-11-17 08:54:05,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 224718 [2024-11-17 08:54:05,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 224718 states and 299408 transitions. [2024-11-17 08:54:06,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:06,001 INFO L218 hiAutomatonCegarLoop]: Abstraction has 224718 states and 299408 transitions. [2024-11-17 08:54:06,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224718 states and 299408 transitions. [2024-11-17 08:54:08,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224718 to 224718. [2024-11-17 08:54:08,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224718 states, 224718 states have (on average 1.3323721286234302) internal successors, (299408), 224717 states have internal predecessors, (299408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:09,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224718 states to 224718 states and 299408 transitions. [2024-11-17 08:54:09,120 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224718 states and 299408 transitions. [2024-11-17 08:54:09,121 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:09,121 INFO L425 stractBuchiCegarLoop]: Abstraction has 224718 states and 299408 transitions. [2024-11-17 08:54:09,121 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-17 08:54:09,121 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224718 states and 299408 transitions. [2024-11-17 08:54:09,737 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 220959 [2024-11-17 08:54:09,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:09,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:09,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:09,737 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:09,738 INFO L745 eck$LassoCheckResult]: Stem: 1423212#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1422467#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1422468#L987 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1422986#L454-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1422382#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1422383#L466 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1422463#L471 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1422464#L476 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1422978#L481 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1422607#L486 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1422608#L491 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1422916#L497 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1423034#L670-1 assume !(0 == ~M_E~0); 1422841#L675-1 assume !(0 == ~T1_E~0); 1422842#L680-1 assume !(0 == ~T2_E~0); 1422953#L685-1 assume !(0 == ~T3_E~0); 1422918#L690-1 assume !(0 == ~T4_E~0); 1422919#L695-1 assume !(0 == ~T5_E~0); 1423008#L700-1 assume !(0 == ~T6_E~0); 1422993#L705-1 assume !(0 == ~E_1~0); 1422994#L710-1 assume !(0 == ~E_2~0); 1422840#L715-1 assume !(0 == ~E_3~0); 1422774#L720-1 assume !(0 == ~E_4~0); 1422775#L725-1 assume !(0 == ~E_5~0); 1422825#L730-1 assume !(0 == ~E_6~0); 1422807#L736-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1422795#L320-8 assume !(1 == ~m_pc~0); 1422796#L330-8 is_master_triggered_~__retres1~0#1 := 0; 1422689#L323-8 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1422690#L332-8 assume true;activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1422594#L825-8 assume !(0 != activate_threads_~tmp~1#1); 1422595#L831-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1423049#L339-8 assume !(1 == ~t1_pc~0); 1422560#L349-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1422561#L342-8 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1422499#L351-8 assume true;activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1422500#L833-8 assume !(0 != activate_threads_~tmp___0~0#1); 1422884#L839-8 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1422885#L358-8 assume !(1 == ~t2_pc~0); 1422661#L368-8 is_transmit2_triggered_~__retres1~2#1 := 0; 1422662#L361-8 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1422913#L370-8 assume true;activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1422898#L841-8 assume !(0 != activate_threads_~tmp___1~0#1); 1422899#L847-8 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1422779#L377-8 assume !(1 == ~t3_pc~0); 1422411#L387-8 is_transmit3_triggered_~__retres1~3#1 := 0; 1422412#L380-8 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1422481#L389-8 assume true;activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1422482#L849-8 assume !(0 != activate_threads_~tmp___2~0#1); 1423043#L855-8 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1423074#L396-8 assume !(1 == ~t4_pc~0); 1423084#L406-8 is_transmit4_triggered_~__retres1~4#1 := 0; 1423200#L399-8 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1422675#L408-8 assume true;activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1422558#L857-8 assume !(0 != activate_threads_~tmp___3~0#1); 1422559#L863-8 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1422895#L415-8 assume !(1 == ~t5_pc~0); 1422539#L425-8 is_transmit5_triggered_~__retres1~5#1 := 0; 1422540#L418-8 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1422790#L427-8 assume true;activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1422710#L865-8 assume !(0 != activate_threads_~tmp___4~0#1); 1422711#L871-8 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1423178#L434-8 assume !(1 == ~t6_pc~0); 1422886#L444-8 is_transmit6_triggered_~__retres1~6#1 := 0; 1422887#L437-8 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1423057#L446-8 assume true;activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1423066#L873-8 assume !(0 != activate_threads_~tmp___5~0#1); 1423067#L879-8 assume true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1423125#L743-1 assume !(1 == ~M_E~0); 1423105#L748-1 assume !(1 == ~T1_E~0); 1422878#L753-1 assume !(1 == ~T2_E~0); 1422879#L758-1 assume !(1 == ~T3_E~0); 1423019#L763-1 assume !(1 == ~T4_E~0); 1423088#L768-1 assume !(1 == ~T5_E~0); 1422687#L773-1 assume !(1 == ~T6_E~0); 1422688#L778-1 assume !(1 == ~E_1~0); 1422664#L783-1 assume !(1 == ~E_2~0); 1422665#L788-1 assume !(1 == ~E_3~0); 1422952#L793-1 assume !(1 == ~E_4~0); 1422915#L798-1 assume !(1 == ~E_5~0); 1422522#L803-1 assume !(1 == ~E_6~0); 1422523#L809-1 assume true;assume { :end_inline_reset_delta_events } true; 1423208#L1024 assume true; 1500082#L1024-1 assume !false; 1500021#start_simulation_while_9_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1500019#L551 [2024-11-17 08:54:09,738 INFO L747 eck$LassoCheckResult]: Loop: 1500019#L551 assume true; 1500017#L551-1 assume !false; 1500015#eval_while_8_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1500012#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1500010#L530-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1500008#L542-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1500006#L556 assume 0 != eval_~tmp~0#1; 1500003#L561-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1500000#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1499998#L561 havoc eval_~tmp_ndt_1~0#1; 1499996#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1499993#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1499990#L575 havoc eval_~tmp_ndt_2~0#1; 1499988#L589-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1499938#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1499986#L589 havoc eval_~tmp_ndt_3~0#1; 1511599#L603-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1511597#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1511595#L603 havoc eval_~tmp_ndt_4~0#1; 1511593#L617-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1511590#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1511588#L617 havoc eval_~tmp_ndt_5~0#1; 1511586#L631-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1511583#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1511584#L631 havoc eval_~tmp_ndt_6~0#1; 1500027#L645-1 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1500024#L648 assume !(0 != eval_~tmp_ndt_7~0#1); 1500022#L645 havoc eval_~tmp_ndt_7~0#1; 1500019#L551 [2024-11-17 08:54:09,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:09,738 INFO L85 PathProgramCache]: Analyzing trace with hash -379598708, now seen corresponding path program 7 times [2024-11-17 08:54:09,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:09,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422231349] [2024-11-17 08:54:09,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:09,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:09,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:09,745 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:54:09,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:09,757 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:54:09,758 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:09,758 INFO L85 PathProgramCache]: Analyzing trace with hash 1549727326, now seen corresponding path program 1 times [2024-11-17 08:54:09,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:09,758 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239540418] [2024-11-17 08:54:09,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:09,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:09,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:09,762 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:54:09,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:09,765 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:54:09,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:09,765 INFO L85 PathProgramCache]: Analyzing trace with hash 1780732009, now seen corresponding path program 1 times [2024-11-17 08:54:09,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:09,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115919877] [2024-11-17 08:54:09,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:09,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:09,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:09,774 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:54:09,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:09,792 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-17 08:54:11,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:11,465 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-17 08:54:11,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-17 08:54:11,652 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 17.11 08:54:11 BoogieIcfgContainer [2024-11-17 08:54:11,652 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-17 08:54:11,652 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-17 08:54:11,652 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-17 08:54:11,653 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-17 08:54:11,654 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:41" (3/4) ... [2024-11-17 08:54:11,657 INFO L140 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-17 08:54:11,734 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-17 08:54:11,735 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-17 08:54:11,735 INFO L158 Benchmark]: Toolchain (without parser) took 31360.15ms. Allocated memory was 140.5MB in the beginning and 13.9GB in the end (delta: 13.8GB). Free memory was 68.6MB in the beginning and 10.5GB in the end (delta: -10.4GB). Peak memory consumption was 3.3GB. Max. memory is 16.1GB. [2024-11-17 08:54:11,735 INFO L158 Benchmark]: CDTParser took 0.15ms. Allocated memory is still 140.5MB. Free memory is still 91.6MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-17 08:54:11,735 INFO L158 Benchmark]: CACSL2BoogieTranslator took 359.11ms. Allocated memory was 140.5MB in the beginning and 201.3MB in the end (delta: 60.8MB). Free memory was 68.5MB in the beginning and 163.2MB in the end (delta: -94.7MB). Peak memory consumption was 12.2MB. Max. memory is 16.1GB. [2024-11-17 08:54:11,736 INFO L158 Benchmark]: Boogie Procedure Inliner took 61.59ms. Allocated memory is still 201.3MB. Free memory was 163.2MB in the beginning and 157.8MB in the end (delta: 5.4MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2024-11-17 08:54:11,736 INFO L158 Benchmark]: Boogie Preprocessor took 77.58ms. Allocated memory is still 201.3MB. Free memory was 157.8MB in the beginning and 152.8MB in the end (delta: 5.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-17 08:54:11,736 INFO L158 Benchmark]: IcfgBuilder took 1121.51ms. Allocated memory is still 201.3MB. Free memory was 152.8MB in the beginning and 133.7MB in the end (delta: 19.0MB). Peak memory consumption was 65.0MB. Max. memory is 16.1GB. [2024-11-17 08:54:11,736 INFO L158 Benchmark]: BuchiAutomizer took 29649.51ms. Allocated memory was 201.3MB in the beginning and 13.9GB in the end (delta: 13.7GB). Free memory was 133.7MB in the beginning and 10.5GB in the end (delta: -10.4GB). Peak memory consumption was 3.3GB. Max. memory is 16.1GB. [2024-11-17 08:54:11,737 INFO L158 Benchmark]: Witness Printer took 82.35ms. Allocated memory is still 13.9GB. Free memory was 10.5GB in the beginning and 10.5GB in the end (delta: 15.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2024-11-17 08:54:11,738 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15ms. Allocated memory is still 140.5MB. Free memory is still 91.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 359.11ms. Allocated memory was 140.5MB in the beginning and 201.3MB in the end (delta: 60.8MB). Free memory was 68.5MB in the beginning and 163.2MB in the end (delta: -94.7MB). Peak memory consumption was 12.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 61.59ms. Allocated memory is still 201.3MB. Free memory was 163.2MB in the beginning and 157.8MB in the end (delta: 5.4MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 77.58ms. Allocated memory is still 201.3MB. Free memory was 157.8MB in the beginning and 152.8MB in the end (delta: 5.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * IcfgBuilder took 1121.51ms. Allocated memory is still 201.3MB. Free memory was 152.8MB in the beginning and 133.7MB in the end (delta: 19.0MB). Peak memory consumption was 65.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 29649.51ms. Allocated memory was 201.3MB in the beginning and 13.9GB in the end (delta: 13.7GB). Free memory was 133.7MB in the beginning and 10.5GB in the end (delta: -10.4GB). Peak memory consumption was 3.3GB. Max. memory is 16.1GB. * Witness Printer took 82.35ms. Allocated memory is still 13.9GB. Free memory was 10.5GB in the beginning and 10.5GB in the end (delta: 15.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 24 terminating modules (24 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.24 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 224718 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 29.4s and 25 iterations. TraceHistogramMax:1. Analysis of lassos took 4.5s. Construction of modules took 0.5s. Büchi inclusion checks took 21.4s. Highest rank in rank-based complementation 0. Minimization of det autom 24. Minimization of nondet autom 0. Automata minimization 10.7s AutomataMinimizationTime, 24 MinimizatonAttempts, 51783 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 6.6s Buchi closure took 0.5s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 20352 SdHoareTripleChecker+Valid, 0.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 20352 mSDsluCounter, 41467 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 16888 mSDsCounter, 262 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 591 IncrementalHoareTripleChecker+Invalid, 853 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 262 mSolverCounterUnsat, 24579 mSDtfsCounter, 591 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc6 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 551]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int m_st ; [L33] int t1_st ; [L34] int t2_st ; [L35] int t3_st ; [L36] int t4_st ; [L37] int t5_st ; [L38] int t6_st ; [L39] int m_i ; [L40] int t1_i ; [L41] int t2_i ; [L42] int t3_i ; [L43] int t4_i ; [L44] int t5_i ; [L45] int t6_i ; [L46] int M_E = 2; [L47] int T1_E = 2; [L48] int T2_E = 2; [L49] int T3_E = 2; [L50] int T4_E = 2; [L51] int T5_E = 2; [L52] int T6_E = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0] [L1069] int __retres1 ; [L1073] CALL init_model() [L979] m_i = 1 [L980] t1_i = 1 [L981] t2_i = 1 [L982] t3_i = 1 [L983] t4_i = 1 [L984] t5_i = 1 [L985] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1073] RET init_model() [L1074] CALL start_simulation() [L1010] int kernel_st ; [L1011] int tmp ; [L1012] int tmp___0 ; [L1016] kernel_st = 0 [L1017] FCALL update_channels() [L1018] CALL init_threads() [L461] COND TRUE m_i == 1 [L462] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t1_i == 1 [L467] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t2_i == 1 [L472] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t3_i == 1 [L477] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t4_i == 1 [L482] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L486] COND TRUE t5_i == 1 [L487] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L491] COND TRUE t6_i == 1 [L492] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1018] RET init_threads() [L1019] CALL fire_delta_events() [L670] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L725] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L730] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1019] RET fire_delta_events() [L1020] CALL activate_threads() [L813] int tmp ; [L814] int tmp___0 ; [L815] int tmp___1 ; [L816] int tmp___2 ; [L817] int tmp___3 ; [L818] int tmp___4 ; [L819] int tmp___5 ; [L823] CALL, EXPR is_master_triggered() [L317] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L320] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L330] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L332] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L823] RET, EXPR is_master_triggered() [L823] tmp = is_master_triggered() [L825] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] CALL, EXPR is_transmit1_triggered() [L336] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L339] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L349] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L351] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] RET, EXPR is_transmit1_triggered() [L831] tmp___0 = is_transmit1_triggered() [L833] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] CALL, EXPR is_transmit2_triggered() [L355] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L358] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L368] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L370] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] RET, EXPR is_transmit2_triggered() [L839] tmp___1 = is_transmit2_triggered() [L841] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] CALL, EXPR is_transmit3_triggered() [L374] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L377] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L387] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L389] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] RET, EXPR is_transmit3_triggered() [L847] tmp___2 = is_transmit3_triggered() [L849] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] CALL, EXPR is_transmit4_triggered() [L393] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L396] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L406] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L408] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] RET, EXPR is_transmit4_triggered() [L855] tmp___3 = is_transmit4_triggered() [L857] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] CALL, EXPR is_transmit5_triggered() [L412] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L415] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L425] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L427] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] RET, EXPR is_transmit5_triggered() [L863] tmp___4 = is_transmit5_triggered() [L865] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] CALL, EXPR is_transmit6_triggered() [L431] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L434] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L444] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L446] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] RET, EXPR is_transmit6_triggered() [L871] tmp___5 = is_transmit6_triggered() [L873] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1020] RET activate_threads() [L1021] CALL reset_delta_events() [L743] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L798] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L803] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1021] RET reset_delta_events() [L1024] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1027] kernel_st = 1 [L1028] CALL eval() [L547] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] Loop: [L551] COND TRUE 1 [L554] CALL, EXPR exists_runnable_thread() [L501] int __retres1 ; [L504] COND TRUE m_st == 0 [L505] __retres1 = 1 [L542] return (__retres1); [L554] RET, EXPR exists_runnable_thread() [L554] tmp = exists_runnable_thread() [L556] COND TRUE \read(tmp) [L561] COND TRUE m_st == 0 [L562] int tmp_ndt_1; [L563] tmp_ndt_1 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_1)) [L575] COND TRUE t1_st == 0 [L576] int tmp_ndt_2; [L577] tmp_ndt_2 = __VERIFIER_nondet_int() [L578] COND FALSE !(\read(tmp_ndt_2)) [L589] COND TRUE t2_st == 0 [L590] int tmp_ndt_3; [L591] tmp_ndt_3 = __VERIFIER_nondet_int() [L592] COND FALSE !(\read(tmp_ndt_3)) [L603] COND TRUE t3_st == 0 [L604] int tmp_ndt_4; [L605] tmp_ndt_4 = __VERIFIER_nondet_int() [L606] COND FALSE !(\read(tmp_ndt_4)) [L617] COND TRUE t4_st == 0 [L618] int tmp_ndt_5; [L619] tmp_ndt_5 = __VERIFIER_nondet_int() [L620] COND FALSE !(\read(tmp_ndt_5)) [L631] COND TRUE t5_st == 0 [L632] int tmp_ndt_6; [L633] tmp_ndt_6 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_6)) [L645] COND TRUE t6_st == 0 [L646] int tmp_ndt_7; [L647] tmp_ndt_7 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 551]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int m_st ; [L33] int t1_st ; [L34] int t2_st ; [L35] int t3_st ; [L36] int t4_st ; [L37] int t5_st ; [L38] int t6_st ; [L39] int m_i ; [L40] int t1_i ; [L41] int t2_i ; [L42] int t3_i ; [L43] int t4_i ; [L44] int t5_i ; [L45] int t6_i ; [L46] int M_E = 2; [L47] int T1_E = 2; [L48] int T2_E = 2; [L49] int T3_E = 2; [L50] int T4_E = 2; [L51] int T5_E = 2; [L52] int T6_E = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0] [L1069] int __retres1 ; [L1073] CALL init_model() [L979] m_i = 1 [L980] t1_i = 1 [L981] t2_i = 1 [L982] t3_i = 1 [L983] t4_i = 1 [L984] t5_i = 1 [L985] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1073] RET init_model() [L1074] CALL start_simulation() [L1010] int kernel_st ; [L1011] int tmp ; [L1012] int tmp___0 ; [L1016] kernel_st = 0 [L1017] FCALL update_channels() [L1018] CALL init_threads() [L461] COND TRUE m_i == 1 [L462] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t1_i == 1 [L467] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t2_i == 1 [L472] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t3_i == 1 [L477] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t4_i == 1 [L482] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L486] COND TRUE t5_i == 1 [L487] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L491] COND TRUE t6_i == 1 [L492] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1018] RET init_threads() [L1019] CALL fire_delta_events() [L670] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L725] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L730] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1019] RET fire_delta_events() [L1020] CALL activate_threads() [L813] int tmp ; [L814] int tmp___0 ; [L815] int tmp___1 ; [L816] int tmp___2 ; [L817] int tmp___3 ; [L818] int tmp___4 ; [L819] int tmp___5 ; [L823] CALL, EXPR is_master_triggered() [L317] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L320] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L330] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L332] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L823] RET, EXPR is_master_triggered() [L823] tmp = is_master_triggered() [L825] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] CALL, EXPR is_transmit1_triggered() [L336] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L339] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L349] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L351] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] RET, EXPR is_transmit1_triggered() [L831] tmp___0 = is_transmit1_triggered() [L833] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] CALL, EXPR is_transmit2_triggered() [L355] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L358] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L368] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L370] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] RET, EXPR is_transmit2_triggered() [L839] tmp___1 = is_transmit2_triggered() [L841] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] CALL, EXPR is_transmit3_triggered() [L374] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L377] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L387] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L389] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] RET, EXPR is_transmit3_triggered() [L847] tmp___2 = is_transmit3_triggered() [L849] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] CALL, EXPR is_transmit4_triggered() [L393] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L396] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L406] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L408] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] RET, EXPR is_transmit4_triggered() [L855] tmp___3 = is_transmit4_triggered() [L857] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] CALL, EXPR is_transmit5_triggered() [L412] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L415] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L425] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L427] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] RET, EXPR is_transmit5_triggered() [L863] tmp___4 = is_transmit5_triggered() [L865] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] CALL, EXPR is_transmit6_triggered() [L431] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L434] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L444] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L446] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] RET, EXPR is_transmit6_triggered() [L871] tmp___5 = is_transmit6_triggered() [L873] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1020] RET activate_threads() [L1021] CALL reset_delta_events() [L743] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L798] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L803] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1021] RET reset_delta_events() [L1024] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1027] kernel_st = 1 [L1028] CALL eval() [L547] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] Loop: [L551] COND TRUE 1 [L554] CALL, EXPR exists_runnable_thread() [L501] int __retres1 ; [L504] COND TRUE m_st == 0 [L505] __retres1 = 1 [L542] return (__retres1); [L554] RET, EXPR exists_runnable_thread() [L554] tmp = exists_runnable_thread() [L556] COND TRUE \read(tmp) [L561] COND TRUE m_st == 0 [L562] int tmp_ndt_1; [L563] tmp_ndt_1 = __VERIFIER_nondet_int() [L564] COND FALSE !(\read(tmp_ndt_1)) [L575] COND TRUE t1_st == 0 [L576] int tmp_ndt_2; [L577] tmp_ndt_2 = __VERIFIER_nondet_int() [L578] COND FALSE !(\read(tmp_ndt_2)) [L589] COND TRUE t2_st == 0 [L590] int tmp_ndt_3; [L591] tmp_ndt_3 = __VERIFIER_nondet_int() [L592] COND FALSE !(\read(tmp_ndt_3)) [L603] COND TRUE t3_st == 0 [L604] int tmp_ndt_4; [L605] tmp_ndt_4 = __VERIFIER_nondet_int() [L606] COND FALSE !(\read(tmp_ndt_4)) [L617] COND TRUE t4_st == 0 [L618] int tmp_ndt_5; [L619] tmp_ndt_5 = __VERIFIER_nondet_int() [L620] COND FALSE !(\read(tmp_ndt_5)) [L631] COND TRUE t5_st == 0 [L632] int tmp_ndt_6; [L633] tmp_ndt_6 = __VERIFIER_nondet_int() [L634] COND FALSE !(\read(tmp_ndt_6)) [L645] COND TRUE t6_st == 0 [L646] int tmp_ndt_7; [L647] tmp_ndt_7 = __VERIFIER_nondet_int() [L648] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-17 08:54:11,767 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)