./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.07.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.07.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:53:40,667 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:53:40,724 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:53:40,728 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:53:40,729 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:53:40,729 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:53:40,771 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:53:40,772 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:53:40,772 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:53:40,773 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:53:40,773 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:53:40,774 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:53:40,774 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:53:40,776 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:53:40,776 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:53:40,776 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:53:40,776 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:53:40,777 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:53:40,777 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:53:40,777 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:53:40,777 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:53:40,780 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:53:40,780 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:53:40,781 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:53:40,781 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:53:40,781 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:53:40,781 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:53:40,781 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:53:40,782 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:53:40,782 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:53:40,782 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:53:40,782 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:53:40,782 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:53:40,782 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:53:40,783 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:53:40,783 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:53:40,783 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:53:40,783 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:53:40,783 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:53:40,784 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:53:40,784 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f [2024-11-17 08:53:41,068 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:53:41,092 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:53:41,094 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:53:41,095 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:53:41,096 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:53:41,097 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.07.cil.c [2024-11-17 08:53:42,494 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:53:42,640 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:53:42,640 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.07.cil.c [2024-11-17 08:53:42,649 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/03c271bac/4612acca5a1e47bdb2b963b5767a7588/FLAG0036dcd1a [2024-11-17 08:53:43,036 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/03c271bac/4612acca5a1e47bdb2b963b5767a7588 [2024-11-17 08:53:43,038 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:53:43,039 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:53:43,040 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:43,040 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:53:43,045 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:53:43,045 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,046 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4d79a810 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43, skipping insertion in model container [2024-11-17 08:53:43,046 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,103 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:53:43,314 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:43,326 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:53:43,380 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:43,400 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:53:43,400 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43 WrapperNode [2024-11-17 08:53:43,400 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:43,401 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:43,401 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:53:43,401 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:53:43,406 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,416 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,478 INFO L138 Inliner]: procedures = 42, calls = 52, calls flagged for inlining = 47, calls inlined = 125, statements flattened = 1850 [2024-11-17 08:53:43,478 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:43,479 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:53:43,479 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:53:43,479 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:53:43,492 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,492 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,504 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,532 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:53:43,532 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,533 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,555 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,559 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,561 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,567 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,571 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:53:43,576 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:53:43,576 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:53:43,576 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:53:43,576 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (1/1) ... [2024-11-17 08:53:43,585 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:53:43,593 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:53:43,608 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:53:43,610 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:53:43,639 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:53:43,639 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:53:43,639 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:53:43,639 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:53:43,707 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:53:43,708 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:53:44,859 INFO L? ?]: Removed 360 outVars from TransFormulas that were not future-live. [2024-11-17 08:53:44,859 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:53:44,897 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:53:44,897 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:53:44,898 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:44 BoogieIcfgContainer [2024-11-17 08:53:44,898 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:53:44,903 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:53:44,903 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:53:44,906 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:53:44,908 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:44,908 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:53:43" (1/3) ... [2024-11-17 08:53:44,909 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b0cfcc6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:44, skipping insertion in model container [2024-11-17 08:53:44,909 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:44,909 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:43" (2/3) ... [2024-11-17 08:53:44,909 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2b0cfcc6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:44, skipping insertion in model container [2024-11-17 08:53:44,909 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:44,910 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:44" (3/3) ... [2024-11-17 08:53:44,912 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.07.cil.c [2024-11-17 08:53:44,978 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:53:44,978 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:53:44,978 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:53:44,978 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:53:44,978 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:53:44,979 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:53:44,979 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:53:44,979 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:53:44,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 823 states, 822 states have (on average 1.4927007299270072) internal successors, (1227), 822 states have internal predecessors, (1227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:45,048 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 717 [2024-11-17 08:53:45,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:45,049 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:45,061 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:45,062 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:45,062 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:53:45,064 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 823 states, 822 states have (on average 1.4927007299270072) internal successors, (1227), 822 states have internal predecessors, (1227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:45,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 717 [2024-11-17 08:53:45,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:45,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:45,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:45,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:45,095 INFO L745 eck$LassoCheckResult]: Stem: 420#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 23#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 765#L1111true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 245#L514-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 688#L521true assume !(1 == ~m_i~0);~m_st~0 := 2; 171#L526true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 461#L531true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 583#L536true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 679#L541true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 459#L546true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 562#L551true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 818#L556true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 393#L562true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 439#L754-1true assume !(0 == ~M_E~0); 550#L759-1true assume !(0 == ~T1_E~0); 414#L764-1true assume !(0 == ~T2_E~0); 375#L769-1true assume !(0 == ~T3_E~0); 415#L774-1true assume !(0 == ~T4_E~0); 670#L779-1true assume !(0 == ~T5_E~0); 568#L784-1true assume !(0 == ~T6_E~0); 372#L789-1true assume !(0 == ~T7_E~0); 466#L794-1true assume !(0 == ~E_1~0); 807#L799-1true assume !(0 == ~E_2~0); 382#L804-1true assume !(0 == ~E_3~0); 413#L809-1true assume !(0 == ~E_4~0); 596#L814-1true assume !(0 == ~E_5~0); 14#L819-1true assume !(0 == ~E_6~0); 196#L824-1true assume !(0 == ~E_7~0); 200#L830-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 806#L361-9true assume 1 == ~m_pc~0; 646#L362-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 78#L364-9true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 527#L373-9true assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 369#L930-9true assume !(0 != activate_threads_~tmp~1#1); 658#L936-9true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 449#L380-9true assume 1 == ~t1_pc~0; 446#L381-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 399#L383-9true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 402#L392-9true assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 749#L938-9true assume !(0 != activate_threads_~tmp___0~0#1); 280#L944-9true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 756#L399-9true assume 1 == ~t2_pc~0; 565#L400-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 580#L402-9true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 423#L411-9true assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 570#L946-9true assume !(0 != activate_threads_~tmp___1~0#1); 597#L952-9true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 531#L418-9true assume 1 == ~t3_pc~0; 311#L419-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 520#L421-9true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 582#L430-9true assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 518#L954-9true assume !(0 != activate_threads_~tmp___2~0#1); 69#L960-9true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 111#L437-9true assume 1 == ~t4_pc~0; 585#L438-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 265#L440-9true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 262#L449-9true assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 303#L962-9true assume !(0 != activate_threads_~tmp___3~0#1); 9#L968-9true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29#L456-9true assume 1 == ~t5_pc~0; 272#L457-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 239#L459-9true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 740#L468-9true assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 181#L970-9true assume !(0 != activate_threads_~tmp___4~0#1); 638#L976-9true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 58#L475-9true assume 1 == ~t6_pc~0; 458#L476-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 535#L478-9true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 260#L487-9true assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 157#L978-9true assume !(0 != activate_threads_~tmp___5~0#1); 767#L984-9true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53#L494-9true assume 1 == ~t7_pc~0; 639#L495-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 299#L497-9true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 484#L506-9true assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 134#L986-9true assume !(0 != activate_threads_~tmp___6~0#1); 378#L992-9true assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 467#L837-1true assume !(1 == ~M_E~0); 476#L842-1true assume !(1 == ~T1_E~0); 243#L847-1true assume !(1 == ~T2_E~0); 300#L852-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 823#L857-1true assume !(1 == ~T4_E~0); 211#L862-1true assume !(1 == ~T5_E~0); 217#L867-1true assume !(1 == ~T6_E~0); 266#L872-1true assume !(1 == ~T7_E~0); 425#L877-1true assume !(1 == ~E_1~0); 632#L882-1true assume !(1 == ~E_2~0); 755#L887-1true assume !(1 == ~E_3~0); 493#L892-1true assume 1 == ~E_4~0;~E_4~0 := 2; 699#L897-1true assume !(1 == ~E_5~0); 228#L902-1true assume !(1 == ~E_6~0); 514#L907-1true assume !(1 == ~E_7~0); 479#L913-1true assume true;assume { :end_inline_reset_delta_events } true; 451#L1148true [2024-11-17 08:53:45,104 INFO L747 eck$LassoCheckResult]: Loop: 451#L1148true assume true; 522#L1148-1true assume !false; 795#start_simulation_while_10_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40#L621true assume !true; 251#L629true assume true; 540#L747true assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 489#L514true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 728#L754true assume !(0 == ~M_E~0); 347#L759true assume 0 == ~T1_E~0;~T1_E~0 := 1; 820#L764true assume 0 == ~T2_E~0;~T2_E~0 := 1; 660#L769true assume 0 == ~T3_E~0;~T3_E~0 := 1; 168#L774true assume 0 == ~T4_E~0;~T4_E~0 := 1; 321#L779true assume 0 == ~T5_E~0;~T5_E~0 := 1; 619#L784true assume 0 == ~T6_E~0;~T6_E~0 := 1; 267#L789true assume 0 == ~T7_E~0;~T7_E~0 := 1; 174#L794true assume !(0 == ~E_1~0); 310#L799true assume 0 == ~E_2~0;~E_2~0 := 1; 635#L804true assume 0 == ~E_3~0;~E_3~0 := 1; 197#L809true assume 0 == ~E_4~0;~E_4~0 := 1; 684#L814true assume 0 == ~E_5~0;~E_5~0 := 1; 359#L819true assume 0 == ~E_6~0;~E_6~0 := 1; 606#L824true assume 0 == ~E_7~0;~E_7~0 := 1; 610#L830true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 549#L361-1true assume 1 == ~m_pc~0; 560#L362-1true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 460#L364-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116#L373-1true assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 622#L930-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 744#L936-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 734#L380-1true assume 1 == ~t1_pc~0; 297#L381-1true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 224#L383-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 396#L392-1true assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 477#L938-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 556#L944-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 714#L399-1true assume 1 == ~t2_pc~0; 154#L400-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 536#L402-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 344#L411-1true assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 279#L946-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 427#L952-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 320#L418-1true assume 1 == ~t3_pc~0; 313#L419-1true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 401#L421-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247#L430-1true assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 263#L954-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 101#L960-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 343#L437-1true assume !(1 == ~t4_pc~0); 513#L447-1true is_transmit4_triggered_~__retres1~4#1 := 0; 559#L440-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 604#L449-1true assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 739#L962-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 523#L968-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 404#L456-1true assume !(1 == ~t5_pc~0); 786#L466-1true is_transmit5_triggered_~__retres1~5#1 := 0; 809#L459-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 627#L468-1true assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30#L970-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 757#L976-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 419#L475-1true assume !(1 == ~t6_pc~0); 390#L485-1true is_transmit6_triggered_~__retres1~6#1 := 0; 83#L478-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 534#L487-1true assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 454#L978-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 784#L984-1true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 521#L494-1true assume !(1 == ~t7_pc~0); 506#L504-1true is_transmit7_triggered_~__retres1~7#1 := 0; 456#L497-1true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 785#L506-1true assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 286#L986-1true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 94#L992-1true assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 708#L837true assume 1 == ~M_E~0;~M_E~0 := 2; 38#L842true assume 1 == ~T1_E~0;~T1_E~0 := 2; 177#L847true assume 1 == ~T2_E~0;~T2_E~0 := 2; 545#L852true assume 1 == ~T3_E~0;~T3_E~0 := 2; 607#L857true assume 1 == ~T4_E~0;~T4_E~0 := 2; 274#L862true assume 1 == ~T5_E~0;~T5_E~0 := 2; 184#L867true assume 1 == ~T6_E~0;~T6_E~0 := 2; 392#L872true assume 1 == ~T7_E~0;~T7_E~0 := 2; 444#L877true assume 1 == ~E_1~0;~E_1~0 := 2; 569#L882true assume 1 == ~E_2~0;~E_2~0 := 2; 526#L887true assume 1 == ~E_3~0;~E_3~0 := 2; 618#L892true assume 1 == ~E_4~0;~E_4~0 := 2; 738#L897true assume 1 == ~E_5~0;~E_5~0 := 2; 690#L902true assume 1 == ~E_6~0;~E_6~0 := 2; 777#L907true assume 1 == ~E_7~0;~E_7~0 := 2; 88#L913true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 634#L569-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 567#L599-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 416#L612-1true assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 726#L1167true assume !(0 == start_simulation_~tmp~3#1); 707#L1178true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 125#L569true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 146#L599true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 216#L612true assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 337#L1122true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 288#L1124true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7#L1130true assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 141#L1180true assume !(0 != start_simulation_~tmp___0~1#1); 451#L1148true [2024-11-17 08:53:45,113 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:45,113 INFO L85 PathProgramCache]: Analyzing trace with hash -959739763, now seen corresponding path program 1 times [2024-11-17 08:53:45,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:45,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26705493] [2024-11-17 08:53:45,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:45,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:45,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:45,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:45,337 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:45,338 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [26705493] [2024-11-17 08:53:45,339 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [26705493] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:45,339 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:45,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:45,340 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038633745] [2024-11-17 08:53:45,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:45,345 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:45,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:45,346 INFO L85 PathProgramCache]: Analyzing trace with hash 973118907, now seen corresponding path program 1 times [2024-11-17 08:53:45,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:45,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [135508432] [2024-11-17 08:53:45,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:45,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:45,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:45,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:45,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:45,420 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [135508432] [2024-11-17 08:53:45,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [135508432] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:45,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:45,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:45,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450683715] [2024-11-17 08:53:45,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:45,424 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:45,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:45,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:45,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:45,453 INFO L87 Difference]: Start difference. First operand has 823 states, 822 states have (on average 1.4927007299270072) internal successors, (1227), 822 states have internal predecessors, (1227), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:45,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:45,523 INFO L93 Difference]: Finished difference Result 812 states and 1192 transitions. [2024-11-17 08:53:45,525 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1192 transitions. [2024-11-17 08:53:45,533 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:45,541 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 805 states and 1185 transitions. [2024-11-17 08:53:45,542 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 805 [2024-11-17 08:53:45,543 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 805 [2024-11-17 08:53:45,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 805 states and 1185 transitions. [2024-11-17 08:53:45,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:45,553 INFO L218 hiAutomatonCegarLoop]: Abstraction has 805 states and 1185 transitions. [2024-11-17 08:53:45,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 805 states and 1185 transitions. [2024-11-17 08:53:45,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 805 to 805. [2024-11-17 08:53:45,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 805 states, 805 states have (on average 1.4720496894409938) internal successors, (1185), 804 states have internal predecessors, (1185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:45,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 805 states to 805 states and 1185 transitions. [2024-11-17 08:53:45,608 INFO L240 hiAutomatonCegarLoop]: Abstraction has 805 states and 1185 transitions. [2024-11-17 08:53:45,609 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:45,612 INFO L425 stractBuchiCegarLoop]: Abstraction has 805 states and 1185 transitions. [2024-11-17 08:53:45,613 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:53:45,613 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 805 states and 1185 transitions. [2024-11-17 08:53:45,616 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:45,616 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:45,616 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:45,618 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:45,618 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:45,618 INFO L745 eck$LassoCheckResult]: Stem: 2267#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1690#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1691#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2075#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2076#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1979#L526 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1980#L531 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2305#L536 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2391#L541 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2303#L546 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2304#L551 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2381#L556 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2242#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2243#L754-1 assume !(0 == ~M_E~0); 2286#L759-1 assume !(0 == ~T1_E~0); 2261#L764-1 assume !(0 == ~T2_E~0); 2227#L769-1 assume !(0 == ~T3_E~0); 2228#L774-1 assume !(0 == ~T4_E~0); 2262#L779-1 assume !(0 == ~T5_E~0); 2383#L784-1 assume !(0 == ~T6_E~0); 2224#L789-1 assume !(0 == ~T7_E~0); 2225#L794-1 assume !(0 == ~E_1~0); 2308#L799-1 assume !(0 == ~E_2~0); 2233#L804-1 assume !(0 == ~E_3~0); 2234#L809-1 assume !(0 == ~E_4~0); 2260#L814-1 assume !(0 == ~E_5~0); 1671#L819-1 assume !(0 == ~E_6~0); 1672#L824-1 assume !(0 == ~E_7~0); 2009#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2015#L361-9 assume 1 == ~m_pc~0; 2409#L362-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1693#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1797#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2220#L930-9 assume !(0 != activate_threads_~tmp~1#1); 2221#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2295#L380-9 assume 1 == ~t1_pc~0; 2292#L381-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2247#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2248#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2249#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 2123#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2124#L399-9 assume 1 == ~t2_pc~0; 2382#L400-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2004#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2269#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2270#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 2384#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2361#L418-9 assume 1 == ~t3_pc~0; 2156#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2149#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2350#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2348#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 1781#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1782#L437-9 assume 1 == ~t4_pc~0; 1861#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2052#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2098#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2099#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 1659#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1660#L456-9 assume 1 == ~t5_pc~0; 1703#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2065#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2066#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1990#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 1991#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1759#L475-9 assume 1 == ~t6_pc~0; 1760#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1981#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2097#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1949#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 1950#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1748#L494-9 assume 1 == ~t7_pc~0; 1749#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1927#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2144#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1907#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 1908#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2230#L837-1 assume !(1 == ~M_E~0); 2309#L842-1 assume !(1 == ~T1_E~0); 2072#L847-1 assume !(1 == ~T2_E~0); 2073#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2145#L857-1 assume !(1 == ~T4_E~0); 2025#L862-1 assume !(1 == ~T5_E~0); 2026#L867-1 assume !(1 == ~T6_E~0); 2037#L872-1 assume !(1 == ~T7_E~0); 2101#L877-1 assume !(1 == ~E_1~0); 2272#L882-1 assume !(1 == ~E_2~0); 2406#L887-1 assume !(1 == ~E_3~0); 2330#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2331#L897-1 assume !(1 == ~E_5~0); 2050#L902-1 assume !(1 == ~E_6~0); 2051#L907-1 assume !(1 == ~E_7~0); 2316#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 1922#L1148 [2024-11-17 08:53:45,619 INFO L747 eck$LassoCheckResult]: Loop: 1922#L1148 assume true; 2297#L1148-1 assume !false; 2352#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1722#L621 assume true; 1723#L621-1 assume !false; 1885#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1886#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1900#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2422#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1943#L626 assume !(0 != eval_~tmp~0#1); 1945#L629 assume true; 2083#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2327#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2328#L754 assume !(0 == ~M_E~0); 2195#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2196#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2414#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1972#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1973#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2166#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2102#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1982#L794 assume !(0 == ~E_1~0); 1983#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 2155#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 2010#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 2011#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 2205#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 2206#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 2397#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2372#L361-1 assume !(1 == ~m_pc~0); 1859#L371-1 is_master_triggered_~__retres1~0#1 := 0; 1860#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1870#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1871#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2400#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2436#L380-1 assume !(1 == ~t1_pc~0); 1984#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1985#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2047#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2245#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2315#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2377#L399-1 assume 1 == ~t2_pc~0; 1940#L400-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1941#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2193#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2121#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2122#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2165#L418-1 assume 1 == ~t3_pc~0; 2157#L419-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1952#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2078#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2079#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1842#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1843#L437-1 assume 1 == ~t4_pc~0; 2192#L438-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2347#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2380#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2396#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2354#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2252#L456-1 assume 1 == ~t5_pc~0; 2253#L457-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2437#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2402#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1705#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1706#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2266#L475-1 assume 1 == ~t6_pc~0; 1700#L476-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1701#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1809#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2299#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2300#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2351#L494-1 assume 1 == ~t7_pc~0; 1778#L495-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1779#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2301#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2133#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1829#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1830#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 1719#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1720#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1987#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2371#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2112#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1995#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1996#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2241#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 2291#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 2356#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 2357#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 2399#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 2425#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 2426#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 1817#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1818#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1674#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2263#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2264#L1167 assume !(0 == start_simulation_~tmp~3#1); 1921#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1889#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1890#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1928#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2036#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2134#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1655#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1656#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1922#L1148 [2024-11-17 08:53:45,619 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:45,620 INFO L85 PathProgramCache]: Analyzing trace with hash -574372980, now seen corresponding path program 1 times [2024-11-17 08:53:45,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:45,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [520417203] [2024-11-17 08:53:45,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:45,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:45,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:45,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:45,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:45,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [520417203] [2024-11-17 08:53:45,677 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [520417203] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:45,677 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:45,677 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:45,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [163458258] [2024-11-17 08:53:45,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:45,678 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:45,678 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:45,678 INFO L85 PathProgramCache]: Analyzing trace with hash 1442362472, now seen corresponding path program 1 times [2024-11-17 08:53:45,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:45,678 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083788526] [2024-11-17 08:53:45,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:45,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:45,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:45,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:45,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:45,796 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083788526] [2024-11-17 08:53:45,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083788526] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:45,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:45,797 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:45,797 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1077009672] [2024-11-17 08:53:45,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:45,797 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:45,798 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:45,798 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:45,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:45,798 INFO L87 Difference]: Start difference. First operand 805 states and 1185 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:45,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:45,813 INFO L93 Difference]: Finished difference Result 805 states and 1184 transitions. [2024-11-17 08:53:45,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 805 states and 1184 transitions. [2024-11-17 08:53:45,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:45,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 805 states to 805 states and 1184 transitions. [2024-11-17 08:53:45,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 805 [2024-11-17 08:53:45,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 805 [2024-11-17 08:53:45,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 805 states and 1184 transitions. [2024-11-17 08:53:45,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:45,825 INFO L218 hiAutomatonCegarLoop]: Abstraction has 805 states and 1184 transitions. [2024-11-17 08:53:45,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 805 states and 1184 transitions. [2024-11-17 08:53:45,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 805 to 805. [2024-11-17 08:53:45,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 805 states, 805 states have (on average 1.470807453416149) internal successors, (1184), 804 states have internal predecessors, (1184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:45,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 805 states to 805 states and 1184 transitions. [2024-11-17 08:53:45,847 INFO L240 hiAutomatonCegarLoop]: Abstraction has 805 states and 1184 transitions. [2024-11-17 08:53:45,848 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:45,848 INFO L425 stractBuchiCegarLoop]: Abstraction has 805 states and 1184 transitions. [2024-11-17 08:53:45,849 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:53:45,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 805 states and 1184 transitions. [2024-11-17 08:53:45,852 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:45,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:45,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:45,853 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:45,853 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:45,854 INFO L745 eck$LassoCheckResult]: Stem: 3886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3309#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3310#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3694#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3695#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 3598#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3599#L531 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3924#L536 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4010#L541 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3922#L546 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3923#L551 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4000#L556 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3861#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3862#L754-1 assume !(0 == ~M_E~0); 3905#L759-1 assume !(0 == ~T1_E~0); 3880#L764-1 assume !(0 == ~T2_E~0); 3846#L769-1 assume !(0 == ~T3_E~0); 3847#L774-1 assume !(0 == ~T4_E~0); 3881#L779-1 assume !(0 == ~T5_E~0); 4002#L784-1 assume !(0 == ~T6_E~0); 3843#L789-1 assume !(0 == ~T7_E~0); 3844#L794-1 assume !(0 == ~E_1~0); 3927#L799-1 assume !(0 == ~E_2~0); 3852#L804-1 assume !(0 == ~E_3~0); 3853#L809-1 assume !(0 == ~E_4~0); 3879#L814-1 assume !(0 == ~E_5~0); 3290#L819-1 assume !(0 == ~E_6~0); 3291#L824-1 assume !(0 == ~E_7~0); 3628#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3634#L361-9 assume 1 == ~m_pc~0; 4028#L362-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3312#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3416#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3839#L930-9 assume !(0 != activate_threads_~tmp~1#1); 3840#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3914#L380-9 assume 1 == ~t1_pc~0; 3911#L381-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3866#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3867#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3868#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 3742#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3743#L399-9 assume 1 == ~t2_pc~0; 4001#L400-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3623#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3888#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3889#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 4003#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3980#L418-9 assume 1 == ~t3_pc~0; 3775#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3768#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3969#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3967#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 3400#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3401#L437-9 assume 1 == ~t4_pc~0; 3480#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3671#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3717#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3718#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 3278#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3279#L456-9 assume 1 == ~t5_pc~0; 3322#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3684#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3685#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3609#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 3610#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3378#L475-9 assume 1 == ~t6_pc~0; 3379#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3600#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3716#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3568#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 3569#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3367#L494-9 assume 1 == ~t7_pc~0; 3368#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3546#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3763#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3526#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 3527#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3849#L837-1 assume !(1 == ~M_E~0); 3928#L842-1 assume !(1 == ~T1_E~0); 3691#L847-1 assume !(1 == ~T2_E~0); 3692#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3764#L857-1 assume !(1 == ~T4_E~0); 3644#L862-1 assume !(1 == ~T5_E~0); 3645#L867-1 assume !(1 == ~T6_E~0); 3656#L872-1 assume !(1 == ~T7_E~0); 3720#L877-1 assume !(1 == ~E_1~0); 3891#L882-1 assume !(1 == ~E_2~0); 4025#L887-1 assume !(1 == ~E_3~0); 3949#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3950#L897-1 assume !(1 == ~E_5~0); 3669#L902-1 assume !(1 == ~E_6~0); 3670#L907-1 assume !(1 == ~E_7~0); 3935#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 3541#L1148 [2024-11-17 08:53:45,854 INFO L747 eck$LassoCheckResult]: Loop: 3541#L1148 assume true; 3916#L1148-1 assume !false; 3971#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3341#L621 assume true; 3342#L621-1 assume !false; 3504#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3505#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3519#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 4041#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3562#L626 assume !(0 != eval_~tmp~0#1); 3564#L629 assume true; 3702#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3946#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3947#L754 assume !(0 == ~M_E~0); 3814#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3815#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4033#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3591#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3592#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3785#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3721#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3601#L794 assume !(0 == ~E_1~0); 3602#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 3774#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 3629#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 3630#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 3824#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 3825#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 4016#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3991#L361-1 assume !(1 == ~m_pc~0); 3478#L371-1 is_master_triggered_~__retres1~0#1 := 0; 3479#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3489#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3490#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4019#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4055#L380-1 assume 1 == ~t1_pc~0; 3761#L381-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3604#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3666#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3864#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3934#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3996#L399-1 assume 1 == ~t2_pc~0; 3559#L400-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3560#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3812#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3740#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3741#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3784#L418-1 assume 1 == ~t3_pc~0; 3776#L419-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3571#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3697#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3698#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3461#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3462#L437-1 assume !(1 == ~t4_pc~0); 3810#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 3966#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3999#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4015#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3973#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3871#L456-1 assume 1 == ~t5_pc~0; 3872#L457-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4056#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4021#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3324#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3325#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3885#L475-1 assume 1 == ~t6_pc~0; 3319#L476-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3320#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3428#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3918#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3919#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3970#L494-1 assume 1 == ~t7_pc~0; 3397#L495-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3398#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3920#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3752#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3448#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3449#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 3338#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3339#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3606#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3990#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3731#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3614#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3615#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3860#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 3910#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 3975#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 3976#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 4018#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 4044#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 4045#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 3436#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3437#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3293#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3882#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3883#L1167 assume !(0 == start_simulation_~tmp~3#1); 3540#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3508#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3509#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3547#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3655#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3753#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3274#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3275#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 3541#L1148 [2024-11-17 08:53:45,855 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:45,855 INFO L85 PathProgramCache]: Analyzing trace with hash 2070457517, now seen corresponding path program 1 times [2024-11-17 08:53:45,855 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:45,855 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972896861] [2024-11-17 08:53:45,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:45,856 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:45,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:45,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:45,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:45,924 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972896861] [2024-11-17 08:53:45,924 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972896861] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:45,924 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:45,925 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:45,925 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523217742] [2024-11-17 08:53:45,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:45,925 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:45,925 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:45,925 INFO L85 PathProgramCache]: Analyzing trace with hash -1501703768, now seen corresponding path program 1 times [2024-11-17 08:53:45,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:45,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670100812] [2024-11-17 08:53:45,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:45,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:45,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:45,997 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:45,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:45,998 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670100812] [2024-11-17 08:53:45,998 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670100812] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:45,998 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:45,998 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:45,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108637085] [2024-11-17 08:53:45,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:45,999 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:45,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:45,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:45,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:45,999 INFO L87 Difference]: Start difference. First operand 805 states and 1184 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,039 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:46,039 INFO L93 Difference]: Finished difference Result 805 states and 1183 transitions. [2024-11-17 08:53:46,039 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 805 states and 1183 transitions. [2024-11-17 08:53:46,043 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 805 states to 805 states and 1183 transitions. [2024-11-17 08:53:46,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 805 [2024-11-17 08:53:46,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 805 [2024-11-17 08:53:46,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 805 states and 1183 transitions. [2024-11-17 08:53:46,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:46,048 INFO L218 hiAutomatonCegarLoop]: Abstraction has 805 states and 1183 transitions. [2024-11-17 08:53:46,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 805 states and 1183 transitions. [2024-11-17 08:53:46,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 805 to 805. [2024-11-17 08:53:46,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 805 states, 805 states have (on average 1.4695652173913043) internal successors, (1183), 804 states have internal predecessors, (1183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 805 states to 805 states and 1183 transitions. [2024-11-17 08:53:46,061 INFO L240 hiAutomatonCegarLoop]: Abstraction has 805 states and 1183 transitions. [2024-11-17 08:53:46,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:46,062 INFO L425 stractBuchiCegarLoop]: Abstraction has 805 states and 1183 transitions. [2024-11-17 08:53:46,063 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:53:46,064 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 805 states and 1183 transitions. [2024-11-17 08:53:46,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:46,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:46,068 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,071 INFO L745 eck$LassoCheckResult]: Stem: 5505#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 4928#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4929#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5314#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5315#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 5217#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5218#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5543#L536 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5629#L541 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5541#L546 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5542#L551 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5619#L556 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5480#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5481#L754-1 assume !(0 == ~M_E~0); 5524#L759-1 assume !(0 == ~T1_E~0); 5499#L764-1 assume !(0 == ~T2_E~0); 5465#L769-1 assume !(0 == ~T3_E~0); 5466#L774-1 assume !(0 == ~T4_E~0); 5502#L779-1 assume !(0 == ~T5_E~0); 5621#L784-1 assume !(0 == ~T6_E~0); 5462#L789-1 assume !(0 == ~T7_E~0); 5463#L794-1 assume !(0 == ~E_1~0); 5546#L799-1 assume !(0 == ~E_2~0); 5471#L804-1 assume !(0 == ~E_3~0); 5472#L809-1 assume !(0 == ~E_4~0); 5498#L814-1 assume !(0 == ~E_5~0); 4909#L819-1 assume !(0 == ~E_6~0); 4910#L824-1 assume !(0 == ~E_7~0); 5247#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5253#L361-9 assume 1 == ~m_pc~0; 5647#L362-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4931#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5035#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5458#L930-9 assume !(0 != activate_threads_~tmp~1#1); 5459#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5533#L380-9 assume 1 == ~t1_pc~0; 5530#L381-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5485#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5486#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5487#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 5361#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5362#L399-9 assume 1 == ~t2_pc~0; 5620#L400-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5242#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5507#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5508#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 5622#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5599#L418-9 assume 1 == ~t3_pc~0; 5394#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5387#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5588#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5586#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 5019#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5020#L437-9 assume 1 == ~t4_pc~0; 5099#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5290#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5336#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5337#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 4897#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4898#L456-9 assume 1 == ~t5_pc~0; 4941#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5303#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5304#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5228#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 5229#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4997#L475-9 assume 1 == ~t6_pc~0; 4998#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5219#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5335#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5187#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 5188#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4986#L494-9 assume 1 == ~t7_pc~0; 4987#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5165#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5382#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5145#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 5146#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5468#L837-1 assume !(1 == ~M_E~0); 5547#L842-1 assume !(1 == ~T1_E~0); 5310#L847-1 assume !(1 == ~T2_E~0); 5311#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5383#L857-1 assume !(1 == ~T4_E~0); 5263#L862-1 assume !(1 == ~T5_E~0); 5264#L867-1 assume !(1 == ~T6_E~0); 5275#L872-1 assume !(1 == ~T7_E~0); 5339#L877-1 assume !(1 == ~E_1~0); 5510#L882-1 assume !(1 == ~E_2~0); 5644#L887-1 assume !(1 == ~E_3~0); 5568#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5569#L897-1 assume !(1 == ~E_5~0); 5288#L902-1 assume !(1 == ~E_6~0); 5289#L907-1 assume !(1 == ~E_7~0); 5554#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 5160#L1148 [2024-11-17 08:53:46,072 INFO L747 eck$LassoCheckResult]: Loop: 5160#L1148 assume true; 5535#L1148-1 assume !false; 5590#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4960#L621 assume true; 4961#L621-1 assume !false; 5123#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5124#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5138#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5660#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5181#L626 assume !(0 != eval_~tmp~0#1); 5183#L629 assume true; 5321#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5565#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5566#L754 assume !(0 == ~M_E~0); 5433#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5434#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5652#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5210#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5211#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5404#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5340#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5220#L794 assume !(0 == ~E_1~0); 5221#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 5393#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 5248#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 5249#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 5443#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 5444#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 5635#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5610#L361-1 assume !(1 == ~m_pc~0); 5097#L371-1 is_master_triggered_~__retres1~0#1 := 0; 5098#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5108#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5109#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5638#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5674#L380-1 assume 1 == ~t1_pc~0; 5380#L381-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5223#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5285#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5483#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5553#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5615#L399-1 assume 1 == ~t2_pc~0; 5178#L400-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5179#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5431#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5359#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5360#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5403#L418-1 assume 1 == ~t3_pc~0; 5395#L419-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5190#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5316#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5317#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5080#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5081#L437-1 assume !(1 == ~t4_pc~0); 5429#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 5585#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5618#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5634#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5592#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5490#L456-1 assume 1 == ~t5_pc~0; 5491#L457-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5675#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5640#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4943#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4944#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5504#L475-1 assume 1 == ~t6_pc~0; 4938#L476-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4939#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5047#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5537#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5538#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5589#L494-1 assume 1 == ~t7_pc~0; 5016#L495-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5017#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5539#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5371#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5067#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5068#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 4957#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4958#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5225#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5609#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5350#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5233#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5234#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5479#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 5529#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 5594#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 5595#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 5637#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 5663#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 5664#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 5055#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5056#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4912#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5500#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5501#L1167 assume !(0 == start_simulation_~tmp~3#1); 5159#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5127#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 5128#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5166#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5274#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5372#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4893#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4894#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 5160#L1148 [2024-11-17 08:53:46,072 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,073 INFO L85 PathProgramCache]: Analyzing trace with hash 216111980, now seen corresponding path program 1 times [2024-11-17 08:53:46,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,073 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692496944] [2024-11-17 08:53:46,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,169 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,169 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [692496944] [2024-11-17 08:53:46,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [692496944] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,169 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:46,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1820409539] [2024-11-17 08:53:46,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,170 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:46,170 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,170 INFO L85 PathProgramCache]: Analyzing trace with hash -1501703768, now seen corresponding path program 2 times [2024-11-17 08:53:46,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120414297] [2024-11-17 08:53:46,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,237 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120414297] [2024-11-17 08:53:46,237 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1120414297] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,238 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,239 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:46,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499954086] [2024-11-17 08:53:46,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,239 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:46,239 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:46,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:46,240 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:46,240 INFO L87 Difference]: Start difference. First operand 805 states and 1183 transitions. cyclomatic complexity: 379 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:46,251 INFO L93 Difference]: Finished difference Result 805 states and 1182 transitions. [2024-11-17 08:53:46,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 805 states and 1182 transitions. [2024-11-17 08:53:46,255 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 805 states to 805 states and 1182 transitions. [2024-11-17 08:53:46,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 805 [2024-11-17 08:53:46,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 805 [2024-11-17 08:53:46,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 805 states and 1182 transitions. [2024-11-17 08:53:46,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:46,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 805 states and 1182 transitions. [2024-11-17 08:53:46,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 805 states and 1182 transitions. [2024-11-17 08:53:46,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 805 to 805. [2024-11-17 08:53:46,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 805 states, 805 states have (on average 1.4683229813664596) internal successors, (1182), 804 states have internal predecessors, (1182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 805 states to 805 states and 1182 transitions. [2024-11-17 08:53:46,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 805 states and 1182 transitions. [2024-11-17 08:53:46,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:46,271 INFO L425 stractBuchiCegarLoop]: Abstraction has 805 states and 1182 transitions. [2024-11-17 08:53:46,271 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:53:46,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 805 states and 1182 transitions. [2024-11-17 08:53:46,273 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:46,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:46,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,278 INFO L745 eck$LassoCheckResult]: Stem: 7124#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6547#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6548#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6933#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6934#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 6836#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6837#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7162#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7248#L541 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7160#L546 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7161#L551 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7238#L556 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7099#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7100#L754-1 assume !(0 == ~M_E~0); 7143#L759-1 assume !(0 == ~T1_E~0); 7118#L764-1 assume !(0 == ~T2_E~0); 7084#L769-1 assume !(0 == ~T3_E~0); 7085#L774-1 assume !(0 == ~T4_E~0); 7121#L779-1 assume !(0 == ~T5_E~0); 7240#L784-1 assume !(0 == ~T6_E~0); 7081#L789-1 assume !(0 == ~T7_E~0); 7082#L794-1 assume !(0 == ~E_1~0); 7165#L799-1 assume !(0 == ~E_2~0); 7090#L804-1 assume !(0 == ~E_3~0); 7091#L809-1 assume !(0 == ~E_4~0); 7117#L814-1 assume !(0 == ~E_5~0); 6528#L819-1 assume !(0 == ~E_6~0); 6529#L824-1 assume !(0 == ~E_7~0); 6866#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6874#L361-9 assume 1 == ~m_pc~0; 7266#L362-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6550#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6654#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7077#L930-9 assume !(0 != activate_threads_~tmp~1#1); 7078#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7152#L380-9 assume 1 == ~t1_pc~0; 7150#L381-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7104#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7105#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7106#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 6980#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6981#L399-9 assume 1 == ~t2_pc~0; 7239#L400-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6861#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7126#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7127#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 7241#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7218#L418-9 assume 1 == ~t3_pc~0; 7014#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7006#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7207#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7205#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 6638#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6639#L437-9 assume 1 == ~t4_pc~0; 6718#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6909#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6955#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6956#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 6516#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6517#L456-9 assume 1 == ~t5_pc~0; 6560#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6922#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6923#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6847#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 6848#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6616#L475-9 assume 1 == ~t6_pc~0; 6617#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6838#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6954#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6806#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 6807#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6607#L494-9 assume 1 == ~t7_pc~0; 6608#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6784#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7001#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6764#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 6765#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7087#L837-1 assume !(1 == ~M_E~0); 7166#L842-1 assume !(1 == ~T1_E~0); 6929#L847-1 assume !(1 == ~T2_E~0); 6930#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7002#L857-1 assume !(1 == ~T4_E~0); 6884#L862-1 assume !(1 == ~T5_E~0); 6885#L867-1 assume !(1 == ~T6_E~0); 6894#L872-1 assume !(1 == ~T7_E~0); 6958#L877-1 assume !(1 == ~E_1~0); 7129#L882-1 assume !(1 == ~E_2~0); 7263#L887-1 assume !(1 == ~E_3~0); 7187#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7188#L897-1 assume !(1 == ~E_5~0); 6907#L902-1 assume !(1 == ~E_6~0); 6908#L907-1 assume !(1 == ~E_7~0); 7173#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 6779#L1148 [2024-11-17 08:53:46,278 INFO L747 eck$LassoCheckResult]: Loop: 6779#L1148 assume true; 7154#L1148-1 assume !false; 7209#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6579#L621 assume true; 6580#L621-1 assume !false; 6742#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6743#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6757#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7279#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6800#L626 assume !(0 != eval_~tmp~0#1); 6802#L629 assume true; 6940#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7184#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7185#L754 assume !(0 == ~M_E~0); 7052#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7053#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7271#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6829#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6830#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7023#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6962#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6839#L794 assume !(0 == ~E_1~0); 6840#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 7012#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 6867#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 6868#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 7062#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 7063#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 7254#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7229#L361-1 assume !(1 == ~m_pc~0); 6716#L371-1 is_master_triggered_~__retres1~0#1 := 0; 6717#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6727#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6728#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7257#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7293#L380-1 assume 1 == ~t1_pc~0; 6999#L381-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6842#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6904#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7102#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7172#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7234#L399-1 assume 1 == ~t2_pc~0; 6797#L400-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6798#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7050#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6978#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6979#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7022#L418-1 assume 1 == ~t3_pc~0; 7013#L419-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6809#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6935#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6936#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6699#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6700#L437-1 assume !(1 == ~t4_pc~0); 7048#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 7204#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7237#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7253#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7211#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7109#L456-1 assume 1 == ~t5_pc~0; 7110#L457-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7294#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7259#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6562#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6563#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7123#L475-1 assume 1 == ~t6_pc~0; 6557#L476-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6558#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6666#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7156#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7157#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7208#L494-1 assume 1 == ~t7_pc~0; 6635#L495-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6636#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7158#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6988#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6683#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6684#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 6576#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6577#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6844#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7227#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6969#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6852#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6853#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7098#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 7148#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 7212#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 7213#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 7256#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 7282#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 7283#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 6674#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6675#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6531#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7119#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7120#L1167 assume !(0 == start_simulation_~tmp~3#1); 6775#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6746#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6747#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6785#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 6893#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6991#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6512#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 6513#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 6779#L1148 [2024-11-17 08:53:46,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,279 INFO L85 PathProgramCache]: Analyzing trace with hash -952084275, now seen corresponding path program 1 times [2024-11-17 08:53:46,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284911380] [2024-11-17 08:53:46,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,309 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284911380] [2024-11-17 08:53:46,310 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284911380] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,310 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,310 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:46,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [363223173] [2024-11-17 08:53:46,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,310 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:46,311 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,311 INFO L85 PathProgramCache]: Analyzing trace with hash -1501703768, now seen corresponding path program 3 times [2024-11-17 08:53:46,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,311 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169153980] [2024-11-17 08:53:46,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,368 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169153980] [2024-11-17 08:53:46,368 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169153980] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,368 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,368 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:46,369 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1241646738] [2024-11-17 08:53:46,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,369 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:46,369 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:46,370 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:46,370 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:46,370 INFO L87 Difference]: Start difference. First operand 805 states and 1182 transitions. cyclomatic complexity: 378 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:46,381 INFO L93 Difference]: Finished difference Result 805 states and 1181 transitions. [2024-11-17 08:53:46,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 805 states and 1181 transitions. [2024-11-17 08:53:46,384 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 805 states to 805 states and 1181 transitions. [2024-11-17 08:53:46,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 805 [2024-11-17 08:53:46,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 805 [2024-11-17 08:53:46,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 805 states and 1181 transitions. [2024-11-17 08:53:46,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:46,388 INFO L218 hiAutomatonCegarLoop]: Abstraction has 805 states and 1181 transitions. [2024-11-17 08:53:46,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 805 states and 1181 transitions. [2024-11-17 08:53:46,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 805 to 805. [2024-11-17 08:53:46,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 805 states, 805 states have (on average 1.4670807453416148) internal successors, (1181), 804 states have internal predecessors, (1181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 805 states to 805 states and 1181 transitions. [2024-11-17 08:53:46,397 INFO L240 hiAutomatonCegarLoop]: Abstraction has 805 states and 1181 transitions. [2024-11-17 08:53:46,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:46,398 INFO L425 stractBuchiCegarLoop]: Abstraction has 805 states and 1181 transitions. [2024-11-17 08:53:46,398 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:53:46,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 805 states and 1181 transitions. [2024-11-17 08:53:46,401 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:46,401 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:46,402 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,402 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,402 INFO L745 eck$LassoCheckResult]: Stem: 8743#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8166#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8167#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8551#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8552#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 8455#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8456#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8781#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8867#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8779#L546 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8780#L551 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8857#L556 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8718#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8719#L754-1 assume !(0 == ~M_E~0); 8762#L759-1 assume !(0 == ~T1_E~0); 8737#L764-1 assume !(0 == ~T2_E~0); 8703#L769-1 assume !(0 == ~T3_E~0); 8704#L774-1 assume !(0 == ~T4_E~0); 8738#L779-1 assume !(0 == ~T5_E~0); 8859#L784-1 assume !(0 == ~T6_E~0); 8700#L789-1 assume !(0 == ~T7_E~0); 8701#L794-1 assume !(0 == ~E_1~0); 8784#L799-1 assume !(0 == ~E_2~0); 8709#L804-1 assume !(0 == ~E_3~0); 8710#L809-1 assume !(0 == ~E_4~0); 8736#L814-1 assume !(0 == ~E_5~0); 8147#L819-1 assume !(0 == ~E_6~0); 8148#L824-1 assume !(0 == ~E_7~0); 8485#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8491#L361-9 assume 1 == ~m_pc~0; 8885#L362-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8169#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8273#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8696#L930-9 assume !(0 != activate_threads_~tmp~1#1); 8697#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8771#L380-9 assume 1 == ~t1_pc~0; 8768#L381-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8723#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8724#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8725#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 8599#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8600#L399-9 assume 1 == ~t2_pc~0; 8858#L400-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8480#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8745#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8746#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 8860#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8837#L418-9 assume 1 == ~t3_pc~0; 8632#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8625#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8826#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8824#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 8257#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8258#L437-9 assume 1 == ~t4_pc~0; 8337#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8528#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8574#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8575#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 8135#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8136#L456-9 assume 1 == ~t5_pc~0; 8179#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8541#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8542#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8466#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 8467#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8235#L475-9 assume 1 == ~t6_pc~0; 8236#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8457#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8573#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8425#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 8426#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8224#L494-9 assume 1 == ~t7_pc~0; 8225#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8403#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8620#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8383#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 8384#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8706#L837-1 assume !(1 == ~M_E~0); 8785#L842-1 assume !(1 == ~T1_E~0); 8548#L847-1 assume !(1 == ~T2_E~0); 8549#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8621#L857-1 assume !(1 == ~T4_E~0); 8501#L862-1 assume !(1 == ~T5_E~0); 8502#L867-1 assume !(1 == ~T6_E~0); 8513#L872-1 assume !(1 == ~T7_E~0); 8577#L877-1 assume !(1 == ~E_1~0); 8748#L882-1 assume !(1 == ~E_2~0); 8882#L887-1 assume !(1 == ~E_3~0); 8806#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8807#L897-1 assume !(1 == ~E_5~0); 8526#L902-1 assume !(1 == ~E_6~0); 8527#L907-1 assume !(1 == ~E_7~0); 8792#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 8398#L1148 [2024-11-17 08:53:46,402 INFO L747 eck$LassoCheckResult]: Loop: 8398#L1148 assume true; 8773#L1148-1 assume !false; 8828#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8198#L621 assume true; 8199#L621-1 assume !false; 8361#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8362#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8376#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8898#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8419#L626 assume !(0 != eval_~tmp~0#1); 8421#L629 assume true; 8559#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8803#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8804#L754 assume !(0 == ~M_E~0); 8671#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8672#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8890#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8448#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8449#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8642#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8578#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8458#L794 assume !(0 == ~E_1~0); 8459#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 8631#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 8486#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 8487#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 8681#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 8682#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 8873#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8848#L361-1 assume 1 == ~m_pc~0; 8849#L362-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8336#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8346#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8347#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8876#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8912#L380-1 assume 1 == ~t1_pc~0; 8618#L381-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8461#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8523#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8721#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8791#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8853#L399-1 assume 1 == ~t2_pc~0; 8416#L400-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8417#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8669#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8597#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8598#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8641#L418-1 assume 1 == ~t3_pc~0; 8633#L419-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8428#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8554#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8555#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8318#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8319#L437-1 assume !(1 == ~t4_pc~0); 8667#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 8823#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8856#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8872#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8830#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8728#L456-1 assume 1 == ~t5_pc~0; 8729#L457-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8913#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8878#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8181#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8182#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8742#L475-1 assume 1 == ~t6_pc~0; 8176#L476-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8177#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8285#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8775#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8776#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8827#L494-1 assume !(1 == ~t7_pc~0); 8256#L504-1 is_transmit7_triggered_~__retres1~7#1 := 0; 8255#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8777#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8609#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8305#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8306#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 8195#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8196#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8463#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8847#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8588#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8471#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8472#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8717#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 8767#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 8832#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 8833#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 8875#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 8901#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 8902#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 8293#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8294#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8150#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8739#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8740#L1167 assume !(0 == start_simulation_~tmp~3#1); 8397#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8365#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8366#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8404#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8512#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8610#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8131#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8132#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 8398#L1148 [2024-11-17 08:53:46,403 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,403 INFO L85 PathProgramCache]: Analyzing trace with hash 257157964, now seen corresponding path program 1 times [2024-11-17 08:53:46,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,403 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [271035768] [2024-11-17 08:53:46,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,431 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [271035768] [2024-11-17 08:53:46,433 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [271035768] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,435 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,435 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:46,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3647483] [2024-11-17 08:53:46,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,435 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:46,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,436 INFO L85 PathProgramCache]: Analyzing trace with hash 221464040, now seen corresponding path program 1 times [2024-11-17 08:53:46,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [219945432] [2024-11-17 08:53:46,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,488 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,488 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [219945432] [2024-11-17 08:53:46,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [219945432] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:46,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920817990] [2024-11-17 08:53:46,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,489 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:46,489 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:46,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:46,490 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:46,490 INFO L87 Difference]: Start difference. First operand 805 states and 1181 transitions. cyclomatic complexity: 377 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:46,501 INFO L93 Difference]: Finished difference Result 805 states and 1180 transitions. [2024-11-17 08:53:46,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 805 states and 1180 transitions. [2024-11-17 08:53:46,504 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 805 states to 805 states and 1180 transitions. [2024-11-17 08:53:46,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 805 [2024-11-17 08:53:46,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 805 [2024-11-17 08:53:46,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 805 states and 1180 transitions. [2024-11-17 08:53:46,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:46,508 INFO L218 hiAutomatonCegarLoop]: Abstraction has 805 states and 1180 transitions. [2024-11-17 08:53:46,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 805 states and 1180 transitions. [2024-11-17 08:53:46,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 805 to 805. [2024-11-17 08:53:46,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 805 states, 805 states have (on average 1.4658385093167703) internal successors, (1180), 804 states have internal predecessors, (1180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 805 states to 805 states and 1180 transitions. [2024-11-17 08:53:46,517 INFO L240 hiAutomatonCegarLoop]: Abstraction has 805 states and 1180 transitions. [2024-11-17 08:53:46,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:46,520 INFO L425 stractBuchiCegarLoop]: Abstraction has 805 states and 1180 transitions. [2024-11-17 08:53:46,520 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:53:46,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 805 states and 1180 transitions. [2024-11-17 08:53:46,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:46,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:46,524 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,524 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,524 INFO L745 eck$LassoCheckResult]: Stem: 10362#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 9785#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9786#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10170#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10171#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 10074#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10075#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10400#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10486#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10398#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10399#L551 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10476#L556 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10337#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10338#L754-1 assume !(0 == ~M_E~0); 10381#L759-1 assume !(0 == ~T1_E~0); 10356#L764-1 assume !(0 == ~T2_E~0); 10322#L769-1 assume !(0 == ~T3_E~0); 10323#L774-1 assume !(0 == ~T4_E~0); 10357#L779-1 assume !(0 == ~T5_E~0); 10478#L784-1 assume !(0 == ~T6_E~0); 10319#L789-1 assume !(0 == ~T7_E~0); 10320#L794-1 assume !(0 == ~E_1~0); 10403#L799-1 assume !(0 == ~E_2~0); 10328#L804-1 assume !(0 == ~E_3~0); 10329#L809-1 assume !(0 == ~E_4~0); 10355#L814-1 assume !(0 == ~E_5~0); 9766#L819-1 assume !(0 == ~E_6~0); 9767#L824-1 assume !(0 == ~E_7~0); 10104#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10110#L361-9 assume 1 == ~m_pc~0; 10504#L362-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9788#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9892#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10315#L930-9 assume !(0 != activate_threads_~tmp~1#1); 10316#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10390#L380-9 assume 1 == ~t1_pc~0; 10387#L381-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10342#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10343#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10344#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 10218#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10219#L399-9 assume 1 == ~t2_pc~0; 10477#L400-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10099#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10364#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10365#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 10479#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10456#L418-9 assume 1 == ~t3_pc~0; 10251#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10244#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10445#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10443#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 9876#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9877#L437-9 assume 1 == ~t4_pc~0; 9956#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10147#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10193#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10194#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 9754#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9755#L456-9 assume 1 == ~t5_pc~0; 9798#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10160#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10161#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10085#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 10086#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9854#L475-9 assume 1 == ~t6_pc~0; 9855#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10076#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10192#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10044#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 10045#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9843#L494-9 assume 1 == ~t7_pc~0; 9844#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10022#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10239#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10002#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 10003#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10325#L837-1 assume !(1 == ~M_E~0); 10404#L842-1 assume !(1 == ~T1_E~0); 10167#L847-1 assume !(1 == ~T2_E~0); 10168#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10240#L857-1 assume !(1 == ~T4_E~0); 10120#L862-1 assume !(1 == ~T5_E~0); 10121#L867-1 assume !(1 == ~T6_E~0); 10132#L872-1 assume !(1 == ~T7_E~0); 10196#L877-1 assume !(1 == ~E_1~0); 10367#L882-1 assume !(1 == ~E_2~0); 10501#L887-1 assume !(1 == ~E_3~0); 10425#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10426#L897-1 assume !(1 == ~E_5~0); 10145#L902-1 assume !(1 == ~E_6~0); 10146#L907-1 assume !(1 == ~E_7~0); 10411#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 10017#L1148 [2024-11-17 08:53:46,524 INFO L747 eck$LassoCheckResult]: Loop: 10017#L1148 assume true; 10392#L1148-1 assume !false; 10447#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9817#L621 assume true; 9818#L621-1 assume !false; 9980#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9981#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9995#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10517#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10038#L626 assume !(0 != eval_~tmp~0#1); 10040#L629 assume true; 10178#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10422#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10423#L754 assume !(0 == ~M_E~0); 10290#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10291#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10509#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10067#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10068#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10261#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10197#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10077#L794 assume !(0 == ~E_1~0); 10078#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 10250#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 10105#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 10106#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 10300#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 10301#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 10492#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10467#L361-1 assume !(1 == ~m_pc~0); 9954#L371-1 is_master_triggered_~__retres1~0#1 := 0; 9955#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9965#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9966#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10495#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10531#L380-1 assume 1 == ~t1_pc~0; 10237#L381-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10080#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10142#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10340#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10410#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10472#L399-1 assume 1 == ~t2_pc~0; 10035#L400-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10036#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10288#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10216#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10217#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10260#L418-1 assume 1 == ~t3_pc~0; 10252#L419-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10047#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10173#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10174#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9937#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9938#L437-1 assume !(1 == ~t4_pc~0); 10286#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 10442#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10475#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10491#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10449#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10347#L456-1 assume 1 == ~t5_pc~0; 10348#L457-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10532#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10497#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9800#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9801#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10361#L475-1 assume 1 == ~t6_pc~0; 9795#L476-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9796#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9904#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10394#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10395#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10446#L494-1 assume 1 == ~t7_pc~0; 9873#L495-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9874#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10396#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10228#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9924#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9925#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 9814#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9815#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10082#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10466#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10207#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10090#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10091#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10336#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 10386#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 10451#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 10452#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 10494#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 10520#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 10521#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 9912#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9913#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9769#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10358#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10359#L1167 assume !(0 == start_simulation_~tmp~3#1); 10016#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9984#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9985#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10023#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10131#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10229#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9750#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 9751#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 10017#L1148 [2024-11-17 08:53:46,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,525 INFO L85 PathProgramCache]: Analyzing trace with hash -950760211, now seen corresponding path program 1 times [2024-11-17 08:53:46,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387143317] [2024-11-17 08:53:46,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,548 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,548 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387143317] [2024-11-17 08:53:46,548 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387143317] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,548 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,548 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:46,548 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [88936367] [2024-11-17 08:53:46,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,549 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:46,549 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,549 INFO L85 PathProgramCache]: Analyzing trace with hash -1501703768, now seen corresponding path program 4 times [2024-11-17 08:53:46,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920500171] [2024-11-17 08:53:46,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,605 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,606 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,606 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920500171] [2024-11-17 08:53:46,606 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920500171] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,606 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:46,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1253097936] [2024-11-17 08:53:46,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,607 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:46,607 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:46,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:46,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:46,607 INFO L87 Difference]: Start difference. First operand 805 states and 1180 transitions. cyclomatic complexity: 376 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:46,619 INFO L93 Difference]: Finished difference Result 805 states and 1179 transitions. [2024-11-17 08:53:46,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 805 states and 1179 transitions. [2024-11-17 08:53:46,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,625 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 805 states to 805 states and 1179 transitions. [2024-11-17 08:53:46,625 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 805 [2024-11-17 08:53:46,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 805 [2024-11-17 08:53:46,626 INFO L73 IsDeterministic]: Start isDeterministic. Operand 805 states and 1179 transitions. [2024-11-17 08:53:46,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:46,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 805 states and 1179 transitions. [2024-11-17 08:53:46,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 805 states and 1179 transitions. [2024-11-17 08:53:46,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 805 to 805. [2024-11-17 08:53:46,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 805 states, 805 states have (on average 1.4645962732919255) internal successors, (1179), 804 states have internal predecessors, (1179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 805 states to 805 states and 1179 transitions. [2024-11-17 08:53:46,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 805 states and 1179 transitions. [2024-11-17 08:53:46,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:46,639 INFO L425 stractBuchiCegarLoop]: Abstraction has 805 states and 1179 transitions. [2024-11-17 08:53:46,639 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:53:46,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 805 states and 1179 transitions. [2024-11-17 08:53:46,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:46,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:46,642 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,642 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,642 INFO L745 eck$LassoCheckResult]: Stem: 11981#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11404#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11405#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11789#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11790#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 11693#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11694#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12019#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12105#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12017#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12018#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12095#L556 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11956#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11957#L754-1 assume !(0 == ~M_E~0); 12000#L759-1 assume !(0 == ~T1_E~0); 11975#L764-1 assume !(0 == ~T2_E~0); 11941#L769-1 assume !(0 == ~T3_E~0); 11942#L774-1 assume !(0 == ~T4_E~0); 11976#L779-1 assume !(0 == ~T5_E~0); 12097#L784-1 assume !(0 == ~T6_E~0); 11938#L789-1 assume !(0 == ~T7_E~0); 11939#L794-1 assume !(0 == ~E_1~0); 12022#L799-1 assume !(0 == ~E_2~0); 11947#L804-1 assume !(0 == ~E_3~0); 11948#L809-1 assume !(0 == ~E_4~0); 11974#L814-1 assume !(0 == ~E_5~0); 11385#L819-1 assume !(0 == ~E_6~0); 11386#L824-1 assume !(0 == ~E_7~0); 11723#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11729#L361-9 assume 1 == ~m_pc~0; 12123#L362-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11407#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11511#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11934#L930-9 assume !(0 != activate_threads_~tmp~1#1); 11935#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12009#L380-9 assume 1 == ~t1_pc~0; 12006#L381-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11961#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11962#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11963#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 11837#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11838#L399-9 assume 1 == ~t2_pc~0; 12096#L400-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11718#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11983#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11984#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 12098#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12075#L418-9 assume 1 == ~t3_pc~0; 11870#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11863#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12064#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12062#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 11495#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11496#L437-9 assume 1 == ~t4_pc~0; 11575#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11766#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11812#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11813#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 11373#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11374#L456-9 assume 1 == ~t5_pc~0; 11417#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11779#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11780#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11704#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 11705#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11473#L475-9 assume 1 == ~t6_pc~0; 11474#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11695#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11811#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11663#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 11664#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11462#L494-9 assume 1 == ~t7_pc~0; 11463#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11641#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11858#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11621#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 11622#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11944#L837-1 assume !(1 == ~M_E~0); 12023#L842-1 assume !(1 == ~T1_E~0); 11786#L847-1 assume !(1 == ~T2_E~0); 11787#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11859#L857-1 assume !(1 == ~T4_E~0); 11739#L862-1 assume !(1 == ~T5_E~0); 11740#L867-1 assume !(1 == ~T6_E~0); 11751#L872-1 assume !(1 == ~T7_E~0); 11815#L877-1 assume !(1 == ~E_1~0); 11986#L882-1 assume !(1 == ~E_2~0); 12120#L887-1 assume !(1 == ~E_3~0); 12044#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 12045#L897-1 assume !(1 == ~E_5~0); 11764#L902-1 assume !(1 == ~E_6~0); 11765#L907-1 assume !(1 == ~E_7~0); 12030#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 11636#L1148 [2024-11-17 08:53:46,643 INFO L747 eck$LassoCheckResult]: Loop: 11636#L1148 assume true; 12011#L1148-1 assume !false; 12066#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11436#L621 assume true; 11437#L621-1 assume !false; 11599#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11600#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11614#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 12136#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11657#L626 assume !(0 != eval_~tmp~0#1); 11659#L629 assume true; 11797#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12041#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12042#L754 assume !(0 == ~M_E~0); 11909#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11910#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12128#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11686#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11687#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11880#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11816#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11696#L794 assume !(0 == ~E_1~0); 11697#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 11869#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 11724#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 11725#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 11919#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 11920#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 12111#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12086#L361-1 assume !(1 == ~m_pc~0); 11573#L371-1 is_master_triggered_~__retres1~0#1 := 0; 11574#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11584#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11585#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12114#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12150#L380-1 assume 1 == ~t1_pc~0; 11856#L381-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11699#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11761#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11959#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12029#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12091#L399-1 assume 1 == ~t2_pc~0; 11654#L400-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11655#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11907#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11835#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11836#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11879#L418-1 assume !(1 == ~t3_pc~0); 11665#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 11666#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11792#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11793#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11556#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11557#L437-1 assume !(1 == ~t4_pc~0); 11905#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 12061#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12094#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12110#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12068#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11966#L456-1 assume !(1 == ~t5_pc~0); 11968#L466-1 is_transmit5_triggered_~__retres1~5#1 := 0; 12151#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12116#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11419#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11420#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11980#L475-1 assume 1 == ~t6_pc~0; 11414#L476-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11415#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11523#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12013#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12014#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12065#L494-1 assume 1 == ~t7_pc~0; 11492#L495-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11493#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12015#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11847#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11543#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11544#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 11433#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11434#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11701#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12085#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11826#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11709#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11710#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11955#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 12005#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 12070#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 12071#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 12113#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 12139#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 12140#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 11531#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11532#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11388#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11977#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11978#L1167 assume !(0 == start_simulation_~tmp~3#1); 11635#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11603#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11604#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11642#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 11750#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11848#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11369#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 11370#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 11636#L1148 [2024-11-17 08:53:46,643 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,643 INFO L85 PathProgramCache]: Analyzing trace with hash 534295340, now seen corresponding path program 1 times [2024-11-17 08:53:46,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,644 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [713297379] [2024-11-17 08:53:46,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [713297379] [2024-11-17 08:53:46,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [713297379] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:46,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122373001] [2024-11-17 08:53:46,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,675 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:46,675 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,675 INFO L85 PathProgramCache]: Analyzing trace with hash 1819860834, now seen corresponding path program 1 times [2024-11-17 08:53:46,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842790113] [2024-11-17 08:53:46,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,714 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,715 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1842790113] [2024-11-17 08:53:46,715 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1842790113] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,715 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,715 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:46,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264643840] [2024-11-17 08:53:46,715 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,716 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:46,716 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:46,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:46,716 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:46,716 INFO L87 Difference]: Start difference. First operand 805 states and 1179 transitions. cyclomatic complexity: 375 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:46,727 INFO L93 Difference]: Finished difference Result 805 states and 1178 transitions. [2024-11-17 08:53:46,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 805 states and 1178 transitions. [2024-11-17 08:53:46,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 805 states to 805 states and 1178 transitions. [2024-11-17 08:53:46,732 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 805 [2024-11-17 08:53:46,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 805 [2024-11-17 08:53:46,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 805 states and 1178 transitions. [2024-11-17 08:53:46,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:46,733 INFO L218 hiAutomatonCegarLoop]: Abstraction has 805 states and 1178 transitions. [2024-11-17 08:53:46,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 805 states and 1178 transitions. [2024-11-17 08:53:46,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 805 to 805. [2024-11-17 08:53:46,740 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 805 states, 805 states have (on average 1.4633540372670808) internal successors, (1178), 804 states have internal predecessors, (1178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 805 states to 805 states and 1178 transitions. [2024-11-17 08:53:46,742 INFO L240 hiAutomatonCegarLoop]: Abstraction has 805 states and 1178 transitions. [2024-11-17 08:53:46,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:46,743 INFO L425 stractBuchiCegarLoop]: Abstraction has 805 states and 1178 transitions. [2024-11-17 08:53:46,743 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:53:46,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 805 states and 1178 transitions. [2024-11-17 08:53:46,745 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 704 [2024-11-17 08:53:46,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:46,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:46,746 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,746 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,746 INFO L745 eck$LassoCheckResult]: Stem: 13600#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 13023#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13024#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13409#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13410#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 13312#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13313#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13638#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13724#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13636#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13637#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13714#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13575#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13576#L754-1 assume !(0 == ~M_E~0); 13619#L759-1 assume !(0 == ~T1_E~0); 13594#L764-1 assume !(0 == ~T2_E~0); 13560#L769-1 assume !(0 == ~T3_E~0); 13561#L774-1 assume !(0 == ~T4_E~0); 13597#L779-1 assume !(0 == ~T5_E~0); 13716#L784-1 assume !(0 == ~T6_E~0); 13557#L789-1 assume !(0 == ~T7_E~0); 13558#L794-1 assume !(0 == ~E_1~0); 13641#L799-1 assume !(0 == ~E_2~0); 13566#L804-1 assume !(0 == ~E_3~0); 13567#L809-1 assume !(0 == ~E_4~0); 13593#L814-1 assume !(0 == ~E_5~0); 13004#L819-1 assume !(0 == ~E_6~0); 13005#L824-1 assume !(0 == ~E_7~0); 13342#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13350#L361-9 assume 1 == ~m_pc~0; 13742#L362-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13026#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13133#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13553#L930-9 assume !(0 != activate_threads_~tmp~1#1); 13554#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13628#L380-9 assume 1 == ~t1_pc~0; 13626#L381-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13580#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13581#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13582#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 13456#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13457#L399-9 assume 1 == ~t2_pc~0; 13715#L400-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13337#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13602#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13603#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 13717#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13694#L418-9 assume 1 == ~t3_pc~0; 13490#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13482#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13683#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13681#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 13114#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13115#L437-9 assume 1 == ~t4_pc~0; 13194#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13385#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13431#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13432#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 12995#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12996#L456-9 assume 1 == ~t5_pc~0; 13036#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13398#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13399#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13326#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 13327#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13092#L475-9 assume 1 == ~t6_pc~0; 13093#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13314#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13430#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13282#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 13283#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13083#L494-9 assume 1 == ~t7_pc~0; 13084#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13260#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13477#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13240#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 13241#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13563#L837-1 assume !(1 == ~M_E~0); 13644#L842-1 assume !(1 == ~T1_E~0); 13405#L847-1 assume !(1 == ~T2_E~0); 13406#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13478#L857-1 assume !(1 == ~T4_E~0); 13362#L862-1 assume !(1 == ~T5_E~0); 13363#L867-1 assume !(1 == ~T6_E~0); 13370#L872-1 assume !(1 == ~T7_E~0); 13434#L877-1 assume !(1 == ~E_1~0); 13607#L882-1 assume !(1 == ~E_2~0); 13739#L887-1 assume !(1 == ~E_3~0); 13663#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13664#L897-1 assume !(1 == ~E_5~0); 13383#L902-1 assume !(1 == ~E_6~0); 13384#L907-1 assume !(1 == ~E_7~0); 13649#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 13255#L1148 [2024-11-17 08:53:46,746 INFO L747 eck$LassoCheckResult]: Loop: 13255#L1148 assume true; 13630#L1148-1 assume !false; 13685#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13055#L621 assume true; 13056#L621-1 assume !false; 13218#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13219#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13233#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13755#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13276#L626 assume !(0 != eval_~tmp~0#1); 13278#L629 assume true; 13416#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13660#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13661#L754 assume !(0 == ~M_E~0); 13528#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13529#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13747#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13305#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13306#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13499#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13435#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13315#L794 assume !(0 == ~E_1~0); 13316#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 13488#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 13343#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 13344#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 13538#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 13539#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 13730#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13705#L361-1 assume !(1 == ~m_pc~0); 13192#L371-1 is_master_triggered_~__retres1~0#1 := 0; 13193#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13203#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13204#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13733#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13769#L380-1 assume 1 == ~t1_pc~0; 13475#L381-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13318#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13380#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13578#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13648#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13710#L399-1 assume 1 == ~t2_pc~0; 13273#L400-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13274#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13526#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13454#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13455#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13498#L418-1 assume 1 == ~t3_pc~0; 13489#L419-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13285#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13411#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13412#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13175#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13176#L437-1 assume !(1 == ~t4_pc~0); 13524#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 13680#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13713#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13729#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13687#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13585#L456-1 assume 1 == ~t5_pc~0; 13586#L457-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13770#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13735#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13038#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13039#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13599#L475-1 assume 1 == ~t6_pc~0; 13033#L476-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13034#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13142#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13632#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13633#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13684#L494-1 assume 1 == ~t7_pc~0; 13111#L495-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13112#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13634#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13466#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13162#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13163#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 13052#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13053#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13320#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13704#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13445#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13328#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13329#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13574#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 13624#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 13689#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 13690#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 13732#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 13758#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 13759#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 13150#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13151#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13007#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13595#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 13596#L1167 assume !(0 == start_simulation_~tmp~3#1); 13254#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13222#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13223#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13261#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 13369#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13467#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12988#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 12989#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 13255#L1148 [2024-11-17 08:53:46,747 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,747 INFO L85 PathProgramCache]: Analyzing trace with hash -249083635, now seen corresponding path program 1 times [2024-11-17 08:53:46,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,747 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248252238] [2024-11-17 08:53:46,747 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,778 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,778 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248252238] [2024-11-17 08:53:46,778 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248252238] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,778 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:46,779 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117339265] [2024-11-17 08:53:46,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,779 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:46,779 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,779 INFO L85 PathProgramCache]: Analyzing trace with hash -1501703768, now seen corresponding path program 5 times [2024-11-17 08:53:46,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933131664] [2024-11-17 08:53:46,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,819 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,819 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,819 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [933131664] [2024-11-17 08:53:46,820 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [933131664] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,820 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,820 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:46,820 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330369685] [2024-11-17 08:53:46,820 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,820 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:46,820 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:46,821 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:46,821 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:46,821 INFO L87 Difference]: Start difference. First operand 805 states and 1178 transitions. cyclomatic complexity: 374 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:46,880 INFO L93 Difference]: Finished difference Result 1496 states and 2167 transitions. [2024-11-17 08:53:46,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1496 states and 2167 transitions. [2024-11-17 08:53:46,885 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1394 [2024-11-17 08:53:46,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1496 states to 1496 states and 2167 transitions. [2024-11-17 08:53:46,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1496 [2024-11-17 08:53:46,891 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1496 [2024-11-17 08:53:46,891 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1496 states and 2167 transitions. [2024-11-17 08:53:46,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:46,892 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1496 states and 2167 transitions. [2024-11-17 08:53:46,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1496 states and 2167 transitions. [2024-11-17 08:53:46,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1496 to 1438. [2024-11-17 08:53:46,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1438 states, 1438 states have (on average 1.4513212795549375) internal successors, (2087), 1437 states have internal predecessors, (2087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:46,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1438 states to 1438 states and 2087 transitions. [2024-11-17 08:53:46,909 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1438 states and 2087 transitions. [2024-11-17 08:53:46,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:46,910 INFO L425 stractBuchiCegarLoop]: Abstraction has 1438 states and 2087 transitions. [2024-11-17 08:53:46,910 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:53:46,911 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1438 states and 2087 transitions. [2024-11-17 08:53:46,914 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1336 [2024-11-17 08:53:46,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:46,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:46,915 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,915 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:46,916 INFO L745 eck$LassoCheckResult]: Stem: 15917#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 15333#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15334#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15723#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15724#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 15622#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15623#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15955#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16048#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15953#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15954#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16038#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15892#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15893#L754-1 assume !(0 == ~M_E~0); 15936#L759-1 assume !(0 == ~T1_E~0); 15911#L764-1 assume !(0 == ~T2_E~0); 15876#L769-1 assume !(0 == ~T3_E~0); 15877#L774-1 assume !(0 == ~T4_E~0); 15914#L779-1 assume !(0 == ~T5_E~0); 16040#L784-1 assume !(0 == ~T6_E~0); 15873#L789-1 assume !(0 == ~T7_E~0); 15874#L794-1 assume !(0 == ~E_1~0); 15958#L799-1 assume !(0 == ~E_2~0); 15883#L804-1 assume !(0 == ~E_3~0); 15884#L809-1 assume !(0 == ~E_4~0); 15910#L814-1 assume !(0 == ~E_5~0); 15314#L819-1 assume !(0 == ~E_6~0); 15315#L824-1 assume !(0 == ~E_7~0); 15654#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15663#L361-9 assume !(1 == ~m_pc~0); 15335#L371-9 is_master_triggered_~__retres1~0#1 := 0; 15336#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15443#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15869#L930-9 assume !(0 != activate_threads_~tmp~1#1); 15870#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15945#L380-9 assume 1 == ~t1_pc~0; 15943#L381-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15897#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15898#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15899#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 15770#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15771#L399-9 assume 1 == ~t2_pc~0; 16039#L400-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15649#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15919#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15920#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 16041#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16013#L418-9 assume 1 == ~t3_pc~0; 15804#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15796#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16002#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16000#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 15424#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15425#L437-9 assume 1 == ~t4_pc~0; 15503#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15699#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15745#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15746#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 15305#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15306#L456-9 assume 1 == ~t5_pc~0; 15346#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15712#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15713#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15638#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 15639#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15402#L475-9 assume 1 == ~t6_pc~0; 15403#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15624#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15744#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15593#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 15594#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15393#L494-9 assume 1 == ~t7_pc~0; 15394#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15570#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15791#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15549#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 15550#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15879#L837-1 assume !(1 == ~M_E~0); 15961#L842-1 assume !(1 == ~T1_E~0); 15719#L847-1 assume !(1 == ~T2_E~0); 15720#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15792#L857-1 assume !(1 == ~T4_E~0); 15676#L862-1 assume !(1 == ~T5_E~0); 15677#L867-1 assume !(1 == ~T6_E~0); 15684#L872-1 assume !(1 == ~T7_E~0); 15748#L877-1 assume !(1 == ~E_1~0); 15924#L882-1 assume !(1 == ~E_2~0); 16067#L887-1 assume !(1 == ~E_3~0); 15981#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15982#L897-1 assume !(1 == ~E_5~0); 15697#L902-1 assume !(1 == ~E_6~0); 15698#L907-1 assume !(1 == ~E_7~0); 15966#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 15967#L1148 [2024-11-17 08:53:46,916 INFO L747 eck$LassoCheckResult]: Loop: 15967#L1148 assume true; 16191#L1148-1 assume !false; 16187#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16184#L621 assume true; 16183#L621-1 assume !false; 16182#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16118#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15542#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16082#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15587#L626 assume !(0 != eval_~tmp~0#1); 15589#L629 assume true; 15730#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16019#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16696#L754 assume !(0 == ~M_E~0); 16695#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16694#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16074#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15615#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15616#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15813#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15752#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15625#L794 assume !(0 == ~E_1~0); 15626#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 15802#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 15655#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 15656#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 15853#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 15854#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 16055#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16025#L361-1 assume !(1 == ~m_pc~0); 15501#L371-1 is_master_triggered_~__retres1~0#1 := 0; 15502#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15512#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15513#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16061#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16103#L380-1 assume !(1 == ~t1_pc~0); 15627#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 15628#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15694#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15895#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15965#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16031#L399-1 assume 1 == ~t2_pc~0; 15584#L400-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15585#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15839#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15768#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15769#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15812#L418-1 assume 1 == ~t3_pc~0; 15803#L419-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15596#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15725#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15726#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15488#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15489#L437-1 assume !(1 == ~t4_pc~0); 15837#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 15998#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16034#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16054#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16006#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15902#L456-1 assume !(1 == ~t5_pc~0); 15904#L466-1 is_transmit5_triggered_~__retres1~5#1 := 0; 16104#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16063#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15348#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15349#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15916#L475-1 assume !(1 == ~t6_pc~0); 15345#L485-1 is_transmit6_triggered_~__retres1~6#1 := 0; 15344#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15452#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15949#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15950#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16003#L494-1 assume 1 == ~t7_pc~0; 15421#L495-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15422#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15951#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15778#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15469#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15470#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 15362#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15363#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15630#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16022#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15759#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15640#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15641#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15891#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 15941#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 16007#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 16008#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 16059#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 16087#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 16088#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 15460#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 15461#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 15317#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 15912#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 15913#L1167 assume !(0 == start_simulation_~tmp~3#1); 16099#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16206#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16203#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16201#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 16199#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16197#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16195#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16193#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 15967#L1148 [2024-11-17 08:53:46,916 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,916 INFO L85 PathProgramCache]: Analyzing trace with hash -2006367126, now seen corresponding path program 1 times [2024-11-17 08:53:46,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981163339] [2024-11-17 08:53:46,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:46,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:46,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:46,949 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981163339] [2024-11-17 08:53:46,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981163339] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:46,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:46,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:46,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427658797] [2024-11-17 08:53:46,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:46,950 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:46,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:46,951 INFO L85 PathProgramCache]: Analyzing trace with hash 1175264831, now seen corresponding path program 1 times [2024-11-17 08:53:46,951 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:46,951 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55702957] [2024-11-17 08:53:46,951 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:46,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:46,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:47,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:47,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:47,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55702957] [2024-11-17 08:53:47,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55702957] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:47,012 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:47,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:47,012 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [502581973] [2024-11-17 08:53:47,012 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:47,013 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:47,013 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:47,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:47,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:47,013 INFO L87 Difference]: Start difference. First operand 1438 states and 2087 transitions. cyclomatic complexity: 651 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:47,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:47,078 INFO L93 Difference]: Finished difference Result 2641 states and 3807 transitions. [2024-11-17 08:53:47,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2641 states and 3807 transitions. [2024-11-17 08:53:47,092 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2534 [2024-11-17 08:53:47,102 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2641 states to 2641 states and 3807 transitions. [2024-11-17 08:53:47,103 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2641 [2024-11-17 08:53:47,104 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2641 [2024-11-17 08:53:47,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2641 states and 3807 transitions. [2024-11-17 08:53:47,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:47,107 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2641 states and 3807 transitions. [2024-11-17 08:53:47,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2641 states and 3807 transitions. [2024-11-17 08:53:47,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2641 to 2633. [2024-11-17 08:53:47,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2633 states, 2633 states have (on average 1.4428408659323966) internal successors, (3799), 2632 states have internal predecessors, (3799), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:47,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2633 states to 2633 states and 3799 transitions. [2024-11-17 08:53:47,144 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2633 states and 3799 transitions. [2024-11-17 08:53:47,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:47,145 INFO L425 stractBuchiCegarLoop]: Abstraction has 2633 states and 3799 transitions. [2024-11-17 08:53:47,145 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:53:47,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2633 states and 3799 transitions. [2024-11-17 08:53:47,151 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2526 [2024-11-17 08:53:47,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:47,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:47,153 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,153 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,153 INFO L745 eck$LassoCheckResult]: Stem: 20009#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 19421#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 19422#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19811#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19812#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 19709#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19710#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20051#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20146#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20049#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20050#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20134#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19984#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19985#L754-1 assume !(0 == ~M_E~0); 20030#L759-1 assume !(0 == ~T1_E~0); 20003#L764-1 assume !(0 == ~T2_E~0); 19969#L769-1 assume !(0 == ~T3_E~0); 19970#L774-1 assume !(0 == ~T4_E~0); 20004#L779-1 assume !(0 == ~T5_E~0); 20136#L784-1 assume !(0 == ~T6_E~0); 19966#L789-1 assume !(0 == ~T7_E~0); 19967#L794-1 assume !(0 == ~E_1~0); 20054#L799-1 assume !(0 == ~E_2~0); 19975#L804-1 assume !(0 == ~E_3~0); 19976#L809-1 assume !(0 == ~E_4~0); 20002#L814-1 assume !(0 == ~E_5~0); 19402#L819-1 assume !(0 == ~E_6~0); 19403#L824-1 assume !(0 == ~E_7~0); 19743#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19750#L361-9 assume !(1 == ~m_pc~0); 19423#L371-9 is_master_triggered_~__retres1~0#1 := 0; 19424#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19527#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19962#L930-9 assume !(0 != activate_threads_~tmp~1#1); 19963#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20040#L380-9 assume !(1 == ~t1_pc~0); 20041#L390-9 is_transmit1_triggered_~__retres1~1#1 := 0; 19989#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19990#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19991#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 19860#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19861#L399-9 assume 1 == ~t2_pc~0; 20135#L400-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19738#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20011#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20012#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 20137#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20111#L418-9 assume 1 == ~t3_pc~0; 19895#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19888#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20101#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20099#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 19511#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19512#L437-9 assume 1 == ~t4_pc~0; 19591#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19788#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19835#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19836#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 19390#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19391#L456-9 assume 1 == ~t5_pc~0; 19434#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19801#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19802#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19724#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 19725#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19489#L475-9 assume 1 == ~t6_pc~0; 19490#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19711#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19834#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19679#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 19680#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19478#L494-9 assume 1 == ~t7_pc~0; 19479#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19658#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19883#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19638#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 19639#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19972#L837-1 assume !(1 == ~M_E~0); 20055#L842-1 assume !(1 == ~T1_E~0); 19808#L847-1 assume !(1 == ~T2_E~0); 19809#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19884#L857-1 assume !(1 == ~T4_E~0); 19761#L862-1 assume !(1 == ~T5_E~0); 19762#L867-1 assume !(1 == ~T6_E~0); 19773#L872-1 assume !(1 == ~T7_E~0); 19838#L877-1 assume !(1 == ~E_1~0); 20014#L882-1 assume !(1 == ~E_2~0); 20161#L887-1 assume !(1 == ~E_3~0); 20081#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 20082#L897-1 assume !(1 == ~E_5~0); 19786#L902-1 assume !(1 == ~E_6~0); 19787#L907-1 assume !(1 == ~E_7~0); 20063#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 20064#L1148 [2024-11-17 08:53:47,154 INFO L747 eck$LassoCheckResult]: Loop: 20064#L1148 assume true; 20795#L1148-1 assume !false; 20791#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20788#L621 assume true; 20786#L621-1 assume !false; 20784#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20293#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20289#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20287#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20284#L626 assume !(0 != eval_~tmp~0#1); 20285#L629 assume true; 20998#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20996#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20994#L754 assume !(0 == ~M_E~0); 20992#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20990#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20987#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20983#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20979#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20978#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20977#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20976#L794 assume !(0 == ~E_1~0); 20975#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 20974#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 20973#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 20972#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 20971#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 20970#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 20969#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20968#L361-1 assume !(1 == ~m_pc~0); 20967#L371-1 is_master_triggered_~__retres1~0#1 := 0; 20966#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20965#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20964#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20963#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20962#L380-1 assume !(1 == ~t1_pc~0); 20961#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 20959#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20957#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20955#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20953#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20951#L399-1 assume !(1 == ~t2_pc~0); 20948#L409-1 is_transmit2_triggered_~__retres1~2#1 := 0; 20946#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20944#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20942#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 20940#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20938#L418-1 assume !(1 == ~t3_pc~0); 20935#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 20933#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20930#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20928#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20926#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20924#L437-1 assume !(1 == ~t4_pc~0); 20921#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 20919#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20916#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20914#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20912#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20910#L456-1 assume 1 == ~t5_pc~0; 20907#L457-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20905#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20902#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20900#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20898#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20896#L475-1 assume !(1 == ~t6_pc~0); 20893#L485-1 is_transmit6_triggered_~__retres1~6#1 := 0; 20891#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20888#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20886#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20884#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20882#L494-1 assume 1 == ~t7_pc~0; 20880#L495-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20877#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20874#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20872#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20870#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20868#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 20866#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20864#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20861#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20859#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20857#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20855#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20853#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20851#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 20849#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 20847#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 20845#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 20843#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 20841#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 20839#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 20837#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20829#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20823#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20821#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 20817#L1167 assume !(0 == start_simulation_~tmp~3#1); 20816#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20810#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20807#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20805#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 20803#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20801#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20799#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 20797#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 20064#L1148 [2024-11-17 08:53:47,154 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:47,154 INFO L85 PathProgramCache]: Analyzing trace with hash -902936185, now seen corresponding path program 1 times [2024-11-17 08:53:47,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:47,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114275754] [2024-11-17 08:53:47,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:47,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:47,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:47,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:47,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:47,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114275754] [2024-11-17 08:53:47,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2114275754] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:47,190 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:47,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:47,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737962253] [2024-11-17 08:53:47,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:47,191 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:47,191 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:47,191 INFO L85 PathProgramCache]: Analyzing trace with hash -1696721380, now seen corresponding path program 1 times [2024-11-17 08:53:47,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:47,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610647154] [2024-11-17 08:53:47,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:47,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:47,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:47,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:47,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:47,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610647154] [2024-11-17 08:53:47,232 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [610647154] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:47,233 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:47,233 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:47,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [418564142] [2024-11-17 08:53:47,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:47,233 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:47,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:47,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:47,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:47,234 INFO L87 Difference]: Start difference. First operand 2633 states and 3799 transitions. cyclomatic complexity: 1170 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:47,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:47,296 INFO L93 Difference]: Finished difference Result 4902 states and 7034 transitions. [2024-11-17 08:53:47,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4902 states and 7034 transitions. [2024-11-17 08:53:47,311 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4780 [2024-11-17 08:53:47,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4902 states to 4902 states and 7034 transitions. [2024-11-17 08:53:47,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4902 [2024-11-17 08:53:47,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4902 [2024-11-17 08:53:47,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4902 states and 7034 transitions. [2024-11-17 08:53:47,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:47,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4902 states and 7034 transitions. [2024-11-17 08:53:47,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4902 states and 7034 transitions. [2024-11-17 08:53:47,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4902 to 4886. [2024-11-17 08:53:47,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4886 states, 4886 states have (on average 1.436348751534998) internal successors, (7018), 4885 states have internal predecessors, (7018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:47,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4886 states to 4886 states and 7018 transitions. [2024-11-17 08:53:47,391 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4886 states and 7018 transitions. [2024-11-17 08:53:47,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:47,392 INFO L425 stractBuchiCegarLoop]: Abstraction has 4886 states and 7018 transitions. [2024-11-17 08:53:47,392 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:53:47,392 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4886 states and 7018 transitions. [2024-11-17 08:53:47,401 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4764 [2024-11-17 08:53:47,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:47,401 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:47,402 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,402 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,403 INFO L745 eck$LassoCheckResult]: Stem: 27567#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 26965#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 26966#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27361#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27362#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 27256#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27257#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27613#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27714#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27611#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27612#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27701#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27542#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27543#L754-1 assume !(0 == ~M_E~0); 27590#L759-1 assume !(0 == ~T1_E~0); 27561#L764-1 assume !(0 == ~T2_E~0); 27525#L769-1 assume !(0 == ~T3_E~0); 27526#L774-1 assume !(0 == ~T4_E~0); 27564#L779-1 assume !(0 == ~T5_E~0); 27702#L784-1 assume !(0 == ~T6_E~0); 27522#L789-1 assume !(0 == ~T7_E~0); 27523#L794-1 assume !(0 == ~E_1~0); 27616#L799-1 assume !(0 == ~E_2~0); 27532#L804-1 assume !(0 == ~E_3~0); 27533#L809-1 assume !(0 == ~E_4~0); 27560#L814-1 assume !(0 == ~E_5~0); 26946#L819-1 assume !(0 == ~E_6~0); 26947#L824-1 assume !(0 == ~E_7~0); 27290#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27299#L361-9 assume !(1 == ~m_pc~0); 26967#L371-9 is_master_triggered_~__retres1~0#1 := 0; 26968#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27076#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27518#L930-9 assume !(0 != activate_threads_~tmp~1#1); 27519#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27600#L380-9 assume !(1 == ~t1_pc~0); 27601#L390-9 is_transmit1_triggered_~__retres1~1#1 := 0; 27547#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27548#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27549#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 27412#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27413#L399-9 assume !(1 == ~t2_pc~0); 27280#L409-9 is_transmit2_triggered_~__retres1~2#1 := 0; 27281#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27569#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27570#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 27703#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27677#L418-9 assume 1 == ~t3_pc~0; 27448#L419-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27439#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27667#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27665#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 27057#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27058#L437-9 assume 1 == ~t4_pc~0; 27139#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27336#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27385#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27386#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 26937#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26938#L456-9 assume 1 == ~t5_pc~0; 26978#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27350#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27351#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27270#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 27271#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27035#L475-9 assume 1 == ~t6_pc~0; 27036#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27258#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27384#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27227#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 27228#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27025#L494-9 assume 1 == ~t7_pc~0; 27026#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27205#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27434#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27185#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 27186#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27529#L837-1 assume !(1 == ~M_E~0); 27619#L842-1 assume !(1 == ~T1_E~0); 27357#L847-1 assume !(1 == ~T2_E~0); 27358#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27435#L857-1 assume !(1 == ~T4_E~0); 27312#L862-1 assume !(1 == ~T5_E~0); 27313#L867-1 assume !(1 == ~T6_E~0); 27320#L872-1 assume !(1 == ~T7_E~0); 27389#L877-1 assume !(1 == ~E_1~0); 27574#L882-1 assume !(1 == ~E_2~0); 27734#L887-1 assume !(1 == ~E_3~0); 27647#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 27648#L897-1 assume !(1 == ~E_5~0); 27334#L902-1 assume !(1 == ~E_6~0); 27335#L907-1 assume !(1 == ~E_7~0); 27625#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 27200#L1148 [2024-11-17 08:53:47,403 INFO L747 eck$LassoCheckResult]: Loop: 27200#L1148 assume true; 27604#L1148-1 assume !false; 27669#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26997#L621 assume true; 26998#L621-1 assume !false; 27163#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27164#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27178#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27759#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27222#L626 assume !(0 != eval_~tmp~0#1); 27224#L629 assume true; 31465#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31464#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31463#L754 assume !(0 == ~M_E~0); 31462#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31461#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31459#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31457#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31455#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31453#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31451#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31449#L794 assume !(0 == ~E_1~0); 31447#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 31444#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 31442#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 31440#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 31438#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 31436#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 31434#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31432#L361-1 assume !(1 == ~m_pc~0); 31430#L371-1 is_master_triggered_~__retres1~0#1 := 0; 31428#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31426#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31424#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31422#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31419#L380-1 assume !(1 == ~t1_pc~0); 31417#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 31415#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31413#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31411#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31409#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31406#L399-1 assume !(1 == ~t2_pc~0); 31404#L409-1 is_transmit2_triggered_~__retres1~2#1 := 0; 31402#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31400#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31398#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31396#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31393#L418-1 assume !(1 == ~t3_pc~0); 31390#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 31388#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31386#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31384#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31382#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31379#L437-1 assume !(1 == ~t4_pc~0); 31376#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 31374#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31372#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31368#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31367#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31366#L456-1 assume 1 == ~t5_pc~0; 31364#L457-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31363#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31362#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31360#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31358#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31356#L475-1 assume !(1 == ~t6_pc~0); 31353#L485-1 is_transmit6_triggered_~__retres1~6#1 := 0; 31350#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31346#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31341#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31336#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31333#L494-1 assume !(1 == ~t7_pc~0); 31330#L504-1 is_transmit7_triggered_~__retres1~7#1 := 0; 31328#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31326#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31325#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27106#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27107#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 26994#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26995#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27264#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27687#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27400#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27272#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27273#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27541#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 27597#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 27672#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 27673#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 27723#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 27766#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 27767#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 27094#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27095#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 26949#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27562#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 27563#L1167 assume !(0 == start_simulation_~tmp~3#1); 27196#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 27167#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 27168#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 27206#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 27316#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 27424#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26930#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 26931#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 27200#L1148 [2024-11-17 08:53:47,404 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:47,404 INFO L85 PathProgramCache]: Analyzing trace with hash 1894819940, now seen corresponding path program 1 times [2024-11-17 08:53:47,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:47,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612739643] [2024-11-17 08:53:47,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:47,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:47,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:47,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:47,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:47,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1612739643] [2024-11-17 08:53:47,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1612739643] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:47,436 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:47,437 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:47,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805973599] [2024-11-17 08:53:47,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:47,437 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:47,437 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:47,437 INFO L85 PathProgramCache]: Analyzing trace with hash -598842823, now seen corresponding path program 1 times [2024-11-17 08:53:47,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:47,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347294371] [2024-11-17 08:53:47,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:47,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:47,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:47,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:47,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:47,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347294371] [2024-11-17 08:53:47,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347294371] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:47,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:47,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:47,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404476404] [2024-11-17 08:53:47,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:47,482 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:47,482 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:47,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:47,482 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:47,482 INFO L87 Difference]: Start difference. First operand 4886 states and 7018 transitions. cyclomatic complexity: 2140 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:47,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:47,604 INFO L93 Difference]: Finished difference Result 9153 states and 13087 transitions. [2024-11-17 08:53:47,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9153 states and 13087 transitions. [2024-11-17 08:53:47,630 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8992 [2024-11-17 08:53:47,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9153 states to 9153 states and 13087 transitions. [2024-11-17 08:53:47,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9153 [2024-11-17 08:53:47,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9153 [2024-11-17 08:53:47,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9153 states and 13087 transitions. [2024-11-17 08:53:47,676 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:47,676 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9153 states and 13087 transitions. [2024-11-17 08:53:47,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9153 states and 13087 transitions. [2024-11-17 08:53:47,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9153 to 9121. [2024-11-17 08:53:47,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9121 states, 9121 states have (on average 1.4313123561013046) internal successors, (13055), 9120 states have internal predecessors, (13055), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:47,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9121 states to 9121 states and 13055 transitions. [2024-11-17 08:53:47,787 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9121 states and 13055 transitions. [2024-11-17 08:53:47,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:47,789 INFO L425 stractBuchiCegarLoop]: Abstraction has 9121 states and 13055 transitions. [2024-11-17 08:53:47,789 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:53:47,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9121 states and 13055 transitions. [2024-11-17 08:53:47,817 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8960 [2024-11-17 08:53:47,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:47,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:47,818 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,818 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,819 INFO L745 eck$LassoCheckResult]: Stem: 41612#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 41013#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 41014#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41402#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41403#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 41301#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41302#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41653#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41770#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41650#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41651#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41753#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41581#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41582#L754-1 assume !(0 == ~M_E~0); 41631#L759-1 assume !(0 == ~T1_E~0); 41606#L764-1 assume !(0 == ~T2_E~0); 41566#L769-1 assume !(0 == ~T3_E~0); 41567#L774-1 assume !(0 == ~T4_E~0); 41609#L779-1 assume !(0 == ~T5_E~0); 41757#L784-1 assume !(0 == ~T6_E~0); 41563#L789-1 assume !(0 == ~T7_E~0); 41564#L794-1 assume !(0 == ~E_1~0); 41657#L799-1 assume !(0 == ~E_2~0); 41572#L804-1 assume !(0 == ~E_3~0); 41573#L809-1 assume !(0 == ~E_4~0); 41605#L814-1 assume !(0 == ~E_5~0); 40994#L819-1 assume !(0 == ~E_6~0); 40995#L824-1 assume !(0 == ~E_7~0); 41332#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41342#L361-9 assume !(1 == ~m_pc~0); 41015#L371-9 is_master_triggered_~__retres1~0#1 := 0; 41016#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41123#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 41559#L930-9 assume !(0 != activate_threads_~tmp~1#1); 41560#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41639#L380-9 assume !(1 == ~t1_pc~0); 41640#L390-9 is_transmit1_triggered_~__retres1~1#1 := 0; 41586#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41587#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41589#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 41450#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41451#L399-9 assume !(1 == ~t2_pc~0); 41325#L409-9 is_transmit2_triggered_~__retres1~2#1 := 0; 41326#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41614#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 41615#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 41758#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41721#L418-9 assume !(1 == ~t3_pc~0); 41476#L428-9 is_transmit3_triggered_~__retres1~3#1 := 0; 41477#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41708#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41706#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 41104#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41105#L437-9 assume 1 == ~t4_pc~0; 41184#L438-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 41380#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41423#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41424#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 40985#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40986#L456-9 assume 1 == ~t5_pc~0; 41026#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41391#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41392#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41315#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 41316#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41082#L475-9 assume 1 == ~t6_pc~0; 41083#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41303#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41422#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41272#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 41273#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41073#L494-9 assume 1 == ~t7_pc~0; 41074#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41250#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41472#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41231#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 41232#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41569#L837-1 assume !(1 == ~M_E~0); 41661#L842-1 assume !(1 == ~T1_E~0); 41398#L847-1 assume !(1 == ~T2_E~0); 41399#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41473#L857-1 assume !(1 == ~T4_E~0); 41357#L862-1 assume !(1 == ~T5_E~0); 41358#L867-1 assume !(1 == ~T6_E~0); 41365#L872-1 assume !(1 == ~T7_E~0); 41427#L877-1 assume !(1 == ~E_1~0); 41618#L882-1 assume !(1 == ~E_2~0); 41797#L887-1 assume !(1 == ~E_3~0); 41684#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 41685#L897-1 assume !(1 == ~E_5~0); 41378#L902-1 assume !(1 == ~E_6~0); 41379#L907-1 assume !(1 == ~E_7~0); 41666#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 41667#L1148 [2024-11-17 08:53:47,819 INFO L747 eck$LassoCheckResult]: Loop: 41667#L1148 assume true; 46139#L1148-1 assume !false; 46116#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46112#L621 assume true; 46110#L621-1 assume !false; 46108#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 46096#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 46092#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 46089#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46086#L626 assume !(0 != eval_~tmp~0#1); 46087#L629 assume true; 46453#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46452#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46451#L754 assume !(0 == ~M_E~0); 46450#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 46449#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 46448#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46447#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46446#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46445#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46444#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46443#L794 assume !(0 == ~E_1~0); 46442#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 46441#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 46440#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 46439#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 46438#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 46437#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 46436#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46434#L361-1 assume !(1 == ~m_pc~0); 46432#L371-1 is_master_triggered_~__retres1~0#1 := 0; 46430#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46428#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46426#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46424#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46422#L380-1 assume !(1 == ~t1_pc~0); 46420#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 46418#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46416#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46414#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46412#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46410#L399-1 assume !(1 == ~t2_pc~0); 46408#L409-1 is_transmit2_triggered_~__retres1~2#1 := 0; 46406#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46404#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46402#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46400#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46398#L418-1 assume !(1 == ~t3_pc~0); 46396#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 46394#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46392#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46390#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46388#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46386#L437-1 assume 1 == ~t4_pc~0; 46384#L438-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46381#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46378#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46376#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46374#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46372#L456-1 assume 1 == ~t5_pc~0; 46369#L457-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46367#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46364#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46362#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 46360#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46358#L475-1 assume !(1 == ~t6_pc~0); 46355#L485-1 is_transmit6_triggered_~__retres1~6#1 := 0; 46353#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46350#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 46348#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46346#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46344#L494-1 assume !(1 == ~t7_pc~0); 46341#L504-1 is_transmit7_triggered_~__retres1~7#1 := 0; 46339#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46336#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 46334#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 46332#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46330#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 46328#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46325#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46323#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46321#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46319#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46317#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46316#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46313#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 46312#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 46311#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 46310#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 46309#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 46308#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 46307#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 46306#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 46301#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 46295#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 46292#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 46229#L1167 assume !(0 == start_simulation_~tmp~3#1); 46227#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 46154#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 46148#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 46147#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 46146#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46145#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46144#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 46142#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 41667#L1148 [2024-11-17 08:53:47,819 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:47,820 INFO L85 PathProgramCache]: Analyzing trace with hash -182013695, now seen corresponding path program 1 times [2024-11-17 08:53:47,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:47,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913530145] [2024-11-17 08:53:47,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:47,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:47,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:47,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:47,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:47,864 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913530145] [2024-11-17 08:53:47,864 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913530145] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:47,864 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:47,864 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:47,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [784169988] [2024-11-17 08:53:47,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:47,864 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:47,865 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:47,865 INFO L85 PathProgramCache]: Analyzing trace with hash 898368348, now seen corresponding path program 1 times [2024-11-17 08:53:47,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:47,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474027521] [2024-11-17 08:53:47,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:47,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:47,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:47,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:47,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:47,906 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [474027521] [2024-11-17 08:53:47,906 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [474027521] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:47,906 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:47,906 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:47,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915011291] [2024-11-17 08:53:47,907 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:47,907 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:47,907 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:47,908 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:47,908 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:47,908 INFO L87 Difference]: Start difference. First operand 9121 states and 13055 transitions. cyclomatic complexity: 3950 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:48,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:48,001 INFO L93 Difference]: Finished difference Result 17104 states and 24380 transitions. [2024-11-17 08:53:48,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17104 states and 24380 transitions. [2024-11-17 08:53:48,124 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 16864 [2024-11-17 08:53:48,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17104 states to 17104 states and 24380 transitions. [2024-11-17 08:53:48,169 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17104 [2024-11-17 08:53:48,182 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17104 [2024-11-17 08:53:48,182 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17104 states and 24380 transitions. [2024-11-17 08:53:48,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:48,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17104 states and 24380 transitions. [2024-11-17 08:53:48,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17104 states and 24380 transitions. [2024-11-17 08:53:48,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17104 to 17040. [2024-11-17 08:53:48,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17040 states, 17040 states have (on average 1.4269953051643192) internal successors, (24316), 17039 states have internal predecessors, (24316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:48,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17040 states to 17040 states and 24316 transitions. [2024-11-17 08:53:48,404 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17040 states and 24316 transitions. [2024-11-17 08:53:48,406 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:48,407 INFO L425 stractBuchiCegarLoop]: Abstraction has 17040 states and 24316 transitions. [2024-11-17 08:53:48,407 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:53:48,407 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17040 states and 24316 transitions. [2024-11-17 08:53:48,442 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 16800 [2024-11-17 08:53:48,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:48,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:48,443 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:48,443 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:48,443 INFO L745 eck$LassoCheckResult]: Stem: 67855#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 67246#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 67247#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 67641#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67642#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 67536#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67537#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67904#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68012#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67901#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 67902#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 67998#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 67826#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67827#L754-1 assume !(0 == ~M_E~0); 67880#L759-1 assume !(0 == ~T1_E~0); 67849#L764-1 assume !(0 == ~T2_E~0); 67809#L769-1 assume !(0 == ~T3_E~0); 67810#L774-1 assume !(0 == ~T4_E~0); 67852#L779-1 assume !(0 == ~T5_E~0); 67999#L784-1 assume !(0 == ~T6_E~0); 67805#L789-1 assume !(0 == ~T7_E~0); 67806#L794-1 assume !(0 == ~E_1~0); 67908#L799-1 assume !(0 == ~E_2~0); 67816#L804-1 assume !(0 == ~E_3~0); 67817#L809-1 assume !(0 == ~E_4~0); 67848#L814-1 assume !(0 == ~E_5~0); 67227#L819-1 assume !(0 == ~E_6~0); 67228#L824-1 assume !(0 == ~E_7~0); 67572#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67580#L361-9 assume !(1 == ~m_pc~0); 67248#L371-9 is_master_triggered_~__retres1~0#1 := 0; 67249#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 67352#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 67801#L930-9 assume !(0 != activate_threads_~tmp~1#1); 67802#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 67892#L380-9 assume !(1 == ~t1_pc~0); 67893#L390-9 is_transmit1_triggered_~__retres1~1#1 := 0; 67833#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 67834#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 67835#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 67692#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 67693#L399-9 assume !(1 == ~t2_pc~0); 67565#L409-9 is_transmit2_triggered_~__retres1~2#1 := 0; 67566#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 67858#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 67859#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 68000#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 67973#L418-9 assume !(1 == ~t3_pc~0); 67722#L428-9 is_transmit3_triggered_~__retres1~3#1 := 0; 67723#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 67961#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 67958#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 67336#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 67337#L437-9 assume !(1 == ~t4_pc~0); 67417#L447-9 is_transmit4_triggered_~__retres1~4#1 := 0; 67619#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67665#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 67666#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 67216#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 67217#L456-9 assume 1 == ~t5_pc~0; 67259#L457-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 67631#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 67632#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 67552#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 67553#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 67314#L475-9 assume 1 == ~t6_pc~0; 67315#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 67538#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67664#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 67506#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 67507#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 67303#L494-9 assume 1 == ~t7_pc~0; 67304#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 67484#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 67718#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67464#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 67465#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67812#L837-1 assume !(1 == ~M_E~0); 67909#L842-1 assume !(1 == ~T1_E~0); 67638#L847-1 assume !(1 == ~T2_E~0); 67639#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 67719#L857-1 assume !(1 == ~T4_E~0); 67591#L862-1 assume !(1 == ~T5_E~0); 67592#L867-1 assume !(1 == ~T6_E~0); 67603#L872-1 assume !(1 == ~T7_E~0); 67669#L877-1 assume !(1 == ~E_1~0); 67861#L882-1 assume !(1 == ~E_2~0); 68043#L887-1 assume !(1 == ~E_3~0); 67931#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 67932#L897-1 assume !(1 == ~E_5~0); 67617#L902-1 assume !(1 == ~E_6~0); 67618#L907-1 assume !(1 == ~E_7~0); 67917#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 67918#L1148 [2024-11-17 08:53:48,444 INFO L747 eck$LassoCheckResult]: Loop: 67918#L1148 assume true; 75312#L1148-1 assume !false; 75291#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75287#L621 assume true; 75285#L621-1 assume !false; 75283#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 75269#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 75265#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 75263#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 75259#L626 assume !(0 != eval_~tmp~0#1); 75260#L629 assume true; 75523#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75521#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75520#L754 assume !(0 == ~M_E~0); 75519#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 75516#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 75513#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 75511#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75509#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 75507#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 75505#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 75502#L794 assume !(0 == ~E_1~0); 75498#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 75494#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 75493#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 75492#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 75491#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 75490#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 75489#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75488#L361-1 assume !(1 == ~m_pc~0); 75487#L371-1 is_master_triggered_~__retres1~0#1 := 0; 75486#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75485#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75484#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75483#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75482#L380-1 assume !(1 == ~t1_pc~0); 75481#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 75479#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75477#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75475#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75473#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75471#L399-1 assume !(1 == ~t2_pc~0); 75469#L409-1 is_transmit2_triggered_~__retres1~2#1 := 0; 75467#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75465#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 75463#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 75461#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75459#L418-1 assume !(1 == ~t3_pc~0); 75457#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 75455#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75453#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 75451#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 75449#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75447#L437-1 assume !(1 == ~t4_pc~0); 75445#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 75443#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75441#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75439#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75437#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75435#L456-1 assume !(1 == ~t5_pc~0); 75433#L466-1 is_transmit5_triggered_~__retres1~5#1 := 0; 75430#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75428#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 75426#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 75424#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75422#L475-1 assume !(1 == ~t6_pc~0); 75419#L485-1 is_transmit6_triggered_~__retres1~6#1 := 0; 75417#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75414#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 75412#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 75410#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 75408#L494-1 assume !(1 == ~t7_pc~0); 75405#L504-1 is_transmit7_triggered_~__retres1~7#1 := 0; 75403#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 75400#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75398#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 75396#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75394#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 75392#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 75390#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75387#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 75385#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 75383#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75381#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 75379#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 75377#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 75375#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 75373#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 75371#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 75369#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 75367#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 75365#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 75363#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 75355#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 75349#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 75347#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 75343#L1167 assume !(0 == start_simulation_~tmp~3#1); 75342#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 75329#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 75325#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 75323#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 75321#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75319#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75317#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 75315#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 67918#L1148 [2024-11-17 08:53:48,444 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:48,444 INFO L85 PathProgramCache]: Analyzing trace with hash -1170033826, now seen corresponding path program 1 times [2024-11-17 08:53:48,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:48,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275603405] [2024-11-17 08:53:48,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:48,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:48,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:48,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:48,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:48,469 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275603405] [2024-11-17 08:53:48,469 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275603405] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:48,469 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:48,469 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:48,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [969010393] [2024-11-17 08:53:48,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:48,469 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:48,469 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:48,469 INFO L85 PathProgramCache]: Analyzing trace with hash 1619290838, now seen corresponding path program 1 times [2024-11-17 08:53:48,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:48,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547132650] [2024-11-17 08:53:48,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:48,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:48,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:48,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:48,578 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:48,578 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547132650] [2024-11-17 08:53:48,578 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [547132650] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:48,578 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:48,579 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:48,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1700239050] [2024-11-17 08:53:48,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:48,579 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:48,579 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:48,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:48,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:48,580 INFO L87 Difference]: Start difference. First operand 17040 states and 24316 transitions. cyclomatic complexity: 7308 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:48,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:48,712 INFO L93 Difference]: Finished difference Result 31967 states and 45481 transitions. [2024-11-17 08:53:48,712 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31967 states and 45481 transitions. [2024-11-17 08:53:48,827 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31520 [2024-11-17 08:53:49,118 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31967 states to 31967 states and 45481 transitions. [2024-11-17 08:53:49,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31967 [2024-11-17 08:53:49,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31967 [2024-11-17 08:53:49,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31967 states and 45481 transitions. [2024-11-17 08:53:49,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:49,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31967 states and 45481 transitions. [2024-11-17 08:53:49,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31967 states and 45481 transitions. [2024-11-17 08:53:49,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31967 to 31839. [2024-11-17 08:53:49,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31839 states, 31839 states have (on average 1.4244480040202268) internal successors, (45353), 31838 states have internal predecessors, (45353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31839 states to 31839 states and 45353 transitions. [2024-11-17 08:53:49,631 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31839 states and 45353 transitions. [2024-11-17 08:53:49,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:49,632 INFO L425 stractBuchiCegarLoop]: Abstraction has 31839 states and 45353 transitions. [2024-11-17 08:53:49,632 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:53:49,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31839 states and 45353 transitions. [2024-11-17 08:53:49,713 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 31392 [2024-11-17 08:53:49,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:49,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:49,715 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,715 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,715 INFO L745 eck$LassoCheckResult]: Stem: 116876#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 116264#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 116265#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 116656#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 116657#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 116551#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 116552#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 116923#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 117044#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 116921#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116922#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 117025#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 116842#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 116843#L754-1 assume !(0 == ~M_E~0); 116901#L759-1 assume !(0 == ~T1_E~0); 116867#L764-1 assume !(0 == ~T2_E~0); 116822#L769-1 assume !(0 == ~T3_E~0); 116823#L774-1 assume !(0 == ~T4_E~0); 116868#L779-1 assume !(0 == ~T5_E~0); 117028#L784-1 assume !(0 == ~T6_E~0); 116818#L789-1 assume !(0 == ~T7_E~0); 116819#L794-1 assume !(0 == ~E_1~0); 116926#L799-1 assume !(0 == ~E_2~0); 116832#L804-1 assume !(0 == ~E_3~0); 116833#L809-1 assume !(0 == ~E_4~0); 116866#L814-1 assume !(0 == ~E_5~0); 116244#L819-1 assume !(0 == ~E_6~0); 116245#L824-1 assume !(0 == ~E_7~0); 116582#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116589#L361-9 assume !(1 == ~m_pc~0); 116266#L371-9 is_master_triggered_~__retres1~0#1 := 0; 116267#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 116370#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 116814#L930-9 assume !(0 != activate_threads_~tmp~1#1); 116815#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116911#L380-9 assume !(1 == ~t1_pc~0); 116912#L390-9 is_transmit1_triggered_~__retres1~1#1 := 0; 116847#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116848#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 116849#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 116707#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116708#L399-9 assume !(1 == ~t2_pc~0); 116575#L409-9 is_transmit2_triggered_~__retres1~2#1 := 0; 116576#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116879#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116880#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 117029#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116993#L418-9 assume !(1 == ~t3_pc~0); 116734#L428-9 is_transmit3_triggered_~__retres1~3#1 := 0; 116735#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116980#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 116977#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 116353#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 116354#L437-9 assume !(1 == ~t4_pc~0); 116433#L447-9 is_transmit4_triggered_~__retres1~4#1 := 0; 116634#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116679#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 116680#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 116232#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116233#L456-9 assume !(1 == ~t5_pc~0); 116277#L466-9 is_transmit5_triggered_~__retres1~5#1 := 0; 116646#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116647#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 116562#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 116563#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116330#L475-9 assume 1 == ~t6_pc~0; 116331#L476-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 116553#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116678#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 116521#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 116522#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116319#L494-9 assume 1 == ~t7_pc~0; 116320#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 116499#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 116730#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116480#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 116481#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116829#L837-1 assume !(1 == ~M_E~0); 116927#L842-1 assume !(1 == ~T1_E~0); 116653#L847-1 assume !(1 == ~T2_E~0); 116654#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116731#L857-1 assume !(1 == ~T4_E~0); 116606#L862-1 assume !(1 == ~T5_E~0); 116607#L867-1 assume !(1 == ~T6_E~0); 116618#L872-1 assume !(1 == ~T7_E~0); 116684#L877-1 assume !(1 == ~E_1~0); 116882#L882-1 assume !(1 == ~E_2~0); 117069#L887-1 assume !(1 == ~E_3~0); 116953#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 116954#L897-1 assume !(1 == ~E_5~0); 116632#L902-1 assume !(1 == ~E_6~0); 116633#L907-1 assume !(1 == ~E_7~0); 116937#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 116938#L1148 [2024-11-17 08:53:49,715 INFO L747 eck$LassoCheckResult]: Loop: 116938#L1148 assume true; 134829#L1148-1 assume !false; 134812#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 134808#L621 assume true; 134806#L621-1 assume !false; 134804#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 134790#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 134786#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 134784#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 134781#L626 assume !(0 != eval_~tmp~0#1); 134782#L629 assume true; 135035#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 135033#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 135030#L754 assume !(0 == ~M_E~0); 135028#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 135026#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 135024#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 135022#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 135019#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 135017#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 135015#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 135013#L794 assume !(0 == ~E_1~0); 135011#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 135010#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 135007#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 135006#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 135004#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 135003#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 135002#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 135001#L361-1 assume !(1 == ~m_pc~0); 135000#L371-1 is_master_triggered_~__retres1~0#1 := 0; 134999#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134998#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 134997#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 134996#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134995#L380-1 assume !(1 == ~t1_pc~0); 134994#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 134992#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134990#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 134988#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 134986#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134984#L399-1 assume !(1 == ~t2_pc~0); 134982#L409-1 is_transmit2_triggered_~__retres1~2#1 := 0; 134980#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134978#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 134976#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 134974#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134972#L418-1 assume !(1 == ~t3_pc~0); 134970#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 134968#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134966#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 134964#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 134962#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134960#L437-1 assume !(1 == ~t4_pc~0); 134958#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 134956#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134954#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 134952#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 134950#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134948#L456-1 assume !(1 == ~t5_pc~0); 134946#L466-1 is_transmit5_triggered_~__retres1~5#1 := 0; 134944#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 134942#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 134940#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 134938#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134936#L475-1 assume 1 == ~t6_pc~0; 134934#L476-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 134931#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 134929#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134927#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 134925#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 134923#L494-1 assume !(1 == ~t7_pc~0); 134920#L504-1 is_transmit7_triggered_~__retres1~7#1 := 0; 134918#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 134915#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 134913#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 134911#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134909#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 134907#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 134905#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134902#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 134900#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 134898#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 134896#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 134894#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 134892#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 134890#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 134888#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 134886#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 134884#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 134882#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 134880#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 134878#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 134870#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 134864#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 134862#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 134858#L1167 assume !(0 == start_simulation_~tmp~3#1); 134857#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 134851#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 134848#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 134846#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 134843#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 134839#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 134838#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 134836#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 116938#L1148 [2024-11-17 08:53:49,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,716 INFO L85 PathProgramCache]: Analyzing trace with hash -72155269, now seen corresponding path program 1 times [2024-11-17 08:53:49,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920395724] [2024-11-17 08:53:49,717 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,771 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,771 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920395724] [2024-11-17 08:53:49,771 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920395724] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,771 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:49,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951149648] [2024-11-17 08:53:49,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,772 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:49,772 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,772 INFO L85 PathProgramCache]: Analyzing trace with hash -1687656327, now seen corresponding path program 1 times [2024-11-17 08:53:49,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412732873] [2024-11-17 08:53:49,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412732873] [2024-11-17 08:53:49,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412732873] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:49,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1189857174] [2024-11-17 08:53:49,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,837 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:49,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:49,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:49,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:49,837 INFO L87 Difference]: Start difference. First operand 31839 states and 45353 transitions. cyclomatic complexity: 13578 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:50,297 INFO L93 Difference]: Finished difference Result 73342 states and 104086 transitions. [2024-11-17 08:53:50,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73342 states and 104086 transitions. [2024-11-17 08:53:50,867 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 72032 [2024-11-17 08:53:51,074 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73342 states to 73342 states and 104086 transitions. [2024-11-17 08:53:51,075 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73342 [2024-11-17 08:53:51,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73342 [2024-11-17 08:53:51,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73342 states and 104086 transitions. [2024-11-17 08:53:51,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:51,311 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73342 states and 104086 transitions. [2024-11-17 08:53:51,401 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73342 states and 104086 transitions. [2024-11-17 08:53:51,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73342 to 59358. [2024-11-17 08:53:51,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59358 states, 59358 states have (on average 1.4233296270089963) internal successors, (84486), 59357 states have internal predecessors, (84486), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:52,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59358 states to 59358 states and 84486 transitions. [2024-11-17 08:53:52,271 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59358 states and 84486 transitions. [2024-11-17 08:53:52,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:52,272 INFO L425 stractBuchiCegarLoop]: Abstraction has 59358 states and 84486 transitions. [2024-11-17 08:53:52,272 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:53:52,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59358 states and 84486 transitions. [2024-11-17 08:53:52,410 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 58560 [2024-11-17 08:53:52,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:52,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:52,411 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:52,411 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:52,411 INFO L745 eck$LassoCheckResult]: Stem: 222065#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 221455#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 221456#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 221847#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 221848#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 221741#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 221742#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 222112#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 222232#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 222109#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 222110#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 222214#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 222032#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222033#L754-1 assume !(0 == ~M_E~0); 222088#L759-1 assume !(0 == ~T1_E~0); 222059#L764-1 assume !(0 == ~T2_E~0); 222013#L769-1 assume !(0 == ~T3_E~0); 222014#L774-1 assume !(0 == ~T4_E~0); 222060#L779-1 assume !(0 == ~T5_E~0); 222217#L784-1 assume !(0 == ~T6_E~0); 222009#L789-1 assume !(0 == ~T7_E~0); 222010#L794-1 assume !(0 == ~E_1~0); 222115#L799-1 assume !(0 == ~E_2~0); 222022#L804-1 assume !(0 == ~E_3~0); 222023#L809-1 assume !(0 == ~E_4~0); 222058#L814-1 assume !(0 == ~E_5~0); 221436#L819-1 assume !(0 == ~E_6~0); 221437#L824-1 assume !(0 == ~E_7~0); 221777#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 221784#L361-9 assume !(1 == ~m_pc~0); 221457#L371-9 is_master_triggered_~__retres1~0#1 := 0; 221458#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 221558#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 222004#L930-9 assume !(0 != activate_threads_~tmp~1#1); 222005#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222099#L380-9 assume !(1 == ~t1_pc~0); 222100#L390-9 is_transmit1_triggered_~__retres1~1#1 := 0; 222039#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222040#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 222041#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 221898#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 221899#L399-9 assume !(1 == ~t2_pc~0); 221769#L409-9 is_transmit2_triggered_~__retres1~2#1 := 0; 221770#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222067#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 222068#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 222218#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 222190#L418-9 assume !(1 == ~t3_pc~0); 221928#L428-9 is_transmit3_triggered_~__retres1~3#1 := 0; 221929#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222177#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 222174#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 221542#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 221543#L437-9 assume !(1 == ~t4_pc~0); 221623#L447-9 is_transmit4_triggered_~__retres1~4#1 := 0; 221825#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 221874#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 221875#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 221425#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 221426#L456-9 assume !(1 == ~t5_pc~0); 221468#L466-9 is_transmit5_triggered_~__retres1~5#1 := 0; 221837#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 221838#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 221755#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 221756#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 221521#L475-9 assume !(1 == ~t6_pc~0); 221522#L485-9 is_transmit6_triggered_~__retres1~6#1 := 0; 221743#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 221873#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 221711#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 221712#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 221509#L494-9 assume 1 == ~t7_pc~0; 221510#L495-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 221689#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 221924#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 221670#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 221671#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 222018#L837-1 assume !(1 == ~M_E~0); 222116#L842-1 assume !(1 == ~T1_E~0); 221844#L847-1 assume !(1 == ~T2_E~0); 221845#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 221925#L857-1 assume !(1 == ~T4_E~0); 221798#L862-1 assume !(1 == ~T5_E~0); 221799#L867-1 assume !(1 == ~T6_E~0); 221809#L872-1 assume !(1 == ~T7_E~0); 221877#L877-1 assume !(1 == ~E_1~0); 222070#L882-1 assume !(1 == ~E_2~0); 222255#L887-1 assume !(1 == ~E_3~0); 222145#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 222146#L897-1 assume !(1 == ~E_5~0); 221823#L902-1 assume !(1 == ~E_6~0); 221824#L907-1 assume !(1 == ~E_7~0); 222123#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 222124#L1148 [2024-11-17 08:53:52,412 INFO L747 eck$LassoCheckResult]: Loop: 222124#L1148 assume true; 270154#L1148-1 assume !false; 270150#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 270147#L621 assume true; 270146#L621-1 assume !false; 270145#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 270138#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 270134#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 270132#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 270128#L626 assume !(0 != eval_~tmp~0#1); 270129#L629 assume true; 270351#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 270349#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 270348#L754 assume !(0 == ~M_E~0); 270347#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 270346#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 270345#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 270342#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 270341#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 270340#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 270336#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 270335#L794 assume !(0 == ~E_1~0); 270334#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 270330#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 270326#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 270325#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 270324#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 270320#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 270316#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 270315#L361-1 assume !(1 == ~m_pc~0); 270314#L371-1 is_master_triggered_~__retres1~0#1 := 0; 270313#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 270312#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 270311#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 270310#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 270309#L380-1 assume !(1 == ~t1_pc~0); 270308#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 270306#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 270304#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 270302#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 270300#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 270298#L399-1 assume !(1 == ~t2_pc~0); 270296#L409-1 is_transmit2_triggered_~__retres1~2#1 := 0; 270294#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270292#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 270290#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 270288#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 270286#L418-1 assume !(1 == ~t3_pc~0); 270284#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 270282#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 270280#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 270278#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 270276#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270274#L437-1 assume !(1 == ~t4_pc~0); 270272#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 270270#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 270268#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 270266#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 270264#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 270262#L456-1 assume !(1 == ~t5_pc~0); 270260#L466-1 is_transmit5_triggered_~__retres1~5#1 := 0; 270258#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 270256#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 270254#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 270252#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 270250#L475-1 assume !(1 == ~t6_pc~0); 230346#L485-1 is_transmit6_triggered_~__retres1~6#1 := 0; 270247#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 270245#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 270243#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 270241#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 270239#L494-1 assume !(1 == ~t7_pc~0); 270236#L504-1 is_transmit7_triggered_~__retres1~7#1 := 0; 270234#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 270233#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 270231#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 270229#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 270227#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 270225#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 270223#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 270220#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 270218#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 270216#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 270214#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 270212#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 270210#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 270208#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 270206#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 270204#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 270202#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 270200#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 270198#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 270196#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 270188#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 270182#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 270180#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 270176#L1167 assume !(0 == start_simulation_~tmp~3#1); 270175#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 270169#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 270166#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 270164#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 270162#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 270160#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 270158#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 270156#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 222124#L1148 [2024-11-17 08:53:52,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:52,412 INFO L85 PathProgramCache]: Analyzing trace with hash 2044847448, now seen corresponding path program 1 times [2024-11-17 08:53:52,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:52,413 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57220433] [2024-11-17 08:53:52,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:52,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:52,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:52,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:52,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:52,602 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [57220433] [2024-11-17 08:53:52,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [57220433] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:52,603 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:52,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:52,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1060039863] [2024-11-17 08:53:52,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:52,603 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:52,603 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:52,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1619290838, now seen corresponding path program 2 times [2024-11-17 08:53:52,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:52,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345532068] [2024-11-17 08:53:52,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:52,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:52,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:52,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:52,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:52,664 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345532068] [2024-11-17 08:53:52,665 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345532068] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:52,665 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:52,665 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:52,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [297777490] [2024-11-17 08:53:52,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:52,665 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:52,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:52,666 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:52,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:52,666 INFO L87 Difference]: Start difference. First operand 59358 states and 84486 transitions. cyclomatic complexity: 25192 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:53,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:53,018 INFO L93 Difference]: Finished difference Result 117661 states and 166467 transitions. [2024-11-17 08:53:53,018 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117661 states and 166467 transitions. [2024-11-17 08:53:53,825 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 115904 [2024-11-17 08:53:54,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117661 states to 117661 states and 166467 transitions. [2024-11-17 08:53:54,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117661 [2024-11-17 08:53:54,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117661 [2024-11-17 08:53:54,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117661 states and 166467 transitions. [2024-11-17 08:53:54,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:54,569 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117661 states and 166467 transitions. [2024-11-17 08:53:54,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117661 states and 166467 transitions. [2024-11-17 08:53:55,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117661 to 116893. [2024-11-17 08:53:55,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116893 states, 116893 states have (on average 1.416432121683933) internal successors, (165571), 116892 states have internal predecessors, (165571), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:55,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116893 states to 116893 states and 165571 transitions. [2024-11-17 08:53:55,924 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116893 states and 165571 transitions. [2024-11-17 08:53:55,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:55,925 INFO L425 stractBuchiCegarLoop]: Abstraction has 116893 states and 165571 transitions. [2024-11-17 08:53:55,925 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:53:55,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116893 states and 165571 transitions. [2024-11-17 08:53:56,271 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 115392 [2024-11-17 08:53:56,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:56,272 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:56,273 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:56,274 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:56,274 INFO L745 eck$LassoCheckResult]: Stem: 399105#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 398484#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 398485#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 398875#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 398876#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 398768#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 398769#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 399157#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 399290#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 399155#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 399156#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 399274#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 399073#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 399074#L754-1 assume !(0 == ~M_E~0); 399133#L759-1 assume !(0 == ~T1_E~0); 399098#L764-1 assume !(0 == ~T2_E~0); 399050#L769-1 assume !(0 == ~T3_E~0); 399051#L774-1 assume !(0 == ~T4_E~0); 399099#L779-1 assume !(0 == ~T5_E~0); 399275#L784-1 assume !(0 == ~T6_E~0); 399046#L789-1 assume !(0 == ~T7_E~0); 399047#L794-1 assume !(0 == ~E_1~0); 399163#L799-1 assume !(0 == ~E_2~0); 399059#L804-1 assume !(0 == ~E_3~0); 399060#L809-1 assume !(0 == ~E_4~0); 399097#L814-1 assume !(0 == ~E_5~0); 398464#L819-1 assume !(0 == ~E_6~0); 398465#L824-1 assume !(0 == ~E_7~0); 398802#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 398809#L361-9 assume !(1 == ~m_pc~0); 398486#L371-9 is_master_triggered_~__retres1~0#1 := 0; 398487#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 398587#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 399042#L930-9 assume !(0 != activate_threads_~tmp~1#1); 399043#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399143#L380-9 assume !(1 == ~t1_pc~0); 399144#L390-9 is_transmit1_triggered_~__retres1~1#1 := 0; 399078#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 399079#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 399080#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 398926#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 398927#L399-9 assume !(1 == ~t2_pc~0); 398796#L409-9 is_transmit2_triggered_~__retres1~2#1 := 0; 398797#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 399108#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 399109#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 399276#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 399243#L418-9 assume !(1 == ~t3_pc~0); 398954#L428-9 is_transmit3_triggered_~__retres1~3#1 := 0; 398955#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 399231#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 399228#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 398571#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 398572#L437-9 assume !(1 == ~t4_pc~0); 398651#L447-9 is_transmit4_triggered_~__retres1~4#1 := 0; 398852#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 398903#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 398904#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 398453#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 398454#L456-9 assume !(1 == ~t5_pc~0); 398497#L466-9 is_transmit5_triggered_~__retres1~5#1 := 0; 398864#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 398865#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 398783#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 398784#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 398549#L475-9 assume !(1 == ~t6_pc~0); 398550#L485-9 is_transmit6_triggered_~__retres1~6#1 := 0; 398772#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 398902#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 398739#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 398740#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 398539#L494-9 assume !(1 == ~t7_pc~0); 398540#L504-9 is_transmit7_triggered_~__retres1~7#1 := 0; 398717#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 398950#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 398698#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 398699#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 399055#L837-1 assume !(1 == ~M_E~0); 399164#L842-1 assume !(1 == ~T1_E~0); 398871#L847-1 assume !(1 == ~T2_E~0); 398872#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 398951#L857-1 assume !(1 == ~T4_E~0); 398824#L862-1 assume !(1 == ~T5_E~0); 398825#L867-1 assume !(1 == ~T6_E~0); 398835#L872-1 assume !(1 == ~T7_E~0); 398906#L877-1 assume !(1 == ~E_1~0); 399111#L882-1 assume !(1 == ~E_2~0); 399323#L887-1 assume !(1 == ~E_3~0); 399197#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 399198#L897-1 assume !(1 == ~E_5~0); 398850#L902-1 assume !(1 == ~E_6~0); 398851#L907-1 assume !(1 == ~E_7~0); 399175#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 399176#L1148 [2024-11-17 08:53:56,274 INFO L747 eck$LassoCheckResult]: Loop: 399176#L1148 assume true; 446618#L1148-1 assume !false; 446613#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 446610#L621 assume true; 446608#L621-1 assume !false; 446606#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 445239#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 445236#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 445234#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 445232#L626 assume !(0 != eval_~tmp~0#1); 445233#L629 assume true; 446803#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 446801#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 446800#L754 assume !(0 == ~M_E~0); 446797#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 446796#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 446795#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 446792#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 446791#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 446790#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 446789#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 446788#L794 assume !(0 == ~E_1~0); 446787#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 446786#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 446785#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 446784#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 446783#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 446782#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 446781#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446780#L361-1 assume !(1 == ~m_pc~0); 446779#L371-1 is_master_triggered_~__retres1~0#1 := 0; 446778#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 446777#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 446776#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 446775#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 446774#L380-1 assume !(1 == ~t1_pc~0); 446773#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 446771#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 446769#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 446767#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 446765#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 446763#L399-1 assume !(1 == ~t2_pc~0); 446761#L409-1 is_transmit2_triggered_~__retres1~2#1 := 0; 446759#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 446757#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 446755#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 446753#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 446751#L418-1 assume !(1 == ~t3_pc~0); 446749#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 446747#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 446745#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 446743#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 446741#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 446739#L437-1 assume !(1 == ~t4_pc~0); 446737#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 446735#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 446733#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 446731#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 446729#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 446727#L456-1 assume !(1 == ~t5_pc~0); 446725#L466-1 is_transmit5_triggered_~__retres1~5#1 := 0; 446723#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 446721#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 446719#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 446717#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 446715#L475-1 assume !(1 == ~t6_pc~0); 444728#L485-1 is_transmit6_triggered_~__retres1~6#1 := 0; 446712#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 446710#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 446708#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 446706#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 446704#L494-1 assume !(1 == ~t7_pc~0); 446702#L504-1 is_transmit7_triggered_~__retres1~7#1 := 0; 446700#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 446699#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 446697#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 446695#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 446693#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 446691#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 446689#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 446687#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 446685#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 446683#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 446681#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 446679#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 446677#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 446675#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 446673#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 446671#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 446669#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 446667#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 446665#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 446663#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 446655#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 446649#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 446647#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 446643#L1167 assume !(0 == start_simulation_~tmp~3#1); 446642#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 446635#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 446631#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 446629#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 446627#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 446625#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 446623#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 446621#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 399176#L1148 [2024-11-17 08:53:56,275 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:56,275 INFO L85 PathProgramCache]: Analyzing trace with hash -415910667, now seen corresponding path program 1 times [2024-11-17 08:53:56,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:56,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251367345] [2024-11-17 08:53:56,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:56,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:56,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:56,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:56,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:56,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [251367345] [2024-11-17 08:53:56,791 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [251367345] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:56,791 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:56,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:56,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1936755008] [2024-11-17 08:53:56,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:56,791 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:56,791 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:56,791 INFO L85 PathProgramCache]: Analyzing trace with hash 1619290838, now seen corresponding path program 3 times [2024-11-17 08:53:56,791 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:56,791 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793231705] [2024-11-17 08:53:56,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:56,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:56,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:56,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:56,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:56,903 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1793231705] [2024-11-17 08:53:56,903 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1793231705] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:56,903 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:56,903 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:56,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [216296988] [2024-11-17 08:53:56,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:56,904 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:56,904 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:56,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:56,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:56,904 INFO L87 Difference]: Start difference. First operand 116893 states and 165571 transitions. cyclomatic complexity: 48806 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:57,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:57,511 INFO L93 Difference]: Finished difference Result 233580 states and 329291 transitions. [2024-11-17 08:53:57,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 233580 states and 329291 transitions. [2024-11-17 08:53:58,851 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 230528 [2024-11-17 08:53:59,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 233580 states to 233580 states and 329291 transitions. [2024-11-17 08:53:59,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 233580 [2024-11-17 08:53:59,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 233580 [2024-11-17 08:53:59,951 INFO L73 IsDeterministic]: Start isDeterministic. Operand 233580 states and 329291 transitions. [2024-11-17 08:54:00,058 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:00,061 INFO L218 hiAutomatonCegarLoop]: Abstraction has 233580 states and 329291 transitions. [2024-11-17 08:54:00,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233580 states and 329291 transitions. [2024-11-17 08:54:02,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233580 to 233580. [2024-11-17 08:54:02,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 233580 states, 233580 states have (on average 1.4097568284955904) internal successors, (329291), 233579 states have internal predecessors, (329291), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233580 states to 233580 states and 329291 transitions. [2024-11-17 08:54:02,847 INFO L240 hiAutomatonCegarLoop]: Abstraction has 233580 states and 329291 transitions. [2024-11-17 08:54:02,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:54:02,848 INFO L425 stractBuchiCegarLoop]: Abstraction has 233580 states and 329291 transitions. [2024-11-17 08:54:02,848 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:54:02,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 233580 states and 329291 transitions. [2024-11-17 08:54:04,027 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 230528 [2024-11-17 08:54:04,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:04,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:04,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:04,029 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:04,029 INFO L745 eck$LassoCheckResult]: Stem: 749606#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 748968#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 748969#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 749372#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 749373#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 749257#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 749258#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 749658#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 749795#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 749655#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 749656#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 749773#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 749571#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 749572#L754-1 assume 0 == ~M_E~0;~M_E~0 := 1; 749633#L759-1 assume !(0 == ~T1_E~0); 749597#L764-1 assume !(0 == ~T2_E~0); 749598#L769-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 749551#L774-1 assume !(0 == ~T4_E~0); 750018#L779-1 assume !(0 == ~T5_E~0); 750017#L784-1 assume !(0 == ~T6_E~0); 750016#L789-1 assume !(0 == ~T7_E~0); 750015#L794-1 assume !(0 == ~E_1~0); 750014#L799-1 assume !(0 == ~E_2~0); 750013#L804-1 assume !(0 == ~E_3~0); 750012#L809-1 assume !(0 == ~E_4~0); 750011#L814-1 assume !(0 == ~E_5~0); 750010#L819-1 assume !(0 == ~E_6~0); 750009#L824-1 assume !(0 == ~E_7~0); 750008#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 750007#L361-9 assume !(1 == ~m_pc~0); 750006#L371-9 is_master_triggered_~__retres1~0#1 := 0; 750005#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 750004#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 750003#L930-9 assume !(0 != activate_threads_~tmp~1#1); 750002#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 750001#L380-9 assume !(1 == ~t1_pc~0); 750000#L390-9 is_transmit1_triggered_~__retres1~1#1 := 0; 749999#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 749998#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 749997#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 749996#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 749995#L399-9 assume !(1 == ~t2_pc~0); 749994#L409-9 is_transmit2_triggered_~__retres1~2#1 := 0; 749993#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 749992#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 749991#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 749990#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 749989#L418-9 assume !(1 == ~t3_pc~0); 749988#L428-9 is_transmit3_triggered_~__retres1~3#1 := 0; 749987#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 749986#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 749985#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 749984#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 749983#L437-9 assume !(1 == ~t4_pc~0); 749982#L447-9 is_transmit4_triggered_~__retres1~4#1 := 0; 749981#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 749980#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 749979#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 749978#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 749977#L456-9 assume !(1 == ~t5_pc~0); 749976#L466-9 is_transmit5_triggered_~__retres1~5#1 := 0; 749975#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 749974#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 749973#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 749972#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 749971#L475-9 assume !(1 == ~t6_pc~0); 749970#L485-9 is_transmit6_triggered_~__retres1~6#1 := 0; 749969#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 749968#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 749967#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 749966#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 749965#L494-9 assume !(1 == ~t7_pc~0); 749964#L504-9 is_transmit7_triggered_~__retres1~7#1 := 0; 749963#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 749962#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 749961#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 749960#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 749959#L837-1 assume !(1 == ~M_E~0); 749958#L842-1 assume !(1 == ~T1_E~0); 749957#L847-1 assume !(1 == ~T2_E~0); 749955#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 749956#L857-1 assume !(1 == ~T4_E~0); 770444#L862-1 assume !(1 == ~T5_E~0); 770442#L867-1 assume !(1 == ~T6_E~0); 770440#L872-1 assume !(1 == ~T7_E~0); 770438#L877-1 assume !(1 == ~E_1~0); 770437#L882-1 assume !(1 == ~E_2~0); 770435#L887-1 assume !(1 == ~E_3~0); 770433#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 770431#L897-1 assume !(1 == ~E_5~0); 770429#L902-1 assume !(1 == ~E_6~0); 770427#L907-1 assume !(1 == ~E_7~0); 770174#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 770172#L1148 [2024-11-17 08:54:04,033 INFO L747 eck$LassoCheckResult]: Loop: 770172#L1148 assume true; 770170#L1148-1 assume !false; 770163#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 770160#L621 assume true; 770158#L621-1 assume !false; 770156#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 770142#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 770137#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 770135#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 770132#L626 assume !(0 != eval_~tmp~0#1); 770133#L629 assume true; 770418#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 770416#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 770412#L754 assume !(0 == ~M_E~0); 770411#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 770409#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 770406#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 770407#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 770514#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 770513#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 770512#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 770511#L794 assume !(0 == ~E_1~0); 770510#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 770509#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 770500#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 770498#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 770496#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 770493#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 770492#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 770490#L361-1 assume !(1 == ~m_pc~0); 770486#L371-1 is_master_triggered_~__retres1~0#1 := 0; 770483#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 770480#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 770477#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 770476#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 770474#L380-1 assume !(1 == ~t1_pc~0); 770473#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 770472#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 770471#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 770470#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 770469#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 770468#L399-1 assume !(1 == ~t2_pc~0); 770467#L409-1 is_transmit2_triggered_~__retres1~2#1 := 0; 770466#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 770465#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 770464#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 770463#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 770462#L418-1 assume !(1 == ~t3_pc~0); 770461#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 770460#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 770459#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 770458#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 770457#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 770456#L437-1 assume !(1 == ~t4_pc~0); 770455#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 770454#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 770453#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 770452#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 770451#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 770450#L456-1 assume !(1 == ~t5_pc~0); 770448#L466-1 is_transmit5_triggered_~__retres1~5#1 := 0; 770446#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 770445#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 770443#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 770441#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 770439#L475-1 assume !(1 == ~t6_pc~0); 768909#L485-1 is_transmit6_triggered_~__retres1~6#1 := 0; 770436#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 770434#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 770432#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 770430#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 770428#L494-1 assume !(1 == ~t7_pc~0); 770426#L504-1 is_transmit7_triggered_~__retres1~7#1 := 0; 770425#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 770424#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 770423#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 770422#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 770421#L837 assume 1 == ~M_E~0;~M_E~0 := 2; 770420#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 770419#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 770274#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 770272#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 770270#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 770268#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 770266#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 770264#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 770262#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 770260#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 770259#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 770257#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 770255#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 770253#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 770251#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 770243#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 770237#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 770235#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 770204#L1167 assume !(0 == start_simulation_~tmp~3#1); 770202#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 770190#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 770186#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 770184#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 770181#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 770179#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 770177#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 770175#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 770172#L1148 [2024-11-17 08:54:04,033 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:04,034 INFO L85 PathProgramCache]: Analyzing trace with hash 141807765, now seen corresponding path program 1 times [2024-11-17 08:54:04,034 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:04,034 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364661445] [2024-11-17 08:54:04,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:04,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:04,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,061 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1364661445] [2024-11-17 08:54:04,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1364661445] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,061 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,061 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:04,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206269415] [2024-11-17 08:54:04,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,062 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:04,062 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:04,062 INFO L85 PathProgramCache]: Analyzing trace with hash 1619290838, now seen corresponding path program 4 times [2024-11-17 08:54:04,062 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:04,062 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889907930] [2024-11-17 08:54:04,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:04,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:04,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,103 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,104 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889907930] [2024-11-17 08:54:04,104 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889907930] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,104 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,104 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:04,104 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1885351646] [2024-11-17 08:54:04,104 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,104 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:04,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:04,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:04,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:04,105 INFO L87 Difference]: Start difference. First operand 233580 states and 329291 transitions. cyclomatic complexity: 95967 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:05,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:05,735 INFO L93 Difference]: Finished difference Result 353897 states and 499501 transitions. [2024-11-17 08:54:05,735 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 353897 states and 499501 transitions. [2024-11-17 08:54:07,574 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 349504 [2024-11-17 08:54:08,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 353897 states to 353897 states and 499501 transitions. [2024-11-17 08:54:08,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 353897 [2024-11-17 08:54:08,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 353897 [2024-11-17 08:54:08,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 353897 states and 499501 transitions. [2024-11-17 08:54:08,871 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:08,872 INFO L218 hiAutomatonCegarLoop]: Abstraction has 353897 states and 499501 transitions. [2024-11-17 08:54:09,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353897 states and 499501 transitions. [2024-11-17 08:54:11,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353897 to 254749. [2024-11-17 08:54:11,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 254749 states, 254749 states have (on average 1.4172616968074458) internal successors, (361046), 254748 states have internal predecessors, (361046), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:13,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254749 states to 254749 states and 361046 transitions. [2024-11-17 08:54:13,144 INFO L240 hiAutomatonCegarLoop]: Abstraction has 254749 states and 361046 transitions. [2024-11-17 08:54:13,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:13,149 INFO L425 stractBuchiCegarLoop]: Abstraction has 254749 states and 361046 transitions. [2024-11-17 08:54:13,149 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:54:13,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 254749 states and 361046 transitions. [2024-11-17 08:54:13,745 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 251776 [2024-11-17 08:54:13,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:13,746 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:13,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:13,751 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:13,752 INFO L745 eck$LassoCheckResult]: Stem: 1337070#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1336456#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1336457#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1336841#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1336842#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1336737#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1336738#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1337118#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1337237#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1337115#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1337116#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1337220#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1337036#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1337037#L754-1 assume !(0 == ~M_E~0); 1337095#L759-1 assume !(0 == ~T1_E~0); 1337062#L764-1 assume !(0 == ~T2_E~0); 1337009#L769-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1337010#L774-1 assume !(0 == ~T4_E~0); 1337065#L779-1 assume !(0 == ~T5_E~0); 1337222#L784-1 assume !(0 == ~T6_E~0); 1337223#L789-1 assume !(0 == ~T7_E~0); 1337378#L794-1 assume !(0 == ~E_1~0); 1337358#L799-1 assume !(0 == ~E_2~0); 1337359#L804-1 assume !(0 == ~E_3~0); 1337060#L809-1 assume !(0 == ~E_4~0); 1337061#L814-1 assume !(0 == ~E_5~0); 1337377#L819-1 assume !(0 == ~E_6~0); 1337376#L824-1 assume !(0 == ~E_7~0); 1336780#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1336781#L361-9 assume !(1 == ~m_pc~0); 1336458#L371-9 is_master_triggered_~__retres1~0#1 := 0; 1336459#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1337188#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1337189#L930-9 assume !(0 != activate_threads_~tmp~1#1); 1337280#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1337105#L380-9 assume !(1 == ~t1_pc~0); 1337106#L390-9 is_transmit1_triggered_~__retres1~1#1 := 0; 1337042#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1337043#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1337334#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 1337335#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1337340#L399-9 assume !(1 == ~t2_pc~0); 1337341#L409-9 is_transmit2_triggered_~__retres1~2#1 := 0; 1337235#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1337073#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1337074#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 1337245#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1337246#L418-9 assume !(1 == ~t3_pc~0); 1336922#L428-9 is_transmit3_triggered_~__retres1~3#1 := 0; 1336923#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1337179#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1337372#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 1336542#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1336543#L437-9 assume !(1 == ~t4_pc~0); 1336622#L447-9 is_transmit4_triggered_~__retres1~4#1 := 0; 1336819#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1336868#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1336869#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 1336427#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1336428#L456-9 assume !(1 == ~t5_pc~0); 1336469#L466-9 is_transmit5_triggered_~__retres1~5#1 := 0; 1336830#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1336831#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1336753#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 1336754#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1337366#L475-9 assume !(1 == ~t6_pc~0); 1336739#L485-9 is_transmit6_triggered_~__retres1~6#1 := 0; 1336740#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1337365#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1336708#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 1336709#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1336512#L494-9 assume !(1 == ~t7_pc~0); 1336513#L504-9 is_transmit7_triggered_~__retres1~7#1 := 0; 1336916#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1336917#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1337144#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 1337015#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1337016#L837-1 assume !(1 == ~M_E~0); 1337126#L842-1 assume !(1 == ~T1_E~0); 1336837#L847-1 assume !(1 == ~T2_E~0); 1336838#L852-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1336919#L857-1 assume !(1 == ~T4_E~0); 1336795#L862-1 assume !(1 == ~T5_E~0); 1336796#L867-1 assume !(1 == ~T6_E~0); 1336803#L872-1 assume !(1 == ~T7_E~0); 1336873#L877-1 assume !(1 == ~E_1~0); 1337078#L882-1 assume !(1 == ~E_2~0); 1337264#L887-1 assume !(1 == ~E_3~0); 1337157#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1337158#L897-1 assume !(1 == ~E_5~0); 1336817#L902-1 assume !(1 == ~E_6~0); 1336818#L907-1 assume !(1 == ~E_7~0); 1337135#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 1337136#L1148 [2024-11-17 08:54:13,752 INFO L747 eck$LassoCheckResult]: Loop: 1337136#L1148 assume true; 1425259#L1148-1 assume !false; 1425253#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1425249#L621 assume true; 1425248#L621-1 assume !false; 1425247#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1425153#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1425144#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1425140#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1425119#L626 assume !(0 != eval_~tmp~0#1); 1425120#L629 assume true; 1507530#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1507523#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1507516#L754 assume !(0 == ~M_E~0); 1507509#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1507497#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1447336#L769 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1447335#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1447333#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1447329#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1447327#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1447325#L794 assume !(0 == ~E_1~0); 1447323#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 1447322#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 1447321#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 1447320#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 1447319#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 1447318#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 1447309#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1447307#L361-1 assume !(1 == ~m_pc~0); 1447305#L371-1 is_master_triggered_~__retres1~0#1 := 0; 1447302#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1447301#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1447299#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1447295#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1447291#L380-1 assume !(1 == ~t1_pc~0); 1447290#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1447288#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1444529#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1444528#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1444527#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1444525#L399-1 assume !(1 == ~t2_pc~0); 1444524#L409-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1444522#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1444505#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1440779#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1440778#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1440777#L418-1 assume !(1 == ~t3_pc~0); 1440776#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1440775#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1440774#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1440773#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1440764#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1440762#L437-1 assume !(1 == ~t4_pc~0); 1440759#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1440760#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1473235#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1473233#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1473231#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1473229#L456-1 assume !(1 == ~t5_pc~0); 1440746#L466-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1440745#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1440743#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1440742#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1440740#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1440738#L475-1 assume !(1 == ~t6_pc~0); 1440737#L485-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1440736#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1440735#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1440734#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1440733#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1440732#L494-1 assume !(1 == ~t7_pc~0); 1440731#L504-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1440730#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1440729#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1440728#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1440727#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1440726#L837 assume !(1 == ~M_E~0); 1347528#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1440725#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1440723#L852 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1440719#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1440717#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1440715#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1440713#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1440712#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 1440711#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 1440710#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 1440709#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 1440708#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 1440707#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 1440706#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 1440705#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1440701#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1440688#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1440686#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1351087#L1167 assume !(0 == start_simulation_~tmp~3#1); 1351088#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1425277#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1425273#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1425271#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1425269#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1425267#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1425265#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1425263#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1337136#L1148 [2024-11-17 08:54:13,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:13,752 INFO L85 PathProgramCache]: Analyzing trace with hash -429443468, now seen corresponding path program 1 times [2024-11-17 08:54:13,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:13,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487576150] [2024-11-17 08:54:13,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:13,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:13,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:13,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:13,799 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:13,799 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487576150] [2024-11-17 08:54:13,799 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487576150] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:13,800 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:13,800 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:13,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100986845] [2024-11-17 08:54:13,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:13,800 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:13,800 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:13,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1364554293, now seen corresponding path program 1 times [2024-11-17 08:54:13,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:13,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [809377709] [2024-11-17 08:54:13,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:13,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:13,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:13,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:13,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:13,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [809377709] [2024-11-17 08:54:13,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [809377709] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:13,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:13,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:13,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [783543870] [2024-11-17 08:54:13,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:13,837 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:13,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:13,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:54:13,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:54:13,838 INFO L87 Difference]: Start difference. First operand 254749 states and 361046 transitions. cyclomatic complexity: 106425 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:15,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:15,575 INFO L93 Difference]: Finished difference Result 319005 states and 448319 transitions. [2024-11-17 08:54:15,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 319005 states and 448319 transitions. [2024-11-17 08:54:17,642 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 314688 [2024-11-17 08:54:18,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 319005 states to 319005 states and 448319 transitions. [2024-11-17 08:54:18,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 319005 [2024-11-17 08:54:18,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 319005 [2024-11-17 08:54:18,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 319005 states and 448319 transitions. [2024-11-17 08:54:18,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:18,888 INFO L218 hiAutomatonCegarLoop]: Abstraction has 319005 states and 448319 transitions. [2024-11-17 08:54:19,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319005 states and 448319 transitions. [2024-11-17 08:54:21,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319005 to 219869. [2024-11-17 08:54:22,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219869 states, 219869 states have (on average 1.410580845867312) internal successors, (310143), 219868 states have internal predecessors, (310143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:22,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219869 states to 219869 states and 310143 transitions. [2024-11-17 08:54:22,834 INFO L240 hiAutomatonCegarLoop]: Abstraction has 219869 states and 310143 transitions. [2024-11-17 08:54:22,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:54:22,835 INFO L425 stractBuchiCegarLoop]: Abstraction has 219869 states and 310143 transitions. [2024-11-17 08:54:22,835 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:54:22,835 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 219869 states and 310143 transitions. [2024-11-17 08:54:23,390 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 216960 [2024-11-17 08:54:23,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:23,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:23,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:23,391 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:23,392 INFO L745 eck$LassoCheckResult]: Stem: 1910828#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1910221#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1910222#L1111 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1910606#L514-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1910607#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1910504#L526 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1910505#L531 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1910879#L536 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1910990#L541 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1910876#L546 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1910877#L551 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1910976#L556 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1910799#L562 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1910800#L754-1 assume !(0 == ~M_E~0); 1910854#L759-1 assume !(0 == ~T1_E~0); 1910822#L764-1 assume !(0 == ~T2_E~0); 1910780#L769-1 assume !(0 == ~T3_E~0); 1910781#L774-1 assume !(0 == ~T4_E~0); 1910823#L779-1 assume !(0 == ~T5_E~0); 1910979#L784-1 assume !(0 == ~T6_E~0); 1910777#L789-1 assume !(0 == ~T7_E~0); 1910778#L794-1 assume !(0 == ~E_1~0); 1910883#L799-1 assume !(0 == ~E_2~0); 1910788#L804-1 assume !(0 == ~E_3~0); 1910789#L809-1 assume !(0 == ~E_4~0); 1910821#L814-1 assume !(0 == ~E_5~0); 1910202#L819-1 assume !(0 == ~E_6~0); 1910203#L824-1 assume !(0 == ~E_7~0); 1910535#L830-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1910542#L361-9 assume !(1 == ~m_pc~0); 1910223#L371-9 is_master_triggered_~__retres1~0#1 := 0; 1910224#L364-9 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1910326#L373-9 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1910773#L930-9 assume !(0 != activate_threads_~tmp~1#1); 1910774#L936-9 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1910865#L380-9 assume !(1 == ~t1_pc~0); 1910866#L390-9 is_transmit1_triggered_~__retres1~1#1 := 0; 1910805#L383-9 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1910806#L392-9 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1910807#L938-9 assume !(0 != activate_threads_~tmp___0~0#1); 1910660#L944-9 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1910661#L399-9 assume !(1 == ~t2_pc~0); 1910529#L409-9 is_transmit2_triggered_~__retres1~2#1 := 0; 1910530#L402-9 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1910830#L411-9 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1910831#L946-9 assume !(0 != activate_threads_~tmp___1~0#1); 1910980#L952-9 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1910950#L418-9 assume !(1 == ~t3_pc~0); 1910688#L428-9 is_transmit3_triggered_~__retres1~3#1 := 0; 1910689#L421-9 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1910939#L430-9 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1910937#L954-9 assume !(0 != activate_threads_~tmp___2~0#1); 1910307#L960-9 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1910308#L437-9 assume !(1 == ~t4_pc~0); 1910390#L447-9 is_transmit4_triggered_~__retres1~4#1 := 0; 1910585#L440-9 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1910635#L449-9 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1910636#L962-9 assume !(0 != activate_threads_~tmp___3~0#1); 1910190#L968-9 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1910191#L456-9 assume !(1 == ~t5_pc~0); 1910234#L466-9 is_transmit5_triggered_~__retres1~5#1 := 0; 1910596#L459-9 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1910597#L468-9 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1910516#L970-9 assume !(0 != activate_threads_~tmp___4~0#1); 1910517#L976-9 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1910285#L475-9 assume !(1 == ~t6_pc~0); 1910286#L485-9 is_transmit6_triggered_~__retres1~6#1 := 0; 1910506#L478-9 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1910634#L487-9 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1910475#L978-9 assume !(0 != activate_threads_~tmp___5~0#1); 1910476#L984-9 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1910275#L494-9 assume !(1 == ~t7_pc~0); 1910276#L504-9 is_transmit7_triggered_~__retres1~7#1 := 0; 1910454#L497-9 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1910684#L506-9 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1910435#L986-9 assume !(0 != activate_threads_~tmp___6~0#1); 1910436#L992-9 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1910784#L837-1 assume !(1 == ~M_E~0); 1910884#L842-1 assume !(1 == ~T1_E~0); 1910603#L847-1 assume !(1 == ~T2_E~0); 1910604#L852-1 assume !(1 == ~T3_E~0); 1910685#L857-1 assume !(1 == ~T4_E~0); 1910556#L862-1 assume !(1 == ~T5_E~0); 1910557#L867-1 assume !(1 == ~T6_E~0); 1910568#L872-1 assume !(1 == ~T7_E~0); 1910639#L877-1 assume !(1 == ~E_1~0); 1910833#L882-1 assume !(1 == ~E_2~0); 1911016#L887-1 assume !(1 == ~E_3~0); 1910914#L892-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1910915#L897-1 assume !(1 == ~E_5~0); 1910583#L902-1 assume !(1 == ~E_6~0); 1910584#L907-1 assume !(1 == ~E_7~0); 1910892#L913-1 assume true;assume { :end_inline_reset_delta_events } true; 1910893#L1148 [2024-11-17 08:54:23,392 INFO L747 eck$LassoCheckResult]: Loop: 1910893#L1148 assume true; 1995052#L1148-1 assume !false; 1995046#start_simulation_while_10_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1995044#L621 assume true; 1995043#L621-1 assume !false; 1995042#eval_while_9_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1995036#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1995033#L599-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1995032#L612-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1995030#L626 assume !(0 != eval_~tmp~0#1); 1995031#L629 assume true; 2112494#L747 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2112491#L514 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2112489#L754 assume !(0 == ~M_E~0); 2112487#L759 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2112485#L764 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2112483#L769 assume !(0 == ~T3_E~0); 2112481#L774 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2112479#L779 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2112477#L784 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2112475#L789 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2112473#L794 assume !(0 == ~E_1~0); 2112471#L799 assume 0 == ~E_2~0;~E_2~0 := 1; 2112469#L804 assume 0 == ~E_3~0;~E_3~0 := 1; 2112466#L809 assume 0 == ~E_4~0;~E_4~0 := 1; 2112464#L814 assume 0 == ~E_5~0;~E_5~0 := 1; 2112462#L819 assume 0 == ~E_6~0;~E_6~0 := 1; 2112460#L824 assume 0 == ~E_7~0;~E_7~0 := 1; 2112458#L830 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2112456#L361-1 assume !(1 == ~m_pc~0); 2112453#L371-1 is_master_triggered_~__retres1~0#1 := 0; 2112451#L364-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2112449#L373-1 assume true;activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2112447#L930-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2112445#L936-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2112443#L380-1 assume !(1 == ~t1_pc~0); 2112440#L390-1 is_transmit1_triggered_~__retres1~1#1 := 0; 2112438#L383-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2112436#L392-1 assume true;activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2112434#L938-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2112432#L944-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2112430#L399-1 assume !(1 == ~t2_pc~0); 2112428#L409-1 is_transmit2_triggered_~__retres1~2#1 := 0; 2112426#L402-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2112424#L411-1 assume true;activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2112422#L946-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2112420#L952-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2112417#L418-1 assume !(1 == ~t3_pc~0); 2112415#L428-1 is_transmit3_triggered_~__retres1~3#1 := 0; 2112413#L421-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2112411#L430-1 assume true;activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2112409#L954-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2112408#L960-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2112405#L437-1 assume !(1 == ~t4_pc~0); 2112404#L447-1 is_transmit4_triggered_~__retres1~4#1 := 0; 2112403#L440-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2112402#L449-1 assume true;activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2112401#L962-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2112400#L968-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2112398#L456-1 assume !(1 == ~t5_pc~0); 2112396#L466-1 is_transmit5_triggered_~__retres1~5#1 := 0; 2112394#L459-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2112392#L468-1 assume true;activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2112391#L970-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2112389#L976-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2105788#L475-1 assume !(1 == ~t6_pc~0); 2105786#L485-1 is_transmit6_triggered_~__retres1~6#1 := 0; 2105784#L478-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2105782#L487-1 assume true;activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2105780#L978-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2105778#L984-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2105776#L494-1 assume !(1 == ~t7_pc~0); 2105774#L504-1 is_transmit7_triggered_~__retres1~7#1 := 0; 2105772#L497-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2105770#L506-1 assume true;activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2105768#L986-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2105766#L992-1 assume true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2105764#L837 assume !(1 == ~M_E~0); 1922740#L842 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2105760#L847 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2105758#L852 assume !(1 == ~T3_E~0); 2105756#L857 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2105754#L862 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2105752#L867 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2105750#L872 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2105748#L877 assume 1 == ~E_1~0;~E_1~0 := 2; 2105746#L882 assume 1 == ~E_2~0;~E_2~0 := 2; 2105744#L887 assume 1 == ~E_3~0;~E_3~0 := 2; 2105742#L892 assume 1 == ~E_4~0;~E_4~0 := 2; 2105740#L897 assume 1 == ~E_5~0;~E_5~0 := 2; 2105738#L902 assume 1 == ~E_6~0;~E_6~0 := 2; 2105737#L907 assume 1 == ~E_7~0;~E_7~0 := 2; 2105735#L913 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2007302#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2007296#L599-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2007295#L612-1 assume true;start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1937190#L1167 assume !(0 == start_simulation_~tmp~3#1); 1937191#L1178 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1995071#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1995067#L599 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1995065#L612 assume true;stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1995063#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1995061#L1124 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1995059#L1130 assume true;start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1995058#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1910893#L1148 [2024-11-17 08:54:23,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:23,393 INFO L85 PathProgramCache]: Analyzing trace with hash -709313674, now seen corresponding path program 1 times [2024-11-17 08:54:23,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:23,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960891115] [2024-11-17 08:54:23,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:23,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:23,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:23,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:23,435 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:23,435 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960891115] [2024-11-17 08:54:23,435 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1960891115] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:23,435 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:23,435 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:23,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402561542] [2024-11-17 08:54:23,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:23,436 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:23,436 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:23,436 INFO L85 PathProgramCache]: Analyzing trace with hash -1098021833, now seen corresponding path program 1 times [2024-11-17 08:54:23,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:23,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697647977] [2024-11-17 08:54:23,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:23,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:23,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:23,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:23,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:23,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697647977] [2024-11-17 08:54:23,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697647977] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:23,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:23,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:23,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509788834] [2024-11-17 08:54:23,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:23,472 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:23,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:23,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:54:23,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:54:23,472 INFO L87 Difference]: Start difference. First operand 219869 states and 310143 transitions. cyclomatic complexity: 90402 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:25,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:25,080 INFO L93 Difference]: Finished difference Result 350305 states and 490266 transitions. [2024-11-17 08:54:25,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350305 states and 490266 transitions.