./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.10.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.10.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:53:42,004 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:53:42,072 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:53:42,077 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:53:42,078 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:53:42,078 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:53:42,101 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:53:42,103 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:53:42,103 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:53:42,105 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:53:42,105 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:53:42,106 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:53:42,107 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:53:42,107 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:53:42,110 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:53:42,110 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:53:42,111 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:53:42,111 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:53:42,111 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:53:42,111 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:53:42,112 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:53:42,112 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:53:42,112 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:53:42,112 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:53:42,113 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:53:42,113 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:53:42,113 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:53:42,113 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:53:42,114 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:53:42,114 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:53:42,114 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:53:42,114 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:53:42,114 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:53:42,115 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:53:42,115 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:53:42,115 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:53:42,115 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:53:42,115 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:53:42,116 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:53:42,116 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:53:42,117 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 [2024-11-17 08:53:42,388 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:53:42,414 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:53:42,418 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:53:42,420 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:53:42,420 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:53:42,421 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.10.cil.c [2024-11-17 08:53:43,880 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:53:44,113 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:53:44,113 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.10.cil.c [2024-11-17 08:53:44,126 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ac4cdfeed/8d625e647cb44ded99d47b884ced1494/FLAGfdafde9a6 [2024-11-17 08:53:44,141 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ac4cdfeed/8d625e647cb44ded99d47b884ced1494 [2024-11-17 08:53:44,143 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:53:44,144 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:53:44,145 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:44,145 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:53:44,150 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:53:44,151 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,151 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2b580abc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44, skipping insertion in model container [2024-11-17 08:53:44,152 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,196 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:53:44,524 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:44,545 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:53:44,613 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:44,639 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:53:44,640 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44 WrapperNode [2024-11-17 08:53:44,640 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:44,641 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:44,641 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:53:44,641 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:53:44,648 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,660 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,738 INFO L138 Inliner]: procedures = 48, calls = 61, calls flagged for inlining = 56, calls inlined = 197, statements flattened = 3002 [2024-11-17 08:53:44,739 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:44,739 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:53:44,740 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:53:44,740 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:53:44,750 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,750 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,764 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,801 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:53:44,801 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,801 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,829 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,833 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,838 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,847 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,860 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:53:44,865 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:53:44,868 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:53:44,868 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:53:44,869 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (1/1) ... [2024-11-17 08:53:44,880 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:53:44,891 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:53:44,907 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:53:44,914 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:53:45,001 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:53:45,005 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:53:45,005 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:53:45,006 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:53:45,197 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:53:45,199 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:53:47,294 INFO L? ?]: Removed 618 outVars from TransFormulas that were not future-live. [2024-11-17 08:53:47,295 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:53:47,344 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:53:47,344 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:53:47,345 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:47 BoogieIcfgContainer [2024-11-17 08:53:47,345 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:53:47,346 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:53:47,347 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:53:47,351 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:53:47,353 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:47,353 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:53:44" (1/3) ... [2024-11-17 08:53:47,354 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7bdae38c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:47, skipping insertion in model container [2024-11-17 08:53:47,354 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:47,354 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:44" (2/3) ... [2024-11-17 08:53:47,355 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7bdae38c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:47, skipping insertion in model container [2024-11-17 08:53:47,355 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:47,355 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:47" (3/3) ... [2024-11-17 08:53:47,357 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.10.cil.c [2024-11-17 08:53:47,449 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:53:47,450 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:53:47,450 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:53:47,450 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:53:47,450 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:53:47,450 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:53:47,451 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:53:47,451 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:53:47,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1348 states, 1347 states have (on average 1.4855233853006682) internal successors, (2001), 1347 states have internal predecessors, (2001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:47,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1206 [2024-11-17 08:53:47,530 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:47,530 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:47,550 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,551 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,551 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:53:47,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1348 states, 1347 states have (on average 1.4855233853006682) internal successors, (2001), 1347 states have internal predecessors, (2001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:47,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1206 [2024-11-17 08:53:47,589 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:47,589 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:47,592 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,594 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:47,607 INFO L745 eck$LassoCheckResult]: Stem: 663#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 20#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1159#L1483true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1326#L694-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1337#L701true assume !(1 == ~m_i~0);~m_st~0 := 2; 1323#L706true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 203#L711true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 733#L716true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 90#L721true assume 1 == ~t4_i~0;~t4_st~0 := 0; 618#L726true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1108#L731true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 195#L736true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 131#L741true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 458#L746true assume !(1 == ~t9_i~0);~t9_st~0 := 2; 17#L751true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 49#L757true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 660#L1006-1true assume 0 == ~M_E~0;~M_E~0 := 1; 1022#L1011-1true assume !(0 == ~T1_E~0); 1058#L1016-1true assume !(0 == ~T2_E~0); 1236#L1021-1true assume !(0 == ~T3_E~0); 16#L1026-1true assume !(0 == ~T4_E~0); 1304#L1031-1true assume !(0 == ~T5_E~0); 594#L1036-1true assume !(0 == ~T6_E~0); 591#L1041-1true assume !(0 == ~T7_E~0); 945#L1046-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 177#L1051-1true assume !(0 == ~T9_E~0); 735#L1056-1true assume !(0 == ~T10_E~0); 784#L1061-1true assume !(0 == ~E_1~0); 128#L1066-1true assume !(0 == ~E_2~0); 1104#L1071-1true assume !(0 == ~E_3~0); 713#L1076-1true assume !(0 == ~E_4~0); 69#L1081-1true assume !(0 == ~E_5~0); 285#L1086-1true assume 0 == ~E_6~0;~E_6~0 := 1; 1121#L1091-1true assume !(0 == ~E_7~0); 999#L1096-1true assume !(0 == ~E_8~0); 1241#L1101-1true assume !(0 == ~E_9~0); 324#L1106-1true assume !(0 == ~E_10~0); 526#L1112-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 254#L484-12true assume 1 == ~m_pc~0; 716#L485-12true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1052#L487-12true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 567#L496-12true assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27#L1245-12true assume !(0 != activate_threads_~tmp~1#1); 169#L1251-12true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 741#L503-12true assume 1 == ~t1_pc~0; 207#L504-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1291#L506-12true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1316#L515-12true assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 521#L1253-12true assume !(0 != activate_threads_~tmp___0~0#1); 682#L1259-12true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 405#L522-12true assume 1 == ~t2_pc~0; 912#L523-12true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 263#L525-12true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 454#L534-12true assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1235#L1261-12true assume !(0 != activate_threads_~tmp___1~0#1); 452#L1267-12true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1252#L541-12true assume !(1 == ~t3_pc~0); 264#L551-12true is_transmit3_triggered_~__retres1~3#1 := 0; 921#L544-12true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 199#L553-12true assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1094#L1269-12true assume !(0 != activate_threads_~tmp___2~0#1); 255#L1275-12true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 728#L560-12true assume 1 == ~t4_pc~0; 808#L561-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 537#L563-12true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 441#L572-12true assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 652#L1277-12true assume !(0 != activate_threads_~tmp___3~0#1); 1244#L1283-12true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 578#L579-12true assume 1 == ~t5_pc~0; 720#L580-12true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 230#L582-12true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 685#L591-12true assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 766#L1285-12true assume !(0 != activate_threads_~tmp___4~0#1); 545#L1291-12true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1205#L598-12true assume 1 == ~t6_pc~0; 86#L599-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 980#L601-12true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 645#L610-12true assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1341#L1293-12true assume !(0 != activate_threads_~tmp___5~0#1); 1251#L1299-12true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1332#L617-12true assume !(1 == ~t7_pc~0); 24#L627-12true is_transmit7_triggered_~__retres1~7#1 := 0; 499#L620-12true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 316#L629-12true assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 706#L1301-12true assume !(0 != activate_threads_~tmp___6~0#1); 854#L1307-12true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1001#L636-12true assume 1 == ~t8_pc~0; 882#L637-12true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1089#L639-12true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 536#L648-12true assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 707#L1309-12true assume !(0 != activate_threads_~tmp___7~0#1); 514#L1315-12true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1177#L655-12true assume 1 == ~t9_pc~0; 686#L656-12true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 64#L658-12true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 164#L667-12true assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 698#L1317-12true assume !(0 != activate_threads_~tmp___8~0#1); 239#L1323-12true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 849#L674-12true assume 1 == ~t10_pc~0; 965#L675-12true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1156#L677-12true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 893#L686-12true assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 227#L1325-12true assume !(0 != activate_threads_~tmp___9~0#1); 1128#L1331-12true assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1270#L1119-1true assume !(1 == ~M_E~0); 375#L1124-1true assume !(1 == ~T1_E~0); 29#L1129-1true assume !(1 == ~T2_E~0); 568#L1134-1true assume !(1 == ~T3_E~0); 200#L1139-1true assume !(1 == ~T4_E~0); 339#L1144-1true assume !(1 == ~T5_E~0); 1313#L1149-1true assume !(1 == ~T6_E~0); 115#L1154-1true assume !(1 == ~T7_E~0); 166#L1159-1true assume !(1 == ~T8_E~0); 1287#L1164-1true assume !(1 == ~T9_E~0); 466#L1169-1true assume !(1 == ~T10_E~0); 365#L1174-1true assume !(1 == ~E_1~0); 231#L1179-1true assume !(1 == ~E_2~0); 158#L1184-1true assume !(1 == ~E_3~0); 196#L1189-1true assume !(1 == ~E_4~0); 274#L1194-1true assume !(1 == ~E_5~0); 1324#L1199-1true assume !(1 == ~E_6~0); 243#L1204-1true assume !(1 == ~E_7~0); 1182#L1209-1true assume !(1 == ~E_8~0); 661#L1214-1true assume !(1 == ~E_9~0); 1283#L1219-1true assume !(1 == ~E_10~0); 941#L1225-1true assume true;assume { :end_inline_reset_delta_events } true; 865#L1520true [2024-11-17 08:53:47,609 INFO L747 eck$LassoCheckResult]: Loop: 865#L1520true assume true; 915#L1520-1true assume !false; 298#start_simulation_while_13_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 620#L831true assume !true; 381#L839true assume true; 1334#L999true assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1097#L694true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 827#L1006true assume 0 == ~M_E~0;~M_E~0 := 1; 252#L1011true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1186#L1016true assume 0 == ~T2_E~0;~T2_E~0 := 1; 611#L1021true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1288#L1026true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1098#L1031true assume 0 == ~T5_E~0;~T5_E~0 := 1; 47#L1036true assume 0 == ~T6_E~0;~T6_E~0 := 1; 646#L1041true assume !(0 == ~T7_E~0); 58#L1046true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1207#L1051true assume 0 == ~T9_E~0;~T9_E~0 := 1; 223#L1056true assume 0 == ~T10_E~0;~T10_E~0 := 1; 813#L1061true assume 0 == ~E_1~0;~E_1~0 := 1; 985#L1066true assume 0 == ~E_2~0;~E_2~0 := 1; 764#L1071true assume 0 == ~E_3~0;~E_3~0 := 1; 1152#L1076true assume 0 == ~E_4~0;~E_4~0 := 1; 1200#L1081true assume !(0 == ~E_5~0); 792#L1086true assume 0 == ~E_6~0;~E_6~0 := 1; 755#L1091true assume 0 == ~E_7~0;~E_7~0 := 1; 144#L1096true assume 0 == ~E_8~0;~E_8~0 := 1; 78#L1101true assume 0 == ~E_9~0;~E_9~0 := 1; 1293#L1106true assume 0 == ~E_10~0;~E_10~0 := 1; 1264#L1112true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1118#L484-1true assume !(1 == ~m_pc~0); 812#L494-1true is_master_triggered_~__retres1~0#1 := 0; 830#L487-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 886#L496-1true assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 422#L1245-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 619#L1251-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 226#L503-1true assume !(1 == ~t1_pc~0); 1011#L513-1true is_transmit1_triggered_~__retres1~1#1 := 0; 1279#L506-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1009#L515-1true assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 727#L1253-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 54#L1259-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 700#L522-1true assume 1 == ~t2_pc~0; 599#L523-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 730#L525-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 517#L534-1true assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10#L1261-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 425#L1267-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 434#L541-1true assume !(1 == ~t3_pc~0); 1017#L551-1true is_transmit3_triggered_~__retres1~3#1 := 0; 1114#L544-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 623#L553-1true assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1338#L1269-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 108#L1275-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1315#L560-1true assume !(1 == ~t4_pc~0); 828#L570-1true is_transmit4_triggered_~__retres1~4#1 := 0; 1188#L563-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 776#L572-1true assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 688#L1277-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 282#L1283-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 162#L579-1true assume 1 == ~t5_pc~0; 502#L580-1true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1031#L582-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 968#L591-1true assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1163#L1285-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 350#L1291-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 777#L598-1true assume 1 == ~t6_pc~0; 869#L599-1true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 382#L601-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 705#L610-1true assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 844#L1293-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 790#L1299-1true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 143#L617-1true assume 1 == ~t7_pc~0; 904#L618-1true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 290#L620-1true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1292#L629-1true assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 938#L1301-1true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 390#L1307-1true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 180#L636-1true assume !(1 == ~t8_pc~0); 863#L646-1true is_transmit8_triggered_~__retres1~8#1 := 0; 401#L639-1true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1095#L648-1true assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1157#L1309-1true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 101#L1315-1true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 870#L655-1true assume 1 == ~t9_pc~0; 1189#L656-1true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1172#L658-1true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 293#L667-1true assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 738#L1317-1true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 222#L1323-1true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 439#L674-1true assume 1 == ~t10_pc~0; 932#L675-1true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 150#L677-1true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 280#L686-1true assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 817#L1325-1true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 182#L1331-1true assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 940#L1119true assume 1 == ~M_E~0;~M_E~0 := 2; 465#L1124true assume 1 == ~T1_E~0;~T1_E~0 := 2; 394#L1129true assume 1 == ~T2_E~0;~T2_E~0 := 2; 771#L1134true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1239#L1139true assume 1 == ~T4_E~0;~T4_E~0 := 2; 486#L1144true assume 1 == ~T5_E~0;~T5_E~0 := 2; 14#L1149true assume 1 == ~T6_E~0;~T6_E~0 := 2; 684#L1154true assume 1 == ~T7_E~0;~T7_E~0 := 2; 846#L1159true assume 1 == ~T8_E~0;~T8_E~0 := 2; 946#L1164true assume 1 == ~T9_E~0;~T9_E~0 := 2; 501#L1169true assume 1 == ~T10_E~0;~T10_E~0 := 2; 360#L1174true assume 1 == ~E_1~0;~E_1~0 := 2; 651#L1179true assume 1 == ~E_2~0;~E_2~0 := 2; 919#L1184true assume 1 == ~E_3~0;~E_3~0 := 2; 957#L1189true assume 1 == ~E_4~0;~E_4~0 := 2; 469#L1194true assume 1 == ~E_5~0;~E_5~0 := 2; 449#L1199true assume 1 == ~E_6~0;~E_6~0 := 2; 621#L1204true assume 1 == ~E_7~0;~E_7~0 := 2; 1247#L1209true assume 1 == ~E_8~0;~E_8~0 := 2; 804#L1214true assume 1 == ~E_9~0;~E_9~0 := 2; 1130#L1219true assume 1 == ~E_10~0;~E_10~0 := 2; 654#L1225true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 640#L764-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 593#L806-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 268#L822-1true assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 322#L1539true assume !(0 == start_simulation_~tmp~3#1); 1003#L1550true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1344#L764true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 238#L806true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 917#L822true assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 259#L1494true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 89#L1496true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 951#L1502true assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 323#L1552true assume !(0 != start_simulation_~tmp___0~1#1); 865#L1520true [2024-11-17 08:53:47,621 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:47,621 INFO L85 PathProgramCache]: Analyzing trace with hash -1955442626, now seen corresponding path program 1 times [2024-11-17 08:53:47,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:47,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402030056] [2024-11-17 08:53:47,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:47,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:47,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:47,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:47,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:47,990 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402030056] [2024-11-17 08:53:47,991 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402030056] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:47,991 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:47,991 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:47,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817752264] [2024-11-17 08:53:47,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:47,999 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:48,000 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:48,000 INFO L85 PathProgramCache]: Analyzing trace with hash 1839073750, now seen corresponding path program 1 times [2024-11-17 08:53:48,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:48,002 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841152202] [2024-11-17 08:53:48,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:48,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:48,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:48,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:48,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:48,061 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841152202] [2024-11-17 08:53:48,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841152202] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:48,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:48,062 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:48,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560734800] [2024-11-17 08:53:48,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:48,064 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:48,069 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:48,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:48,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:48,108 INFO L87 Difference]: Start difference. First operand has 1348 states, 1347 states have (on average 1.4855233853006682) internal successors, (2001), 1347 states have internal predecessors, (2001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:48,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:48,187 INFO L93 Difference]: Finished difference Result 1334 states and 1957 transitions. [2024-11-17 08:53:48,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1334 states and 1957 transitions. [2024-11-17 08:53:48,198 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:48,210 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1334 states to 1327 states and 1950 transitions. [2024-11-17 08:53:48,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1327 [2024-11-17 08:53:48,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1327 [2024-11-17 08:53:48,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1327 states and 1950 transitions. [2024-11-17 08:53:48,222 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:48,222 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1950 transitions. [2024-11-17 08:53:48,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states and 1950 transitions. [2024-11-17 08:53:48,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1327. [2024-11-17 08:53:48,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1327 states, 1327 states have (on average 1.46948003014318) internal successors, (1950), 1326 states have internal predecessors, (1950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:48,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1327 states to 1327 states and 1950 transitions. [2024-11-17 08:53:48,308 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1950 transitions. [2024-11-17 08:53:48,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:48,313 INFO L425 stractBuchiCegarLoop]: Abstraction has 1327 states and 1950 transitions. [2024-11-17 08:53:48,314 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:53:48,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1327 states and 1950 transitions. [2024-11-17 08:53:48,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:48,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:48,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:48,325 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:48,327 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:48,328 INFO L745 eck$LassoCheckResult]: Stem: 3722#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 2734#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2735#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3996#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4017#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 4016#L706 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 3099#L711 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3100#L716 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2879#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2880#L726 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3678#L731 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3084#L736 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2965#L741 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2966#L746 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 2727#L751 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2728#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2792#L1006-1 assume 0 == ~M_E~0;~M_E~0 := 1; 3717#L1011-1 assume !(0 == ~T1_E~0); 3951#L1016-1 assume !(0 == ~T2_E~0); 3962#L1021-1 assume !(0 == ~T3_E~0); 2725#L1026-1 assume !(0 == ~T4_E~0); 2726#L1031-1 assume !(0 == ~T5_E~0); 3653#L1036-1 assume !(0 == ~T6_E~0); 3647#L1041-1 assume !(0 == ~T7_E~0); 3648#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3050#L1051-1 assume !(0 == ~T9_E~0); 3051#L1056-1 assume !(0 == ~T10_E~0); 3777#L1061-1 assume !(0 == ~E_1~0); 2957#L1066-1 assume !(0 == ~E_2~0); 2958#L1071-1 assume !(0 == ~E_3~0); 3761#L1076-1 assume !(0 == ~E_4~0); 2833#L1081-1 assume !(0 == ~E_5~0); 2834#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3229#L1091-1 assume !(0 == ~E_7~0); 3940#L1096-1 assume !(0 == ~E_8~0); 3941#L1101-1 assume !(0 == ~E_9~0); 3292#L1106-1 assume !(0 == ~E_10~0); 3293#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3183#L484-12 assume 1 == ~m_pc~0; 3184#L485-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2784#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3630#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2750#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 2751#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3036#L503-12 assume 1 == ~t1_pc~0; 3104#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2695#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4013#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3579#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 3580#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3415#L522-12 assume 1 == ~t2_pc~0; 3416#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3195#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3196#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3484#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 3479#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3480#L541-12 assume !(1 == ~t3_pc~0); 3197#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 3198#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3089#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3090#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 3185#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3186#L560-12 assume 1 == ~t4_pc~0; 3773#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3595#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3465#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3466#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 3709#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3635#L579-12 assume 1 == ~t5_pc~0; 3636#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3149#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3150#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3738#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 3604#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3605#L598-12 assume 1 == ~t6_pc~0; 2874#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2875#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3701#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3702#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 4006#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4007#L617-12 assume !(1 == ~t7_pc~0); 2746#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 2747#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3282#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3283#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 3754#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3866#L636-12 assume 1 == ~t8_pc~0; 3881#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3842#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3593#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3594#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 3568#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3569#L655-12 assume 1 == ~t9_pc~0; 3740#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2824#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2825#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3030#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 3159#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3160#L674-12 assume 1 == ~t10_pc~0; 3863#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3529#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3887#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3142#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 3143#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3988#L1119-1 assume !(1 == ~M_E~0); 3380#L1124-1 assume !(1 == ~T1_E~0); 2752#L1129-1 assume !(1 == ~T2_E~0); 2753#L1134-1 assume !(1 == ~T3_E~0); 3091#L1139-1 assume !(1 == ~T4_E~0); 3092#L1144-1 assume !(1 == ~T5_E~0); 3319#L1149-1 assume !(1 == ~T6_E~0); 2932#L1154-1 assume !(1 == ~T7_E~0); 2933#L1159-1 assume !(1 == ~T8_E~0); 3032#L1164-1 assume !(1 == ~T9_E~0); 3495#L1169-1 assume !(1 == ~T10_E~0); 3362#L1174-1 assume !(1 == ~E_1~0); 3151#L1179-1 assume !(1 == ~E_2~0); 3015#L1184-1 assume !(1 == ~E_3~0); 3016#L1189-1 assume !(1 == ~E_4~0); 3085#L1194-1 assume !(1 == ~E_5~0); 3215#L1199-1 assume !(1 == ~E_6~0); 3165#L1204-1 assume !(1 == ~E_7~0); 3166#L1209-1 assume !(1 == ~E_8~0); 3718#L1214-1 assume !(1 == ~E_9~0); 3719#L1219-1 assume !(1 == ~E_10~0); 3912#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 3291#L1520 [2024-11-17 08:53:48,329 INFO L747 eck$LassoCheckResult]: Loop: 3291#L1520 assume true; 3870#L1520-1 assume !false; 3248#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3023#L831 assume true; 3610#L831-1 assume !false; 3611#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3498#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3277#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3431#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3432#L836 assume !(0 != eval_~tmp~0#1); 3384#L839 assume true; 3385#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3975#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3843#L1006 assume 0 == ~M_E~0;~M_E~0 := 1; 3181#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3182#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3671#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3672#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3978#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2785#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2786#L1041 assume !(0 == ~T7_E~0); 2808#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2809#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3137#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3138#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 3832#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 3801#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 3802#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 3995#L1081 assume !(0 == ~E_5~0); 3818#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 3794#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 2988#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 2852#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 2853#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 4010#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3985#L484-1 assume 1 == ~m_pc~0; 3654#L485-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3656#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3847#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3441#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3442#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3139#L503-1 assume 1 == ~t1_pc~0; 3140#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3816#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3948#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3771#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2802#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2803#L522-1 assume 1 == ~t2_pc~0; 3657#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3658#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3572#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2711#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2712#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3443#L541-1 assume 1 == ~t3_pc~0; 3112#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3113#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3681#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3682#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2916#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2917#L560-1 assume !(1 == ~t4_pc~0); 3844#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 3845#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3809#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3742#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3227#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3024#L579-1 assume 1 == ~t5_pc~0; 3025#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3547#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3926#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3927#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3334#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3335#L598-1 assume 1 == ~t6_pc~0; 3810#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3205#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3386#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3753#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3817#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2982#L617-1 assume 1 == ~t7_pc~0; 2983#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3236#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3237#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3909#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3396#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3054#L636-1 assume !(1 == ~t8_pc~0); 3056#L646-1 is_transmit8_triggered_~__retres1~8#1 := 0; 3408#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3409#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3974#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2899#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2900#L655-1 assume 1 == ~t9_pc~0; 3872#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3379#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3241#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3242#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3131#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3132#L674-1 assume 1 == ~t10_pc~0; 3462#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2999#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3000#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3221#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3059#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3060#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 3492#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3400#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3401#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3806#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3525#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2721#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2722#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3737#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3861#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3545#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3354#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 3355#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 3708#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 3900#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 3497#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 3476#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 3477#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 3679#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 3826#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 3827#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 3711#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3696#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2797#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3206#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3207#L1539 assume !(0 == start_simulation_~tmp~3#1); 3289#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3943#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2708#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3158#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3188#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2877#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2878#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3290#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 3291#L1520 [2024-11-17 08:53:48,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:48,332 INFO L85 PathProgramCache]: Analyzing trace with hash 1217245471, now seen corresponding path program 1 times [2024-11-17 08:53:48,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:48,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542041753] [2024-11-17 08:53:48,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:48,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:48,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:48,424 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:48,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:48,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542041753] [2024-11-17 08:53:48,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542041753] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:48,425 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:48,426 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:48,426 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556927710] [2024-11-17 08:53:48,426 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:48,426 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:48,427 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:48,427 INFO L85 PathProgramCache]: Analyzing trace with hash -559753082, now seen corresponding path program 1 times [2024-11-17 08:53:48,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:48,429 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554126111] [2024-11-17 08:53:48,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:48,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:48,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:48,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:48,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:48,610 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [554126111] [2024-11-17 08:53:48,610 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [554126111] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:48,610 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:48,610 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:48,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1835281453] [2024-11-17 08:53:48,611 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:48,611 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:48,611 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:48,612 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:48,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:48,612 INFO L87 Difference]: Start difference. First operand 1327 states and 1950 transitions. cyclomatic complexity: 624 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:48,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:48,639 INFO L93 Difference]: Finished difference Result 1327 states and 1949 transitions. [2024-11-17 08:53:48,639 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1327 states and 1949 transitions. [2024-11-17 08:53:48,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:48,656 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1327 states to 1327 states and 1949 transitions. [2024-11-17 08:53:48,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1327 [2024-11-17 08:53:48,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1327 [2024-11-17 08:53:48,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1327 states and 1949 transitions. [2024-11-17 08:53:48,662 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:48,662 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1949 transitions. [2024-11-17 08:53:48,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states and 1949 transitions. [2024-11-17 08:53:48,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1327. [2024-11-17 08:53:48,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1327 states, 1327 states have (on average 1.4687264506405426) internal successors, (1949), 1326 states have internal predecessors, (1949), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:48,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1327 states to 1327 states and 1949 transitions. [2024-11-17 08:53:48,688 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1949 transitions. [2024-11-17 08:53:48,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:48,692 INFO L425 stractBuchiCegarLoop]: Abstraction has 1327 states and 1949 transitions. [2024-11-17 08:53:48,692 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:53:48,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1327 states and 1949 transitions. [2024-11-17 08:53:48,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:48,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:48,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:48,703 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:48,703 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:48,703 INFO L745 eck$LassoCheckResult]: Stem: 6385#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 5397#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5398#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6659#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6680#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 6679#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5762#L711 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5763#L716 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5542#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5543#L726 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6341#L731 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5747#L736 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5628#L741 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5629#L746 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 5390#L751 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5391#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5455#L1006-1 assume 0 == ~M_E~0;~M_E~0 := 1; 6382#L1011-1 assume !(0 == ~T1_E~0); 6614#L1016-1 assume !(0 == ~T2_E~0); 6625#L1021-1 assume !(0 == ~T3_E~0); 5388#L1026-1 assume !(0 == ~T4_E~0); 5389#L1031-1 assume !(0 == ~T5_E~0); 6316#L1036-1 assume !(0 == ~T6_E~0); 6310#L1041-1 assume !(0 == ~T7_E~0); 6311#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5713#L1051-1 assume !(0 == ~T9_E~0); 5714#L1056-1 assume !(0 == ~T10_E~0); 6440#L1061-1 assume !(0 == ~E_1~0); 5620#L1066-1 assume !(0 == ~E_2~0); 5621#L1071-1 assume !(0 == ~E_3~0); 6424#L1076-1 assume !(0 == ~E_4~0); 5496#L1081-1 assume !(0 == ~E_5~0); 5497#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5892#L1091-1 assume !(0 == ~E_7~0); 6603#L1096-1 assume !(0 == ~E_8~0); 6604#L1101-1 assume !(0 == ~E_9~0); 5955#L1106-1 assume !(0 == ~E_10~0); 5956#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5846#L484-12 assume 1 == ~m_pc~0; 5847#L485-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5447#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6293#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5413#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 5414#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5699#L503-12 assume 1 == ~t1_pc~0; 5767#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5358#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6676#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6244#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 6245#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6078#L522-12 assume 1 == ~t2_pc~0; 6079#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5858#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5859#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6147#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 6144#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6145#L541-12 assume !(1 == ~t3_pc~0); 5860#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 5861#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5754#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5755#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 5848#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5849#L560-12 assume 1 == ~t4_pc~0; 6436#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6258#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6128#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6129#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 6372#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6298#L579-12 assume 1 == ~t5_pc~0; 6299#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5810#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5811#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6401#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 6267#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6268#L598-12 assume 1 == ~t6_pc~0; 5533#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5534#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6364#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6365#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 6669#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6670#L617-12 assume !(1 == ~t7_pc~0); 5405#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 5406#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5945#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5946#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 6417#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6529#L636-12 assume 1 == ~t8_pc~0; 6544#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6505#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6256#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6257#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 6229#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6230#L655-12 assume 1 == ~t9_pc~0; 6402#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5484#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5485#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5692#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 5822#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5823#L674-12 assume 1 == ~t10_pc~0; 6526#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6192#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6549#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5805#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 5806#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6650#L1119-1 assume !(1 == ~M_E~0); 6039#L1124-1 assume !(1 == ~T1_E~0); 5415#L1129-1 assume !(1 == ~T2_E~0); 5416#L1134-1 assume !(1 == ~T3_E~0); 5752#L1139-1 assume !(1 == ~T4_E~0); 5753#L1144-1 assume !(1 == ~T5_E~0); 5981#L1149-1 assume !(1 == ~T6_E~0); 5593#L1154-1 assume !(1 == ~T7_E~0); 5594#L1159-1 assume !(1 == ~T8_E~0); 5694#L1164-1 assume !(1 == ~T9_E~0); 6158#L1169-1 assume !(1 == ~T10_E~0); 6025#L1174-1 assume !(1 == ~E_1~0); 5812#L1179-1 assume !(1 == ~E_2~0); 5678#L1184-1 assume !(1 == ~E_3~0); 5679#L1189-1 assume !(1 == ~E_4~0); 5748#L1194-1 assume !(1 == ~E_5~0); 5878#L1199-1 assume !(1 == ~E_6~0); 5828#L1204-1 assume !(1 == ~E_7~0); 5829#L1209-1 assume !(1 == ~E_8~0); 6380#L1214-1 assume !(1 == ~E_9~0); 6381#L1219-1 assume !(1 == ~E_10~0); 6574#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 5954#L1520 [2024-11-17 08:53:48,709 INFO L747 eck$LassoCheckResult]: Loop: 5954#L1520 assume true; 6533#L1520-1 assume !false; 5911#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5683#L831 assume true; 6273#L831-1 assume !false; 6274#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6160#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5938#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6090#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6091#L836 assume !(0 != eval_~tmp~0#1); 6047#L839 assume true; 6048#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6638#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6506#L1006 assume 0 == ~M_E~0;~M_E~0 := 1; 5842#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5843#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6334#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6335#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6639#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5448#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5449#L1041 assume !(0 == ~T7_E~0); 5471#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5472#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5796#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5797#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 6495#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 6464#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 6465#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 6658#L1081 assume !(0 == ~E_5~0); 6481#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 6457#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 5651#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 5515#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 5516#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 6673#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6648#L484-1 assume 1 == ~m_pc~0; 6317#L485-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6319#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6510#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6104#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6105#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5802#L503-1 assume 1 == ~t1_pc~0; 5803#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6479#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6611#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6434#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5463#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5464#L522-1 assume 1 == ~t2_pc~0; 6320#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6321#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6235#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5374#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5375#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6108#L541-1 assume !(1 == ~t3_pc~0); 5777#L551-1 is_transmit3_triggered_~__retres1~3#1 := 0; 5776#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6344#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6345#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5579#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5580#L560-1 assume 1 == ~t4_pc~0; 6576#L561-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6508#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6472#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6405#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5890#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5687#L579-1 assume 1 == ~t5_pc~0; 5688#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6210#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6589#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6590#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5997#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5998#L598-1 assume 1 == ~t6_pc~0; 6473#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5868#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6049#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6416#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6480#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5648#L617-1 assume 1 == ~t7_pc~0; 5649#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5899#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5900#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6572#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6059#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5717#L636-1 assume 1 == ~t8_pc~0; 5718#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6074#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6075#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6637#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5563#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5564#L655-1 assume 1 == ~t9_pc~0; 6535#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6045#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5906#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5907#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5794#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5795#L674-1 assume 1 == ~t10_pc~0; 6125#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5665#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5666#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5887#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5722#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5723#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 6157#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6063#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6064#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6469#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6188#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5384#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5385#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6400#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6524#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6209#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6017#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 6018#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 6371#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 6563#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 6162#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 6139#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 6140#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 6342#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 6489#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 6490#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 6374#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6360#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5462#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5869#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5870#L1539 assume !(0 == start_simulation_~tmp~3#1); 5952#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6606#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5373#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5821#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 5851#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5540#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5541#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5953#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 5954#L1520 [2024-11-17 08:53:48,710 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:48,710 INFO L85 PathProgramCache]: Analyzing trace with hash -1174261730, now seen corresponding path program 1 times [2024-11-17 08:53:48,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:48,711 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1358810191] [2024-11-17 08:53:48,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:48,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:48,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:48,764 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:48,765 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:48,765 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1358810191] [2024-11-17 08:53:48,765 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1358810191] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:48,765 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:48,765 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:48,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [356349232] [2024-11-17 08:53:48,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:48,766 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:48,766 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:48,767 INFO L85 PathProgramCache]: Analyzing trace with hash -891002903, now seen corresponding path program 1 times [2024-11-17 08:53:48,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:48,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4572946] [2024-11-17 08:53:48,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:48,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:48,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:48,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:48,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:48,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [4572946] [2024-11-17 08:53:48,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [4572946] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:48,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:48,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:48,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [10287858] [2024-11-17 08:53:48,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:48,886 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:48,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:48,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:48,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:48,887 INFO L87 Difference]: Start difference. First operand 1327 states and 1949 transitions. cyclomatic complexity: 623 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:48,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:48,912 INFO L93 Difference]: Finished difference Result 1327 states and 1948 transitions. [2024-11-17 08:53:48,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1327 states and 1948 transitions. [2024-11-17 08:53:48,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:48,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1327 states to 1327 states and 1948 transitions. [2024-11-17 08:53:48,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1327 [2024-11-17 08:53:48,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1327 [2024-11-17 08:53:48,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1327 states and 1948 transitions. [2024-11-17 08:53:48,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:48,930 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1948 transitions. [2024-11-17 08:53:48,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states and 1948 transitions. [2024-11-17 08:53:48,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1327. [2024-11-17 08:53:48,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1327 states, 1327 states have (on average 1.467972871137905) internal successors, (1948), 1326 states have internal predecessors, (1948), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:48,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1327 states to 1327 states and 1948 transitions. [2024-11-17 08:53:48,952 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1948 transitions. [2024-11-17 08:53:48,952 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:48,954 INFO L425 stractBuchiCegarLoop]: Abstraction has 1327 states and 1948 transitions. [2024-11-17 08:53:48,954 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:53:48,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1327 states and 1948 transitions. [2024-11-17 08:53:48,961 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:48,961 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:48,961 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:48,964 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:48,964 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:48,964 INFO L745 eck$LassoCheckResult]: Stem: 9047#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 8060#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8061#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9322#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9343#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 9342#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8422#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8423#L716 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8205#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8206#L726 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9004#L731 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8410#L736 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8289#L741 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8290#L746 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 8053#L751 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8054#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8116#L1006-1 assume 0 == ~M_E~0;~M_E~0 := 1; 9043#L1011-1 assume !(0 == ~T1_E~0); 9277#L1016-1 assume !(0 == ~T2_E~0); 9288#L1021-1 assume !(0 == ~T3_E~0); 8051#L1026-1 assume !(0 == ~T4_E~0); 8052#L1031-1 assume !(0 == ~T5_E~0); 8976#L1036-1 assume !(0 == ~T6_E~0); 8973#L1041-1 assume !(0 == ~T7_E~0); 8974#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8374#L1051-1 assume !(0 == ~T9_E~0); 8375#L1056-1 assume !(0 == ~T10_E~0); 9103#L1061-1 assume !(0 == ~E_1~0); 8283#L1066-1 assume !(0 == ~E_2~0); 8284#L1071-1 assume !(0 == ~E_3~0); 9087#L1076-1 assume !(0 == ~E_4~0); 8159#L1081-1 assume !(0 == ~E_5~0); 8160#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 8555#L1091-1 assume !(0 == ~E_7~0); 9266#L1096-1 assume !(0 == ~E_8~0); 9267#L1101-1 assume !(0 == ~E_9~0); 8618#L1106-1 assume !(0 == ~E_10~0); 8619#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8509#L484-12 assume 1 == ~m_pc~0; 8510#L485-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8110#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8956#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8074#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 8075#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8361#L503-12 assume 1 == ~t1_pc~0; 8430#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8018#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9339#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8903#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 8904#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8741#L522-12 assume 1 == ~t2_pc~0; 8742#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8521#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8522#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8809#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 8805#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8806#L541-12 assume !(1 == ~t3_pc~0); 8523#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 8524#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8415#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8416#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 8511#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8512#L560-12 assume 1 == ~t4_pc~0; 9098#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8921#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8791#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8792#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 9035#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8961#L579-12 assume 1 == ~t5_pc~0; 8962#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8473#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8474#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9064#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 8930#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8931#L598-12 assume 1 == ~t6_pc~0; 8196#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8197#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9027#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9028#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 9332#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9333#L617-12 assume !(1 == ~t7_pc~0); 8068#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 8069#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8608#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8609#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 9080#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9192#L636-12 assume 1 == ~t8_pc~0; 9207#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9168#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8919#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8920#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 8892#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8893#L655-12 assume 1 == ~t9_pc~0; 9065#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8147#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8148#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8355#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 8485#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8486#L674-12 assume 1 == ~t10_pc~0; 9189#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8855#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9212#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8468#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 8469#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9313#L1119-1 assume !(1 == ~M_E~0); 8702#L1124-1 assume !(1 == ~T1_E~0); 8078#L1129-1 assume !(1 == ~T2_E~0); 8079#L1134-1 assume !(1 == ~T3_E~0); 8417#L1139-1 assume !(1 == ~T4_E~0); 8418#L1144-1 assume !(1 == ~T5_E~0); 8644#L1149-1 assume !(1 == ~T6_E~0); 8256#L1154-1 assume !(1 == ~T7_E~0); 8257#L1159-1 assume !(1 == ~T8_E~0); 8357#L1164-1 assume !(1 == ~T9_E~0); 8821#L1169-1 assume !(1 == ~T10_E~0); 8688#L1174-1 assume !(1 == ~E_1~0); 8475#L1179-1 assume !(1 == ~E_2~0); 8341#L1184-1 assume !(1 == ~E_3~0); 8342#L1189-1 assume !(1 == ~E_4~0); 8411#L1194-1 assume !(1 == ~E_5~0); 8541#L1199-1 assume !(1 == ~E_6~0); 8491#L1204-1 assume !(1 == ~E_7~0); 8492#L1209-1 assume !(1 == ~E_8~0); 9044#L1214-1 assume !(1 == ~E_9~0); 9045#L1219-1 assume !(1 == ~E_10~0); 9237#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 8617#L1520 [2024-11-17 08:53:48,965 INFO L747 eck$LassoCheckResult]: Loop: 8617#L1520 assume true; 9196#L1520-1 assume !false; 8574#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8346#L831 assume true; 8936#L831-1 assume !false; 8937#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8823#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8601#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8753#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8754#L836 assume !(0 != eval_~tmp~0#1); 8710#L839 assume true; 8711#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9301#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9169#L1006 assume 0 == ~M_E~0;~M_E~0 := 1; 8505#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8506#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8997#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8998#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9302#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8111#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8112#L1041 assume !(0 == ~T7_E~0); 8134#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8135#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8459#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8460#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 9158#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 9127#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 9128#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 9321#L1081 assume !(0 == ~E_5~0); 9144#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 9120#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 8314#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 8178#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 8179#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 9336#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9311#L484-1 assume 1 == ~m_pc~0; 8980#L485-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8982#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9173#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8767#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8768#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8465#L503-1 assume 1 == ~t1_pc~0; 8466#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9142#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9274#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9097#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8126#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8127#L522-1 assume 1 == ~t2_pc~0; 8983#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8984#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8898#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8037#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8038#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8771#L541-1 assume 1 == ~t3_pc~0; 8438#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8439#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9007#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9008#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8242#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8243#L560-1 assume !(1 == ~t4_pc~0); 9170#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 9171#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9135#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9068#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8553#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8350#L579-1 assume !(1 == ~t5_pc~0); 8352#L589-1 is_transmit5_triggered_~__retres1~5#1 := 0; 8873#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9252#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9253#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8661#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8662#L598-1 assume 1 == ~t6_pc~0; 9136#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8531#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8712#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9079#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9143#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8311#L617-1 assume 1 == ~t7_pc~0; 8312#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8562#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8563#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9235#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8722#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8380#L636-1 assume 1 == ~t8_pc~0; 8381#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8737#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8738#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9300#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8226#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8227#L655-1 assume !(1 == ~t9_pc~0); 8707#L665-1 is_transmit9_triggered_~__retres1~9#1 := 0; 8708#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8569#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8570#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8457#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8458#L674-1 assume 1 == ~t10_pc~0; 8788#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8328#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8329#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8550#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8385#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8386#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 8820#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8726#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8727#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9132#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8851#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8047#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8048#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9063#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9187#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8872#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8680#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 8681#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 9034#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 9226#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 8825#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 8802#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 8803#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 9005#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 9152#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 9153#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 9037#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9023#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8125#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8532#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 8533#L1539 assume !(0 == start_simulation_~tmp~3#1); 8615#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9269#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8036#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8484#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 8514#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8203#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8204#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8616#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 8617#L1520 [2024-11-17 08:53:48,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:48,966 INFO L85 PathProgramCache]: Analyzing trace with hash 1519539519, now seen corresponding path program 1 times [2024-11-17 08:53:48,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:48,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [636701572] [2024-11-17 08:53:48,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:48,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:48,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,018 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [636701572] [2024-11-17 08:53:49,018 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [636701572] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,018 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,018 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:49,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1149157003] [2024-11-17 08:53:49,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,020 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:49,020 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,020 INFO L85 PathProgramCache]: Analyzing trace with hash 307479523, now seen corresponding path program 1 times [2024-11-17 08:53:49,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212783863] [2024-11-17 08:53:49,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212783863] [2024-11-17 08:53:49,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212783863] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,130 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,130 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:49,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2091113458] [2024-11-17 08:53:49,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,131 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:49,131 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:49,131 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:49,131 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:49,132 INFO L87 Difference]: Start difference. First operand 1327 states and 1948 transitions. cyclomatic complexity: 622 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:49,154 INFO L93 Difference]: Finished difference Result 1327 states and 1947 transitions. [2024-11-17 08:53:49,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1327 states and 1947 transitions. [2024-11-17 08:53:49,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:49,171 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1327 states to 1327 states and 1947 transitions. [2024-11-17 08:53:49,171 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1327 [2024-11-17 08:53:49,172 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1327 [2024-11-17 08:53:49,172 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1327 states and 1947 transitions. [2024-11-17 08:53:49,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:49,174 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1947 transitions. [2024-11-17 08:53:49,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states and 1947 transitions. [2024-11-17 08:53:49,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1327. [2024-11-17 08:53:49,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1327 states, 1327 states have (on average 1.4672192916352675) internal successors, (1947), 1326 states have internal predecessors, (1947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1327 states to 1327 states and 1947 transitions. [2024-11-17 08:53:49,198 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1947 transitions. [2024-11-17 08:53:49,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:49,200 INFO L425 stractBuchiCegarLoop]: Abstraction has 1327 states and 1947 transitions. [2024-11-17 08:53:49,200 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:53:49,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1327 states and 1947 transitions. [2024-11-17 08:53:49,207 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:49,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:49,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:49,209 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,212 INFO L745 eck$LassoCheckResult]: Stem: 11711#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 10723#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 10724#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11985#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12006#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 12005#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11088#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11089#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10868#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10869#L726 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11667#L731 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11073#L736 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10954#L741 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10955#L746 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 10716#L751 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10717#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10781#L1006-1 assume 0 == ~M_E~0;~M_E~0 := 1; 11706#L1011-1 assume !(0 == ~T1_E~0); 11940#L1016-1 assume !(0 == ~T2_E~0); 11951#L1021-1 assume !(0 == ~T3_E~0); 10714#L1026-1 assume !(0 == ~T4_E~0); 10715#L1031-1 assume !(0 == ~T5_E~0); 11639#L1036-1 assume !(0 == ~T6_E~0); 11636#L1041-1 assume !(0 == ~T7_E~0); 11637#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11039#L1051-1 assume !(0 == ~T9_E~0); 11040#L1056-1 assume !(0 == ~T10_E~0); 11766#L1061-1 assume !(0 == ~E_1~0); 10946#L1066-1 assume !(0 == ~E_2~0); 10947#L1071-1 assume !(0 == ~E_3~0); 11750#L1076-1 assume !(0 == ~E_4~0); 10822#L1081-1 assume !(0 == ~E_5~0); 10823#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 11218#L1091-1 assume !(0 == ~E_7~0); 11929#L1096-1 assume !(0 == ~E_8~0); 11930#L1101-1 assume !(0 == ~E_9~0); 11281#L1106-1 assume !(0 == ~E_10~0); 11282#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11172#L484-12 assume 1 == ~m_pc~0; 11173#L485-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10773#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11619#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10739#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 10740#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11024#L503-12 assume 1 == ~t1_pc~0; 11093#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10684#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12002#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11568#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 11569#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11404#L522-12 assume 1 == ~t2_pc~0; 11405#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11184#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11185#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11472#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 11468#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11469#L541-12 assume !(1 == ~t3_pc~0); 11186#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 11187#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11078#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11079#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 11174#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11175#L560-12 assume 1 == ~t4_pc~0; 11761#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11584#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11454#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11455#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 11698#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11624#L579-12 assume 1 == ~t5_pc~0; 11625#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11138#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11139#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11727#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 11593#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11594#L598-12 assume 1 == ~t6_pc~0; 10861#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10862#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11690#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11691#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 11995#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11996#L617-12 assume !(1 == ~t7_pc~0); 10733#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 10734#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11271#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11272#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 11743#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11855#L636-12 assume 1 == ~t8_pc~0; 11870#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11831#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11582#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11583#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 11555#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11556#L655-12 assume 1 == ~t9_pc~0; 11729#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10813#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10814#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11019#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 11148#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11149#L674-12 assume 1 == ~t10_pc~0; 11852#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11518#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11876#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11131#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 11132#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11976#L1119-1 assume !(1 == ~M_E~0); 11369#L1124-1 assume !(1 == ~T1_E~0); 10741#L1129-1 assume !(1 == ~T2_E~0); 10742#L1134-1 assume !(1 == ~T3_E~0); 11080#L1139-1 assume !(1 == ~T4_E~0); 11081#L1144-1 assume !(1 == ~T5_E~0); 11308#L1149-1 assume !(1 == ~T6_E~0); 10919#L1154-1 assume !(1 == ~T7_E~0); 10920#L1159-1 assume !(1 == ~T8_E~0); 11021#L1164-1 assume !(1 == ~T9_E~0); 11484#L1169-1 assume !(1 == ~T10_E~0); 11351#L1174-1 assume !(1 == ~E_1~0); 11140#L1179-1 assume !(1 == ~E_2~0); 11004#L1184-1 assume !(1 == ~E_3~0); 11005#L1189-1 assume !(1 == ~E_4~0); 11074#L1194-1 assume !(1 == ~E_5~0); 11204#L1199-1 assume !(1 == ~E_6~0); 11154#L1204-1 assume !(1 == ~E_7~0); 11155#L1209-1 assume !(1 == ~E_8~0); 11707#L1214-1 assume !(1 == ~E_9~0); 11708#L1219-1 assume !(1 == ~E_10~0); 11900#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 11278#L1520 [2024-11-17 08:53:49,212 INFO L747 eck$LassoCheckResult]: Loop: 11278#L1520 assume true; 11859#L1520-1 assume !false; 11237#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11012#L831 assume true; 11599#L831-1 assume !false; 11600#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11487#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 11266#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11420#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11421#L836 assume !(0 != eval_~tmp~0#1); 11373#L839 assume true; 11374#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11964#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11832#L1006 assume 0 == ~M_E~0;~M_E~0 := 1; 11168#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11169#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11660#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11661#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11965#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10774#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10775#L1041 assume !(0 == ~T7_E~0); 10797#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10798#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11126#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11127#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 11821#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 11790#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 11791#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 11984#L1081 assume !(0 == ~E_5~0); 11807#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 11783#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 10977#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 10841#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 10842#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 11999#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11974#L484-1 assume 1 == ~m_pc~0; 11643#L485-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11645#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11836#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11430#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11431#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11128#L503-1 assume 1 == ~t1_pc~0; 11129#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11805#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11937#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11760#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10789#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10790#L522-1 assume !(1 == ~t2_pc~0); 11648#L532-1 is_transmit2_triggered_~__retres1~2#1 := 0; 11647#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11561#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10700#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10701#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11434#L541-1 assume 1 == ~t3_pc~0; 11101#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11102#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11670#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11671#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10905#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10906#L560-1 assume !(1 == ~t4_pc~0); 11833#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 11834#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11799#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11732#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11216#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11013#L579-1 assume 1 == ~t5_pc~0; 11014#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11536#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11915#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11916#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11323#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11324#L598-1 assume 1 == ~t6_pc~0; 11798#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11194#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11375#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11742#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11806#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10971#L617-1 assume 1 == ~t7_pc~0; 10972#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11223#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11224#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11898#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11385#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11041#L636-1 assume 1 == ~t8_pc~0; 11042#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11397#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11398#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11963#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10888#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10889#L655-1 assume 1 == ~t9_pc~0; 11861#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11368#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11230#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11231#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11120#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11121#L674-1 assume 1 == ~t10_pc~0; 11451#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10988#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10989#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11210#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11048#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11049#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 11481#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11389#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11390#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11795#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11514#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10710#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10711#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11726#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11850#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11534#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11343#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 11344#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 11697#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 11889#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 11486#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 11465#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 11466#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 11668#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 11815#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 11816#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 11699#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11685#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10786#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11195#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 11196#L1539 assume !(0 == start_simulation_~tmp~3#1); 11276#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11932#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10697#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 11147#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 11177#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10866#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10867#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 11277#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 11278#L1520 [2024-11-17 08:53:49,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,213 INFO L85 PathProgramCache]: Analyzing trace with hash -2134341634, now seen corresponding path program 1 times [2024-11-17 08:53:49,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,213 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143414268] [2024-11-17 08:53:49,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,266 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,266 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143414268] [2024-11-17 08:53:49,267 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143414268] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,267 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,267 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:49,267 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1803571905] [2024-11-17 08:53:49,267 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,268 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:49,268 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,268 INFO L85 PathProgramCache]: Analyzing trace with hash -1121096186, now seen corresponding path program 1 times [2024-11-17 08:53:49,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,268 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1528500281] [2024-11-17 08:53:49,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,356 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1528500281] [2024-11-17 08:53:49,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1528500281] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,357 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:49,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250188604] [2024-11-17 08:53:49,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,358 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:49,358 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:49,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:49,358 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:49,359 INFO L87 Difference]: Start difference. First operand 1327 states and 1947 transitions. cyclomatic complexity: 621 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:49,381 INFO L93 Difference]: Finished difference Result 1327 states and 1946 transitions. [2024-11-17 08:53:49,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1327 states and 1946 transitions. [2024-11-17 08:53:49,389 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:49,394 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1327 states to 1327 states and 1946 transitions. [2024-11-17 08:53:49,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1327 [2024-11-17 08:53:49,396 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1327 [2024-11-17 08:53:49,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1327 states and 1946 transitions. [2024-11-17 08:53:49,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:49,398 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1946 transitions. [2024-11-17 08:53:49,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states and 1946 transitions. [2024-11-17 08:53:49,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1327. [2024-11-17 08:53:49,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1327 states, 1327 states have (on average 1.4664657121326299) internal successors, (1946), 1326 states have internal predecessors, (1946), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1327 states to 1327 states and 1946 transitions. [2024-11-17 08:53:49,418 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1946 transitions. [2024-11-17 08:53:49,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:49,419 INFO L425 stractBuchiCegarLoop]: Abstraction has 1327 states and 1946 transitions. [2024-11-17 08:53:49,420 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:53:49,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1327 states and 1946 transitions. [2024-11-17 08:53:49,425 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:49,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:49,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:49,427 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,427 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,428 INFO L745 eck$LassoCheckResult]: Stem: 14374#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 13386#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 13387#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14648#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14669#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 14668#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13751#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13752#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13531#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13532#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14330#L731 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13736#L736 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13617#L741 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13618#L746 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 13379#L751 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13380#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13444#L1006-1 assume 0 == ~M_E~0;~M_E~0 := 1; 14369#L1011-1 assume !(0 == ~T1_E~0); 14603#L1016-1 assume !(0 == ~T2_E~0); 14614#L1021-1 assume !(0 == ~T3_E~0); 13377#L1026-1 assume !(0 == ~T4_E~0); 13378#L1031-1 assume !(0 == ~T5_E~0); 14305#L1036-1 assume !(0 == ~T6_E~0); 14299#L1041-1 assume !(0 == ~T7_E~0); 14300#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13702#L1051-1 assume !(0 == ~T9_E~0); 13703#L1056-1 assume !(0 == ~T10_E~0); 14429#L1061-1 assume !(0 == ~E_1~0); 13609#L1066-1 assume !(0 == ~E_2~0); 13610#L1071-1 assume !(0 == ~E_3~0); 14413#L1076-1 assume !(0 == ~E_4~0); 13485#L1081-1 assume !(0 == ~E_5~0); 13486#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 13881#L1091-1 assume !(0 == ~E_7~0); 14592#L1096-1 assume !(0 == ~E_8~0); 14593#L1101-1 assume !(0 == ~E_9~0); 13944#L1106-1 assume !(0 == ~E_10~0); 13945#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13835#L484-12 assume 1 == ~m_pc~0; 13836#L485-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13436#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14282#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13402#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 13403#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13688#L503-12 assume 1 == ~t1_pc~0; 13756#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13347#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14665#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14233#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 14234#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14067#L522-12 assume 1 == ~t2_pc~0; 14068#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13847#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13848#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14136#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 14133#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14134#L541-12 assume !(1 == ~t3_pc~0); 13849#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 13850#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13741#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13742#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 13837#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13838#L560-12 assume 1 == ~t4_pc~0; 14425#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14247#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14117#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14118#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 14361#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14287#L579-12 assume 1 == ~t5_pc~0; 14288#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13801#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13802#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14390#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 14256#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14257#L598-12 assume 1 == ~t6_pc~0; 13526#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13527#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14353#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14354#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 14658#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14659#L617-12 assume !(1 == ~t7_pc~0); 13398#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 13399#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13934#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13935#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 14406#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14518#L636-12 assume 1 == ~t8_pc~0; 14534#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14494#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14245#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14246#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 14220#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14221#L655-12 assume 1 == ~t9_pc~0; 14392#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13476#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13477#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13682#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 13812#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13813#L674-12 assume 1 == ~t10_pc~0; 14515#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 14181#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14539#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13794#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 13795#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14640#L1119-1 assume !(1 == ~M_E~0); 14032#L1124-1 assume !(1 == ~T1_E~0); 13404#L1129-1 assume !(1 == ~T2_E~0); 13405#L1134-1 assume !(1 == ~T3_E~0); 13743#L1139-1 assume !(1 == ~T4_E~0); 13744#L1144-1 assume !(1 == ~T5_E~0); 13971#L1149-1 assume !(1 == ~T6_E~0); 13586#L1154-1 assume !(1 == ~T7_E~0); 13587#L1159-1 assume !(1 == ~T8_E~0); 13684#L1164-1 assume !(1 == ~T9_E~0); 14147#L1169-1 assume !(1 == ~T10_E~0); 14014#L1174-1 assume !(1 == ~E_1~0); 13803#L1179-1 assume !(1 == ~E_2~0); 13667#L1184-1 assume !(1 == ~E_3~0); 13668#L1189-1 assume !(1 == ~E_4~0); 13738#L1194-1 assume !(1 == ~E_5~0); 13867#L1199-1 assume !(1 == ~E_6~0); 13820#L1204-1 assume !(1 == ~E_7~0); 13821#L1209-1 assume !(1 == ~E_8~0); 14370#L1214-1 assume !(1 == ~E_9~0); 14371#L1219-1 assume !(1 == ~E_10~0); 14564#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 13943#L1520 [2024-11-17 08:53:49,428 INFO L747 eck$LassoCheckResult]: Loop: 13943#L1520 assume true; 14522#L1520-1 assume !false; 13900#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13672#L831 assume true; 14262#L831-1 assume !false; 14263#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14150#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13929#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 14083#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14084#L836 assume !(0 != eval_~tmp~0#1); 14036#L839 assume true; 14037#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14627#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14495#L1006 assume 0 == ~M_E~0;~M_E~0 := 1; 13833#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13834#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14323#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14324#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14630#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13437#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13438#L1041 assume !(0 == ~T7_E~0); 13460#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13461#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13785#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13786#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 14484#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 14453#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 14454#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 14647#L1081 assume !(0 == ~E_5~0); 14470#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 14446#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 13640#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 13504#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 13505#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 14662#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14637#L484-1 assume 1 == ~m_pc~0; 14306#L485-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14308#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14499#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14093#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14094#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13791#L503-1 assume 1 == ~t1_pc~0; 13792#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14468#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14600#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14423#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13452#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13453#L522-1 assume 1 == ~t2_pc~0; 14309#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14310#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14224#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13363#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13364#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14097#L541-1 assume 1 == ~t3_pc~0; 13764#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13765#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14333#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14334#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13568#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13569#L560-1 assume !(1 == ~t4_pc~0); 14496#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 14497#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14461#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14394#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13879#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13676#L579-1 assume 1 == ~t5_pc~0; 13677#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14199#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14578#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14579#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13986#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13987#L598-1 assume !(1 == ~t6_pc~0); 13856#L608-1 is_transmit6_triggered_~__retres1~6#1 := 0; 13857#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14038#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14405#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 14469#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13635#L617-1 assume 1 == ~t7_pc~0; 13636#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13888#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13889#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14561#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14048#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13706#L636-1 assume 1 == ~t8_pc~0; 13707#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14063#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14064#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14626#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13552#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13553#L655-1 assume 1 == ~t9_pc~0; 14524#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 14031#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13893#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13894#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13783#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13784#L674-1 assume 1 == ~t10_pc~0; 14114#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13654#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13655#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13876#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13711#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13712#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 14146#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14052#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14053#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14458#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14177#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13373#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13374#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14389#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14513#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14198#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14006#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 14007#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 14360#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 14552#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 14149#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 14128#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 14129#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 14331#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 14478#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 14479#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 14363#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14349#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13451#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13858#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 13859#L1539 assume !(0 == start_simulation_~tmp~3#1); 13941#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 14595#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13362#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13810#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 13840#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13529#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13530#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 13942#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 13943#L1520 [2024-11-17 08:53:49,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,429 INFO L85 PathProgramCache]: Analyzing trace with hash 874143357, now seen corresponding path program 1 times [2024-11-17 08:53:49,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017721730] [2024-11-17 08:53:49,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,506 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2017721730] [2024-11-17 08:53:49,506 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2017721730] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,506 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,506 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:49,506 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190259728] [2024-11-17 08:53:49,506 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,507 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:49,507 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,507 INFO L85 PathProgramCache]: Analyzing trace with hash -819825402, now seen corresponding path program 1 times [2024-11-17 08:53:49,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,508 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609253759] [2024-11-17 08:53:49,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,509 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1609253759] [2024-11-17 08:53:49,596 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1609253759] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,596 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:49,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462019726] [2024-11-17 08:53:49,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,597 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:49,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:49,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:49,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:49,598 INFO L87 Difference]: Start difference. First operand 1327 states and 1946 transitions. cyclomatic complexity: 620 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:49,626 INFO L93 Difference]: Finished difference Result 1327 states and 1945 transitions. [2024-11-17 08:53:49,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1327 states and 1945 transitions. [2024-11-17 08:53:49,634 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:49,641 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1327 states to 1327 states and 1945 transitions. [2024-11-17 08:53:49,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1327 [2024-11-17 08:53:49,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1327 [2024-11-17 08:53:49,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1327 states and 1945 transitions. [2024-11-17 08:53:49,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:49,646 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1945 transitions. [2024-11-17 08:53:49,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states and 1945 transitions. [2024-11-17 08:53:49,662 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1327. [2024-11-17 08:53:49,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1327 states, 1327 states have (on average 1.4657121326299924) internal successors, (1945), 1326 states have internal predecessors, (1945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1327 states to 1327 states and 1945 transitions. [2024-11-17 08:53:49,669 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1945 transitions. [2024-11-17 08:53:49,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:49,670 INFO L425 stractBuchiCegarLoop]: Abstraction has 1327 states and 1945 transitions. [2024-11-17 08:53:49,671 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:53:49,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1327 states and 1945 transitions. [2024-11-17 08:53:49,676 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:49,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:49,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:49,678 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,678 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,679 INFO L745 eck$LassoCheckResult]: Stem: 17036#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 16049#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 16050#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17311#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17332#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 17331#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16411#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16412#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16194#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16195#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16993#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16399#L736 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16278#L741 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16279#L746 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 16042#L751 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16043#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16105#L1006-1 assume 0 == ~M_E~0;~M_E~0 := 1; 17032#L1011-1 assume !(0 == ~T1_E~0); 17266#L1016-1 assume !(0 == ~T2_E~0); 17277#L1021-1 assume !(0 == ~T3_E~0); 16040#L1026-1 assume !(0 == ~T4_E~0); 16041#L1031-1 assume !(0 == ~T5_E~0); 16965#L1036-1 assume !(0 == ~T6_E~0); 16962#L1041-1 assume !(0 == ~T7_E~0); 16963#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16363#L1051-1 assume !(0 == ~T9_E~0); 16364#L1056-1 assume !(0 == ~T10_E~0); 17092#L1061-1 assume !(0 == ~E_1~0); 16272#L1066-1 assume !(0 == ~E_2~0); 16273#L1071-1 assume !(0 == ~E_3~0); 17076#L1076-1 assume !(0 == ~E_4~0); 16148#L1081-1 assume !(0 == ~E_5~0); 16149#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 16544#L1091-1 assume !(0 == ~E_7~0); 17255#L1096-1 assume !(0 == ~E_8~0); 17256#L1101-1 assume !(0 == ~E_9~0); 16607#L1106-1 assume !(0 == ~E_10~0); 16608#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16498#L484-12 assume 1 == ~m_pc~0; 16499#L485-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16099#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16945#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16063#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 16064#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16350#L503-12 assume 1 == ~t1_pc~0; 16419#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16007#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17328#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16892#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 16893#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16730#L522-12 assume 1 == ~t2_pc~0; 16731#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16510#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16511#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16798#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 16794#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16795#L541-12 assume !(1 == ~t3_pc~0); 16512#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 16513#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16404#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16405#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 16500#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16501#L560-12 assume 1 == ~t4_pc~0; 17087#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16910#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16780#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16781#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 17024#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16950#L579-12 assume 1 == ~t5_pc~0; 16951#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16462#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16463#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17053#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 16919#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16920#L598-12 assume 1 == ~t6_pc~0; 16185#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16186#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17016#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17017#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 17321#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17322#L617-12 assume !(1 == ~t7_pc~0); 16057#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 16058#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16597#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16598#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 17069#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17181#L636-12 assume 1 == ~t8_pc~0; 17196#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 17157#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16908#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16909#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 16881#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16882#L655-12 assume 1 == ~t9_pc~0; 17054#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16136#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16137#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16344#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 16474#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16475#L674-12 assume 1 == ~t10_pc~0; 17178#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16844#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17201#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16457#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 16458#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17302#L1119-1 assume !(1 == ~M_E~0); 16691#L1124-1 assume !(1 == ~T1_E~0); 16067#L1129-1 assume !(1 == ~T2_E~0); 16068#L1134-1 assume !(1 == ~T3_E~0); 16406#L1139-1 assume !(1 == ~T4_E~0); 16407#L1144-1 assume !(1 == ~T5_E~0); 16633#L1149-1 assume !(1 == ~T6_E~0); 16245#L1154-1 assume !(1 == ~T7_E~0); 16246#L1159-1 assume !(1 == ~T8_E~0); 16346#L1164-1 assume !(1 == ~T9_E~0); 16810#L1169-1 assume !(1 == ~T10_E~0); 16677#L1174-1 assume !(1 == ~E_1~0); 16464#L1179-1 assume !(1 == ~E_2~0); 16330#L1184-1 assume !(1 == ~E_3~0); 16331#L1189-1 assume !(1 == ~E_4~0); 16400#L1194-1 assume !(1 == ~E_5~0); 16530#L1199-1 assume !(1 == ~E_6~0); 16480#L1204-1 assume !(1 == ~E_7~0); 16481#L1209-1 assume !(1 == ~E_8~0); 17033#L1214-1 assume !(1 == ~E_9~0); 17034#L1219-1 assume !(1 == ~E_10~0); 17226#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 16606#L1520 [2024-11-17 08:53:49,679 INFO L747 eck$LassoCheckResult]: Loop: 16606#L1520 assume true; 17185#L1520-1 assume !false; 16563#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16335#L831 assume true; 16925#L831-1 assume !false; 16926#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16812#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16590#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16742#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16743#L836 assume !(0 != eval_~tmp~0#1); 16699#L839 assume true; 16700#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17290#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17158#L1006 assume 0 == ~M_E~0;~M_E~0 := 1; 16494#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16495#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16986#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16987#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17291#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16100#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16101#L1041 assume !(0 == ~T7_E~0); 16123#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16124#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16448#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16449#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 17147#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 17116#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 17117#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 17310#L1081 assume !(0 == ~E_5~0); 17133#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 17109#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 16303#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 16167#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 16168#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 17325#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17300#L484-1 assume 1 == ~m_pc~0; 16969#L485-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16971#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17162#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16756#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16757#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16454#L503-1 assume 1 == ~t1_pc~0; 16455#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17131#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17263#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17086#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16115#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16116#L522-1 assume 1 == ~t2_pc~0; 16972#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16973#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16887#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16026#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16027#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16760#L541-1 assume 1 == ~t3_pc~0; 16427#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16428#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16996#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16997#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16231#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16232#L560-1 assume !(1 == ~t4_pc~0); 17159#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 17160#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17124#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17057#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16542#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16339#L579-1 assume 1 == ~t5_pc~0; 16340#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16862#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17241#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17242#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16650#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16651#L598-1 assume 1 == ~t6_pc~0; 17125#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16520#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16701#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17068#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17132#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16300#L617-1 assume 1 == ~t7_pc~0; 16301#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16551#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16552#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17224#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16711#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16369#L636-1 assume 1 == ~t8_pc~0; 16370#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16726#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16727#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17289#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16215#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16216#L655-1 assume 1 == ~t9_pc~0; 17187#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16697#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16558#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16559#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16446#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16447#L674-1 assume 1 == ~t10_pc~0; 16777#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16317#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16318#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16539#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16374#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16375#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 16809#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16715#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16716#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17121#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16840#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16036#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16037#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17052#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17176#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16861#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16669#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 16670#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 17023#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 17215#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 16814#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 16791#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 16792#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 16994#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 17141#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 17142#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 17026#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17012#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16114#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16521#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16522#L1539 assume !(0 == start_simulation_~tmp~3#1); 16604#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 17258#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16025#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16473#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 16503#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16192#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16193#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 16605#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 16606#L1520 [2024-11-17 08:53:49,680 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,680 INFO L85 PathProgramCache]: Analyzing trace with hash -1107018722, now seen corresponding path program 1 times [2024-11-17 08:53:49,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,681 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063995146] [2024-11-17 08:53:49,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,718 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,718 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,718 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1063995146] [2024-11-17 08:53:49,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1063995146] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,718 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:49,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193788559] [2024-11-17 08:53:49,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,719 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:49,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,719 INFO L85 PathProgramCache]: Analyzing trace with hash 937458089, now seen corresponding path program 1 times [2024-11-17 08:53:49,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,720 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [456490441] [2024-11-17 08:53:49,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,791 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [456490441] [2024-11-17 08:53:49,792 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [456490441] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,792 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,792 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:49,792 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [753600338] [2024-11-17 08:53:49,792 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,792 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:49,793 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:49,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:49,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:49,793 INFO L87 Difference]: Start difference. First operand 1327 states and 1945 transitions. cyclomatic complexity: 619 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:49,817 INFO L93 Difference]: Finished difference Result 1327 states and 1944 transitions. [2024-11-17 08:53:49,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1327 states and 1944 transitions. [2024-11-17 08:53:49,824 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:49,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1327 states to 1327 states and 1944 transitions. [2024-11-17 08:53:49,831 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1327 [2024-11-17 08:53:49,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1327 [2024-11-17 08:53:49,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1327 states and 1944 transitions. [2024-11-17 08:53:49,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:49,833 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1944 transitions. [2024-11-17 08:53:49,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states and 1944 transitions. [2024-11-17 08:53:49,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1327. [2024-11-17 08:53:49,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1327 states, 1327 states have (on average 1.464958553127355) internal successors, (1944), 1326 states have internal predecessors, (1944), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:49,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1327 states to 1327 states and 1944 transitions. [2024-11-17 08:53:49,852 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1944 transitions. [2024-11-17 08:53:49,853 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:49,853 INFO L425 stractBuchiCegarLoop]: Abstraction has 1327 states and 1944 transitions. [2024-11-17 08:53:49,854 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:53:49,854 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1327 states and 1944 transitions. [2024-11-17 08:53:49,858 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:49,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:49,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:49,861 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,861 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:49,862 INFO L745 eck$LassoCheckResult]: Stem: 19699#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 18712#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 18713#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19974#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19995#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 19994#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19077#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19078#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18857#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18858#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19656#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19062#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18943#L741 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18944#L746 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 18705#L751 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18706#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18770#L1006-1 assume 0 == ~M_E~0;~M_E~0 := 1; 19695#L1011-1 assume !(0 == ~T1_E~0); 19929#L1016-1 assume !(0 == ~T2_E~0); 19940#L1021-1 assume !(0 == ~T3_E~0); 18703#L1026-1 assume !(0 == ~T4_E~0); 18704#L1031-1 assume !(0 == ~T5_E~0); 19628#L1036-1 assume !(0 == ~T6_E~0); 19625#L1041-1 assume !(0 == ~T7_E~0); 19626#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19028#L1051-1 assume !(0 == ~T9_E~0); 19029#L1056-1 assume !(0 == ~T10_E~0); 19755#L1061-1 assume !(0 == ~E_1~0); 18935#L1066-1 assume !(0 == ~E_2~0); 18936#L1071-1 assume !(0 == ~E_3~0); 19739#L1076-1 assume !(0 == ~E_4~0); 18811#L1081-1 assume !(0 == ~E_5~0); 18812#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 19207#L1091-1 assume !(0 == ~E_7~0); 19918#L1096-1 assume !(0 == ~E_8~0); 19919#L1101-1 assume !(0 == ~E_9~0); 19270#L1106-1 assume !(0 == ~E_10~0); 19271#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19161#L484-12 assume 1 == ~m_pc~0; 19162#L485-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18762#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19608#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18726#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 18727#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19013#L503-12 assume 1 == ~t1_pc~0; 19082#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18673#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19991#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19557#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 19558#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19393#L522-12 assume 1 == ~t2_pc~0; 19394#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19173#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19174#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19461#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 19457#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19458#L541-12 assume !(1 == ~t3_pc~0); 19175#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 19176#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19067#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19068#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 19163#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19164#L560-12 assume 1 == ~t4_pc~0; 19750#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19573#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19443#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19444#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 19687#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19613#L579-12 assume 1 == ~t5_pc~0; 19614#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19127#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19128#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19716#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 19582#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19583#L598-12 assume 1 == ~t6_pc~0; 18848#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18849#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19679#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19680#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 19984#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19985#L617-12 assume !(1 == ~t7_pc~0); 18722#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 18723#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19260#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19261#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 19732#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19844#L636-12 assume 1 == ~t8_pc~0; 19859#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19820#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19571#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19572#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 19544#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19545#L655-12 assume 1 == ~t9_pc~0; 19718#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18802#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18803#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19008#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 19137#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19138#L674-12 assume 1 == ~t10_pc~0; 19841#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19507#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19864#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19120#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 19121#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19965#L1119-1 assume !(1 == ~M_E~0); 19356#L1124-1 assume !(1 == ~T1_E~0); 18730#L1129-1 assume !(1 == ~T2_E~0); 18731#L1134-1 assume !(1 == ~T3_E~0); 19069#L1139-1 assume !(1 == ~T4_E~0); 19070#L1144-1 assume !(1 == ~T5_E~0); 19297#L1149-1 assume !(1 == ~T6_E~0); 18908#L1154-1 assume !(1 == ~T7_E~0); 18909#L1159-1 assume !(1 == ~T8_E~0); 19010#L1164-1 assume !(1 == ~T9_E~0); 19473#L1169-1 assume !(1 == ~T10_E~0); 19340#L1174-1 assume !(1 == ~E_1~0); 19129#L1179-1 assume !(1 == ~E_2~0); 18993#L1184-1 assume !(1 == ~E_3~0); 18994#L1189-1 assume !(1 == ~E_4~0); 19063#L1194-1 assume !(1 == ~E_5~0); 19193#L1199-1 assume !(1 == ~E_6~0); 19143#L1204-1 assume !(1 == ~E_7~0); 19144#L1209-1 assume !(1 == ~E_8~0); 19696#L1214-1 assume !(1 == ~E_9~0); 19697#L1219-1 assume !(1 == ~E_10~0); 19889#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 19267#L1520 [2024-11-17 08:53:49,862 INFO L747 eck$LassoCheckResult]: Loop: 19267#L1520 assume true; 19848#L1520-1 assume !false; 19226#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19001#L831 assume true; 19588#L831-1 assume !false; 19589#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19476#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 19253#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19409#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19410#L836 assume !(0 != eval_~tmp~0#1); 19362#L839 assume true; 19363#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19953#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19821#L1006 assume 0 == ~M_E~0;~M_E~0 := 1; 19157#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19158#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19649#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19650#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19954#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18763#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18764#L1041 assume !(0 == ~T7_E~0); 18786#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18787#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19113#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19114#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 19810#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 19779#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 19780#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 19973#L1081 assume !(0 == ~E_5~0); 19796#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 19772#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 18966#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 18830#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 18831#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 19988#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19963#L484-1 assume 1 == ~m_pc~0; 19632#L485-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19634#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19825#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19419#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19420#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19117#L503-1 assume 1 == ~t1_pc~0; 19118#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19794#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19926#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19749#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18778#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18779#L522-1 assume 1 == ~t2_pc~0; 19635#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19636#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19550#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18689#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18690#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19423#L541-1 assume 1 == ~t3_pc~0; 19090#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19091#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19659#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19660#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18894#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18895#L560-1 assume 1 == ~t4_pc~0; 19891#L561-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19823#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19787#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19720#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19205#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19002#L579-1 assume 1 == ~t5_pc~0; 19003#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19525#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19904#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19905#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19313#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19314#L598-1 assume !(1 == ~t6_pc~0); 19184#L608-1 is_transmit6_triggered_~__retres1~6#1 := 0; 19185#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19364#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19731#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19795#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18963#L617-1 assume 1 == ~t7_pc~0; 18964#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19214#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19215#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19887#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19372#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19030#L636-1 assume 1 == ~t8_pc~0; 19031#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19386#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19387#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19952#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18877#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18878#L655-1 assume 1 == ~t9_pc~0; 19850#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19355#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19216#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19217#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 19109#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19110#L674-1 assume !(1 == ~t10_pc~0); 19440#L684-1 is_transmit10_triggered_~__retres1~10#1 := 0; 18977#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18978#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19197#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19037#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19038#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 19470#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19378#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19379#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19784#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19503#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18699#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18700#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19715#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19839#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19523#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19332#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 19333#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 19686#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 19878#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 19475#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 19454#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 19455#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 19657#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 19804#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 19805#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 19688#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19674#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18775#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19182#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 19183#L1539 assume !(0 == start_simulation_~tmp~3#1); 19265#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19921#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18686#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 19136#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 19166#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18855#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18856#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 19266#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 19267#L1520 [2024-11-17 08:53:49,863 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,863 INFO L85 PathProgramCache]: Analyzing trace with hash 75998813, now seen corresponding path program 1 times [2024-11-17 08:53:49,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264988755] [2024-11-17 08:53:49,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:49,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:49,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:49,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264988755] [2024-11-17 08:53:49,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1264988755] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:49,932 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:49,932 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:49,932 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419487193] [2024-11-17 08:53:49,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:49,937 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:49,937 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:49,937 INFO L85 PathProgramCache]: Analyzing trace with hash -1182556282, now seen corresponding path program 1 times [2024-11-17 08:53:49,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:49,937 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1292405833] [2024-11-17 08:53:49,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:49,937 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:49,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:50,009 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:50,010 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:50,010 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1292405833] [2024-11-17 08:53:50,010 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1292405833] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:50,010 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:50,010 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:50,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431016135] [2024-11-17 08:53:50,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:50,014 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:50,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:50,014 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:50,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:50,015 INFO L87 Difference]: Start difference. First operand 1327 states and 1944 transitions. cyclomatic complexity: 618 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:50,040 INFO L93 Difference]: Finished difference Result 1327 states and 1943 transitions. [2024-11-17 08:53:50,040 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1327 states and 1943 transitions. [2024-11-17 08:53:50,046 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:50,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1327 states to 1327 states and 1943 transitions. [2024-11-17 08:53:50,053 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1327 [2024-11-17 08:53:50,054 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1327 [2024-11-17 08:53:50,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1327 states and 1943 transitions. [2024-11-17 08:53:50,056 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:50,056 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1943 transitions. [2024-11-17 08:53:50,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states and 1943 transitions. [2024-11-17 08:53:50,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1327. [2024-11-17 08:53:50,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1327 states, 1327 states have (on average 1.4642049736247174) internal successors, (1943), 1326 states have internal predecessors, (1943), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1327 states to 1327 states and 1943 transitions. [2024-11-17 08:53:50,079 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1943 transitions. [2024-11-17 08:53:50,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:50,081 INFO L425 stractBuchiCegarLoop]: Abstraction has 1327 states and 1943 transitions. [2024-11-17 08:53:50,081 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:53:50,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1327 states and 1943 transitions. [2024-11-17 08:53:50,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:50,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:50,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:50,088 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,088 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,089 INFO L745 eck$LassoCheckResult]: Stem: 22363#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 21375#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 21376#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22637#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22658#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 22657#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21740#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21741#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21520#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21521#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22319#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21725#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21606#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21607#L746 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 21368#L751 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21369#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21433#L1006-1 assume 0 == ~M_E~0;~M_E~0 := 1; 22358#L1011-1 assume !(0 == ~T1_E~0); 22592#L1016-1 assume !(0 == ~T2_E~0); 22603#L1021-1 assume !(0 == ~T3_E~0); 21366#L1026-1 assume !(0 == ~T4_E~0); 21367#L1031-1 assume !(0 == ~T5_E~0); 22294#L1036-1 assume !(0 == ~T6_E~0); 22288#L1041-1 assume !(0 == ~T7_E~0); 22289#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21691#L1051-1 assume !(0 == ~T9_E~0); 21692#L1056-1 assume !(0 == ~T10_E~0); 22418#L1061-1 assume !(0 == ~E_1~0); 21598#L1066-1 assume !(0 == ~E_2~0); 21599#L1071-1 assume !(0 == ~E_3~0); 22402#L1076-1 assume !(0 == ~E_4~0); 21474#L1081-1 assume !(0 == ~E_5~0); 21475#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 21870#L1091-1 assume !(0 == ~E_7~0); 22581#L1096-1 assume !(0 == ~E_8~0); 22582#L1101-1 assume !(0 == ~E_9~0); 21933#L1106-1 assume !(0 == ~E_10~0); 21934#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21824#L484-12 assume 1 == ~m_pc~0; 21825#L485-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21425#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22271#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21391#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 21392#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21677#L503-12 assume 1 == ~t1_pc~0; 21745#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21336#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22654#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22220#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 22221#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22056#L522-12 assume 1 == ~t2_pc~0; 22057#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21836#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21837#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22125#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 22122#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22123#L541-12 assume !(1 == ~t3_pc~0); 21838#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 21839#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21730#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21731#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 21826#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21827#L560-12 assume 1 == ~t4_pc~0; 22414#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22236#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22106#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22107#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 22350#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22276#L579-12 assume 1 == ~t5_pc~0; 22277#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21790#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21791#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22379#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 22245#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22246#L598-12 assume 1 == ~t6_pc~0; 21515#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21516#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22342#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22343#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 22647#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22648#L617-12 assume !(1 == ~t7_pc~0); 21387#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 21388#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21923#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21924#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 22395#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22507#L636-12 assume 1 == ~t8_pc~0; 22522#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22483#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22234#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22235#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 22209#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22210#L655-12 assume 1 == ~t9_pc~0; 22381#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21465#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21466#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21671#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 21801#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21802#L674-12 assume 1 == ~t10_pc~0; 22504#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22170#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22528#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21783#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 21784#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22629#L1119-1 assume !(1 == ~M_E~0); 22021#L1124-1 assume !(1 == ~T1_E~0); 21393#L1129-1 assume !(1 == ~T2_E~0); 21394#L1134-1 assume !(1 == ~T3_E~0); 21732#L1139-1 assume !(1 == ~T4_E~0); 21733#L1144-1 assume !(1 == ~T5_E~0); 21960#L1149-1 assume !(1 == ~T6_E~0); 21573#L1154-1 assume !(1 == ~T7_E~0); 21574#L1159-1 assume !(1 == ~T8_E~0); 21673#L1164-1 assume !(1 == ~T9_E~0); 22136#L1169-1 assume !(1 == ~T10_E~0); 22003#L1174-1 assume !(1 == ~E_1~0); 21792#L1179-1 assume !(1 == ~E_2~0); 21656#L1184-1 assume !(1 == ~E_3~0); 21657#L1189-1 assume !(1 == ~E_4~0); 21726#L1194-1 assume !(1 == ~E_5~0); 21856#L1199-1 assume !(1 == ~E_6~0); 21809#L1204-1 assume !(1 == ~E_7~0); 21810#L1209-1 assume !(1 == ~E_8~0); 22359#L1214-1 assume !(1 == ~E_9~0); 22360#L1219-1 assume !(1 == ~E_10~0); 22553#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 21932#L1520 [2024-11-17 08:53:50,089 INFO L747 eck$LassoCheckResult]: Loop: 21932#L1520 assume true; 22511#L1520-1 assume !false; 21889#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21664#L831 assume true; 22251#L831-1 assume !false; 22252#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22139#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21918#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 22072#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22073#L836 assume !(0 != eval_~tmp~0#1); 22025#L839 assume true; 22026#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22616#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22484#L1006 assume 0 == ~M_E~0;~M_E~0 := 1; 21822#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21823#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22312#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22313#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22619#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21426#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21427#L1041 assume !(0 == ~T7_E~0); 21449#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21450#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21778#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21779#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 22473#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 22442#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 22443#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 22636#L1081 assume !(0 == ~E_5~0); 22459#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 22435#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 21632#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 21495#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 21496#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 22650#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22626#L484-1 assume 1 == ~m_pc~0; 22295#L485-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22297#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22488#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22082#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22083#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21780#L503-1 assume 1 == ~t1_pc~0; 21781#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22457#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22589#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22412#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21441#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21442#L522-1 assume 1 == ~t2_pc~0; 22298#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22299#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22213#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21352#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21353#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22085#L541-1 assume 1 == ~t3_pc~0; 21753#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21754#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22322#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22323#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21557#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21558#L560-1 assume !(1 == ~t4_pc~0); 22485#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 22486#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22450#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22383#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21868#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21665#L579-1 assume 1 == ~t5_pc~0; 21666#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22188#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22567#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22568#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21975#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21976#L598-1 assume 1 == ~t6_pc~0; 22451#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21846#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22027#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22394#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22458#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21623#L617-1 assume 1 == ~t7_pc~0; 21624#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21877#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21878#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22550#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22037#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21695#L636-1 assume 1 == ~t8_pc~0; 21696#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22052#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22053#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22615#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21541#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21542#L655-1 assume 1 == ~t9_pc~0; 22513#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22020#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21882#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21883#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21772#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21773#L674-1 assume 1 == ~t10_pc~0; 22103#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21640#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21641#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21862#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21700#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21701#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 22133#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22041#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22042#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22447#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22166#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21362#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21363#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22378#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22502#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22187#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21995#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 21996#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 22349#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 22541#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 22138#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 22117#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 22118#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 22320#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 22467#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 22468#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 22352#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22337#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21438#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21847#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 21848#L1539 assume !(0 == start_simulation_~tmp~3#1); 21930#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 22584#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21349#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21799#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 21829#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21518#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21519#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 21931#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 21932#L1520 [2024-11-17 08:53:50,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,090 INFO L85 PathProgramCache]: Analyzing trace with hash 1222539326, now seen corresponding path program 1 times [2024-11-17 08:53:50,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1330789352] [2024-11-17 08:53:50,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:50,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:50,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:50,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1330789352] [2024-11-17 08:53:50,130 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1330789352] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:50,130 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:50,130 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:50,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615085936] [2024-11-17 08:53:50,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:50,131 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:50,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,131 INFO L85 PathProgramCache]: Analyzing trace with hash 937458089, now seen corresponding path program 2 times [2024-11-17 08:53:50,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [948038136] [2024-11-17 08:53:50,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:50,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:50,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:50,202 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [948038136] [2024-11-17 08:53:50,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [948038136] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:50,202 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:50,202 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:50,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1226020572] [2024-11-17 08:53:50,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:50,203 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:50,204 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:50,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:50,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:50,204 INFO L87 Difference]: Start difference. First operand 1327 states and 1943 transitions. cyclomatic complexity: 617 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:50,226 INFO L93 Difference]: Finished difference Result 1327 states and 1942 transitions. [2024-11-17 08:53:50,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1327 states and 1942 transitions. [2024-11-17 08:53:50,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:50,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1327 states to 1327 states and 1942 transitions. [2024-11-17 08:53:50,239 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1327 [2024-11-17 08:53:50,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1327 [2024-11-17 08:53:50,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1327 states and 1942 transitions. [2024-11-17 08:53:50,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:50,242 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1942 transitions. [2024-11-17 08:53:50,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states and 1942 transitions. [2024-11-17 08:53:50,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1327. [2024-11-17 08:53:50,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1327 states, 1327 states have (on average 1.46345139412208) internal successors, (1942), 1326 states have internal predecessors, (1942), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1327 states to 1327 states and 1942 transitions. [2024-11-17 08:53:50,262 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1942 transitions. [2024-11-17 08:53:50,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:50,264 INFO L425 stractBuchiCegarLoop]: Abstraction has 1327 states and 1942 transitions. [2024-11-17 08:53:50,264 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:53:50,264 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1327 states and 1942 transitions. [2024-11-17 08:53:50,268 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:50,268 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:50,268 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:50,270 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,270 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,271 INFO L745 eck$LassoCheckResult]: Stem: 25025#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 24038#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24039#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25300#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25321#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 25320#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24400#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24401#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24183#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24184#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24982#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24388#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24267#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24268#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24031#L751 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24032#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24094#L1006-1 assume 0 == ~M_E~0;~M_E~0 := 1; 25021#L1011-1 assume !(0 == ~T1_E~0); 25255#L1016-1 assume !(0 == ~T2_E~0); 25266#L1021-1 assume !(0 == ~T3_E~0); 24029#L1026-1 assume !(0 == ~T4_E~0); 24030#L1031-1 assume !(0 == ~T5_E~0); 24954#L1036-1 assume !(0 == ~T6_E~0); 24951#L1041-1 assume !(0 == ~T7_E~0); 24952#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24352#L1051-1 assume !(0 == ~T9_E~0); 24353#L1056-1 assume !(0 == ~T10_E~0); 25081#L1061-1 assume !(0 == ~E_1~0); 24261#L1066-1 assume !(0 == ~E_2~0); 24262#L1071-1 assume !(0 == ~E_3~0); 25065#L1076-1 assume !(0 == ~E_4~0); 24137#L1081-1 assume !(0 == ~E_5~0); 24138#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 24533#L1091-1 assume !(0 == ~E_7~0); 25244#L1096-1 assume !(0 == ~E_8~0); 25245#L1101-1 assume !(0 == ~E_9~0); 24596#L1106-1 assume !(0 == ~E_10~0); 24597#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24487#L484-12 assume 1 == ~m_pc~0; 24488#L485-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24088#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24934#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24052#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 24053#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24339#L503-12 assume 1 == ~t1_pc~0; 24408#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23996#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25317#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24881#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 24882#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24719#L522-12 assume 1 == ~t2_pc~0; 24720#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24499#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24500#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24787#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 24783#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24784#L541-12 assume !(1 == ~t3_pc~0); 24501#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 24502#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24393#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24394#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 24489#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24490#L560-12 assume 1 == ~t4_pc~0; 25076#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 24899#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24769#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24770#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 25013#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24939#L579-12 assume 1 == ~t5_pc~0; 24940#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24451#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24452#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25042#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 24908#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24909#L598-12 assume 1 == ~t6_pc~0; 24174#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24175#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25005#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25006#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 25310#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25311#L617-12 assume !(1 == ~t7_pc~0); 24046#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 24047#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24586#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24587#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 25058#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25170#L636-12 assume 1 == ~t8_pc~0; 25185#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25146#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24897#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24898#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 24870#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24871#L655-12 assume 1 == ~t9_pc~0; 25043#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24125#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24126#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24333#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 24463#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24464#L674-12 assume 1 == ~t10_pc~0; 25167#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24833#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25190#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24446#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 24447#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25291#L1119-1 assume !(1 == ~M_E~0); 24680#L1124-1 assume !(1 == ~T1_E~0); 24056#L1129-1 assume !(1 == ~T2_E~0); 24057#L1134-1 assume !(1 == ~T3_E~0); 24395#L1139-1 assume !(1 == ~T4_E~0); 24396#L1144-1 assume !(1 == ~T5_E~0); 24622#L1149-1 assume !(1 == ~T6_E~0); 24234#L1154-1 assume !(1 == ~T7_E~0); 24235#L1159-1 assume !(1 == ~T8_E~0); 24335#L1164-1 assume !(1 == ~T9_E~0); 24799#L1169-1 assume !(1 == ~T10_E~0); 24666#L1174-1 assume !(1 == ~E_1~0); 24453#L1179-1 assume !(1 == ~E_2~0); 24319#L1184-1 assume !(1 == ~E_3~0); 24320#L1189-1 assume !(1 == ~E_4~0); 24389#L1194-1 assume !(1 == ~E_5~0); 24519#L1199-1 assume !(1 == ~E_6~0); 24469#L1204-1 assume !(1 == ~E_7~0); 24470#L1209-1 assume !(1 == ~E_8~0); 25022#L1214-1 assume !(1 == ~E_9~0); 25023#L1219-1 assume !(1 == ~E_10~0); 25215#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 24595#L1520 [2024-11-17 08:53:50,271 INFO L747 eck$LassoCheckResult]: Loop: 24595#L1520 assume true; 25174#L1520-1 assume !false; 24552#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24324#L831 assume true; 24914#L831-1 assume !false; 24915#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24801#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24579#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24731#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24732#L836 assume !(0 != eval_~tmp~0#1); 24688#L839 assume true; 24689#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25279#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25147#L1006 assume 0 == ~M_E~0;~M_E~0 := 1; 24483#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24484#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24975#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24976#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25280#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24089#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24090#L1041 assume !(0 == ~T7_E~0); 24112#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24113#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24437#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24438#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 25136#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 25105#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 25106#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 25299#L1081 assume !(0 == ~E_5~0); 25122#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 25098#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 24292#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 24156#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 24157#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 25314#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25289#L484-1 assume 1 == ~m_pc~0; 24958#L485-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24960#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25151#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24745#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24746#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24443#L503-1 assume 1 == ~t1_pc~0; 24444#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25120#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25252#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25075#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24104#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24105#L522-1 assume 1 == ~t2_pc~0; 24961#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24962#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24876#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24015#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24016#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24749#L541-1 assume 1 == ~t3_pc~0; 24416#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24417#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24985#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24986#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24220#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24221#L560-1 assume 1 == ~t4_pc~0; 25217#L561-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25149#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25113#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25046#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24531#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24328#L579-1 assume 1 == ~t5_pc~0; 24329#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24851#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25230#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25231#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24639#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24640#L598-1 assume 1 == ~t6_pc~0; 25114#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24509#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24690#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25057#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25121#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24289#L617-1 assume 1 == ~t7_pc~0; 24290#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 24540#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24541#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25213#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24700#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24358#L636-1 assume 1 == ~t8_pc~0; 24359#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24715#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24716#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25278#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24204#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24205#L655-1 assume 1 == ~t9_pc~0; 25176#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24686#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24547#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24548#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24435#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24436#L674-1 assume 1 == ~t10_pc~0; 24766#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24306#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24307#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24528#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24363#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24364#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 24798#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24704#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24705#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25110#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24829#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24025#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24026#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25041#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25165#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24850#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24658#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 24659#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 25012#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 25204#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 24803#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 24780#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 24781#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 24983#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 25130#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 25131#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 25015#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25001#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24103#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24510#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 24511#L1539 assume !(0 == start_simulation_~tmp~3#1); 24593#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 25247#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 24014#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 24462#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 24492#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24181#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24182#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 24594#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 24595#L1520 [2024-11-17 08:53:50,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,273 INFO L85 PathProgramCache]: Analyzing trace with hash -1788516803, now seen corresponding path program 1 times [2024-11-17 08:53:50,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1885202589] [2024-11-17 08:53:50,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:50,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:50,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:50,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1885202589] [2024-11-17 08:53:50,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1885202589] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:50,328 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:50,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:50,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [345651877] [2024-11-17 08:53:50,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:50,329 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:50,329 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,329 INFO L85 PathProgramCache]: Analyzing trace with hash 1562747340, now seen corresponding path program 1 times [2024-11-17 08:53:50,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,330 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361919300] [2024-11-17 08:53:50,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,330 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:50,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:50,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:50,431 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1361919300] [2024-11-17 08:53:50,431 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1361919300] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:50,431 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:50,432 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:50,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850812906] [2024-11-17 08:53:50,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:50,432 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:50,432 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:50,433 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:50,433 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:50,433 INFO L87 Difference]: Start difference. First operand 1327 states and 1942 transitions. cyclomatic complexity: 616 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:50,457 INFO L93 Difference]: Finished difference Result 1327 states and 1941 transitions. [2024-11-17 08:53:50,457 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1327 states and 1941 transitions. [2024-11-17 08:53:50,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:50,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1327 states to 1327 states and 1941 transitions. [2024-11-17 08:53:50,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1327 [2024-11-17 08:53:50,471 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1327 [2024-11-17 08:53:50,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1327 states and 1941 transitions. [2024-11-17 08:53:50,473 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:50,473 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1941 transitions. [2024-11-17 08:53:50,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1327 states and 1941 transitions. [2024-11-17 08:53:50,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1327 to 1327. [2024-11-17 08:53:50,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1327 states, 1327 states have (on average 1.4626978146194423) internal successors, (1941), 1326 states have internal predecessors, (1941), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1327 states to 1327 states and 1941 transitions. [2024-11-17 08:53:50,496 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1327 states and 1941 transitions. [2024-11-17 08:53:50,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:50,497 INFO L425 stractBuchiCegarLoop]: Abstraction has 1327 states and 1941 transitions. [2024-11-17 08:53:50,497 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:53:50,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1327 states and 1941 transitions. [2024-11-17 08:53:50,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1190 [2024-11-17 08:53:50,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:50,502 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:50,504 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,504 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,504 INFO L745 eck$LassoCheckResult]: Stem: 27688#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 26701#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 26702#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 27963#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27984#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 27983#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27065#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27066#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26846#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26847#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27645#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27051#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26930#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26931#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26694#L751 assume 1 == ~t10_i~0;~t10_st~0 := 0; 26695#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26757#L1006-1 assume 0 == ~M_E~0;~M_E~0 := 1; 27684#L1011-1 assume !(0 == ~T1_E~0); 27918#L1016-1 assume !(0 == ~T2_E~0); 27929#L1021-1 assume !(0 == ~T3_E~0); 26692#L1026-1 assume !(0 == ~T4_E~0); 26693#L1031-1 assume !(0 == ~T5_E~0); 27617#L1036-1 assume !(0 == ~T6_E~0); 27614#L1041-1 assume !(0 == ~T7_E~0); 27615#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27015#L1051-1 assume !(0 == ~T9_E~0); 27016#L1056-1 assume !(0 == ~T10_E~0); 27744#L1061-1 assume !(0 == ~E_1~0); 26924#L1066-1 assume !(0 == ~E_2~0); 26925#L1071-1 assume !(0 == ~E_3~0); 27728#L1076-1 assume !(0 == ~E_4~0); 26800#L1081-1 assume !(0 == ~E_5~0); 26801#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 27196#L1091-1 assume !(0 == ~E_7~0); 27907#L1096-1 assume !(0 == ~E_8~0); 27908#L1101-1 assume !(0 == ~E_9~0); 27259#L1106-1 assume !(0 == ~E_10~0); 27260#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27150#L484-12 assume 1 == ~m_pc~0; 27151#L485-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 26751#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27597#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 26715#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 26716#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27002#L503-12 assume 1 == ~t1_pc~0; 27071#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26659#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27980#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27544#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 27545#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27382#L522-12 assume 1 == ~t2_pc~0; 27383#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27162#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27163#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27450#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 27446#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27447#L541-12 assume !(1 == ~t3_pc~0); 27164#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 27165#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27056#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27057#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 27152#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27153#L560-12 assume 1 == ~t4_pc~0; 27739#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27562#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27432#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27433#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 27676#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27602#L579-12 assume 1 == ~t5_pc~0; 27603#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27114#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27115#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27705#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 27571#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27572#L598-12 assume 1 == ~t6_pc~0; 26837#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26838#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27668#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27669#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 27973#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27974#L617-12 assume !(1 == ~t7_pc~0); 26711#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 26712#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27249#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27250#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 27721#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27833#L636-12 assume 1 == ~t8_pc~0; 27848#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27809#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27560#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27561#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 27533#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27534#L655-12 assume 1 == ~t9_pc~0; 27706#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26788#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26789#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26996#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 27126#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27127#L674-12 assume 1 == ~t10_pc~0; 27830#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27496#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27853#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27109#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 27110#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27954#L1119-1 assume !(1 == ~M_E~0); 27343#L1124-1 assume !(1 == ~T1_E~0); 26719#L1129-1 assume !(1 == ~T2_E~0); 26720#L1134-1 assume !(1 == ~T3_E~0); 27058#L1139-1 assume !(1 == ~T4_E~0); 27059#L1144-1 assume !(1 == ~T5_E~0); 27286#L1149-1 assume !(1 == ~T6_E~0); 26897#L1154-1 assume !(1 == ~T7_E~0); 26898#L1159-1 assume !(1 == ~T8_E~0); 26998#L1164-1 assume !(1 == ~T9_E~0); 27462#L1169-1 assume !(1 == ~T10_E~0); 27329#L1174-1 assume !(1 == ~E_1~0); 27116#L1179-1 assume !(1 == ~E_2~0); 26982#L1184-1 assume !(1 == ~E_3~0); 26983#L1189-1 assume !(1 == ~E_4~0); 27052#L1194-1 assume !(1 == ~E_5~0); 27182#L1199-1 assume !(1 == ~E_6~0); 27132#L1204-1 assume !(1 == ~E_7~0); 27133#L1209-1 assume !(1 == ~E_8~0); 27685#L1214-1 assume !(1 == ~E_9~0); 27686#L1219-1 assume !(1 == ~E_10~0); 27878#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 27258#L1520 [2024-11-17 08:53:50,505 INFO L747 eck$LassoCheckResult]: Loop: 27258#L1520 assume true; 27837#L1520-1 assume !false; 27215#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26987#L831 assume true; 27577#L831-1 assume !false; 27578#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 27464#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 27242#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 27394#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27395#L836 assume !(0 != eval_~tmp~0#1); 27351#L839 assume true; 27352#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27942#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27810#L1006 assume 0 == ~M_E~0;~M_E~0 := 1; 27146#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27147#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27638#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27639#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27943#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26752#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26753#L1041 assume !(0 == ~T7_E~0); 26775#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26776#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27100#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 27101#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 27799#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 27768#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 27769#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 27962#L1081 assume !(0 == ~E_5~0); 27785#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 27761#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 26955#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 26819#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 26820#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 27977#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27952#L484-1 assume 1 == ~m_pc~0; 27621#L485-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27623#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27814#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27408#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27409#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27106#L503-1 assume 1 == ~t1_pc~0; 27107#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27783#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27915#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27738#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26767#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26768#L522-1 assume 1 == ~t2_pc~0; 27624#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27625#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27539#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26678#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26679#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27412#L541-1 assume 1 == ~t3_pc~0; 27079#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27080#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27648#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27649#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26883#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26884#L560-1 assume !(1 == ~t4_pc~0); 27811#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 27812#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27776#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27709#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27194#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26991#L579-1 assume 1 == ~t5_pc~0; 26992#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27514#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27893#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27894#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27302#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27303#L598-1 assume 1 == ~t6_pc~0; 27777#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27172#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27353#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27720#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27784#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26952#L617-1 assume 1 == ~t7_pc~0; 26953#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27203#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27204#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27876#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27363#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27021#L636-1 assume 1 == ~t8_pc~0; 27022#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27378#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27379#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27941#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26867#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26868#L655-1 assume !(1 == ~t9_pc~0); 27348#L665-1 is_transmit9_triggered_~__retres1~9#1 := 0; 27349#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27210#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27211#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27098#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27099#L674-1 assume 1 == ~t10_pc~0; 27429#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26969#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26970#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27191#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 27026#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27027#L1119 assume 1 == ~M_E~0;~M_E~0 := 2; 27461#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27367#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27368#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27773#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27492#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26688#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26689#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27704#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27828#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27513#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 27321#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 27322#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 27675#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 27867#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 27466#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 27443#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 27444#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 27646#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 27793#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 27794#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 27678#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 27664#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 26766#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 27173#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 27174#L1539 assume !(0 == start_simulation_~tmp~3#1); 27256#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 27910#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 26677#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 27125#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 27155#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26844#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26845#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 27257#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 27258#L1520 [2024-11-17 08:53:50,505 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,505 INFO L85 PathProgramCache]: Analyzing trace with hash -2024194978, now seen corresponding path program 1 times [2024-11-17 08:53:50,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [507779875] [2024-11-17 08:53:50,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:50,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:50,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:50,563 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [507779875] [2024-11-17 08:53:50,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [507779875] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:50,563 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:50,563 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:50,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1773634431] [2024-11-17 08:53:50,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:50,564 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:50,564 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,564 INFO L85 PathProgramCache]: Analyzing trace with hash -1139375546, now seen corresponding path program 1 times [2024-11-17 08:53:50,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,564 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076706403] [2024-11-17 08:53:50,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:50,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:50,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:50,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076706403] [2024-11-17 08:53:50,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2076706403] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:50,644 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:50,644 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:50,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680021250] [2024-11-17 08:53:50,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:50,645 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:50,645 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:50,646 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:50,646 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:50,646 INFO L87 Difference]: Start difference. First operand 1327 states and 1941 transitions. cyclomatic complexity: 615 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:50,801 INFO L93 Difference]: Finished difference Result 2438 states and 3540 transitions. [2024-11-17 08:53:50,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2438 states and 3540 transitions. [2024-11-17 08:53:50,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2301 [2024-11-17 08:53:50,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2438 states to 2438 states and 3540 transitions. [2024-11-17 08:53:50,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2438 [2024-11-17 08:53:50,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2438 [2024-11-17 08:53:50,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2438 states and 3540 transitions. [2024-11-17 08:53:50,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:50,835 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2438 states and 3540 transitions. [2024-11-17 08:53:50,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2438 states and 3540 transitions. [2024-11-17 08:53:50,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2438 to 2438. [2024-11-17 08:53:50,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2438 states, 2438 states have (on average 1.4520098441345366) internal successors, (3540), 2437 states have internal predecessors, (3540), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:50,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2438 states to 2438 states and 3540 transitions. [2024-11-17 08:53:50,878 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2438 states and 3540 transitions. [2024-11-17 08:53:50,879 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:50,879 INFO L425 stractBuchiCegarLoop]: Abstraction has 2438 states and 3540 transitions. [2024-11-17 08:53:50,879 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:53:50,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2438 states and 3540 transitions. [2024-11-17 08:53:50,886 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2301 [2024-11-17 08:53:50,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:50,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:50,888 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,888 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:50,889 INFO L745 eck$LassoCheckResult]: Stem: 31468#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 30475#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 30476#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 31762#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31787#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 31786#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30841#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30842#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30620#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30621#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31424#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30826#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30707#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30708#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 30468#L751 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30469#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30533#L1006-1 assume !(0 == ~M_E~0); 31463#L1011-1 assume !(0 == ~T1_E~0); 31708#L1016-1 assume !(0 == ~T2_E~0); 31719#L1021-1 assume !(0 == ~T3_E~0); 30466#L1026-1 assume !(0 == ~T4_E~0); 30467#L1031-1 assume !(0 == ~T5_E~0); 31400#L1036-1 assume !(0 == ~T6_E~0); 31394#L1041-1 assume !(0 == ~T7_E~0); 31395#L1046-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30792#L1051-1 assume !(0 == ~T9_E~0); 30793#L1056-1 assume !(0 == ~T10_E~0); 31527#L1061-1 assume !(0 == ~E_1~0); 30699#L1066-1 assume !(0 == ~E_2~0); 30700#L1071-1 assume !(0 == ~E_3~0); 31509#L1076-1 assume !(0 == ~E_4~0); 30574#L1081-1 assume !(0 == ~E_5~0); 30575#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 30971#L1091-1 assume !(0 == ~E_7~0); 31696#L1096-1 assume !(0 == ~E_8~0); 31697#L1101-1 assume !(0 == ~E_9~0); 31034#L1106-1 assume !(0 == ~E_10~0); 31035#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30925#L484-12 assume !(1 == ~m_pc~0); 30524#L494-12 is_master_triggered_~__retres1~0#1 := 0; 30525#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31377#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30491#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 30492#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30778#L503-12 assume 1 == ~t1_pc~0; 30846#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30436#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31783#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31327#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 31328#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31158#L522-12 assume 1 == ~t2_pc~0; 31159#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30937#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30938#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 31228#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 31225#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31226#L541-12 assume !(1 == ~t3_pc~0); 30939#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 30940#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30831#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30832#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 30927#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30928#L560-12 assume 1 == ~t4_pc~0; 31521#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31341#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31209#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31210#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 31455#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31382#L579-12 assume 1 == ~t5_pc~0; 31383#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30891#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30892#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31484#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 31350#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31351#L598-12 assume 1 == ~t6_pc~0; 30615#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30616#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31447#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31448#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 31776#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31777#L617-12 assume !(1 == ~t7_pc~0); 30487#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 30488#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31024#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31025#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 31502#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31619#L636-12 assume 1 == ~t8_pc~0; 31636#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31593#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31339#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31340#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 31314#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31315#L655-12 assume 1 == ~t9_pc~0; 31486#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30565#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30566#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30772#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 30902#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30903#L674-12 assume 1 == ~t10_pc~0; 31616#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 31273#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31640#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30884#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 30885#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31754#L1119-1 assume !(1 == ~M_E~0); 31125#L1124-1 assume !(1 == ~T1_E~0); 30493#L1129-1 assume !(1 == ~T2_E~0); 30494#L1134-1 assume !(1 == ~T3_E~0); 30833#L1139-1 assume !(1 == ~T4_E~0); 30834#L1144-1 assume !(1 == ~T5_E~0); 31064#L1149-1 assume !(1 == ~T6_E~0); 30675#L1154-1 assume !(1 == ~T7_E~0); 30676#L1159-1 assume !(1 == ~T8_E~0); 30774#L1164-1 assume !(1 == ~T9_E~0); 31239#L1169-1 assume !(1 == ~T10_E~0); 31105#L1174-1 assume !(1 == ~E_1~0); 30893#L1179-1 assume !(1 == ~E_2~0); 30757#L1184-1 assume !(1 == ~E_3~0); 30758#L1189-1 assume !(1 == ~E_4~0); 30828#L1194-1 assume !(1 == ~E_5~0); 30957#L1199-1 assume !(1 == ~E_6~0); 30910#L1204-1 assume !(1 == ~E_7~0); 30911#L1209-1 assume !(1 == ~E_8~0); 31464#L1214-1 assume !(1 == ~E_9~0); 31465#L1219-1 assume !(1 == ~E_10~0); 31668#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 31033#L1520 [2024-11-17 08:53:50,889 INFO L747 eck$LassoCheckResult]: Loop: 31033#L1520 assume true; 31623#L1520-1 assume !false; 30990#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30765#L831 assume true; 31357#L831-1 assume !false; 31358#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 31242#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 31019#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 31175#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31176#L836 assume !(0 != eval_~tmp~0#1); 31127#L839 assume true; 31128#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31734#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31594#L1006 assume !(0 == ~M_E~0); 30923#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30924#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31417#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31418#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31737#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30526#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30527#L1041 assume !(0 == ~T7_E~0); 30549#L1046 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30550#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30879#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30880#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 31583#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 31551#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 31552#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 31761#L1081 assume !(0 == ~E_5~0); 31568#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 31544#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 30730#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 30593#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 30594#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 31780#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31746#L484-1 assume !(1 == ~m_pc~0); 31402#L494-1 is_master_triggered_~__retres1~0#1 := 0; 31582#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31598#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31185#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31186#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30881#L503-1 assume 1 == ~t1_pc~0; 30882#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31566#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31704#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31519#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30543#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30544#L522-1 assume 1 == ~t2_pc~0; 31403#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31404#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31318#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30452#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30453#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31187#L541-1 assume 1 == ~t3_pc~0; 30854#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30855#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31427#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 31428#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30657#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30658#L560-1 assume 1 == ~t4_pc~0; 31666#L561-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31596#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32574#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32573#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32572#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32571#L579-1 assume 1 == ~t5_pc~0; 31291#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31292#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31682#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31683#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31076#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31077#L598-1 assume !(1 == ~t6_pc~0); 30946#L608-1 is_transmit6_triggered_~__retres1~6#1 := 0; 30947#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31129#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31501#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 31567#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30724#L617-1 assume 1 == ~t7_pc~0; 30725#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30978#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30979#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31663#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31139#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30796#L636-1 assume 1 == ~t8_pc~0; 30797#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31151#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31152#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31733#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 30641#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30642#L655-1 assume !(1 == ~t9_pc~0); 31121#L665-1 is_transmit9_triggered_~__retres1~9#1 := 0; 31122#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30983#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30984#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30873#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 30874#L674-1 assume 1 == ~t10_pc~0; 31206#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30741#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30742#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30963#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 30801#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30802#L1119 assume !(1 == ~M_E~0); 31664#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32466#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32464#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32462#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32460#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32458#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32456#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32454#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32452#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32450#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32448#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 32446#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 32444#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 32442#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 32440#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 32438#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 32436#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 32434#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 32432#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 32430#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 32428#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 32416#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 32414#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 32412#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 32410#L1539 assume !(0 == start_simulation_~tmp~3#1); 32408#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 31788#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 30449#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 30900#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 30930#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30618#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30619#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 31032#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 31033#L1520 [2024-11-17 08:53:50,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,890 INFO L85 PathProgramCache]: Analyzing trace with hash 1294026330, now seen corresponding path program 1 times [2024-11-17 08:53:50,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413011294] [2024-11-17 08:53:50,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:50,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:50,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:50,985 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:50,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413011294] [2024-11-17 08:53:50,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413011294] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:50,987 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:50,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:50,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [675246640] [2024-11-17 08:53:50,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:50,988 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:50,989 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:50,989 INFO L85 PathProgramCache]: Analyzing trace with hash 1941592545, now seen corresponding path program 1 times [2024-11-17 08:53:50,989 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:50,989 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679965866] [2024-11-17 08:53:50,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:50,990 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:51,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:51,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:51,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:51,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1679965866] [2024-11-17 08:53:51,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1679965866] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:51,062 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:51,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:51,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1741358529] [2024-11-17 08:53:51,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:51,063 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:51,063 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:51,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:51,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:51,064 INFO L87 Difference]: Start difference. First operand 2438 states and 3540 transitions. cyclomatic complexity: 1103 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:51,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:51,192 INFO L93 Difference]: Finished difference Result 4759 states and 6901 transitions. [2024-11-17 08:53:51,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4759 states and 6901 transitions. [2024-11-17 08:53:51,217 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4602 [2024-11-17 08:53:51,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4759 states to 4759 states and 6901 transitions. [2024-11-17 08:53:51,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4759 [2024-11-17 08:53:51,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4759 [2024-11-17 08:53:51,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4759 states and 6901 transitions. [2024-11-17 08:53:51,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:51,254 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4759 states and 6901 transitions. [2024-11-17 08:53:51,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4759 states and 6901 transitions. [2024-11-17 08:53:51,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4759 to 4759. [2024-11-17 08:53:51,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4759 states, 4759 states have (on average 1.450094557680185) internal successors, (6901), 4758 states have internal predecessors, (6901), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:51,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4759 states to 4759 states and 6901 transitions. [2024-11-17 08:53:51,342 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4759 states and 6901 transitions. [2024-11-17 08:53:51,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:51,343 INFO L425 stractBuchiCegarLoop]: Abstraction has 4759 states and 6901 transitions. [2024-11-17 08:53:51,343 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:53:51,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4759 states and 6901 transitions. [2024-11-17 08:53:51,360 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4602 [2024-11-17 08:53:51,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:51,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:51,363 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:51,363 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:51,363 INFO L745 eck$LassoCheckResult]: Stem: 38697#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 37684#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 37685#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39038#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39077#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 39076#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38053#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38054#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37829#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37830#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38650#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38040#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37915#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37916#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37677#L751 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37678#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37740#L1006-1 assume !(0 == ~M_E~0); 38693#L1011-1 assume !(0 == ~T1_E~0); 38967#L1016-1 assume !(0 == ~T2_E~0); 38983#L1021-1 assume !(0 == ~T3_E~0); 37675#L1026-1 assume !(0 == ~T4_E~0); 37676#L1031-1 assume !(0 == ~T5_E~0); 38623#L1036-1 assume !(0 == ~T6_E~0); 38620#L1041-1 assume !(0 == ~T7_E~0); 38621#L1046-1 assume !(0 == ~T8_E~0); 38004#L1051-1 assume !(0 == ~T9_E~0); 38005#L1056-1 assume !(0 == ~T10_E~0); 38758#L1061-1 assume !(0 == ~E_1~0); 37909#L1066-1 assume !(0 == ~E_2~0); 37910#L1071-1 assume !(0 == ~E_3~0); 38737#L1076-1 assume !(0 == ~E_4~0); 37783#L1081-1 assume !(0 == ~E_5~0); 37784#L1086-1 assume 0 == ~E_6~0;~E_6~0 := 1; 38186#L1091-1 assume !(0 == ~E_7~0); 38947#L1096-1 assume !(0 == ~E_8~0); 38948#L1101-1 assume !(0 == ~E_9~0); 38250#L1106-1 assume !(0 == ~E_10~0); 38251#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38140#L484-12 assume !(1 == ~m_pc~0); 37733#L494-12 is_master_triggered_~__retres1~0#1 := 0; 37734#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38603#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37698#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 37699#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37991#L503-12 assume 1 == ~t1_pc~0; 38061#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37642#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39069#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38549#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 38550#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38381#L522-12 assume 1 == ~t2_pc~0; 38382#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38152#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38153#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38450#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 38446#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38447#L541-12 assume !(1 == ~t3_pc~0); 38154#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 38155#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38046#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38047#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 38142#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38143#L560-12 assume 1 == ~t4_pc~0; 38751#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38567#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38432#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38433#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 38685#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38608#L579-12 assume 1 == ~t5_pc~0; 38609#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38104#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38105#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38714#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 38576#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38577#L598-12 assume 1 == ~t6_pc~0; 37820#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37821#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38676#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38677#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 39056#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39057#L617-12 assume !(1 == ~t7_pc~0); 37692#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 37693#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38240#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38241#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 38730#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38859#L636-12 assume 1 == ~t8_pc~0; 38875#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38831#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38565#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38566#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 38538#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38539#L655-12 assume 1 == ~t9_pc~0; 38715#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37771#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37772#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37984#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 38116#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38117#L674-12 assume 1 == ~t10_pc~0; 38855#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38499#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38884#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38099#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 38100#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39028#L1119-1 assume !(1 == ~M_E~0); 38338#L1124-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38339#L1129-1 assume !(1 == ~T2_E~0); 41273#L1134-1 assume !(1 == ~T3_E~0); 41272#L1139-1 assume !(1 == ~T4_E~0); 41271#L1144-1 assume !(1 == ~T5_E~0); 41270#L1149-1 assume !(1 == ~T6_E~0); 41269#L1154-1 assume !(1 == ~T7_E~0); 41268#L1159-1 assume !(1 == ~T8_E~0); 37986#L1164-1 assume !(1 == ~T9_E~0); 41267#L1169-1 assume !(1 == ~T10_E~0); 41266#L1174-1 assume !(1 == ~E_1~0); 41265#L1179-1 assume !(1 == ~E_2~0); 41264#L1184-1 assume !(1 == ~E_3~0); 41263#L1189-1 assume !(1 == ~E_4~0); 41262#L1194-1 assume !(1 == ~E_5~0); 41261#L1199-1 assume !(1 == ~E_6~0); 41260#L1204-1 assume !(1 == ~E_7~0); 41259#L1209-1 assume !(1 == ~E_8~0); 41258#L1214-1 assume !(1 == ~E_9~0); 41257#L1219-1 assume !(1 == ~E_10~0); 38911#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 38249#L1520 [2024-11-17 08:53:51,364 INFO L747 eck$LassoCheckResult]: Loop: 38249#L1520 assume true; 38899#L1520-1 assume !false; 38205#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37975#L831 assume true; 38652#L831-1 assume !false; 38931#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 38932#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 41228#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 38393#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38394#L836 assume !(0 != eval_~tmp~0#1); 41226#L839 assume true; 39078#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 39079#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38833#L1006 assume !(0 == ~M_E~0); 38136#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 38137#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 39042#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41223#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39007#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37735#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37736#L1041 assume !(0 == ~T7_E~0); 41221#L1046 assume !(0 == ~T8_E~0); 41220#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41219#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38821#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 38822#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 38783#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 38784#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 39037#L1081 assume !(0 == ~E_5~0); 39044#L1086 assume 0 == ~E_6~0;~E_6~0 := 1; 38775#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 38776#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 37802#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 37803#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 41216#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41215#L484-1 assume !(1 == ~m_pc~0); 38819#L494-1 is_master_triggered_~__retres1~0#1 := 0; 38820#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38878#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38407#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38408#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41212#L503-1 assume !(1 == ~t1_pc~0); 38801#L513-1 is_transmit1_triggered_~__retres1~1#1 := 0; 38800#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39064#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38750#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37750#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37751#L522-1 assume 1 == ~t2_pc~0; 38629#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38630#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41206#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41205#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41198#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41197#L541-1 assume !(1 == ~t3_pc~0); 41195#L551-1 is_transmit3_triggered_~__retres1~3#1 := 0; 41194#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41193#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41192#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40469#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40468#L560-1 assume !(1 == ~t4_pc~0); 40466#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 40465#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40464#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40463#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40462#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40461#L579-1 assume !(1 == ~t5_pc~0); 40459#L589-1 is_transmit5_triggered_~__retres1~5#1 := 0; 40458#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40457#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40456#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40455#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40454#L598-1 assume !(1 == ~t6_pc~0); 40452#L608-1 is_transmit6_triggered_~__retres1~6#1 := 0; 40451#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40450#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40449#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40448#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40447#L617-1 assume !(1 == ~t7_pc~0); 40445#L627-1 is_transmit7_triggered_~__retres1~7#1 := 0; 40444#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40443#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40442#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 40441#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40440#L636-1 assume !(1 == ~t8_pc~0); 40438#L646-1 is_transmit8_triggered_~__retres1~8#1 := 0; 40437#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40436#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40435#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 40434#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40433#L655-1 assume 1 == ~t9_pc~0; 40432#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40430#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40429#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40428#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40427#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40426#L674-1 assume !(1 == ~t10_pc~0); 40424#L684-1 is_transmit10_triggered_~__retres1~10#1 := 0; 40423#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40422#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40421#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40420#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40419#L1119 assume !(1 == ~M_E~0); 40025#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38462#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40418#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40417#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40416#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40415#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40414#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40413#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38852#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40412#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40411#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 40410#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 40409#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 40408#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 40407#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 40406#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 40405#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 40404#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 40403#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 40402#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 40401#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 40390#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 40389#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 40388#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 40387#L1539 assume !(0 == start_simulation_~tmp~3#1); 38950#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 38951#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 37660#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 38115#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 38145#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 37827#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 37828#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 38248#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 38249#L1520 [2024-11-17 08:53:51,364 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:51,365 INFO L85 PathProgramCache]: Analyzing trace with hash 149321080, now seen corresponding path program 1 times [2024-11-17 08:53:51,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:51,365 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483165181] [2024-11-17 08:53:51,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:51,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:51,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:51,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:51,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:51,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483165181] [2024-11-17 08:53:51,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483165181] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:51,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:51,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:51,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491000727] [2024-11-17 08:53:51,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:51,469 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:51,469 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:51,469 INFO L85 PathProgramCache]: Analyzing trace with hash -68077586, now seen corresponding path program 1 times [2024-11-17 08:53:51,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:51,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152546786] [2024-11-17 08:53:51,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:51,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:51,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:51,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:51,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:51,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152546786] [2024-11-17 08:53:51,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152546786] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:51,559 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:51,559 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:51,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1328814785] [2024-11-17 08:53:51,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:51,560 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:51,560 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:51,560 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:51,560 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:51,561 INFO L87 Difference]: Start difference. First operand 4759 states and 6901 transitions. cyclomatic complexity: 2144 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:51,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:51,765 INFO L93 Difference]: Finished difference Result 9067 states and 13136 transitions. [2024-11-17 08:53:51,765 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9067 states and 13136 transitions. [2024-11-17 08:53:51,818 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8888 [2024-11-17 08:53:51,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9067 states to 9067 states and 13136 transitions. [2024-11-17 08:53:51,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9067 [2024-11-17 08:53:51,874 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9067 [2024-11-17 08:53:51,874 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9067 states and 13136 transitions. [2024-11-17 08:53:51,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:51,890 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9067 states and 13136 transitions. [2024-11-17 08:53:51,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9067 states and 13136 transitions. [2024-11-17 08:53:52,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9067 to 9063. [2024-11-17 08:53:52,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9063 states, 9063 states have (on average 1.4489683327816396) internal successors, (13132), 9062 states have internal predecessors, (13132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:52,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9063 states to 9063 states and 13132 transitions. [2024-11-17 08:53:52,075 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9063 states and 13132 transitions. [2024-11-17 08:53:52,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:53:52,077 INFO L425 stractBuchiCegarLoop]: Abstraction has 9063 states and 13132 transitions. [2024-11-17 08:53:52,077 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:53:52,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9063 states and 13132 transitions. [2024-11-17 08:53:52,117 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8888 [2024-11-17 08:53:52,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:52,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:52,119 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:52,119 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:52,120 INFO L745 eck$LassoCheckResult]: Stem: 52535#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 51522#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 51523#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52855#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52901#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 52898#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51890#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51891#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51668#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 51669#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52489#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 51876#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 51755#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 51756#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 51515#L751 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51516#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51579#L1006-1 assume !(0 == ~M_E~0); 52530#L1011-1 assume !(0 == ~T1_E~0); 52792#L1016-1 assume !(0 == ~T2_E~0); 52808#L1021-1 assume !(0 == ~T3_E~0); 51513#L1026-1 assume !(0 == ~T4_E~0); 51514#L1031-1 assume !(0 == ~T5_E~0); 52464#L1036-1 assume !(0 == ~T6_E~0); 52457#L1041-1 assume !(0 == ~T7_E~0); 52458#L1046-1 assume !(0 == ~T8_E~0); 51841#L1051-1 assume !(0 == ~T9_E~0); 51842#L1056-1 assume !(0 == ~T10_E~0); 52596#L1061-1 assume !(0 == ~E_1~0); 51747#L1066-1 assume !(0 == ~E_2~0); 51748#L1071-1 assume !(0 == ~E_3~0); 52577#L1076-1 assume !(0 == ~E_4~0); 51622#L1081-1 assume !(0 == ~E_5~0); 51623#L1086-1 assume !(0 == ~E_6~0); 52026#L1091-1 assume !(0 == ~E_7~0); 52778#L1096-1 assume !(0 == ~E_8~0); 52779#L1101-1 assume !(0 == ~E_9~0); 52090#L1106-1 assume !(0 == ~E_10~0); 52091#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51977#L484-12 assume !(1 == ~m_pc~0); 51572#L494-12 is_master_triggered_~__retres1~0#1 := 0; 51573#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52440#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 51538#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 51539#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51827#L503-12 assume 1 == ~t1_pc~0; 51897#L504-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 51480#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52891#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52385#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 52386#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52218#L522-12 assume 1 == ~t2_pc~0; 52219#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51989#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51990#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 52290#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 52285#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52286#L541-12 assume !(1 == ~t3_pc~0); 51991#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 51992#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51882#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51883#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 51979#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51980#L560-12 assume 1 == ~t4_pc~0; 52591#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52404#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52271#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52272#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 52522#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52445#L579-12 assume 1 == ~t5_pc~0; 52446#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51941#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51942#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52553#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 52413#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52414#L598-12 assume 1 == ~t6_pc~0; 51663#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51664#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52514#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52515#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 52875#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52876#L617-12 assume !(1 == ~t7_pc~0); 51532#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 51533#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52080#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52081#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 52570#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52693#L636-12 assume 1 == ~t8_pc~0; 52710#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52665#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52402#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52403#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 52376#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52377#L655-12 assume 1 == ~t9_pc~0; 52555#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51610#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51611#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51819#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 51953#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51954#L674-12 assume 1 == ~t10_pc~0; 52688#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52337#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52717#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51935#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 51936#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52845#L1119-1 assume !(1 == ~M_E~0); 52180#L1124-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52181#L1129-1 assume !(1 == ~T2_E~0); 56645#L1134-1 assume !(1 == ~T3_E~0); 56644#L1139-1 assume !(1 == ~T4_E~0); 56643#L1144-1 assume !(1 == ~T5_E~0); 56642#L1149-1 assume !(1 == ~T6_E~0); 56641#L1154-1 assume !(1 == ~T7_E~0); 56638#L1159-1 assume !(1 == ~T8_E~0); 56636#L1164-1 assume !(1 == ~T9_E~0); 52303#L1169-1 assume !(1 == ~T10_E~0); 52161#L1174-1 assume !(1 == ~E_1~0); 51943#L1179-1 assume !(1 == ~E_2~0); 51805#L1184-1 assume !(1 == ~E_3~0); 51806#L1189-1 assume !(1 == ~E_4~0); 51877#L1194-1 assume !(1 == ~E_5~0); 56106#L1199-1 assume !(1 == ~E_6~0); 55910#L1204-1 assume !(1 == ~E_7~0); 55727#L1209-1 assume !(1 == ~E_8~0); 55600#L1214-1 assume !(1 == ~E_9~0); 55334#L1219-1 assume !(1 == ~E_10~0); 55228#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 53905#L1520 [2024-11-17 08:53:52,120 INFO L747 eck$LassoCheckResult]: Loop: 53905#L1520 assume true; 53902#L1520-1 assume !false; 53892#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53887#L831 assume true; 53885#L831-1 assume !false; 53884#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 53877#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 53860#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 53858#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 53855#L836 assume !(0 != eval_~tmp~0#1); 53852#L839 assume true; 53850#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53848#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53846#L1006 assume !(0 == ~M_E~0); 53843#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52865#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52481#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52482#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52832#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 51574#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 51575#L1041 assume !(0 == ~T7_E~0); 51597#L1046 assume !(0 == ~T8_E~0); 51598#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 51930#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51931#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 52656#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 52620#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 52621#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 52854#L1081 assume !(0 == ~E_5~0); 52640#L1086 assume !(0 == ~E_6~0); 52613#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 51778#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 51641#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 51642#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 52883#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52842#L484-1 assume !(1 == ~m_pc~0); 52466#L494-1 is_master_triggered_~__retres1~0#1 := 0; 52655#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52670#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52245#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52246#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51932#L503-1 assume 1 == ~t1_pc~0; 51933#L504-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52637#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52789#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52589#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51589#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51590#L522-1 assume 1 == ~t2_pc~0; 52467#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52468#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52380#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 51499#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 51500#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52247#L541-1 assume 1 == ~t3_pc~0; 51905#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 51906#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52493#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52494#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 51705#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 51706#L560-1 assume 1 == ~t4_pc~0; 52745#L561-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52668#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52630#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52557#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52024#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 51814#L579-1 assume 1 == ~t5_pc~0; 51815#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 52355#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52762#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52763#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 52133#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52134#L598-1 assume 1 == ~t6_pc~0; 52631#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51999#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52187#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52569#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 52638#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52639#L617-1 assume !(1 == ~t7_pc~0); 53771#L627-1 is_transmit7_triggered_~__retres1~7#1 := 0; 53770#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53769#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53768#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53767#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53766#L636-1 assume !(1 == ~t8_pc~0); 53764#L646-1 is_transmit8_triggered_~__retres1~8#1 := 0; 53763#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53762#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53761#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53760#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53759#L655-1 assume !(1 == ~t9_pc~0); 53757#L665-1 is_transmit9_triggered_~__retres1~9#1 := 0; 52859#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52038#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52039#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 51924#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51925#L674-1 assume 1 == ~t10_pc~0; 52268#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51789#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51790#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52018#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 51850#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51851#L1119 assume !(1 == ~M_E~0); 52300#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52203#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52204#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52626#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52333#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51509#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51510#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52552#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52686#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52353#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52153#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 52154#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 52521#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 52733#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 52305#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 52282#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 52283#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 56494#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 56492#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 56489#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 56487#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 56473#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 56471#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 56469#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 56467#L1539 assume !(0 == start_simulation_~tmp~3#1); 56463#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 56314#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 56127#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 55928#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 55735#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55603#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55336#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 55229#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 53905#L1520 [2024-11-17 08:53:52,121 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:52,121 INFO L85 PathProgramCache]: Analyzing trace with hash -660166377, now seen corresponding path program 1 times [2024-11-17 08:53:52,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:52,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55124015] [2024-11-17 08:53:52,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:52,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:52,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:52,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:52,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:52,223 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [55124015] [2024-11-17 08:53:52,223 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [55124015] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:52,223 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:52,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:52,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920665150] [2024-11-17 08:53:52,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:52,224 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:52,224 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:52,224 INFO L85 PathProgramCache]: Analyzing trace with hash -300569156, now seen corresponding path program 1 times [2024-11-17 08:53:52,225 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:52,225 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740141814] [2024-11-17 08:53:52,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:52,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:52,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:52,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:52,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:52,303 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740141814] [2024-11-17 08:53:52,303 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740141814] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:52,303 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:52,303 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:52,304 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681969508] [2024-11-17 08:53:52,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:52,304 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:52,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:52,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:52,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:52,306 INFO L87 Difference]: Start difference. First operand 9063 states and 13132 transitions. cyclomatic complexity: 4073 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:52,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:52,469 INFO L93 Difference]: Finished difference Result 17222 states and 24825 transitions. [2024-11-17 08:53:52,469 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17222 states and 24825 transitions. [2024-11-17 08:53:52,569 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17032 [2024-11-17 08:53:52,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17222 states to 17222 states and 24825 transitions. [2024-11-17 08:53:52,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17222 [2024-11-17 08:53:52,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17222 [2024-11-17 08:53:52,663 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17222 states and 24825 transitions. [2024-11-17 08:53:52,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:52,686 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17222 states and 24825 transitions. [2024-11-17 08:53:52,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17222 states and 24825 transitions. [2024-11-17 08:53:53,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17222 to 17190. [2024-11-17 08:53:53,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17190 states, 17190 states have (on average 1.4422920302501454) internal successors, (24793), 17189 states have internal predecessors, (24793), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:53,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17190 states to 17190 states and 24793 transitions. [2024-11-17 08:53:53,081 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17190 states and 24793 transitions. [2024-11-17 08:53:53,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:53,082 INFO L425 stractBuchiCegarLoop]: Abstraction has 17190 states and 24793 transitions. [2024-11-17 08:53:53,082 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:53:53,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17190 states and 24793 transitions. [2024-11-17 08:53:53,145 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17000 [2024-11-17 08:53:53,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:53,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:53,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:53,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:53,148 INFO L745 eck$LassoCheckResult]: Stem: 78828#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 77816#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 77817#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 79146#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79190#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 79186#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78186#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78187#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77962#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77963#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78782#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 78170#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 78050#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 78051#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 77809#L751 assume 1 == ~t10_i~0;~t10_st~0 := 0; 77810#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77875#L1006-1 assume !(0 == ~M_E~0); 78823#L1011-1 assume !(0 == ~T1_E~0); 79092#L1016-1 assume !(0 == ~T2_E~0); 79104#L1021-1 assume !(0 == ~T3_E~0); 77807#L1026-1 assume !(0 == ~T4_E~0); 77808#L1031-1 assume !(0 == ~T5_E~0); 78753#L1036-1 assume !(0 == ~T6_E~0); 78747#L1041-1 assume !(0 == ~T7_E~0); 78748#L1046-1 assume !(0 == ~T8_E~0); 78136#L1051-1 assume !(0 == ~T9_E~0); 78137#L1056-1 assume !(0 == ~T10_E~0); 78887#L1061-1 assume !(0 == ~E_1~0); 78042#L1066-1 assume !(0 == ~E_2~0); 78043#L1071-1 assume !(0 == ~E_3~0); 78871#L1076-1 assume !(0 == ~E_4~0); 77916#L1081-1 assume !(0 == ~E_5~0); 77917#L1086-1 assume !(0 == ~E_6~0); 78313#L1091-1 assume !(0 == ~E_7~0); 79079#L1096-1 assume !(0 == ~E_8~0); 79080#L1101-1 assume !(0 == ~E_9~0); 78381#L1106-1 assume !(0 == ~E_10~0); 78382#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 78268#L484-12 assume !(1 == ~m_pc~0); 77866#L494-12 is_master_triggered_~__retres1~0#1 := 0; 77867#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78731#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77832#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 77833#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78122#L503-12 assume !(1 == ~t1_pc~0); 77776#L513-12 is_transmit1_triggered_~__retres1~1#1 := 0; 77777#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79177#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 78681#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 78682#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 78507#L522-12 assume 1 == ~t2_pc~0; 78508#L523-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78280#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78281#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 78580#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 78577#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78578#L541-12 assume !(1 == ~t3_pc~0); 78282#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 78283#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78176#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78177#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 78270#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78271#L560-12 assume 1 == ~t4_pc~0; 78883#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78695#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78561#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78562#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 78815#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78736#L579-12 assume 1 == ~t5_pc~0; 78737#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 78234#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 78235#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 78845#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 78704#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78705#L598-12 assume 1 == ~t6_pc~0; 77957#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77958#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78807#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78808#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 79162#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 79163#L617-12 assume !(1 == ~t7_pc~0); 77828#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 77829#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78369#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 78370#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 78863#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78991#L636-12 assume 1 == ~t8_pc~0; 79010#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 78962#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78693#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 78694#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 78668#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 78669#L655-12 assume 1 == ~t9_pc~0; 78847#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 77907#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77908#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78116#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 78245#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78246#L674-12 assume 1 == ~t10_pc~0; 78987#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 78629#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 79014#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78227#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 78228#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79137#L1119-1 assume !(1 == ~M_E~0); 78472#L1124-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77834#L1129-1 assume !(1 == ~T2_E~0); 77835#L1134-1 assume !(1 == ~T3_E~0); 78178#L1139-1 assume !(1 == ~T4_E~0); 78179#L1144-1 assume !(1 == ~T5_E~0); 78411#L1149-1 assume !(1 == ~T6_E~0); 78018#L1154-1 assume !(1 == ~T7_E~0); 78019#L1159-1 assume !(1 == ~T8_E~0); 78118#L1164-1 assume !(1 == ~T9_E~0); 78594#L1169-1 assume !(1 == ~T10_E~0); 78595#L1174-1 assume !(1 == ~E_1~0); 85760#L1179-1 assume !(1 == ~E_2~0); 85758#L1184-1 assume !(1 == ~E_3~0); 78172#L1189-1 assume !(1 == ~E_4~0); 78173#L1194-1 assume !(1 == ~E_5~0); 78300#L1199-1 assume !(1 == ~E_6~0); 85228#L1204-1 assume !(1 == ~E_7~0); 85226#L1209-1 assume !(1 == ~E_8~0); 85107#L1214-1 assume !(1 == ~E_9~0); 85105#L1219-1 assume !(1 == ~E_10~0); 85083#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 85074#L1520 [2024-11-17 08:53:53,148 INFO L747 eck$LassoCheckResult]: Loop: 85074#L1520 assume true; 85066#L1520-1 assume !false; 85059#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85052#L831 assume true; 85049#L831-1 assume !false; 85047#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 85040#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 85033#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 85031#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 85027#L836 assume !(0 != eval_~tmp~0#1); 85028#L839 assume true; 94334#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94333#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 78963#L1006 assume !(0 == ~M_E~0); 78266#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78267#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 79151#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 79176#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 79123#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77868#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 77869#L1041 assume !(0 == ~T7_E~0); 77891#L1046 assume !(0 == ~T8_E~0); 77892#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 78223#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 78224#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 78954#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 78916#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 78917#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 79144#L1081 assume !(0 == ~E_5~0); 78937#L1086 assume !(0 == ~E_6~0); 78909#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 78076#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 77935#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 77936#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 79170#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79133#L484-1 assume !(1 == ~m_pc~0); 78759#L494-1 is_master_triggered_~__retres1~0#1 := 0; 78953#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 78967#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 78535#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 78536#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 78225#L503-1 assume !(1 == ~t1_pc~0); 78226#L513-1 is_transmit1_triggered_~__retres1~1#1 := 0; 79173#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79089#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 78881#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77883#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77884#L522-1 assume 1 == ~t2_pc~0; 78760#L523-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 78761#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 78672#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77793#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77794#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 78537#L541-1 assume 1 == ~t3_pc~0; 78198#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 78199#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 78785#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 78786#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78000#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 78001#L560-1 assume 1 == ~t4_pc~0; 79042#L561-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 78965#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 78926#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 78850#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 78311#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 78110#L579-1 assume !(1 == ~t5_pc~0); 78112#L589-1 is_transmit5_triggered_~__retres1~5#1 := 0; 78647#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79064#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 79065#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 78423#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 78424#L598-1 assume !(1 == ~t6_pc~0); 78289#L608-1 is_transmit6_triggered_~__retres1~6#1 := 0; 78290#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 78477#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 78862#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 78935#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 78067#L617-1 assume !(1 == ~t7_pc~0); 78069#L627-1 is_transmit7_triggered_~__retres1~7#1 := 0; 78319#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 78320#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 79039#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 78487#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 78138#L636-1 assume 1 == ~t8_pc~0; 78139#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 78500#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 78501#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 79120#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 77983#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77984#L655-1 assume !(1 == ~t9_pc~0); 78468#L665-1 is_transmit9_triggered_~__retres1~9#1 := 0; 78469#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 78326#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 78327#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 78217#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 78218#L674-1 assume !(1 == ~t10_pc~0); 78559#L684-1 is_transmit10_triggered_~__retres1~10#1 := 0; 78084#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 78085#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 78305#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 78145#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78146#L1119 assume !(1 == ~M_E~0); 79040#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85993#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 90513#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 90511#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 90509#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 90507#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 90505#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 90502#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 90498#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 90496#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 90494#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 90492#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 90490#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 90487#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 90485#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 90483#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 85966#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 90480#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 90478#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 90475#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 90473#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 89504#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 89501#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 89497#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 85771#L1539 assume !(0 == start_simulation_~tmp~3#1); 85235#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 85122#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 85117#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 85115#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 85113#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 85111#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 85109#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 85084#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 85074#L1520 [2024-11-17 08:53:53,149 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:53,149 INFO L85 PathProgramCache]: Analyzing trace with hash 1181050676, now seen corresponding path program 1 times [2024-11-17 08:53:53,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:53,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1195968011] [2024-11-17 08:53:53,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:53,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:53,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:53,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:53,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:53,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1195968011] [2024-11-17 08:53:53,200 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1195968011] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:53,200 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:53,200 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:53,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1229545892] [2024-11-17 08:53:53,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:53,201 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:53,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:53,202 INFO L85 PathProgramCache]: Analyzing trace with hash -27785005, now seen corresponding path program 1 times [2024-11-17 08:53:53,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:53,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291600081] [2024-11-17 08:53:53,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:53,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:53,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:53,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:53,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:53,262 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1291600081] [2024-11-17 08:53:53,262 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1291600081] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:53,262 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:53,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:53,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806688907] [2024-11-17 08:53:53,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:53,263 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:53,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:53,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:53,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:53,265 INFO L87 Difference]: Start difference. First operand 17190 states and 24793 transitions. cyclomatic complexity: 7611 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:53,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:53,580 INFO L93 Difference]: Finished difference Result 32765 states and 47042 transitions. [2024-11-17 08:53:53,580 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32765 states and 47042 transitions. [2024-11-17 08:53:53,850 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 32528 [2024-11-17 08:53:54,004 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32765 states to 32765 states and 47042 transitions. [2024-11-17 08:53:54,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32765 [2024-11-17 08:53:54,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32765 [2024-11-17 08:53:54,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32765 states and 47042 transitions. [2024-11-17 08:53:54,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:54,082 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32765 states and 47042 transitions. [2024-11-17 08:53:54,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32765 states and 47042 transitions. [2024-11-17 08:53:54,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32765 to 32701. [2024-11-17 08:53:54,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32701 states, 32701 states have (on average 1.4365921531451638) internal successors, (46978), 32700 states have internal predecessors, (46978), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:54,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32701 states to 32701 states and 46978 transitions. [2024-11-17 08:53:54,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32701 states and 46978 transitions. [2024-11-17 08:53:54,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:54,722 INFO L425 stractBuchiCegarLoop]: Abstraction has 32701 states and 46978 transitions. [2024-11-17 08:53:54,722 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:53:54,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32701 states and 46978 transitions. [2024-11-17 08:53:54,854 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 32464 [2024-11-17 08:53:54,855 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:54,855 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:54,857 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:54,857 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:54,858 INFO L745 eck$LassoCheckResult]: Stem: 128789#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 127780#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 127781#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 129114#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 129166#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 129164#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 128142#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 128143#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 127923#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127924#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 128739#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 128130#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 128008#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 128009#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 127773#L751 assume 1 == ~t10_i~0;~t10_st~0 := 0; 127774#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127836#L1006-1 assume !(0 == ~M_E~0); 128785#L1011-1 assume !(0 == ~T1_E~0); 129056#L1016-1 assume !(0 == ~T2_E~0); 129071#L1021-1 assume !(0 == ~T3_E~0); 127771#L1026-1 assume !(0 == ~T4_E~0); 127772#L1031-1 assume !(0 == ~T5_E~0); 128708#L1036-1 assume !(0 == ~T6_E~0); 128705#L1041-1 assume !(0 == ~T7_E~0); 128706#L1046-1 assume !(0 == ~T8_E~0); 128094#L1051-1 assume !(0 == ~T9_E~0); 128095#L1056-1 assume !(0 == ~T10_E~0); 128855#L1061-1 assume !(0 == ~E_1~0); 128002#L1066-1 assume !(0 == ~E_2~0); 128003#L1071-1 assume !(0 == ~E_3~0); 128837#L1076-1 assume !(0 == ~E_4~0); 127879#L1081-1 assume !(0 == ~E_5~0); 127880#L1086-1 assume !(0 == ~E_6~0); 128276#L1091-1 assume !(0 == ~E_7~0); 129041#L1096-1 assume !(0 == ~E_8~0); 129042#L1101-1 assume !(0 == ~E_9~0); 128340#L1106-1 assume !(0 == ~E_10~0); 128341#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 128229#L484-12 assume !(1 == ~m_pc~0); 127829#L494-12 is_master_triggered_~__retres1~0#1 := 0; 127830#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128688#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 127794#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 127795#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 128081#L503-12 assume !(1 == ~t1_pc~0); 127737#L513-12 is_transmit1_triggered_~__retres1~1#1 := 0; 127738#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129159#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 128634#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 128635#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128467#L522-12 assume !(1 == ~t2_pc~0); 128468#L532-12 is_transmit2_triggered_~__retres1~2#1 := 0; 128241#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 128242#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 128538#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 128534#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 128535#L541-12 assume !(1 == ~t3_pc~0); 128243#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 128244#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 128135#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 128136#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 128231#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128232#L560-12 assume 1 == ~t4_pc~0; 128849#L561-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 128653#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 128518#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 128519#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 128775#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128694#L579-12 assume 1 == ~t5_pc~0; 128695#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 128193#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 128194#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 128808#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 128662#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 128663#L598-12 assume 1 == ~t6_pc~0; 127914#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 127915#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 128766#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 128767#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 129141#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 129142#L617-12 assume !(1 == ~t7_pc~0); 127788#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 127789#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 128329#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 128330#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 128830#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 128952#L636-12 assume 1 == ~t8_pc~0; 128970#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 128926#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 128651#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 128652#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 128623#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 128624#L655-12 assume 1 == ~t9_pc~0; 128809#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 127867#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 127868#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 128074#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 128205#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 128206#L674-12 assume 1 == ~t10_pc~0; 128948#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 128585#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 128976#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 128187#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 128188#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129104#L1119-1 assume !(1 == ~M_E~0); 128425#L1124-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 127798#L1129-1 assume !(1 == ~T2_E~0); 127799#L1134-1 assume !(1 == ~T3_E~0); 128137#L1139-1 assume !(1 == ~T4_E~0); 128138#L1144-1 assume !(1 == ~T5_E~0); 138147#L1149-1 assume !(1 == ~T6_E~0); 138145#L1154-1 assume !(1 == ~T7_E~0); 128076#L1159-1 assume !(1 == ~T8_E~0); 128077#L1164-1 assume !(1 == ~T9_E~0); 128551#L1169-1 assume !(1 == ~T10_E~0); 128411#L1174-1 assume !(1 == ~E_1~0); 128195#L1179-1 assume !(1 == ~E_2~0); 128060#L1184-1 assume !(1 == ~E_3~0); 128061#L1189-1 assume !(1 == ~E_4~0); 128131#L1194-1 assume !(1 == ~E_5~0); 128261#L1199-1 assume !(1 == ~E_6~0); 129165#L1204-1 assume !(1 == ~E_7~0); 143302#L1209-1 assume !(1 == ~E_8~0); 143300#L1214-1 assume !(1 == ~E_9~0); 143298#L1219-1 assume !(1 == ~E_10~0); 143295#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 143294#L1520 [2024-11-17 08:53:54,859 INFO L747 eck$LassoCheckResult]: Loop: 143294#L1520 assume true; 143292#L1520-1 assume !false; 143290#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 143268#L831 assume true; 143231#L831-1 assume !false; 143225#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 136374#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 136367#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 136365#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 136362#L836 assume !(0 != eval_~tmp~0#1); 136363#L839 assume true; 138067#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 138065#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 138063#L1006 assume !(0 == ~M_E~0); 138061#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 138059#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 138057#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 138055#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 138053#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 138051#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 138049#L1041 assume !(0 == ~T7_E~0); 138047#L1046 assume !(0 == ~T8_E~0); 138045#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 138043#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 138041#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 138039#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 138037#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 138035#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 138033#L1081 assume !(0 == ~E_5~0); 138030#L1086 assume !(0 == ~E_6~0); 138028#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 138026#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 138024#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 138022#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 138020#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138018#L484-1 assume !(1 == ~m_pc~0); 138015#L494-1 is_master_triggered_~__retres1~0#1 := 0; 138013#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138011#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 138009#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 138007#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138005#L503-1 assume !(1 == ~t1_pc~0); 138003#L513-1 is_transmit1_triggered_~__retres1~1#1 := 0; 138001#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 137999#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 137997#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 137995#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 137993#L522-1 assume !(1 == ~t2_pc~0); 137990#L532-1 is_transmit2_triggered_~__retres1~2#1 := 0; 137988#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 137986#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 137984#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 137982#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 137980#L541-1 assume !(1 == ~t3_pc~0); 137976#L551-1 is_transmit3_triggered_~__retres1~3#1 := 0; 137974#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 137972#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 137970#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 137968#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 137966#L560-1 assume !(1 == ~t4_pc~0); 137962#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 137960#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 137958#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 137956#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 137954#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 137952#L579-1 assume !(1 == ~t5_pc~0); 137948#L589-1 is_transmit5_triggered_~__retres1~5#1 := 0; 137946#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 137944#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 137942#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 137940#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 137938#L598-1 assume !(1 == ~t6_pc~0); 137934#L608-1 is_transmit6_triggered_~__retres1~6#1 := 0; 137932#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 137930#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 137928#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 137926#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 137924#L617-1 assume !(1 == ~t7_pc~0); 137920#L627-1 is_transmit7_triggered_~__retres1~7#1 := 0; 137918#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 137916#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 137914#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 137912#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 137910#L636-1 assume !(1 == ~t8_pc~0); 137906#L646-1 is_transmit8_triggered_~__retres1~8#1 := 0; 137904#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 137902#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 137900#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 137898#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 137896#L655-1 assume !(1 == ~t9_pc~0); 137892#L665-1 is_transmit9_triggered_~__retres1~9#1 := 0; 137890#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 137888#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 137886#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 137884#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 137880#L674-1 assume 1 == ~t10_pc~0; 137878#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 137875#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 137873#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 137871#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 137869#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 137867#L1119 assume !(1 == ~M_E~0); 137863#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 137860#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 137859#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 137857#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 137855#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 137853#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 137852#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 137849#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 137845#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 137843#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 137841#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 137839#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 137837#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 137835#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 137833#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 137831#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 137827#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 137825#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 137823#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 137821#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 137818#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 137040#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 137039#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 137038#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 137036#L1539 assume !(0 == start_simulation_~tmp~3#1); 137037#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 143308#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 143304#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 143303#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 143301#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 143299#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 143297#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 143296#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 143294#L1520 [2024-11-17 08:53:54,859 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:54,860 INFO L85 PathProgramCache]: Analyzing trace with hash 555761425, now seen corresponding path program 1 times [2024-11-17 08:53:54,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:54,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [731068657] [2024-11-17 08:53:54,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:54,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:54,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:55,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:55,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:55,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [731068657] [2024-11-17 08:53:55,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [731068657] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:55,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:55,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:55,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386297299] [2024-11-17 08:53:55,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:55,090 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:55,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:55,091 INFO L85 PathProgramCache]: Analyzing trace with hash -1379602518, now seen corresponding path program 1 times [2024-11-17 08:53:55,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:55,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192064477] [2024-11-17 08:53:55,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:55,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:55,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:55,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:55,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:55,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192064477] [2024-11-17 08:53:55,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192064477] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:55,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:55,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:55,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762237278] [2024-11-17 08:53:55,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:55,151 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:55,151 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:55,151 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:55,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:55,152 INFO L87 Difference]: Start difference. First operand 32701 states and 46978 transitions. cyclomatic complexity: 14293 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:55,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:55,684 INFO L93 Difference]: Finished difference Result 62348 states and 89183 transitions. [2024-11-17 08:53:55,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62348 states and 89183 transitions. [2024-11-17 08:53:56,000 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62016 [2024-11-17 08:53:56,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62348 states to 62348 states and 89183 transitions. [2024-11-17 08:53:56,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62348 [2024-11-17 08:53:56,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62348 [2024-11-17 08:53:56,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62348 states and 89183 transitions. [2024-11-17 08:53:56,560 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:56,561 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62348 states and 89183 transitions. [2024-11-17 08:53:56,623 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62348 states and 89183 transitions. [2024-11-17 08:53:57,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62348 to 62220. [2024-11-17 08:53:57,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62220 states, 62220 states have (on average 1.4312921890067503) internal successors, (89055), 62219 states have internal predecessors, (89055), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:57,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62220 states to 62220 states and 89055 transitions. [2024-11-17 08:53:57,910 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62220 states and 89055 transitions. [2024-11-17 08:53:57,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:57,911 INFO L425 stractBuchiCegarLoop]: Abstraction has 62220 states and 89055 transitions. [2024-11-17 08:53:57,911 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:53:57,911 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62220 states and 89055 transitions. [2024-11-17 08:53:58,283 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 61888 [2024-11-17 08:53:58,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:58,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:58,286 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:58,286 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:58,287 INFO L745 eck$LassoCheckResult]: Stem: 223865#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 222837#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 222838#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 224235#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 224289#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 224286#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 223201#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 223202#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 222981#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 222982#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 223814#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 223189#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 223065#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 223066#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 222830#L751 assume 1 == ~t10_i~0;~t10_st~0 := 0; 222831#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222893#L1006-1 assume !(0 == ~M_E~0); 223861#L1011-1 assume !(0 == ~T1_E~0); 224164#L1016-1 assume !(0 == ~T2_E~0); 224181#L1021-1 assume !(0 == ~T3_E~0); 222828#L1026-1 assume !(0 == ~T4_E~0); 222829#L1031-1 assume !(0 == ~T5_E~0); 223782#L1036-1 assume !(0 == ~T6_E~0); 223779#L1041-1 assume !(0 == ~T7_E~0); 223780#L1046-1 assume !(0 == ~T8_E~0); 223152#L1051-1 assume !(0 == ~T9_E~0); 223153#L1056-1 assume !(0 == ~T10_E~0); 223940#L1061-1 assume !(0 == ~E_1~0); 223059#L1066-1 assume !(0 == ~E_2~0); 223060#L1071-1 assume !(0 == ~E_3~0); 223918#L1076-1 assume !(0 == ~E_4~0); 222936#L1081-1 assume !(0 == ~E_5~0); 222937#L1086-1 assume !(0 == ~E_6~0); 223338#L1091-1 assume !(0 == ~E_7~0); 224148#L1096-1 assume !(0 == ~E_8~0); 224149#L1101-1 assume !(0 == ~E_9~0); 223404#L1106-1 assume !(0 == ~E_10~0); 223405#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 223292#L484-12 assume !(1 == ~m_pc~0); 222886#L494-12 is_master_triggered_~__retres1~0#1 := 0; 222887#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223759#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 222851#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 222852#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 223139#L503-12 assume !(1 == ~t1_pc~0); 222795#L513-12 is_transmit1_triggered_~__retres1~1#1 := 0; 222796#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 224277#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 223704#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 223705#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223533#L522-12 assume !(1 == ~t2_pc~0); 223534#L532-12 is_transmit2_triggered_~__retres1~2#1 := 0; 223305#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223306#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 223603#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 223599#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223600#L541-12 assume !(1 == ~t3_pc~0); 223307#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 223308#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 223194#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 223195#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 223294#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223295#L560-12 assume !(1 == ~t4_pc~0); 223934#L570-12 is_transmit4_triggered_~__retres1~4#1 := 0; 223723#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223584#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 223585#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 223852#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 223764#L579-12 assume 1 == ~t5_pc~0; 223765#L580-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 223253#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223254#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 223889#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 223732#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 223733#L598-12 assume 1 == ~t6_pc~0; 222972#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 222973#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223844#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 223845#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 224263#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 224264#L617-12 assume !(1 == ~t7_pc~0); 222845#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 222846#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 223392#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 223393#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 223910#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 224046#L636-12 assume 1 == ~t8_pc~0; 224065#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 224019#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 223721#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 223722#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 223693#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 223694#L655-12 assume 1 == ~t9_pc~0; 223890#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 222924#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 222925#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 223132#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 223265#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 223266#L674-12 assume 1 == ~t10_pc~0; 224042#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 223654#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 224070#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 223248#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 223249#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 224223#L1119-1 assume !(1 == ~M_E~0); 223489#L1124-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 222855#L1129-1 assume !(1 == ~T2_E~0); 222856#L1134-1 assume !(1 == ~T3_E~0); 223196#L1139-1 assume !(1 == ~T4_E~0); 223197#L1144-1 assume !(1 == ~T5_E~0); 223430#L1149-1 assume !(1 == ~T6_E~0); 223032#L1154-1 assume !(1 == ~T7_E~0); 223033#L1159-1 assume !(1 == ~T8_E~0); 223134#L1164-1 assume !(1 == ~T9_E~0); 223618#L1169-1 assume !(1 == ~T10_E~0); 223475#L1174-1 assume !(1 == ~E_1~0); 223255#L1179-1 assume !(1 == ~E_2~0); 223118#L1184-1 assume !(1 == ~E_3~0); 223119#L1189-1 assume !(1 == ~E_4~0); 223190#L1194-1 assume !(1 == ~E_5~0); 223325#L1199-1 assume !(1 == ~E_6~0); 224287#L1204-1 assume !(1 == ~E_7~0); 263637#L1209-1 assume !(1 == ~E_8~0); 263635#L1214-1 assume !(1 == ~E_9~0); 263633#L1219-1 assume !(1 == ~E_10~0); 258724#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 258721#L1520 [2024-11-17 08:53:58,288 INFO L747 eck$LassoCheckResult]: Loop: 258721#L1520 assume true; 258719#L1520-1 assume !false; 258717#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 258712#L831 assume true; 258710#L831-1 assume !false; 258708#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 258686#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 258677#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 258676#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 258673#L836 assume !(0 != eval_~tmp~0#1); 258674#L839 assume true; 259039#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 259037#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 259035#L1006 assume !(0 == ~M_E~0); 259033#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 259031#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 259029#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 259027#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 259025#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 259023#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 259021#L1041 assume !(0 == ~T7_E~0); 259019#L1046 assume !(0 == ~T8_E~0); 259017#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 259015#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 259013#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 259011#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 259009#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 259007#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 259004#L1081 assume !(0 == ~E_5~0); 259002#L1086 assume !(0 == ~E_6~0); 259000#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 258998#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 258996#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 258994#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 258992#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 258990#L484-1 assume !(1 == ~m_pc~0); 258987#L494-1 is_master_triggered_~__retres1~0#1 := 0; 258985#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 258983#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 258981#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 258979#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 258977#L503-1 assume !(1 == ~t1_pc~0); 258975#L513-1 is_transmit1_triggered_~__retres1~1#1 := 0; 258973#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 258971#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 258969#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 258966#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 258964#L522-1 assume !(1 == ~t2_pc~0); 258962#L532-1 is_transmit2_triggered_~__retres1~2#1 := 0; 258960#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 258958#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 258956#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 258954#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 258952#L541-1 assume 1 == ~t3_pc~0; 258950#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 258947#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 258945#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 258943#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 258940#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 258938#L560-1 assume !(1 == ~t4_pc~0); 258936#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 258934#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 258932#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 258930#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 258927#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 258925#L579-1 assume 1 == ~t5_pc~0; 258923#L580-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 258920#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 258918#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 258916#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 258913#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 258911#L598-1 assume 1 == ~t6_pc~0; 258909#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 258906#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 258904#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 258902#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 258899#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 258897#L617-1 assume 1 == ~t7_pc~0; 258895#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 258892#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 258890#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 258888#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 258885#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 258883#L636-1 assume 1 == ~t8_pc~0; 258881#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 258878#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 258876#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 258874#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 258871#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 258869#L655-1 assume 1 == ~t9_pc~0; 258867#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 258864#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 258862#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 258861#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 258860#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 258859#L674-1 assume 1 == ~t10_pc~0; 258857#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 258854#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 258852#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 258851#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 258848#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 258846#L1119 assume !(1 == ~M_E~0); 258842#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 258838#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 258836#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 258834#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 258832#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 258830#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 258828#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 258826#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 258822#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 258820#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 258818#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 258816#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 258814#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 258812#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 258810#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 258808#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 258804#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 258801#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 258799#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 258797#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 258795#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 258771#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 258769#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 258767#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 258763#L1539 assume !(0 == start_simulation_~tmp~3#1); 258760#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 258741#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 258735#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 258733#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 258731#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 258729#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 258727#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 258725#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 258721#L1520 [2024-11-17 08:53:58,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:58,289 INFO L85 PathProgramCache]: Analyzing trace with hash -1201522066, now seen corresponding path program 1 times [2024-11-17 08:53:58,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:58,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501423153] [2024-11-17 08:53:58,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:58,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:58,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:58,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:58,369 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:58,369 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [501423153] [2024-11-17 08:53:58,370 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [501423153] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:58,370 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:58,370 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:58,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [906477927] [2024-11-17 08:53:58,370 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:58,371 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:58,371 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:58,371 INFO L85 PathProgramCache]: Analyzing trace with hash -439777284, now seen corresponding path program 1 times [2024-11-17 08:53:58,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:58,372 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088909047] [2024-11-17 08:53:58,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:58,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:58,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:58,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:58,450 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:58,450 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088909047] [2024-11-17 08:53:58,450 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088909047] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:58,450 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:58,451 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:58,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1106861541] [2024-11-17 08:53:58,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:58,451 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:58,451 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:58,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:53:58,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:53:58,452 INFO L87 Difference]: Start difference. First operand 62220 states and 89055 transitions. cyclomatic complexity: 26867 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:59,411 INFO L93 Difference]: Finished difference Result 150315 states and 213764 transitions. [2024-11-17 08:53:59,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 150315 states and 213764 transitions. [2024-11-17 08:54:00,441 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 149408 [2024-11-17 08:54:01,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 150315 states to 150315 states and 213764 transitions. [2024-11-17 08:54:01,112 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 150315 [2024-11-17 08:54:01,284 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 150315 [2024-11-17 08:54:01,285 INFO L73 IsDeterministic]: Start isDeterministic. Operand 150315 states and 213764 transitions. [2024-11-17 08:54:01,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:01,383 INFO L218 hiAutomatonCegarLoop]: Abstraction has 150315 states and 213764 transitions. [2024-11-17 08:54:01,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150315 states and 213764 transitions. [2024-11-17 08:54:03,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150315 to 120827. [2024-11-17 08:54:03,402 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120827 states, 120827 states have (on average 1.4254760939194053) internal successors, (172236), 120826 states have internal predecessors, (172236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120827 states to 120827 states and 172236 transitions. [2024-11-17 08:54:03,701 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120827 states and 172236 transitions. [2024-11-17 08:54:03,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:54:03,702 INFO L425 stractBuchiCegarLoop]: Abstraction has 120827 states and 172236 transitions. [2024-11-17 08:54:03,702 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:54:03,702 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120827 states and 172236 transitions. [2024-11-17 08:54:04,014 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 120336 [2024-11-17 08:54:04,014 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:04,014 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:04,017 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:04,017 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:04,017 INFO L745 eck$LassoCheckResult]: Stem: 436429#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 435384#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 435385#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 436807#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 436871#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 436870#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 435751#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 435752#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 435528#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 435529#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 436382#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 435739#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 435615#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 435616#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 435377#L751 assume 1 == ~t10_i~0;~t10_st~0 := 0; 435378#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 435439#L1006-1 assume !(0 == ~M_E~0); 436425#L1011-1 assume !(0 == ~T1_E~0); 436728#L1016-1 assume !(0 == ~T2_E~0); 436749#L1021-1 assume !(0 == ~T3_E~0); 435375#L1026-1 assume !(0 == ~T4_E~0); 435376#L1031-1 assume !(0 == ~T5_E~0); 436351#L1036-1 assume !(0 == ~T6_E~0); 436348#L1041-1 assume !(0 == ~T7_E~0); 436349#L1046-1 assume !(0 == ~T8_E~0); 435703#L1051-1 assume !(0 == ~T9_E~0); 435704#L1056-1 assume !(0 == ~T10_E~0); 436497#L1061-1 assume !(0 == ~E_1~0); 435609#L1066-1 assume !(0 == ~E_2~0); 435610#L1071-1 assume !(0 == ~E_3~0); 436480#L1076-1 assume !(0 == ~E_4~0); 435482#L1081-1 assume !(0 == ~E_5~0); 435483#L1086-1 assume !(0 == ~E_6~0); 435890#L1091-1 assume !(0 == ~E_7~0); 436713#L1096-1 assume !(0 == ~E_8~0); 436714#L1101-1 assume !(0 == ~E_9~0); 435955#L1106-1 assume !(0 == ~E_10~0); 435956#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 435840#L484-12 assume !(1 == ~m_pc~0); 435433#L494-12 is_master_triggered_~__retres1~0#1 := 0; 435434#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 436323#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 435398#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 435399#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 435690#L503-12 assume !(1 == ~t1_pc~0); 435342#L513-12 is_transmit1_triggered_~__retres1~1#1 := 0; 435343#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 436856#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 436264#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 436265#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 436089#L522-12 assume !(1 == ~t2_pc~0); 436090#L532-12 is_transmit2_triggered_~__retres1~2#1 := 0; 435855#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 435856#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 436158#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 436154#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 436155#L541-12 assume !(1 == ~t3_pc~0); 435853#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 435854#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 435744#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 435745#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 435842#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 435843#L560-12 assume !(1 == ~t4_pc~0); 436493#L570-12 is_transmit4_triggered_~__retres1~4#1 := 0; 436285#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 436140#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 436141#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 436414#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 436332#L579-12 assume !(1 == ~t5_pc~0); 436333#L589-12 is_transmit5_triggered_~__retres1~5#1 := 0; 435802#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 435803#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 436450#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 436295#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 436296#L598-12 assume 1 == ~t6_pc~0; 435519#L599-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 435520#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 436406#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 436407#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 436840#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 436841#L617-12 assume !(1 == ~t7_pc~0); 435392#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 435393#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 435943#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 435944#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 436471#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 436609#L636-12 assume 1 == ~t8_pc~0; 436628#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 436579#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 436283#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 436284#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 436253#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 436254#L655-12 assume 1 == ~t9_pc~0; 436451#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 435470#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 435471#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 435681#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 435815#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 435816#L674-12 assume 1 == ~t10_pc~0; 436604#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 436212#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 436638#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 435796#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 435797#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 436795#L1119-1 assume !(1 == ~M_E~0); 436042#L1124-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 435402#L1129-1 assume !(1 == ~T2_E~0); 435403#L1134-1 assume !(1 == ~T3_E~0); 435746#L1139-1 assume !(1 == ~T4_E~0); 435747#L1144-1 assume !(1 == ~T5_E~0); 436866#L1149-1 assume !(1 == ~T6_E~0); 436867#L1154-1 assume !(1 == ~T7_E~0); 435684#L1159-1 assume !(1 == ~T8_E~0); 435685#L1164-1 assume !(1 == ~T9_E~0); 436175#L1169-1 assume !(1 == ~T10_E~0); 436028#L1174-1 assume !(1 == ~E_1~0); 435804#L1179-1 assume !(1 == ~E_2~0); 435668#L1184-1 assume !(1 == ~E_3~0); 435669#L1189-1 assume !(1 == ~E_4~0); 435740#L1194-1 assume !(1 == ~E_5~0); 435873#L1199-1 assume !(1 == ~E_6~0); 435821#L1204-1 assume !(1 == ~E_7~0); 435822#L1209-1 assume !(1 == ~E_8~0); 436426#L1214-1 assume !(1 == ~E_9~0); 436427#L1219-1 assume !(1 == ~E_10~0); 436672#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 436673#L1520 [2024-11-17 08:54:04,018 INFO L747 eck$LassoCheckResult]: Loop: 436673#L1520 assume true; 460089#L1520-1 assume !false; 460086#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 460081#L831 assume true; 460079#L831-1 assume !false; 460077#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 460060#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 460053#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 460051#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 460048#L836 assume !(0 != eval_~tmp~0#1); 460046#L839 assume true; 460044#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 460041#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 460039#L1006 assume !(0 == ~M_E~0); 460037#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 460035#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 460033#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 460032#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 460031#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 460028#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 460025#L1041 assume !(0 == ~T7_E~0); 460023#L1046 assume !(0 == ~T8_E~0); 460021#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 460019#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 460017#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 460014#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 460010#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 460009#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 460008#L1081 assume !(0 == ~E_5~0); 460007#L1086 assume !(0 == ~E_6~0); 460006#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 460005#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 460004#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 460003#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 460002#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 460001#L484-1 assume !(1 == ~m_pc~0); 459999#L494-1 is_master_triggered_~__retres1~0#1 := 0; 459998#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 459997#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 459996#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 459995#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 459994#L503-1 assume !(1 == ~t1_pc~0); 459993#L513-1 is_transmit1_triggered_~__retres1~1#1 := 0; 459992#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 459991#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 459989#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 459987#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 459984#L522-1 assume !(1 == ~t2_pc~0); 459982#L532-1 is_transmit2_triggered_~__retres1~2#1 := 0; 459980#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 459978#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 459976#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 459974#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 459972#L541-1 assume 1 == ~t3_pc~0; 459970#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 459967#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 459965#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 459963#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 459961#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 459959#L560-1 assume !(1 == ~t4_pc~0); 459957#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 459955#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 459953#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 459951#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 459949#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 459947#L579-1 assume !(1 == ~t5_pc~0); 442132#L589-1 is_transmit5_triggered_~__retres1~5#1 := 0; 459943#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 459941#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 459939#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 459937#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 459935#L598-1 assume 1 == ~t6_pc~0; 459933#L599-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 459930#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 459928#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 459926#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 459924#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 459922#L617-1 assume 1 == ~t7_pc~0; 459921#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 459918#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 459916#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 459914#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 459912#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 459910#L636-1 assume 1 == ~t8_pc~0; 459907#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 459904#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 459902#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 459900#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 459898#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 459896#L655-1 assume 1 == ~t9_pc~0; 459893#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 459890#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 459888#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 459886#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 459884#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 459882#L674-1 assume 1 == ~t10_pc~0; 459879#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 459876#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 459874#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 459872#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 459870#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 459868#L1119 assume !(1 == ~M_E~0); 458642#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 451284#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 459863#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 459861#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 459859#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 459857#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 459854#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 459852#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 459395#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 459849#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 459847#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 459844#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 459842#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 459840#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 459838#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 459836#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 451368#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 459830#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 459829#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 459828#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 459827#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 459816#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 459815#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 459814#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 459812#L1539 assume !(0 == start_simulation_~tmp~3#1); 459813#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 460108#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 460103#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 460101#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 460098#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 460096#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 460094#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 460092#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 436673#L1520 [2024-11-17 08:54:04,018 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:04,018 INFO L85 PathProgramCache]: Analyzing trace with hash -98091125, now seen corresponding path program 1 times [2024-11-17 08:54:04,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:04,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644868409] [2024-11-17 08:54:04,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:04,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:04,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,081 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,082 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1644868409] [2024-11-17 08:54:04,082 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1644868409] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,082 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,082 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:04,082 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2118465915] [2024-11-17 08:54:04,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,083 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:04,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:04,083 INFO L85 PathProgramCache]: Analyzing trace with hash 1007077785, now seen corresponding path program 1 times [2024-11-17 08:54:04,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:04,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1040182599] [2024-11-17 08:54:04,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:04,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:04,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1040182599] [2024-11-17 08:54:04,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1040182599] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,151 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,151 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:04,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057216125] [2024-11-17 08:54:04,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,151 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:04,151 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:04,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:54:04,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:54:04,152 INFO L87 Difference]: Start difference. First operand 120827 states and 172236 transitions. cyclomatic complexity: 51441 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:06,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:06,371 INFO L93 Difference]: Finished difference Result 286618 states and 406385 transitions. [2024-11-17 08:54:06,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 286618 states and 406385 transitions. [2024-11-17 08:54:07,979 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 284976 [2024-11-17 08:54:08,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 286618 states to 286618 states and 406385 transitions. [2024-11-17 08:54:08,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 286618 [2024-11-17 08:54:09,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 286618 [2024-11-17 08:54:09,052 INFO L73 IsDeterministic]: Start isDeterministic. Operand 286618 states and 406385 transitions. [2024-11-17 08:54:09,208 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:09,208 INFO L218 hiAutomatonCegarLoop]: Abstraction has 286618 states and 406385 transitions. [2024-11-17 08:54:09,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286618 states and 406385 transitions. [2024-11-17 08:54:11,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286618 to 229802. [2024-11-17 08:54:11,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 229802 states, 229802 states have (on average 1.4213670899295916) internal successors, (326633), 229801 states have internal predecessors, (326633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:12,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229802 states to 229802 states and 326633 transitions. [2024-11-17 08:54:12,969 INFO L240 hiAutomatonCegarLoop]: Abstraction has 229802 states and 326633 transitions. [2024-11-17 08:54:12,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:54:12,975 INFO L425 stractBuchiCegarLoop]: Abstraction has 229802 states and 326633 transitions. [2024-11-17 08:54:12,975 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:54:12,975 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 229802 states and 326633 transitions. [2024-11-17 08:54:13,687 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 228992 [2024-11-17 08:54:13,687 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:13,687 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:13,691 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:13,691 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:13,691 INFO L745 eck$LassoCheckResult]: Stem: 843875#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 842841#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 842842#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 844254#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 844324#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 844320#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 843204#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 843205#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 842981#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 842982#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 843828#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 843191#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 843067#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 843068#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 842834#L751 assume 1 == ~t10_i~0;~t10_st~0 := 0; 842835#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 842896#L1006-1 assume !(0 == ~M_E~0); 843871#L1011-1 assume !(0 == ~T1_E~0); 844176#L1016-1 assume !(0 == ~T2_E~0); 844194#L1021-1 assume !(0 == ~T3_E~0); 842832#L1026-1 assume !(0 == ~T4_E~0); 842833#L1031-1 assume !(0 == ~T5_E~0); 843797#L1036-1 assume !(0 == ~T6_E~0); 843793#L1041-1 assume !(0 == ~T7_E~0); 843794#L1046-1 assume !(0 == ~T8_E~0); 843155#L1051-1 assume !(0 == ~T9_E~0); 843156#L1056-1 assume !(0 == ~T10_E~0); 843945#L1061-1 assume !(0 == ~E_1~0); 843061#L1066-1 assume !(0 == ~E_2~0); 843062#L1071-1 assume !(0 == ~E_3~0); 843926#L1076-1 assume !(0 == ~E_4~0); 842939#L1081-1 assume !(0 == ~E_5~0); 842940#L1086-1 assume !(0 == ~E_6~0); 843340#L1091-1 assume !(0 == ~E_7~0); 844160#L1096-1 assume !(0 == ~E_8~0); 844161#L1101-1 assume !(0 == ~E_9~0); 843411#L1106-1 assume !(0 == ~E_10~0); 843412#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 843292#L484-12 assume !(1 == ~m_pc~0); 842890#L494-12 is_master_triggered_~__retres1~0#1 := 0; 842891#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 843772#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 842855#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 842856#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 843142#L503-12 assume !(1 == ~t1_pc~0); 842799#L513-12 is_transmit1_triggered_~__retres1~1#1 := 0; 842800#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 844306#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 843714#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 843715#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 843544#L522-12 assume !(1 == ~t2_pc~0); 843545#L532-12 is_transmit2_triggered_~__retres1~2#1 := 0; 843305#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 843306#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 843615#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 843611#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 843612#L541-12 assume !(1 == ~t3_pc~0); 843307#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 843308#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 843197#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 843198#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 843294#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 843295#L560-12 assume !(1 == ~t4_pc~0); 843941#L570-12 is_transmit4_triggered_~__retres1~4#1 := 0; 843733#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 843596#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 843597#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 843863#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 843778#L579-12 assume !(1 == ~t5_pc~0); 843779#L589-12 is_transmit5_triggered_~__retres1~5#1 := 0; 843255#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 843256#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 843894#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 843745#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 843746#L598-12 assume !(1 == ~t6_pc~0); 844185#L608-12 is_transmit6_triggered_~__retres1~6#1 := 0; 844149#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 843855#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 843856#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 844290#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 844291#L617-12 assume !(1 == ~t7_pc~0); 842849#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 842850#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 843395#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 843396#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 843916#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 844052#L636-12 assume 1 == ~t8_pc~0; 844074#L637-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 844024#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 843731#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 843732#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 843703#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 843704#L655-12 assume 1 == ~t9_pc~0; 843895#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 842927#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 842928#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 843134#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 843267#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 843268#L674-12 assume 1 == ~t10_pc~0; 844048#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 843664#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 844083#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 843250#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 843251#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 844239#L1119-1 assume !(1 == ~M_E~0); 843497#L1124-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 842859#L1129-1 assume !(1 == ~T2_E~0); 842860#L1134-1 assume !(1 == ~T3_E~0); 843199#L1139-1 assume !(1 == ~T4_E~0); 843200#L1144-1 assume !(1 == ~T5_E~0); 843439#L1149-1 assume !(1 == ~T6_E~0); 843034#L1154-1 assume !(1 == ~T7_E~0); 843035#L1159-1 assume !(1 == ~T8_E~0); 843137#L1164-1 assume !(1 == ~T9_E~0); 1009776#L1169-1 assume !(1 == ~T10_E~0); 1009775#L1174-1 assume !(1 == ~E_1~0); 1009774#L1179-1 assume !(1 == ~E_2~0); 1009773#L1184-1 assume !(1 == ~E_3~0); 1009772#L1189-1 assume !(1 == ~E_4~0); 1009771#L1194-1 assume !(1 == ~E_5~0); 1009759#L1199-1 assume !(1 == ~E_6~0); 844321#L1204-1 assume !(1 == ~E_7~0); 1009756#L1209-1 assume !(1 == ~E_8~0); 1009754#L1214-1 assume !(1 == ~E_9~0); 1009752#L1219-1 assume !(1 == ~E_10~0); 1009749#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 1009746#L1520 [2024-11-17 08:54:13,692 INFO L747 eck$LassoCheckResult]: Loop: 1009746#L1520 assume true; 1009742#L1520-1 assume !false; 1009741#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1009737#L831 assume true; 1009736#L831-1 assume !false; 1009735#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1009729#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1009723#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1009722#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1009720#L836 assume !(0 != eval_~tmp~0#1); 1009719#L839 assume true; 1009718#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1009717#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1009715#L1006 assume !(0 == ~M_E~0); 1009713#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1009711#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1009709#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1009707#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1009705#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1009702#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1009700#L1041 assume !(0 == ~T7_E~0); 1009698#L1046 assume !(0 == ~T8_E~0); 1009696#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1009694#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1009692#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 1009689#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 1009687#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 1009685#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 1009683#L1081 assume !(0 == ~E_5~0); 1009681#L1086 assume !(0 == ~E_6~0); 1009679#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 1009676#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 1009674#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 1009672#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 1009670#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1009668#L484-1 assume !(1 == ~m_pc~0); 1009665#L494-1 is_master_triggered_~__retres1~0#1 := 0; 1009662#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1009660#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1009658#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1009656#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1009654#L503-1 assume !(1 == ~t1_pc~0); 1009651#L513-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1009649#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1009647#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1009645#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1009643#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1009642#L522-1 assume !(1 == ~t2_pc~0); 1009639#L532-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1009635#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1009634#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1009633#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1009632#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1009631#L541-1 assume 1 == ~t3_pc~0; 1009630#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1009628#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1009626#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1009624#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1009622#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1009621#L560-1 assume !(1 == ~t4_pc~0); 1009620#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1009619#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1009617#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1009615#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1009613#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1009611#L579-1 assume !(1 == ~t5_pc~0); 1007943#L589-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1009610#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1009609#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1009608#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1009607#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1009606#L598-1 assume !(1 == ~t6_pc~0); 916932#L608-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1009605#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1009604#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1009603#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1009591#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1009589#L617-1 assume 1 == ~t7_pc~0; 1009587#L618-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1009583#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1009581#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1009580#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1009579#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1009578#L636-1 assume 1 == ~t8_pc~0; 1009577#L637-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1009575#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1009574#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1009573#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1009572#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1009571#L655-1 assume 1 == ~t9_pc~0; 1009570#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1009557#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1009555#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1009553#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1009551#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1009549#L674-1 assume 1 == ~t10_pc~0; 1009547#L675-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1009544#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1009542#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1009540#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1009535#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1009533#L1119 assume !(1 == ~M_E~0); 1009026#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 886283#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1009529#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1009528#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1009527#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1009526#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1009525#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1009524#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 991664#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1009511#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1009509#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 1009506#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 1009504#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 1009502#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 1009500#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 1009498#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 1009494#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 1009492#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 1009490#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 1009488#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 1009486#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1009464#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1009462#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1009460#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1009457#L1539 assume !(0 == start_simulation_~tmp~3#1); 1009458#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1009763#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1009758#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1009757#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1009755#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1009753#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1009751#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1009750#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 1009746#L1520 [2024-11-17 08:54:13,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:13,692 INFO L85 PathProgramCache]: Analyzing trace with hash -1595302296, now seen corresponding path program 1 times [2024-11-17 08:54:13,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:13,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685730202] [2024-11-17 08:54:13,693 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:13,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:13,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:13,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:13,741 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:13,741 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685730202] [2024-11-17 08:54:13,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685730202] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:13,742 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:13,742 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:13,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830330234] [2024-11-17 08:54:13,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:13,742 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:13,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:13,743 INFO L85 PathProgramCache]: Analyzing trace with hash -750205706, now seen corresponding path program 1 times [2024-11-17 08:54:13,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:13,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152994249] [2024-11-17 08:54:13,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:13,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:13,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:13,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:13,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:13,796 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152994249] [2024-11-17 08:54:13,796 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152994249] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:13,796 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:13,796 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:13,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920730999] [2024-11-17 08:54:13,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:13,798 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:13,798 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:13,798 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:13,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:13,798 INFO L87 Difference]: Start difference. First operand 229802 states and 326633 transitions. cyclomatic complexity: 96863 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:15,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:15,748 INFO L93 Difference]: Finished difference Result 437353 states and 619654 transitions. [2024-11-17 08:54:15,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 437353 states and 619654 transitions. [2024-11-17 08:54:18,310 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 435392 [2024-11-17 08:54:19,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 437353 states to 437353 states and 619654 transitions. [2024-11-17 08:54:19,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 437353 [2024-11-17 08:54:20,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437353 [2024-11-17 08:54:20,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 437353 states and 619654 transitions. [2024-11-17 08:54:20,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:20,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 437353 states and 619654 transitions. [2024-11-17 08:54:20,553 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 437353 states and 619654 transitions. [2024-11-17 08:54:24,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 437353 to 436329. [2024-11-17 08:54:25,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 436329 states, 436329 states have (on average 1.4178062883741398) internal successors, (618630), 436328 states have internal predecessors, (618630), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:27,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436329 states to 436329 states and 618630 transitions. [2024-11-17 08:54:27,306 INFO L240 hiAutomatonCegarLoop]: Abstraction has 436329 states and 618630 transitions. [2024-11-17 08:54:27,314 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:27,315 INFO L425 stractBuchiCegarLoop]: Abstraction has 436329 states and 618630 transitions. [2024-11-17 08:54:27,315 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:54:27,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 436329 states and 618630 transitions. [2024-11-17 08:54:28,438 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 434368 [2024-11-17 08:54:28,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:28,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:28,441 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:28,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:28,442 INFO L745 eck$LassoCheckResult]: Stem: 1511070#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1510005#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1510006#L1483 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1511500#L694-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1511566#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 1511563#L706 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1510372#L711 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1510373#L716 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1510146#L721 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1510147#L726 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1511017#L731 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1510359#L736 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1510232#L741 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1510233#L746 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1509998#L751 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1509999#L757 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1510061#L1006-1 assume !(0 == ~M_E~0); 1511066#L1011-1 assume !(0 == ~T1_E~0); 1511395#L1016-1 assume !(0 == ~T2_E~0); 1511420#L1021-1 assume !(0 == ~T3_E~0); 1509996#L1026-1 assume !(0 == ~T4_E~0); 1509997#L1031-1 assume !(0 == ~T5_E~0); 1510985#L1036-1 assume !(0 == ~T6_E~0); 1510981#L1041-1 assume !(0 == ~T7_E~0); 1510982#L1046-1 assume !(0 == ~T8_E~0); 1510322#L1051-1 assume !(0 == ~T9_E~0); 1510323#L1056-1 assume !(0 == ~T10_E~0); 1511139#L1061-1 assume !(0 == ~E_1~0); 1510226#L1066-1 assume !(0 == ~E_2~0); 1510227#L1071-1 assume !(0 == ~E_3~0); 1511120#L1076-1 assume !(0 == ~E_4~0); 1510103#L1081-1 assume !(0 == ~E_5~0); 1510104#L1086-1 assume !(0 == ~E_6~0); 1510514#L1091-1 assume !(0 == ~E_7~0); 1511378#L1096-1 assume !(0 == ~E_8~0); 1511379#L1101-1 assume !(0 == ~E_9~0); 1510584#L1106-1 assume !(0 == ~E_10~0); 1510585#L1112-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1510465#L484-12 assume !(1 == ~m_pc~0); 1510055#L494-12 is_master_triggered_~__retres1~0#1 := 0; 1510056#L487-12 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1510959#L496-12 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1510019#L1245-12 assume !(0 != activate_threads_~tmp~1#1); 1510020#L1251-12 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1510309#L503-12 assume !(1 == ~t1_pc~0); 1509963#L513-12 is_transmit1_triggered_~__retres1~1#1 := 0; 1509964#L506-12 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1511551#L515-12 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1510902#L1253-12 assume !(0 != activate_threads_~tmp___0~0#1); 1510903#L1259-12 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1510719#L522-12 assume !(1 == ~t2_pc~0); 1510720#L532-12 is_transmit2_triggered_~__retres1~2#1 := 0; 1510477#L525-12 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1510478#L534-12 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1510789#L1261-12 assume !(0 != activate_threads_~tmp___1~0#1); 1510785#L1267-12 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1510786#L541-12 assume !(1 == ~t3_pc~0); 1510479#L551-12 is_transmit3_triggered_~__retres1~3#1 := 0; 1510480#L544-12 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1510365#L553-12 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1510366#L1269-12 assume !(0 != activate_threads_~tmp___2~0#1); 1510467#L1275-12 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1510468#L560-12 assume !(1 == ~t4_pc~0); 1511133#L570-12 is_transmit4_triggered_~__retres1~4#1 := 0; 1510923#L563-12 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1510771#L572-12 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1510772#L1277-12 assume !(0 != activate_threads_~tmp___3~0#1); 1511057#L1283-12 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1510967#L579-12 assume !(1 == ~t5_pc~0); 1510968#L589-12 is_transmit5_triggered_~__retres1~5#1 := 0; 1510424#L582-12 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1510425#L591-12 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1511093#L1285-12 assume !(0 != activate_threads_~tmp___4~0#1); 1510933#L1291-12 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1510934#L598-12 assume !(1 == ~t6_pc~0); 1511409#L608-12 is_transmit6_triggered_~__retres1~6#1 := 0; 1511362#L601-12 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1511048#L610-12 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1511049#L1293-12 assume !(0 != activate_threads_~tmp___5~0#1); 1511530#L1299-12 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1511531#L617-12 assume !(1 == ~t7_pc~0); 1510013#L627-12 is_transmit7_triggered_~__retres1~7#1 := 0; 1510014#L620-12 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1510570#L629-12 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1510571#L1301-12 assume !(0 != activate_threads_~tmp___6~0#1); 1511112#L1307-12 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1511259#L636-12 assume !(1 == ~t8_pc~0); 1511227#L646-12 is_transmit8_triggered_~__retres1~8#1 := 0; 1511228#L639-12 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1510921#L648-12 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1510922#L1309-12 assume !(0 != activate_threads_~tmp___7~0#1); 1510889#L1315-12 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1510890#L655-12 assume 1 == ~t9_pc~0; 1511094#L656-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1510091#L658-12 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1510092#L667-12 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1510301#L1317-12 assume !(0 != activate_threads_~tmp___8~0#1); 1510438#L1323-12 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1510439#L674-12 assume 1 == ~t10_pc~0; 1511253#L675-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1510845#L677-12 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1511291#L686-12 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1510419#L1325-12 assume !(0 != activate_threads_~tmp___9~0#1); 1510420#L1331-12 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1511479#L1119-1 assume !(1 == ~M_E~0); 1510673#L1124-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1510674#L1129-1 assume !(1 == ~T2_E~0); 1616911#L1134-1 assume !(1 == ~T3_E~0); 1616910#L1139-1 assume !(1 == ~T4_E~0); 1616909#L1144-1 assume !(1 == ~T5_E~0); 1616908#L1149-1 assume !(1 == ~T6_E~0); 1616907#L1154-1 assume !(1 == ~T7_E~0); 1616906#L1159-1 assume !(1 == ~T8_E~0); 1616905#L1164-1 assume !(1 == ~T9_E~0); 1616904#L1169-1 assume !(1 == ~T10_E~0); 1616903#L1174-1 assume !(1 == ~E_1~0); 1616902#L1179-1 assume !(1 == ~E_2~0); 1616901#L1184-1 assume !(1 == ~E_3~0); 1616900#L1189-1 assume !(1 == ~E_4~0); 1616899#L1194-1 assume !(1 == ~E_5~0); 1616887#L1199-1 assume !(1 == ~E_6~0); 1616884#L1204-1 assume !(1 == ~E_7~0); 1616882#L1209-1 assume !(1 == ~E_8~0); 1616880#L1214-1 assume !(1 == ~E_9~0); 1616878#L1219-1 assume !(1 == ~E_10~0); 1616875#L1225-1 assume true;assume { :end_inline_reset_delta_events } true; 1616872#L1520 [2024-11-17 08:54:28,443 INFO L747 eck$LassoCheckResult]: Loop: 1616872#L1520 assume true; 1616868#L1520-1 assume !false; 1616867#start_simulation_while_13_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1616863#L831 assume true; 1616862#L831-1 assume !false; 1616861#eval_while_12_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1614277#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1614270#L806-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1614268#L822-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1614265#L836 assume !(0 != eval_~tmp~0#1); 1614266#L839 assume true; 1688030#L999 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1688028#L694 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1688026#L1006 assume !(0 == ~M_E~0); 1688024#L1011 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1688022#L1016 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1688020#L1021 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1688018#L1026 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1688016#L1031 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1688014#L1036 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1688012#L1041 assume !(0 == ~T7_E~0); 1688010#L1046 assume !(0 == ~T8_E~0); 1688008#L1051 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1688006#L1056 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1688004#L1061 assume 0 == ~E_1~0;~E_1~0 := 1; 1688002#L1066 assume 0 == ~E_2~0;~E_2~0 := 1; 1688000#L1071 assume 0 == ~E_3~0;~E_3~0 := 1; 1687998#L1076 assume 0 == ~E_4~0;~E_4~0 := 1; 1687996#L1081 assume !(0 == ~E_5~0); 1687994#L1086 assume !(0 == ~E_6~0); 1687991#L1091 assume 0 == ~E_7~0;~E_7~0 := 1; 1687989#L1096 assume 0 == ~E_8~0;~E_8~0 := 1; 1687987#L1101 assume 0 == ~E_9~0;~E_9~0 := 1; 1687985#L1106 assume 0 == ~E_10~0;~E_10~0 := 1; 1687983#L1112 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1687981#L484-1 assume !(1 == ~m_pc~0); 1687978#L494-1 is_master_triggered_~__retres1~0#1 := 0; 1687976#L487-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1687974#L496-1 assume true;activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1687972#L1245-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1687970#L1251-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1687968#L503-1 assume !(1 == ~t1_pc~0); 1687966#L513-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1687964#L506-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1687962#L515-1 assume true;activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1687960#L1253-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1687958#L1259-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1687956#L522-1 assume !(1 == ~t2_pc~0); 1687953#L532-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1687951#L525-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1687949#L534-1 assume true;activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1687947#L1261-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1687945#L1267-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1687943#L541-1 assume 1 == ~t3_pc~0; 1687941#L542-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1687938#L544-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1687936#L553-1 assume true;activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1687934#L1269-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1687932#L1275-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1687930#L560-1 assume !(1 == ~t4_pc~0); 1687929#L570-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1687927#L563-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1687925#L572-1 assume true;activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1687923#L1277-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1687921#L1283-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1687920#L579-1 assume !(1 == ~t5_pc~0); 1656601#L589-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1687919#L582-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1687916#L591-1 assume true;activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1687914#L1285-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1687912#L1291-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1617345#L598-1 assume !(1 == ~t6_pc~0); 1617343#L608-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1617341#L601-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1617339#L610-1 assume true;activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1617337#L1293-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1617334#L1299-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1617332#L617-1 assume !(1 == ~t7_pc~0); 1617329#L627-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1617327#L620-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1617325#L629-1 assume true;activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1617323#L1301-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1617321#L1307-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1617319#L636-1 assume !(1 == ~t8_pc~0); 1617317#L646-1 is_transmit8_triggered_~__retres1~8#1 := 0; 1617315#L639-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1617313#L648-1 assume true;activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1617311#L1309-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1617308#L1315-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1617306#L655-1 assume 1 == ~t9_pc~0; 1617304#L656-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1617301#L658-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1617299#L667-1 assume true;activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1617297#L1317-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1617294#L1323-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1617292#L674-1 assume !(1 == ~t10_pc~0); 1617289#L684-1 is_transmit10_triggered_~__retres1~10#1 := 0; 1617287#L677-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1617285#L686-1 assume true;activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1617281#L1325-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1617279#L1331-1 assume true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1617277#L1119 assume !(1 == ~M_E~0); 1617273#L1124 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1617269#L1129 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1617267#L1134 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1617265#L1139 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1617263#L1144 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1617259#L1149 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1617257#L1154 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1617255#L1159 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1617251#L1164 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1617249#L1169 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1617247#L1174 assume 1 == ~E_1~0;~E_1~0 := 2; 1617245#L1179 assume 1 == ~E_2~0;~E_2~0 := 2; 1617243#L1184 assume 1 == ~E_3~0;~E_3~0 := 2; 1617242#L1189 assume 1 == ~E_4~0;~E_4~0 := 2; 1617241#L1194 assume 1 == ~E_5~0;~E_5~0 := 2; 1617239#L1199 assume 1 == ~E_6~0;~E_6~0 := 2; 1617235#L1204 assume 1 == ~E_7~0;~E_7~0 := 2; 1617233#L1209 assume 1 == ~E_8~0;~E_8~0 := 2; 1617231#L1214 assume 1 == ~E_9~0;~E_9~0 := 2; 1617229#L1219 assume 1 == ~E_10~0;~E_10~0 := 2; 1617227#L1225 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1616920#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1616918#L806-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1616916#L822-1 assume true;start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1616914#L1539 assume !(0 == start_simulation_~tmp~3#1); 1616912#L1550 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1616891#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1616885#L806 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1616883#L822 assume true;stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1616881#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1616879#L1496 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1616877#L1502 assume true;start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1616876#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 1616872#L1520 [2024-11-17 08:54:28,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:28,443 INFO L85 PathProgramCache]: Analyzing trace with hash 1711644869, now seen corresponding path program 1 times [2024-11-17 08:54:28,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:28,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828914172] [2024-11-17 08:54:28,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:28,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:28,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:28,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:28,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:28,490 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828914172] [2024-11-17 08:54:28,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1828914172] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:28,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:28,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:28,491 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [810994133] [2024-11-17 08:54:28,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:28,491 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:28,492 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:28,492 INFO L85 PathProgramCache]: Analyzing trace with hash -2132006067, now seen corresponding path program 1 times [2024-11-17 08:54:28,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:28,492 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019238337] [2024-11-17 08:54:28,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:28,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:28,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:28,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:28,550 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:28,550 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019238337] [2024-11-17 08:54:28,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1019238337] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:28,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:28,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:28,551 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1744086549] [2024-11-17 08:54:28,551 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:28,551 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:28,551 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:28,552 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:28,552 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:28,552 INFO L87 Difference]: Start difference. First operand 436329 states and 618630 transitions. cyclomatic complexity: 182365 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:32,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:32,727 INFO L93 Difference]: Finished difference Result 828840 states and 1171843 transitions. [2024-11-17 08:54:32,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 828840 states and 1171843 transitions.