./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:53:50,209 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:53:50,290 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:53:50,297 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:53:50,297 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:53:50,298 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:53:50,332 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:53:50,333 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:53:50,333 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:53:50,334 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:53:50,334 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:53:50,335 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:53:50,336 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:53:50,337 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:53:50,340 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:53:50,340 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:53:50,340 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:53:50,341 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:53:50,341 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:53:50,341 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:53:50,341 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:53:50,343 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:53:50,344 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:53:50,344 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:53:50,344 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:53:50,344 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:53:50,345 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:53:50,345 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:53:50,345 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:53:50,345 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:53:50,346 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:53:50,347 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:53:50,347 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:53:50,347 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:53:50,348 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:53:50,348 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:53:50,348 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:53:50,348 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:53:50,349 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:53:50,349 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:53:50,349 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2024-11-17 08:53:50,609 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:53:50,641 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:53:50,644 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:53:50,645 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:53:50,646 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:53:50,648 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.15.cil.c [2024-11-17 08:53:52,172 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:53:52,445 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:53:52,449 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.15.cil.c [2024-11-17 08:53:52,476 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c7f913cf8/e26c1a89df4a48d8a74b5c4b3405ba36/FLAG3ca67fbe5 [2024-11-17 08:53:52,759 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c7f913cf8/e26c1a89df4a48d8a74b5c4b3405ba36 [2024-11-17 08:53:52,762 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:53:52,764 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:53:52,768 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:52,769 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:53:52,775 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:53:52,775 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:52" (1/1) ... [2024-11-17 08:53:52,776 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6eb21a0c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:52, skipping insertion in model container [2024-11-17 08:53:52,777 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:52" (1/1) ... [2024-11-17 08:53:52,830 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:53:53,192 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:53,213 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:53:53,303 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:53,336 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:53:53,337 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53 WrapperNode [2024-11-17 08:53:53,337 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:53,339 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:53,339 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:53:53,339 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:53:53,347 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,358 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,507 INFO L138 Inliner]: procedures = 54, calls = 70, calls flagged for inlining = 65, calls inlined = 287, statements flattened = 4424 [2024-11-17 08:53:53,508 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:53,508 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:53:53,508 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:53:53,509 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:53:53,520 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,521 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,536 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,602 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:53:53,603 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,606 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,650 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,658 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,668 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,680 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,698 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:53:53,700 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:53:53,700 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:53:53,700 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:53:53,701 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (1/1) ... [2024-11-17 08:53:53,707 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:53:53,719 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:53:53,741 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:53:53,745 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:53:53,800 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:53:53,800 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:53:53,800 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:53:53,800 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:53:53,960 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:53:53,963 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:53:57,111 INFO L? ?]: Removed 948 outVars from TransFormulas that were not future-live. [2024-11-17 08:53:57,111 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:53:57,164 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:53:57,164 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:53:57,165 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:57 BoogieIcfgContainer [2024-11-17 08:53:57,165 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:53:57,167 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:53:57,167 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:53:57,170 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:53:57,171 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:57,173 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:53:52" (1/3) ... [2024-11-17 08:53:57,174 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2610f93c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:57, skipping insertion in model container [2024-11-17 08:53:57,174 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:57,174 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:53" (2/3) ... [2024-11-17 08:53:57,174 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2610f93c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:57, skipping insertion in model container [2024-11-17 08:53:57,175 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:57,175 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:57" (3/3) ... [2024-11-17 08:53:57,176 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.15.cil.c [2024-11-17 08:53:57,275 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:53:57,275 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:53:57,275 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:53:57,275 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:53:57,275 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:53:57,276 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:53:57,276 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:53:57,277 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:53:57,290 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1999 states, 1998 states have (on average 1.478978978978979) internal successors, (2955), 1998 states have internal predecessors, (2955), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:57,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1821 [2024-11-17 08:53:57,364 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:57,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:57,384 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:57,385 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:57,385 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:53:57,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1999 states, 1998 states have (on average 1.478978978978979) internal successors, (2955), 1998 states have internal predecessors, (2955), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:57,413 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1821 [2024-11-17 08:53:57,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:57,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:57,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:57,418 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:57,431 INFO L745 eck$LassoCheckResult]: Stem: 502#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1021#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 383#L1855true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 855#L874-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1826#L881true assume !(1 == ~m_i~0);~m_st~0 := 2; 384#L886true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 695#L891true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1265#L896true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 509#L901true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1224#L906true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 919#L911true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1722#L916true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 608#L921true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 717#L926true assume !(1 == ~t9_i~0);~t9_st~0 := 2; 1000#L931true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 417#L936true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1356#L941true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 267#L946true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 630#L952true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 735#L1258-1true assume !(0 == ~M_E~0); 537#L1263-1true assume !(0 == ~T1_E~0); 761#L1268-1true assume !(0 == ~T2_E~0); 1417#L1273-1true assume !(0 == ~T3_E~0); 1808#L1278-1true assume !(0 == ~T4_E~0); 1215#L1283-1true assume !(0 == ~T5_E~0); 1851#L1288-1true assume !(0 == ~T6_E~0); 1633#L1293-1true assume !(0 == ~T7_E~0); 1607#L1298-1true assume !(0 == ~T8_E~0); 1438#L1303-1true assume !(0 == ~T9_E~0); 245#L1308-1true assume !(0 == ~T10_E~0); 208#L1313-1true assume !(0 == ~T11_E~0); 1912#L1318-1true assume !(0 == ~T12_E~0); 214#L1323-1true assume !(0 == ~T13_E~0); 316#L1328-1true assume !(0 == ~E_1~0); 1862#L1333-1true assume !(0 == ~E_2~0); 1015#L1338-1true assume !(0 == ~E_3~0); 1168#L1343-1true assume !(0 == ~E_4~0); 1710#L1348-1true assume !(0 == ~E_5~0); 1729#L1353-1true assume !(0 == ~E_6~0); 769#L1358-1true assume !(0 == ~E_7~0); 1049#L1363-1true assume !(0 == ~E_8~0); 1108#L1368-1true assume !(0 == ~E_9~0); 111#L1373-1true assume !(0 == ~E_10~0); 536#L1378-1true assume !(0 == ~E_11~0); 288#L1383-1true assume !(0 == ~E_12~0); 1160#L1388-1true assume !(0 == ~E_13~0); 1379#L1394-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1497#L607-15true assume 1 == ~m_pc~0; 1750#L608-15true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1513#L610-15true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1001#L619-15true assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1897#L1560-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 263#L1566-15true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136#L626-15true assume 1 == ~t1_pc~0; 1297#L627-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 569#L629-15true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1355#L638-15true assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1383#L1568-15true assume !(0 != activate_threads_~tmp___0~0#1); 1092#L1574-15true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1385#L645-15true assume 1 == ~t2_pc~0; 850#L646-15true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 181#L648-15true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1791#L657-15true assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1260#L1576-15true assume !(0 != activate_threads_~tmp___1~0#1); 614#L1582-15true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28#L664-15true assume 1 == ~t3_pc~0; 1037#L665-15true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1886#L667-15true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 543#L676-15true assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 155#L1584-15true assume !(0 != activate_threads_~tmp___2~0#1); 394#L1590-15true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1565#L683-15true assume 1 == ~t4_pc~0; 755#L684-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 725#L686-15true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 996#L695-15true assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 963#L1592-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 655#L1598-15true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1274#L702-15true assume 1 == ~t5_pc~0; 1204#L703-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1292#L705-15true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1995#L714-15true assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1382#L1600-15true assume !(0 != activate_threads_~tmp___4~0#1); 580#L1606-15true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66#L721-15true assume 1 == ~t6_pc~0; 1922#L722-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1774#L724-15true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1521#L733-15true assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 513#L1608-15true assume !(0 != activate_threads_~tmp___5~0#1); 736#L1614-15true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96#L740-15true assume 1 == ~t7_pc~0; 2000#L741-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1792#L743-15true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 596#L752-15true assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1636#L1616-15true assume !(0 != activate_threads_~tmp___6~0#1); 1418#L1622-15true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1484#L759-15true assume 1 == ~t8_pc~0; 1209#L760-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1753#L762-15true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1349#L771-15true assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 998#L1624-15true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1002#L1630-15true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 144#L778-15true assume 1 == ~t9_pc~0; 1170#L779-15true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 423#L781-15true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 463#L790-15true assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 215#L1632-15true assume !(0 != activate_threads_~tmp___8~0#1); 1535#L1638-15true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 968#L797-15true assume 1 == ~t10_pc~0; 392#L798-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1435#L800-15true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 896#L809-15true assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 218#L1640-15true assume !(0 != activate_threads_~tmp___9~0#1); 1175#L1646-15true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 578#L816-15true assume 1 == ~t11_pc~0; 551#L817-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1027#L819-15true assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1567#L828-15true assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 400#L1648-15true assume !(0 != activate_threads_~tmp___10~0#1); 1039#L1654-15true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1085#L835-15true assume 1 == ~t12_pc~0; 1785#L836-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1731#L838-15true assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1489#L847-15true assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 632#L1656-15true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42#L1662-15true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1206#L854-15true assume 1 == ~t13_pc~0; 506#L855-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1517#L857-15true assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 197#L866-15true assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 426#L1664-15true assume !(0 != activate_threads_~tmp___12~0#1); 1180#L1670-15true assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 684#L1401-1true assume 1 == ~M_E~0;~M_E~0 := 2; 1291#L1406-1true assume !(1 == ~T1_E~0); 897#L1411-1true assume !(1 == ~T2_E~0); 1672#L1416-1true assume !(1 == ~T3_E~0); 637#L1421-1true assume !(1 == ~T4_E~0); 338#L1426-1true assume !(1 == ~T5_E~0); 1065#L1431-1true assume !(1 == ~T6_E~0); 72#L1436-1true assume !(1 == ~T7_E~0); 799#L1441-1true assume 1 == ~T8_E~0;~T8_E~0 := 2; 529#L1446-1true assume !(1 == ~T9_E~0); 1842#L1451-1true assume !(1 == ~T10_E~0); 1166#L1456-1true assume !(1 == ~T11_E~0); 798#L1461-1true assume !(1 == ~T12_E~0); 471#L1466-1true assume !(1 == ~T13_E~0); 1833#L1471-1true assume !(1 == ~E_1~0); 1131#L1476-1true assume !(1 == ~E_2~0); 1363#L1481-1true assume 1 == ~E_3~0;~E_3~0 := 2; 1649#L1486-1true assume !(1 == ~E_4~0); 259#L1491-1true assume !(1 == ~E_5~0); 37#L1496-1true assume !(1 == ~E_6~0); 810#L1501-1true assume !(1 == ~E_7~0); 525#L1506-1true assume !(1 == ~E_8~0); 1086#L1511-1true assume !(1 == ~E_9~0); 492#L1516-1true assume !(1 == ~E_10~0); 16#L1521-1true assume 1 == ~E_11~0;~E_11~0 := 2; 36#L1526-1true assume !(1 == ~E_12~0); 349#L1531-1true assume !(1 == ~E_13~0); 1984#L1537-1true assume true;assume { :end_inline_reset_delta_events } true; 65#L1892true [2024-11-17 08:53:57,455 INFO L747 eck$LassoCheckResult]: Loop: 65#L1892true assume true; 39#L1892-1true assume !false; 355#start_simulation_while_16_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 487#L1041true assume !true; 1430#L1049true assume true; 1184#L1251true assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 233#L874true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1887#L1258true assume 0 == ~M_E~0;~M_E~0 := 1; 246#L1263true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1458#L1268true assume 0 == ~T2_E~0;~T2_E~0 := 1; 482#L1273true assume 0 == ~T3_E~0;~T3_E~0 := 1; 435#L1278true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1558#L1283true assume 0 == ~T5_E~0;~T5_E~0 := 1; 644#L1288true assume !(0 == ~T6_E~0); 1652#L1293true assume 0 == ~T7_E~0;~T7_E~0 := 1; 264#L1298true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1899#L1303true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1898#L1308true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1991#L1313true assume 0 == ~T11_E~0;~T11_E~0 := 1; 429#L1318true assume 0 == ~T12_E~0;~T12_E~0 := 1; 1915#L1323true assume 0 == ~T13_E~0;~T13_E~0 := 1; 1637#L1328true assume !(0 == ~E_1~0); 1844#L1333true assume 0 == ~E_2~0;~E_2~0 := 1; 210#L1338true assume 0 == ~E_3~0;~E_3~0 := 1; 1583#L1343true assume 0 == ~E_4~0;~E_4~0 := 1; 187#L1348true assume 0 == ~E_5~0;~E_5~0 := 1; 367#L1353true assume 0 == ~E_6~0;~E_6~0 := 1; 1097#L1358true assume 0 == ~E_7~0;~E_7~0 := 1; 826#L1363true assume 0 == ~E_8~0;~E_8~0 := 1; 542#L1368true assume !(0 == ~E_9~0); 691#L1373true assume 0 == ~E_10~0;~E_10~0 := 1; 425#L1378true assume 0 == ~E_11~0;~E_11~0 := 1; 1889#L1383true assume 0 == ~E_12~0;~E_12~0 := 1; 1314#L1388true assume 0 == ~E_13~0;~E_13~0 := 1; 1270#L1394true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 190#L607-1true assume !(1 == ~m_pc~0); 140#L617-1true is_master_triggered_~__retres1~0#1 := 0; 1532#L610-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 152#L619-1true assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 310#L1560-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1226#L1566-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1552#L626-1true assume !(1 == ~t1_pc~0); 1146#L636-1true is_transmit1_triggered_~__retres1~1#1 := 0; 1944#L629-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 790#L638-1true assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 401#L1568-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1714#L1574-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119#L645-1true assume 1 == ~t2_pc~0; 1642#L646-1true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 833#L648-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97#L657-1true assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1271#L1576-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1719#L1582-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180#L664-1true assume 1 == ~t3_pc~0; 1289#L665-1true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 248#L667-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 634#L676-1true assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 935#L1584-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1031#L1590-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1551#L683-1true assume 1 == ~t4_pc~0; 1601#L684-1true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1213#L686-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 978#L695-1true assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 476#L1592-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 602#L1598-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1958#L702-1true assume !(1 == ~t5_pc~0); 1191#L712-1true is_transmit5_triggered_~__retres1~5#1 := 0; 1318#L705-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 166#L714-1true assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1837#L1600-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1073#L1606-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1921#L721-1true assume !(1 == ~t6_pc~0); 1823#L731-1true is_transmit6_triggered_~__retres1~6#1 := 0; 1431#L724-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4#L733-1true assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1783#L1608-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1277#L1614-1true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 611#L740-1true assume 1 == ~t7_pc~0; 1720#L741-1true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1987#L743-1true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57#L752-1true assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1352#L1616-1true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1910#L1622-1true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1638#L759-1true assume !(1 == ~t8_pc~0); 1434#L769-1true is_transmit8_triggered_~__retres1~8#1 := 0; 107#L762-1true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1246#L771-1true assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1779#L1624-1true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 923#L1630-1true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 500#L778-1true assume 1 == ~t9_pc~0; 811#L779-1true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1007#L781-1true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1358#L790-1true assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 439#L1632-1true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 289#L1638-1true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 90#L797-1true assume !(1 == ~t10_pc~0); 1662#L807-1true is_transmit10_triggered_~__retres1~10#1 := 0; 374#L800-1true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1487#L809-1true assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1452#L1640-1true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 350#L1646-1true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1171#L816-1true assume 1 == ~t11_pc~0; 1453#L817-1true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 11#L819-1true assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34#L828-1true assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 834#L1648-1true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 101#L1654-1true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1148#L835-1true assume 1 == ~t12_pc~0; 1262#L836-1true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 292#L838-1true assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1295#L847-1true assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 139#L1656-1true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1369#L1662-1true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 213#L854-1true assume !(1 == ~t13_pc~0); 1061#L864-1true is_transmit13_triggered_~__retres1~13#1 := 0; 1998#L857-1true assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 562#L866-1true assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 870#L1664-1true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1244#L1670-1true assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1864#L1401true assume 1 == ~M_E~0;~M_E~0 := 2; 475#L1406true assume 1 == ~T1_E~0;~T1_E~0 := 2; 713#L1411true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1980#L1416true assume 1 == ~T3_E~0;~T3_E~0 := 2; 307#L1421true assume 1 == ~T4_E~0;~T4_E~0 := 2; 224#L1426true assume 1 == ~T5_E~0;~T5_E~0 := 2; 636#L1431true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1788#L1436true assume 1 == ~T7_E~0;~T7_E~0 := 2; 828#L1441true assume 1 == ~T8_E~0;~T8_E~0 := 2; 354#L1446true assume 1 == ~T9_E~0;~T9_E~0 := 2; 747#L1451true assume 1 == ~T10_E~0;~T10_E~0 := 2; 272#L1456true assume 1 == ~T11_E~0;~T11_E~0 := 2; 1743#L1461true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1664#L1466true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1443#L1471true assume 1 == ~E_1~0;~E_1~0 := 2; 942#L1476true assume 1 == ~E_2~0;~E_2~0 := 2; 1640#L1481true assume 1 == ~E_3~0;~E_3~0 := 2; 1868#L1486true assume 1 == ~E_4~0;~E_4~0 := 2; 1169#L1491true assume 1 == ~E_5~0;~E_5~0 := 2; 89#L1496true assume 1 == ~E_6~0;~E_6~0 := 2; 1580#L1501true assume 1 == ~E_7~0;~E_7~0 := 2; 332#L1506true assume 1 == ~E_8~0;~E_8~0 := 2; 689#L1511true assume 1 == ~E_9~0;~E_9~0 := 2; 14#L1516true assume 1 == ~E_10~0;~E_10~0 := 2; 1978#L1521true assume 1 == ~E_11~0;~E_11~0 := 2; 1534#L1526true assume 1 == ~E_12~0;~E_12~0 := 2; 240#L1531true assume 1 == ~E_13~0;~E_13~0 := 2; 1192#L1537true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1917#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 134#L1013-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 813#L1032-1true assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 540#L1911true assume !(0 == start_simulation_~tmp~3#1); 1499#L1922true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 723#L959true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 143#L1013true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 829#L1032true assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 121#L1866true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1786#L1868true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 258#L1874true assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1390#L1924true assume !(0 != start_simulation_~tmp___0~1#1); 65#L1892true [2024-11-17 08:53:57,468 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:57,469 INFO L85 PathProgramCache]: Analyzing trace with hash 1999782795, now seen corresponding path program 1 times [2024-11-17 08:53:57,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:57,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988789650] [2024-11-17 08:53:57,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:57,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:57,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:57,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:57,874 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:57,874 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988789650] [2024-11-17 08:53:57,875 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1988789650] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:57,875 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:57,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:57,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566139630] [2024-11-17 08:53:57,878 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:57,883 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:57,884 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:57,885 INFO L85 PathProgramCache]: Analyzing trace with hash -59240987, now seen corresponding path program 1 times [2024-11-17 08:53:57,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:57,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [277242815] [2024-11-17 08:53:57,885 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:57,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:57,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:58,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:58,000 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:58,000 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [277242815] [2024-11-17 08:53:58,001 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [277242815] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:58,001 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:58,001 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:58,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1370424900] [2024-11-17 08:53:58,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:58,005 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:58,006 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:58,043 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-17 08:53:58,045 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-17 08:53:58,051 INFO L87 Difference]: Start difference. First operand has 1999 states, 1998 states have (on average 1.478978978978979) internal successors, (2955), 1998 states have internal predecessors, (2955), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:58,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:58,137 INFO L93 Difference]: Finished difference Result 1982 states and 2903 transitions. [2024-11-17 08:53:58,139 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1982 states and 2903 transitions. [2024-11-17 08:53:58,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:58,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1982 states to 1976 states and 2897 transitions. [2024-11-17 08:53:58,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:53:58,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:53:58,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2897 transitions. [2024-11-17 08:53:58,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:58,199 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2897 transitions. [2024-11-17 08:53:58,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2897 transitions. [2024-11-17 08:53:58,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:53:58,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.466093117408907) internal successors, (2897), 1975 states have internal predecessors, (2897), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:58,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2897 transitions. [2024-11-17 08:53:58,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2897 transitions. [2024-11-17 08:53:58,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-17 08:53:58,322 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2897 transitions. [2024-11-17 08:53:58,323 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:53:58,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2897 transitions. [2024-11-17 08:53:58,332 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:58,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:58,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:58,338 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:58,340 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:58,341 INFO L745 eck$LassoCheckResult]: Stem: 4926#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4927#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4729#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4730#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5382#L881 assume !(1 == ~m_i~0);~m_st~0 := 2; 4731#L886 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 4732#L891 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5196#L896 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4937#L901 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4938#L906 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5464#L911 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5465#L916 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5067#L921 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5068#L926 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 5225#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4789#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4790#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 4535#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4536#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5098#L1258-1 assume !(0 == ~M_E~0); 4978#L1263-1 assume !(0 == ~T1_E~0); 4979#L1268-1 assume !(0 == ~T2_E~0); 5285#L1273-1 assume !(0 == ~T3_E~0); 5831#L1278-1 assume !(0 == ~T4_E~0); 5715#L1283-1 assume !(0 == ~T5_E~0); 5716#L1288-1 assume !(0 == ~T6_E~0); 5912#L1293-1 assume !(0 == ~T7_E~0); 5902#L1298-1 assume !(0 == ~T8_E~0); 5842#L1303-1 assume !(0 == ~T9_E~0); 4499#L1308-1 assume !(0 == ~T10_E~0); 4424#L1313-1 assume !(0 == ~T11_E~0); 4425#L1318-1 assume !(0 == ~T12_E~0); 4438#L1323-1 assume !(0 == ~T13_E~0); 4439#L1328-1 assume !(0 == ~E_1~0); 4619#L1333-1 assume !(0 == ~E_2~0); 5560#L1338-1 assume !(0 == ~E_3~0); 5561#L1343-1 assume !(0 == ~E_4~0); 5685#L1348-1 assume !(0 == ~E_5~0); 5937#L1353-1 assume !(0 == ~E_6~0); 5295#L1358-1 assume !(0 == ~E_7~0); 5296#L1363-1 assume !(0 == ~E_8~0); 5589#L1368-1 assume !(0 == ~E_9~0); 4223#L1373-1 assume !(0 == ~E_10~0); 4224#L1378-1 assume !(0 == ~E_11~0); 4571#L1383-1 assume !(0 == ~E_12~0); 4572#L1388-1 assume !(0 == ~E_13~0); 5677#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5808#L607-15 assume 1 == ~m_pc~0; 5862#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5646#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5550#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5551#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4527#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4275#L626-15 assume 1 == ~t1_pc~0; 4276#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4975#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5021#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5797#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 5624#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5625#L645-15 assume 1 == ~t2_pc~0; 5376#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4376#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4377#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5742#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 5077#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4047#L664-15 assume 1 == ~t3_pc~0; 4048#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5380#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4987#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4321#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 4322#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4750#L683-15 assume 1 == ~t4_pc~0; 5276#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5236#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5237#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5506#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5140#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5141#L702-15 assume 1 == ~t5_pc~0; 5709#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5084#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5759#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5810#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 5034#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4127#L721-15 assume 1 == ~t6_pc~0; 4128#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4355#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5869#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4943#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 4944#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4189#L740-15 assume 1 == ~t7_pc~0; 4190#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5636#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5052#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5053#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 5832#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5833#L759-15 assume 1 == ~t8_pc~0; 5713#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4741#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5793#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5546#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5547#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4295#L778-15 assume 1 == ~t9_pc~0; 4296#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4800#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4801#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4440#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 4441#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5509#L797-15 assume 1 == ~t10_pc~0; 4745#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4746#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5435#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4446#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 4447#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5031#L816-15 assume 1 == ~t11_pc~0; 4998#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4999#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5572#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4760#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 4761#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5583#L835-15 assume 1 == ~t12_pc~0; 5618#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 5861#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5859#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5100#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4073#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4074#L854-15 assume 1 == ~t13_pc~0; 4932#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4933#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4402#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4403#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 4807#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5182#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 5183#L1406-1 assume !(1 == ~T1_E~0); 5436#L1411-1 assume !(1 == ~T2_E~0); 5437#L1416-1 assume !(1 == ~T3_E~0); 5107#L1421-1 assume !(1 == ~T4_E~0); 4656#L1426-1 assume !(1 == ~T5_E~0); 4657#L1431-1 assume !(1 == ~T6_E~0); 4138#L1436-1 assume !(1 == ~T7_E~0); 4139#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4968#L1446-1 assume !(1 == ~T9_E~0); 4969#L1451-1 assume !(1 == ~T10_E~0); 5683#L1456-1 assume !(1 == ~T11_E~0); 5322#L1461-1 assume !(1 == ~T12_E~0); 4879#L1466-1 assume !(1 == ~T13_E~0); 4880#L1471-1 assume !(1 == ~E_1~0); 5654#L1476-1 assume !(1 == ~E_2~0); 5655#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5799#L1486-1 assume !(1 == ~E_4~0); 4519#L1491-1 assume !(1 == ~E_5~0); 4064#L1496-1 assume !(1 == ~E_6~0); 4065#L1501-1 assume !(1 == ~E_7~0); 4961#L1506-1 assume !(1 == ~E_8~0); 4962#L1511-1 assume !(1 == ~E_9~0); 4911#L1516-1 assume !(1 == ~E_10~0); 4020#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 4021#L1526-1 assume !(1 == ~E_12~0); 4063#L1531-1 assume !(1 == ~E_13~0); 4674#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 4126#L1892 [2024-11-17 08:53:58,343 INFO L747 eck$LassoCheckResult]: Loop: 4126#L1892 assume true; 4069#L1892-1 assume !false; 4070#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4686#L1041 assume true; 4855#L1041-1 assume !false; 4856#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5503#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4583#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5416#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4116#L1046 assume !(0 != eval_~tmp~0#1); 4118#L1049 assume true; 5693#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4474#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4475#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 4500#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4501#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4897#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4819#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4820#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5118#L1288 assume !(0 == ~T6_E~0); 5119#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4528#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4529#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5959#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5960#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4811#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4812#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5914#L1328 assume !(0 == ~E_1~0); 5915#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 4429#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 4430#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 4388#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 4389#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 4705#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 5358#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 4985#L1368 assume !(0 == ~E_9~0); 4986#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 4805#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 4806#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 5769#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 5746#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4391#L607-1 assume 1 == ~m_pc~0; 4392#L608-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4287#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4314#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4315#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4609#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5723#L626-1 assume 1 == ~t1_pc~0; 5510#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5511#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5313#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4762#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4763#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4238#L645-1 assume !(1 == ~t2_pc~0); 4240#L655-1 is_transmit2_triggered_~__retres1~2#1 := 0; 5162#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4192#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4193#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5747#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4373#L664-1 assume !(1 == ~t3_pc~0); 4374#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 4503#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4504#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5102#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5477#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5576#L683-1 assume !(1 == ~t4_pc~0); 5548#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 5549#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5523#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4888#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4889#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5062#L702-1 assume 1 == ~t5_pc~0; 4615#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4616#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4345#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4346#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5611#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5612#L721-1 assume 1 == ~t6_pc~0; 5760#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5761#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3994#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3995#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5750#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5071#L740-1 assume !(1 == ~t7_pc~0); 5072#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 5806#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4106#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4107#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5795#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5916#L759-1 assume !(1 == ~t8_pc~0); 5841#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 4214#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4215#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5736#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5470#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4923#L778-1 assume 1 == ~t9_pc~0; 4924#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5338#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5555#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4828#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4573#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4176#L797-1 assume 1 == ~t10_pc~0; 4177#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4714#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4715#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5849#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4675#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4676#L816-1 assume !(1 == ~t11_pc~0); 5586#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 4009#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4010#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4060#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4202#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4203#L835-1 assume 1 == ~t12_pc~0; 5665#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4579#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4580#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4284#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4285#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4435#L854-1 assume 1 == ~t13_pc~0; 4436#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5603#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5014#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5015#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5403#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5735#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 4886#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4887#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5220#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4604#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4457#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4458#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5106#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5359#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4684#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4685#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4544#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4545#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5924#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5844#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 5483#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 5484#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 5918#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 5686#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 4174#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 4175#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 4647#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 4648#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 4016#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 4017#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 5875#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 4488#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 4489#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5700#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4271#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4272#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4982#L1911 assume !(0 == start_simulation_~tmp~3#1); 4942#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5233#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4293#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4294#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4243#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4244#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4517#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4518#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 4126#L1892 [2024-11-17 08:53:58,344 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:58,345 INFO L85 PathProgramCache]: Analyzing trace with hash 1999782795, now seen corresponding path program 2 times [2024-11-17 08:53:58,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:58,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519162277] [2024-11-17 08:53:58,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:58,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:58,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:58,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:58,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:58,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519162277] [2024-11-17 08:53:58,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [519162277] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:58,442 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:58,442 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:58,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [364570586] [2024-11-17 08:53:58,442 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:58,443 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:58,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:58,444 INFO L85 PathProgramCache]: Analyzing trace with hash 998539887, now seen corresponding path program 1 times [2024-11-17 08:53:58,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:58,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339949329] [2024-11-17 08:53:58,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:58,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:58,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:58,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:58,613 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:58,613 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339949329] [2024-11-17 08:53:58,613 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339949329] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:58,613 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:58,614 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:58,614 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2108518170] [2024-11-17 08:53:58,614 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:58,614 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:58,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:58,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:58,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:58,616 INFO L87 Difference]: Start difference. First operand 1976 states and 2897 transitions. cyclomatic complexity: 922 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:58,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:58,716 INFO L93 Difference]: Finished difference Result 1976 states and 2896 transitions. [2024-11-17 08:53:58,716 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2896 transitions. [2024-11-17 08:53:58,727 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:58,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2896 transitions. [2024-11-17 08:53:58,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:53:58,739 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:53:58,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2896 transitions. [2024-11-17 08:53:58,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:58,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2896 transitions. [2024-11-17 08:53:58,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2896 transitions. [2024-11-17 08:53:58,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:53:58,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.465587044534413) internal successors, (2896), 1975 states have internal predecessors, (2896), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:58,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2896 transitions. [2024-11-17 08:53:58,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2896 transitions. [2024-11-17 08:53:58,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:58,783 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2896 transitions. [2024-11-17 08:53:58,783 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:53:58,783 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2896 transitions. [2024-11-17 08:53:58,794 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:58,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:58,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:58,799 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:58,802 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:58,802 INFO L745 eck$LassoCheckResult]: Stem: 8887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8888#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8690#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8691#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9343#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 8692#L886 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 8693#L891 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 9157#L896 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8898#L901 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8899#L906 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9425#L911 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9426#L916 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9028#L921 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9029#L926 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 9186#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8750#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8751#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8496#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8497#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9059#L1258-1 assume !(0 == ~M_E~0); 8939#L1263-1 assume !(0 == ~T1_E~0); 8940#L1268-1 assume !(0 == ~T2_E~0); 9246#L1273-1 assume !(0 == ~T3_E~0); 9792#L1278-1 assume !(0 == ~T4_E~0); 9676#L1283-1 assume !(0 == ~T5_E~0); 9677#L1288-1 assume !(0 == ~T6_E~0); 9873#L1293-1 assume !(0 == ~T7_E~0); 9863#L1298-1 assume !(0 == ~T8_E~0); 9803#L1303-1 assume !(0 == ~T9_E~0); 8460#L1308-1 assume !(0 == ~T10_E~0); 8385#L1313-1 assume !(0 == ~T11_E~0); 8386#L1318-1 assume !(0 == ~T12_E~0); 8399#L1323-1 assume !(0 == ~T13_E~0); 8400#L1328-1 assume !(0 == ~E_1~0); 8580#L1333-1 assume !(0 == ~E_2~0); 9521#L1338-1 assume !(0 == ~E_3~0); 9522#L1343-1 assume !(0 == ~E_4~0); 9646#L1348-1 assume !(0 == ~E_5~0); 9898#L1353-1 assume !(0 == ~E_6~0); 9256#L1358-1 assume !(0 == ~E_7~0); 9257#L1363-1 assume !(0 == ~E_8~0); 9550#L1368-1 assume !(0 == ~E_9~0); 8184#L1373-1 assume !(0 == ~E_10~0); 8185#L1378-1 assume !(0 == ~E_11~0); 8532#L1383-1 assume !(0 == ~E_12~0); 8533#L1388-1 assume !(0 == ~E_13~0); 9638#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9769#L607-15 assume 1 == ~m_pc~0; 9823#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9607#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9511#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9512#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8488#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8236#L626-15 assume 1 == ~t1_pc~0; 8237#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8936#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8982#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9758#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 9585#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9586#L645-15 assume 1 == ~t2_pc~0; 9337#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8337#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8338#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9703#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 9038#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8008#L664-15 assume 1 == ~t3_pc~0; 8009#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9341#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8948#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8282#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 8283#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8711#L683-15 assume 1 == ~t4_pc~0; 9237#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9197#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9198#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9467#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9101#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9102#L702-15 assume 1 == ~t5_pc~0; 9670#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9045#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9720#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9771#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 8995#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8088#L721-15 assume 1 == ~t6_pc~0; 8089#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8316#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9830#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8904#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 8905#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8150#L740-15 assume 1 == ~t7_pc~0; 8151#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9597#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9013#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9014#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 9793#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9794#L759-15 assume 1 == ~t8_pc~0; 9674#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8702#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9754#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9507#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9508#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8256#L778-15 assume 1 == ~t9_pc~0; 8257#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8761#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8762#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8401#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 8402#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9470#L797-15 assume 1 == ~t10_pc~0; 8706#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8707#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9396#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8407#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 8408#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8992#L816-15 assume 1 == ~t11_pc~0; 8959#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 8960#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9533#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8721#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 8722#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9544#L835-15 assume 1 == ~t12_pc~0; 9579#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 9822#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9820#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9061#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8034#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8035#L854-15 assume 1 == ~t13_pc~0; 8893#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8894#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8363#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8364#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 8768#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9143#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 9144#L1406-1 assume !(1 == ~T1_E~0); 9397#L1411-1 assume !(1 == ~T2_E~0); 9398#L1416-1 assume !(1 == ~T3_E~0); 9068#L1421-1 assume !(1 == ~T4_E~0); 8617#L1426-1 assume !(1 == ~T5_E~0); 8618#L1431-1 assume !(1 == ~T6_E~0); 8099#L1436-1 assume !(1 == ~T7_E~0); 8100#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8929#L1446-1 assume !(1 == ~T9_E~0); 8930#L1451-1 assume !(1 == ~T10_E~0); 9644#L1456-1 assume !(1 == ~T11_E~0); 9283#L1461-1 assume !(1 == ~T12_E~0); 8840#L1466-1 assume !(1 == ~T13_E~0); 8841#L1471-1 assume !(1 == ~E_1~0); 9615#L1476-1 assume !(1 == ~E_2~0); 9616#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9760#L1486-1 assume !(1 == ~E_4~0); 8480#L1491-1 assume !(1 == ~E_5~0); 8025#L1496-1 assume !(1 == ~E_6~0); 8026#L1501-1 assume !(1 == ~E_7~0); 8922#L1506-1 assume !(1 == ~E_8~0); 8923#L1511-1 assume !(1 == ~E_9~0); 8872#L1516-1 assume !(1 == ~E_10~0); 7981#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 7982#L1526-1 assume !(1 == ~E_12~0); 8024#L1531-1 assume !(1 == ~E_13~0); 8635#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 8087#L1892 [2024-11-17 08:53:58,803 INFO L747 eck$LassoCheckResult]: Loop: 8087#L1892 assume true; 8030#L1892-1 assume !false; 8031#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8647#L1041 assume true; 8816#L1041-1 assume !false; 8817#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9464#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8544#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9377#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8077#L1046 assume !(0 != eval_~tmp~0#1); 8079#L1049 assume true; 9654#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8435#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8436#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 8461#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8462#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8858#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8780#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8781#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9079#L1288 assume !(0 == ~T6_E~0); 9080#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8489#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8490#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9920#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9921#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8772#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8773#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9875#L1328 assume !(0 == ~E_1~0); 9876#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 8390#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 8391#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 8349#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 8350#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 8666#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 9319#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 8946#L1368 assume !(0 == ~E_9~0); 8947#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 8766#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 8767#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 9730#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 9707#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8352#L607-1 assume 1 == ~m_pc~0; 8353#L608-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8248#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8275#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8276#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8570#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9684#L626-1 assume !(1 == ~t1_pc~0); 9473#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 9472#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9274#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8723#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8724#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8199#L645-1 assume 1 == ~t2_pc~0; 8200#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9123#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8153#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8154#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9708#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8334#L664-1 assume 1 == ~t3_pc~0; 8336#L665-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8464#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8465#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9063#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9438#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9537#L683-1 assume !(1 == ~t4_pc~0); 9509#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 9510#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9484#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8849#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8850#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9023#L702-1 assume 1 == ~t5_pc~0; 8576#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8577#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8306#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8307#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9572#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9573#L721-1 assume 1 == ~t6_pc~0; 9721#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9722#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7955#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7956#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9711#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9032#L740-1 assume !(1 == ~t7_pc~0); 9033#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 9767#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8067#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8068#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9756#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9877#L759-1 assume 1 == ~t8_pc~0; 9878#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8175#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8176#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9697#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9431#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8884#L778-1 assume 1 == ~t9_pc~0; 8885#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9299#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9516#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8789#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8534#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8137#L797-1 assume 1 == ~t10_pc~0; 8138#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8675#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8676#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9810#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8636#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8637#L816-1 assume 1 == ~t11_pc~0; 9648#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7970#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7971#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8021#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8163#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8164#L835-1 assume 1 == ~t12_pc~0; 9626#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8540#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8541#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8245#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8246#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8396#L854-1 assume 1 == ~t13_pc~0; 8397#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9564#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8975#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8976#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 9364#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9696#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 8847#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8848#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9181#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8565#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8418#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8419#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9067#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9320#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8645#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8646#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8505#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8506#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9885#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9805#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 9444#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 9445#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 9879#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 9647#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 8135#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 8136#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 8608#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 8609#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 7977#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 7978#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 9836#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 8449#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 8450#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9661#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8232#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8233#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 8943#L1911 assume !(0 == start_simulation_~tmp~3#1); 8903#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9194#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8254#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8255#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 8204#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8205#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8478#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8479#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 8087#L1892 [2024-11-17 08:53:58,804 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:58,804 INFO L85 PathProgramCache]: Analyzing trace with hash -1410448694, now seen corresponding path program 1 times [2024-11-17 08:53:58,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:58,804 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244281059] [2024-11-17 08:53:58,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:58,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:58,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:58,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:58,881 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:58,882 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [244281059] [2024-11-17 08:53:58,882 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [244281059] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:58,882 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:58,882 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:58,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027814588] [2024-11-17 08:53:58,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:58,883 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:58,884 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:58,884 INFO L85 PathProgramCache]: Analyzing trace with hash -131795816, now seen corresponding path program 1 times [2024-11-17 08:53:58,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:58,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165947571] [2024-11-17 08:53:58,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:58,885 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:58,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:58,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:58,996 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:58,996 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165947571] [2024-11-17 08:53:58,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1165947571] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:58,997 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:58,997 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:58,997 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879816904] [2024-11-17 08:53:58,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:58,999 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:58,999 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:58,999 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:58,999 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:59,000 INFO L87 Difference]: Start difference. First operand 1976 states and 2896 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:59,033 INFO L93 Difference]: Finished difference Result 1976 states and 2895 transitions. [2024-11-17 08:53:59,034 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2895 transitions. [2024-11-17 08:53:59,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:59,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2895 transitions. [2024-11-17 08:53:59,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:53:59,054 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:53:59,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2895 transitions. [2024-11-17 08:53:59,058 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:59,058 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2895 transitions. [2024-11-17 08:53:59,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2895 transitions. [2024-11-17 08:53:59,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:53:59,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.4650809716599191) internal successors, (2895), 1975 states have internal predecessors, (2895), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2895 transitions. [2024-11-17 08:53:59,092 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2895 transitions. [2024-11-17 08:53:59,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:59,093 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2895 transitions. [2024-11-17 08:53:59,094 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:53:59,094 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2895 transitions. [2024-11-17 08:53:59,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:59,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:59,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:59,108 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:59,108 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:59,108 INFO L745 eck$LassoCheckResult]: Stem: 12848#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 12849#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12651#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12652#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13304#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 12653#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12654#L891 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 13118#L896 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 12859#L901 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12860#L906 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13386#L911 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13387#L916 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12989#L921 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12990#L926 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 13147#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12711#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12712#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12457#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12458#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13020#L1258-1 assume !(0 == ~M_E~0); 12900#L1263-1 assume !(0 == ~T1_E~0); 12901#L1268-1 assume !(0 == ~T2_E~0); 13207#L1273-1 assume !(0 == ~T3_E~0); 13753#L1278-1 assume !(0 == ~T4_E~0); 13637#L1283-1 assume !(0 == ~T5_E~0); 13638#L1288-1 assume !(0 == ~T6_E~0); 13834#L1293-1 assume !(0 == ~T7_E~0); 13824#L1298-1 assume !(0 == ~T8_E~0); 13764#L1303-1 assume !(0 == ~T9_E~0); 12421#L1308-1 assume !(0 == ~T10_E~0); 12346#L1313-1 assume !(0 == ~T11_E~0); 12347#L1318-1 assume !(0 == ~T12_E~0); 12360#L1323-1 assume !(0 == ~T13_E~0); 12361#L1328-1 assume !(0 == ~E_1~0); 12541#L1333-1 assume !(0 == ~E_2~0); 13482#L1338-1 assume !(0 == ~E_3~0); 13483#L1343-1 assume !(0 == ~E_4~0); 13607#L1348-1 assume !(0 == ~E_5~0); 13859#L1353-1 assume !(0 == ~E_6~0); 13217#L1358-1 assume !(0 == ~E_7~0); 13218#L1363-1 assume !(0 == ~E_8~0); 13511#L1368-1 assume !(0 == ~E_9~0); 12145#L1373-1 assume !(0 == ~E_10~0); 12146#L1378-1 assume !(0 == ~E_11~0); 12493#L1383-1 assume !(0 == ~E_12~0); 12494#L1388-1 assume !(0 == ~E_13~0); 13599#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13730#L607-15 assume 1 == ~m_pc~0; 13784#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13568#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13472#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13473#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12449#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12197#L626-15 assume 1 == ~t1_pc~0; 12198#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12897#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12943#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13719#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 13546#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13547#L645-15 assume 1 == ~t2_pc~0; 13298#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12298#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12299#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13664#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 12999#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11969#L664-15 assume 1 == ~t3_pc~0; 11970#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13302#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12909#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12243#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 12244#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12672#L683-15 assume 1 == ~t4_pc~0; 13198#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13158#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13159#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13428#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13062#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13063#L702-15 assume 1 == ~t5_pc~0; 13631#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13006#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13681#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13732#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 12956#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12049#L721-15 assume 1 == ~t6_pc~0; 12050#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12277#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13791#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12865#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 12866#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12111#L740-15 assume 1 == ~t7_pc~0; 12112#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13558#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12974#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12975#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 13754#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13755#L759-15 assume 1 == ~t8_pc~0; 13635#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12663#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13715#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13468#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13469#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12217#L778-15 assume 1 == ~t9_pc~0; 12218#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12722#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12723#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12362#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 12363#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13431#L797-15 assume 1 == ~t10_pc~0; 12667#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12668#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13357#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12368#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 12369#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12953#L816-15 assume 1 == ~t11_pc~0; 12920#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12921#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13494#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12682#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 12683#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13505#L835-15 assume 1 == ~t12_pc~0; 13540#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 13783#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13781#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13022#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11995#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 11996#L854-15 assume 1 == ~t13_pc~0; 12854#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12855#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12324#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12325#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 12729#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13104#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 13105#L1406-1 assume !(1 == ~T1_E~0); 13358#L1411-1 assume !(1 == ~T2_E~0); 13359#L1416-1 assume !(1 == ~T3_E~0); 13029#L1421-1 assume !(1 == ~T4_E~0); 12578#L1426-1 assume !(1 == ~T5_E~0); 12579#L1431-1 assume !(1 == ~T6_E~0); 12060#L1436-1 assume !(1 == ~T7_E~0); 12061#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12890#L1446-1 assume !(1 == ~T9_E~0); 12891#L1451-1 assume !(1 == ~T10_E~0); 13605#L1456-1 assume !(1 == ~T11_E~0); 13244#L1461-1 assume !(1 == ~T12_E~0); 12801#L1466-1 assume !(1 == ~T13_E~0); 12802#L1471-1 assume !(1 == ~E_1~0); 13576#L1476-1 assume !(1 == ~E_2~0); 13577#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 13721#L1486-1 assume !(1 == ~E_4~0); 12441#L1491-1 assume !(1 == ~E_5~0); 11986#L1496-1 assume !(1 == ~E_6~0); 11987#L1501-1 assume !(1 == ~E_7~0); 12883#L1506-1 assume !(1 == ~E_8~0); 12884#L1511-1 assume !(1 == ~E_9~0); 12833#L1516-1 assume !(1 == ~E_10~0); 11942#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 11943#L1526-1 assume !(1 == ~E_12~0); 11985#L1531-1 assume !(1 == ~E_13~0); 12596#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 12048#L1892 [2024-11-17 08:53:59,109 INFO L747 eck$LassoCheckResult]: Loop: 12048#L1892 assume true; 11991#L1892-1 assume !false; 11992#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12608#L1041 assume true; 12777#L1041-1 assume !false; 12778#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13425#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12505#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 13338#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12038#L1046 assume !(0 != eval_~tmp~0#1); 12040#L1049 assume true; 13615#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12396#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12397#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 12422#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12423#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12819#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12741#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12742#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13040#L1288 assume !(0 == ~T6_E~0); 13041#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12450#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12451#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13881#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13882#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12733#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12734#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13836#L1328 assume !(0 == ~E_1~0); 13837#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 12351#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 12352#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 12310#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 12311#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 12627#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 13280#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 12907#L1368 assume !(0 == ~E_9~0); 12908#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 12727#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 12728#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 13691#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 13668#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12313#L607-1 assume !(1 == ~m_pc~0); 12208#L617-1 is_master_triggered_~__retres1~0#1 := 0; 12209#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12236#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12237#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12531#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13645#L626-1 assume 1 == ~t1_pc~0; 13432#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13433#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13235#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12684#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12685#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12160#L645-1 assume 1 == ~t2_pc~0; 12161#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13084#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12114#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12115#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13669#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12295#L664-1 assume !(1 == ~t3_pc~0); 12296#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 12425#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12426#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13024#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13399#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13498#L683-1 assume 1 == ~t4_pc~0; 13808#L684-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13471#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13445#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12810#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12811#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12984#L702-1 assume 1 == ~t5_pc~0; 12537#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12538#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12267#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12268#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13533#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13534#L721-1 assume 1 == ~t6_pc~0; 13682#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13683#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11916#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11917#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13672#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12993#L740-1 assume !(1 == ~t7_pc~0); 12994#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 13728#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12028#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12029#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13717#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13838#L759-1 assume !(1 == ~t8_pc~0); 13763#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 12136#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12137#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13658#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13392#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12845#L778-1 assume 1 == ~t9_pc~0; 12846#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13260#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13477#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12750#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12495#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12098#L797-1 assume 1 == ~t10_pc~0; 12099#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12636#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12637#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13771#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12597#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12598#L816-1 assume !(1 == ~t11_pc~0); 13508#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 11931#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11932#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11982#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12124#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12125#L835-1 assume 1 == ~t12_pc~0; 13587#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 12501#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12502#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12206#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 12207#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12357#L854-1 assume 1 == ~t13_pc~0; 12358#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13525#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12936#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12937#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 13325#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13657#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 12808#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12809#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13142#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12526#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12379#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12380#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13028#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13281#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12606#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12607#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12466#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12467#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13846#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13766#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 13405#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 13406#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 13840#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 13608#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 12096#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 12097#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 12569#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 12570#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 11938#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 11939#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 13797#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 12410#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 12411#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13622#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12193#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12194#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 12904#L1911 assume !(0 == start_simulation_~tmp~3#1); 12864#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13155#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12215#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12216#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 12165#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12166#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12439#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12440#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 12048#L1892 [2024-11-17 08:53:59,110 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,110 INFO L85 PathProgramCache]: Analyzing trace with hash -1104814165, now seen corresponding path program 1 times [2024-11-17 08:53:59,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803973247] [2024-11-17 08:53:59,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:59,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:59,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:59,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [803973247] [2024-11-17 08:53:59,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [803973247] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:59,166 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:59,166 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:59,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [602063132] [2024-11-17 08:53:59,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:59,167 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:59,167 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,167 INFO L85 PathProgramCache]: Analyzing trace with hash 956960274, now seen corresponding path program 1 times [2024-11-17 08:53:59,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1892244728] [2024-11-17 08:53:59,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:59,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:59,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:59,307 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1892244728] [2024-11-17 08:53:59,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1892244728] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:59,308 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:59,308 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:59,308 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146148679] [2024-11-17 08:53:59,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:59,310 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:59,310 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:59,310 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:59,310 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:59,311 INFO L87 Difference]: Start difference. First operand 1976 states and 2895 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:59,346 INFO L93 Difference]: Finished difference Result 1976 states and 2894 transitions. [2024-11-17 08:53:59,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2894 transitions. [2024-11-17 08:53:59,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:59,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2894 transitions. [2024-11-17 08:53:59,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:53:59,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:53:59,370 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2894 transitions. [2024-11-17 08:53:59,373 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:59,374 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2894 transitions. [2024-11-17 08:53:59,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2894 transitions. [2024-11-17 08:53:59,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:53:59,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.464574898785425) internal successors, (2894), 1975 states have internal predecessors, (2894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2894 transitions. [2024-11-17 08:53:59,415 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2894 transitions. [2024-11-17 08:53:59,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:59,416 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2894 transitions. [2024-11-17 08:53:59,416 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:53:59,417 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2894 transitions. [2024-11-17 08:53:59,428 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:59,428 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:59,428 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:59,432 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:59,433 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:59,433 INFO L745 eck$LassoCheckResult]: Stem: 16809#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 16810#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16612#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16613#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17265#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 16614#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16615#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17079#L896 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 16820#L901 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 16821#L906 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17347#L911 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17348#L916 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16950#L921 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16951#L926 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 17108#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16672#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16673#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16418#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 16419#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16981#L1258-1 assume !(0 == ~M_E~0); 16861#L1263-1 assume !(0 == ~T1_E~0); 16862#L1268-1 assume !(0 == ~T2_E~0); 17168#L1273-1 assume !(0 == ~T3_E~0); 17714#L1278-1 assume !(0 == ~T4_E~0); 17598#L1283-1 assume !(0 == ~T5_E~0); 17599#L1288-1 assume !(0 == ~T6_E~0); 17795#L1293-1 assume !(0 == ~T7_E~0); 17785#L1298-1 assume !(0 == ~T8_E~0); 17725#L1303-1 assume !(0 == ~T9_E~0); 16382#L1308-1 assume !(0 == ~T10_E~0); 16307#L1313-1 assume !(0 == ~T11_E~0); 16308#L1318-1 assume !(0 == ~T12_E~0); 16321#L1323-1 assume !(0 == ~T13_E~0); 16322#L1328-1 assume !(0 == ~E_1~0); 16502#L1333-1 assume !(0 == ~E_2~0); 17443#L1338-1 assume !(0 == ~E_3~0); 17444#L1343-1 assume !(0 == ~E_4~0); 17568#L1348-1 assume !(0 == ~E_5~0); 17820#L1353-1 assume !(0 == ~E_6~0); 17178#L1358-1 assume !(0 == ~E_7~0); 17179#L1363-1 assume !(0 == ~E_8~0); 17472#L1368-1 assume !(0 == ~E_9~0); 16106#L1373-1 assume !(0 == ~E_10~0); 16107#L1378-1 assume !(0 == ~E_11~0); 16454#L1383-1 assume !(0 == ~E_12~0); 16455#L1388-1 assume !(0 == ~E_13~0); 17560#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17691#L607-15 assume 1 == ~m_pc~0; 17745#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17529#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17433#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17434#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16410#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16158#L626-15 assume 1 == ~t1_pc~0; 16159#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16858#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16904#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17680#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 17507#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17508#L645-15 assume 1 == ~t2_pc~0; 17259#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16259#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16260#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17625#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 16960#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15930#L664-15 assume 1 == ~t3_pc~0; 15931#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17263#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16870#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16204#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 16205#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16633#L683-15 assume 1 == ~t4_pc~0; 17159#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17119#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17120#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17389#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17023#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17024#L702-15 assume 1 == ~t5_pc~0; 17592#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16967#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17642#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17693#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 16917#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16010#L721-15 assume 1 == ~t6_pc~0; 16011#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16238#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17752#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16826#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 16827#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16072#L740-15 assume 1 == ~t7_pc~0; 16073#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17519#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16935#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16936#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 17715#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17716#L759-15 assume 1 == ~t8_pc~0; 17596#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16624#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17676#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17429#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17430#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16178#L778-15 assume 1 == ~t9_pc~0; 16179#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16683#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16684#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16323#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 16324#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17392#L797-15 assume 1 == ~t10_pc~0; 16628#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16629#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17318#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16329#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 16330#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16914#L816-15 assume 1 == ~t11_pc~0; 16881#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16882#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17455#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16643#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 16644#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17466#L835-15 assume 1 == ~t12_pc~0; 17501#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 17744#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17742#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16983#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 15956#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 15957#L854-15 assume 1 == ~t13_pc~0; 16815#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 16816#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16285#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16286#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 16690#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17065#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 17066#L1406-1 assume !(1 == ~T1_E~0); 17319#L1411-1 assume !(1 == ~T2_E~0); 17320#L1416-1 assume !(1 == ~T3_E~0); 16990#L1421-1 assume !(1 == ~T4_E~0); 16539#L1426-1 assume !(1 == ~T5_E~0); 16540#L1431-1 assume !(1 == ~T6_E~0); 16021#L1436-1 assume !(1 == ~T7_E~0); 16022#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16851#L1446-1 assume !(1 == ~T9_E~0); 16852#L1451-1 assume !(1 == ~T10_E~0); 17566#L1456-1 assume !(1 == ~T11_E~0); 17205#L1461-1 assume !(1 == ~T12_E~0); 16762#L1466-1 assume !(1 == ~T13_E~0); 16763#L1471-1 assume !(1 == ~E_1~0); 17537#L1476-1 assume !(1 == ~E_2~0); 17538#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 17682#L1486-1 assume !(1 == ~E_4~0); 16402#L1491-1 assume !(1 == ~E_5~0); 15947#L1496-1 assume !(1 == ~E_6~0); 15948#L1501-1 assume !(1 == ~E_7~0); 16844#L1506-1 assume !(1 == ~E_8~0); 16845#L1511-1 assume !(1 == ~E_9~0); 16794#L1516-1 assume !(1 == ~E_10~0); 15903#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 15904#L1526-1 assume !(1 == ~E_12~0); 15946#L1531-1 assume !(1 == ~E_13~0); 16557#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 16009#L1892 [2024-11-17 08:53:59,434 INFO L747 eck$LassoCheckResult]: Loop: 16009#L1892 assume true; 15952#L1892-1 assume !false; 15953#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16569#L1041 assume true; 16738#L1041-1 assume !false; 16739#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17386#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16466#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 17299#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15999#L1046 assume !(0 != eval_~tmp~0#1); 16001#L1049 assume true; 17576#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16357#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16358#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 16383#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16384#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16780#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16702#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16703#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17001#L1288 assume !(0 == ~T6_E~0); 17002#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16411#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16412#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17842#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17843#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16694#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16695#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17797#L1328 assume !(0 == ~E_1~0); 17798#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 16312#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 16313#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 16271#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 16272#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 16588#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 17241#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 16868#L1368 assume !(0 == ~E_9~0); 16869#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 16688#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 16689#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 17652#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 17629#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16274#L607-1 assume 1 == ~m_pc~0; 16275#L608-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16170#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16197#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16198#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16492#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17606#L626-1 assume 1 == ~t1_pc~0; 17393#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17394#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17196#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16645#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16646#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16121#L645-1 assume 1 == ~t2_pc~0; 16122#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 17045#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16075#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16076#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17630#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16256#L664-1 assume !(1 == ~t3_pc~0); 16257#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 16386#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16387#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16985#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17360#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17459#L683-1 assume !(1 == ~t4_pc~0); 17431#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 17432#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17406#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16771#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16772#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16945#L702-1 assume 1 == ~t5_pc~0; 16498#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16499#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16228#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16229#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17494#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17495#L721-1 assume 1 == ~t6_pc~0; 17643#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17644#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15877#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15878#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17633#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16954#L740-1 assume !(1 == ~t7_pc~0); 16955#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 17689#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15989#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15990#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17678#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17799#L759-1 assume 1 == ~t8_pc~0; 17800#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16097#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16098#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17619#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17353#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16806#L778-1 assume 1 == ~t9_pc~0; 16807#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17221#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17438#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16711#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16456#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16059#L797-1 assume 1 == ~t10_pc~0; 16060#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16597#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16598#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17732#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16558#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16559#L816-1 assume 1 == ~t11_pc~0; 17570#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15892#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15893#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 15943#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16085#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16086#L835-1 assume 1 == ~t12_pc~0; 17548#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 16462#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16463#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16167#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 16168#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 16318#L854-1 assume !(1 == ~t13_pc~0); 16320#L864-1 is_transmit13_triggered_~__retres1~13#1 := 0; 17486#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 16897#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16898#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 17286#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17618#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 16769#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16770#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17103#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16487#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16340#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16341#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16989#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17242#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16567#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16568#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16427#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16428#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 17807#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17727#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 17366#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 17367#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 17801#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 17569#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 16057#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 16058#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 16530#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 16531#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 15899#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 15900#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 17758#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 16371#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 16372#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17583#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16154#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16155#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16865#L1911 assume !(0 == start_simulation_~tmp~3#1); 16825#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17116#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16176#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16177#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 16126#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16127#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16400#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 16401#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 16009#L1892 [2024-11-17 08:53:59,435 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,435 INFO L85 PathProgramCache]: Analyzing trace with hash -402218326, now seen corresponding path program 1 times [2024-11-17 08:53:59,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,436 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549509714] [2024-11-17 08:53:59,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:59,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:59,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:59,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1549509714] [2024-11-17 08:53:59,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1549509714] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:59,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:59,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:59,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880163906] [2024-11-17 08:53:59,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:59,489 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:59,489 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,489 INFO L85 PathProgramCache]: Analyzing trace with hash 855490741, now seen corresponding path program 1 times [2024-11-17 08:53:59,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225926652] [2024-11-17 08:53:59,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,490 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:59,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:59,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:59,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1225926652] [2024-11-17 08:53:59,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1225926652] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:59,588 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:59,588 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:59,588 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848275286] [2024-11-17 08:53:59,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:59,589 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:59,590 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:59,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:59,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:59,590 INFO L87 Difference]: Start difference. First operand 1976 states and 2894 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:59,626 INFO L93 Difference]: Finished difference Result 1976 states and 2893 transitions. [2024-11-17 08:53:59,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2893 transitions. [2024-11-17 08:53:59,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:59,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2893 transitions. [2024-11-17 08:53:59,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:53:59,645 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:53:59,645 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2893 transitions. [2024-11-17 08:53:59,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:59,648 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2893 transitions. [2024-11-17 08:53:59,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2893 transitions. [2024-11-17 08:53:59,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:53:59,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.4640688259109311) internal successors, (2893), 1975 states have internal predecessors, (2893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2893 transitions. [2024-11-17 08:53:59,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2893 transitions. [2024-11-17 08:53:59,705 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:59,707 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2893 transitions. [2024-11-17 08:53:59,707 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:53:59,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2893 transitions. [2024-11-17 08:53:59,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:59,715 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:59,715 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:59,717 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:59,717 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:59,718 INFO L745 eck$LassoCheckResult]: Stem: 20770#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 20771#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20573#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20574#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21226#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 20575#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20576#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21040#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20781#L901 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 20782#L906 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21308#L911 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21309#L916 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20911#L921 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20912#L926 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 21069#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20633#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20634#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20379#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 20380#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20942#L1258-1 assume !(0 == ~M_E~0); 20822#L1263-1 assume !(0 == ~T1_E~0); 20823#L1268-1 assume !(0 == ~T2_E~0); 21129#L1273-1 assume !(0 == ~T3_E~0); 21675#L1278-1 assume !(0 == ~T4_E~0); 21559#L1283-1 assume !(0 == ~T5_E~0); 21560#L1288-1 assume !(0 == ~T6_E~0); 21756#L1293-1 assume !(0 == ~T7_E~0); 21746#L1298-1 assume !(0 == ~T8_E~0); 21686#L1303-1 assume !(0 == ~T9_E~0); 20343#L1308-1 assume !(0 == ~T10_E~0); 20268#L1313-1 assume !(0 == ~T11_E~0); 20269#L1318-1 assume !(0 == ~T12_E~0); 20282#L1323-1 assume !(0 == ~T13_E~0); 20283#L1328-1 assume !(0 == ~E_1~0); 20463#L1333-1 assume !(0 == ~E_2~0); 21404#L1338-1 assume !(0 == ~E_3~0); 21405#L1343-1 assume !(0 == ~E_4~0); 21529#L1348-1 assume !(0 == ~E_5~0); 21781#L1353-1 assume !(0 == ~E_6~0); 21139#L1358-1 assume !(0 == ~E_7~0); 21140#L1363-1 assume !(0 == ~E_8~0); 21433#L1368-1 assume !(0 == ~E_9~0); 20067#L1373-1 assume !(0 == ~E_10~0); 20068#L1378-1 assume !(0 == ~E_11~0); 20415#L1383-1 assume !(0 == ~E_12~0); 20416#L1388-1 assume !(0 == ~E_13~0); 21521#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21652#L607-15 assume 1 == ~m_pc~0; 21706#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21490#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21394#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21395#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20371#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20119#L626-15 assume 1 == ~t1_pc~0; 20120#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20819#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20865#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21641#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 21468#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21469#L645-15 assume 1 == ~t2_pc~0; 21220#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20220#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20221#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21586#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 20921#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19891#L664-15 assume 1 == ~t3_pc~0; 19892#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21224#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20831#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20165#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 20166#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20594#L683-15 assume 1 == ~t4_pc~0; 21120#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21080#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21081#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21350#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20984#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20985#L702-15 assume 1 == ~t5_pc~0; 21553#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20928#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21603#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21654#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 20878#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19971#L721-15 assume 1 == ~t6_pc~0; 19972#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20199#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21713#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20787#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 20788#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20033#L740-15 assume 1 == ~t7_pc~0; 20034#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21480#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20896#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20897#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 21676#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21677#L759-15 assume 1 == ~t8_pc~0; 21557#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20585#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21637#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21390#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21391#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20139#L778-15 assume 1 == ~t9_pc~0; 20140#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20644#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20645#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20284#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 20285#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21353#L797-15 assume 1 == ~t10_pc~0; 20589#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20590#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21279#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20290#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 20291#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20875#L816-15 assume 1 == ~t11_pc~0; 20842#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20843#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21416#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20604#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 20605#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21427#L835-15 assume 1 == ~t12_pc~0; 21462#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 21705#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 21703#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20944#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 19917#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 19918#L854-15 assume 1 == ~t13_pc~0; 20776#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 20777#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20246#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20247#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 20651#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21026#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 21027#L1406-1 assume !(1 == ~T1_E~0); 21280#L1411-1 assume !(1 == ~T2_E~0); 21281#L1416-1 assume !(1 == ~T3_E~0); 20951#L1421-1 assume !(1 == ~T4_E~0); 20500#L1426-1 assume !(1 == ~T5_E~0); 20501#L1431-1 assume !(1 == ~T6_E~0); 19982#L1436-1 assume !(1 == ~T7_E~0); 19983#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20812#L1446-1 assume !(1 == ~T9_E~0); 20813#L1451-1 assume !(1 == ~T10_E~0); 21527#L1456-1 assume !(1 == ~T11_E~0); 21166#L1461-1 assume !(1 == ~T12_E~0); 20723#L1466-1 assume !(1 == ~T13_E~0); 20724#L1471-1 assume !(1 == ~E_1~0); 21498#L1476-1 assume !(1 == ~E_2~0); 21499#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 21643#L1486-1 assume !(1 == ~E_4~0); 20363#L1491-1 assume !(1 == ~E_5~0); 19908#L1496-1 assume !(1 == ~E_6~0); 19909#L1501-1 assume !(1 == ~E_7~0); 20805#L1506-1 assume !(1 == ~E_8~0); 20806#L1511-1 assume !(1 == ~E_9~0); 20755#L1516-1 assume !(1 == ~E_10~0); 19864#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 19865#L1526-1 assume !(1 == ~E_12~0); 19907#L1531-1 assume !(1 == ~E_13~0); 20518#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 19970#L1892 [2024-11-17 08:53:59,718 INFO L747 eck$LassoCheckResult]: Loop: 19970#L1892 assume true; 19913#L1892-1 assume !false; 19914#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20530#L1041 assume true; 20699#L1041-1 assume !false; 20700#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21347#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20427#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 21260#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19960#L1046 assume !(0 != eval_~tmp~0#1); 19962#L1049 assume true; 21537#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20318#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20319#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 20344#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20345#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20741#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20663#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20664#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20962#L1288 assume !(0 == ~T6_E~0); 20963#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20372#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20373#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21803#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21804#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20655#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20656#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21758#L1328 assume !(0 == ~E_1~0); 21759#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 20273#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 20274#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 20232#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 20233#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 20549#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 21202#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 20829#L1368 assume !(0 == ~E_9~0); 20830#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 20649#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 20650#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 21613#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 21590#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20235#L607-1 assume !(1 == ~m_pc~0); 20130#L617-1 is_master_triggered_~__retres1~0#1 := 0; 20131#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20158#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20159#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20453#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21567#L626-1 assume 1 == ~t1_pc~0; 21354#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21355#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21157#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20606#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20607#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20082#L645-1 assume 1 == ~t2_pc~0; 20083#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 21006#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20036#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20037#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21591#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20217#L664-1 assume !(1 == ~t3_pc~0); 20218#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 20347#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20348#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20946#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21321#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21420#L683-1 assume !(1 == ~t4_pc~0); 21392#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 21393#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21367#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20732#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20733#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20906#L702-1 assume 1 == ~t5_pc~0; 20459#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20460#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20189#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20190#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21455#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21456#L721-1 assume 1 == ~t6_pc~0; 21604#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21605#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19838#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19839#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21594#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20915#L740-1 assume !(1 == ~t7_pc~0); 20916#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 21650#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19950#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19951#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21639#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21760#L759-1 assume 1 == ~t8_pc~0; 21761#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20058#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20059#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21580#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21314#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20767#L778-1 assume 1 == ~t9_pc~0; 20768#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21182#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21399#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20672#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20417#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20020#L797-1 assume 1 == ~t10_pc~0; 20021#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20558#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20559#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21693#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 20519#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20520#L816-1 assume !(1 == ~t11_pc~0); 21430#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 19853#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19854#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19904#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20046#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20047#L835-1 assume 1 == ~t12_pc~0; 21509#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 20423#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20424#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20128#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 20129#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 20279#L854-1 assume 1 == ~t13_pc~0; 20280#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21447#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 20858#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20859#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 21247#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21579#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 20730#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20731#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21064#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20448#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20301#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20302#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20950#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21203#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20528#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 20529#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20388#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20389#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 21768#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21688#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 21327#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 21328#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 21762#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 21530#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 20018#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 20019#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 20491#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 20492#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 19860#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 19861#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 21719#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 20332#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 20333#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21544#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20115#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20116#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 20826#L1911 assume !(0 == start_simulation_~tmp~3#1); 20786#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21077#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20137#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20138#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 20087#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20088#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20361#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 20362#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 19970#L1892 [2024-11-17 08:53:59,720 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,720 INFO L85 PathProgramCache]: Analyzing trace with hash -1349385269, now seen corresponding path program 1 times [2024-11-17 08:53:59,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,720 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [670200374] [2024-11-17 08:53:59,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:59,779 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:59,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:59,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [670200374] [2024-11-17 08:53:59,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [670200374] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:59,785 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:59,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:59,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2094579346] [2024-11-17 08:53:59,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:59,786 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:59,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,786 INFO L85 PathProgramCache]: Analyzing trace with hash -647526638, now seen corresponding path program 1 times [2024-11-17 08:53:59,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1117224966] [2024-11-17 08:53:59,787 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:59,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:59,880 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:59,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1117224966] [2024-11-17 08:53:59,881 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1117224966] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:59,881 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:59,881 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:53:59,881 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618508820] [2024-11-17 08:53:59,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:59,881 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:59,882 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:59,883 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:53:59,883 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:53:59,883 INFO L87 Difference]: Start difference. First operand 1976 states and 2893 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:59,917 INFO L93 Difference]: Finished difference Result 1976 states and 2892 transitions. [2024-11-17 08:53:59,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2892 transitions. [2024-11-17 08:53:59,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:59,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2892 transitions. [2024-11-17 08:53:59,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:53:59,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:53:59,937 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2892 transitions. [2024-11-17 08:53:59,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:59,940 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2892 transitions. [2024-11-17 08:53:59,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2892 transitions. [2024-11-17 08:53:59,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:53:59,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.4635627530364372) internal successors, (2892), 1975 states have internal predecessors, (2892), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2892 transitions. [2024-11-17 08:53:59,991 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2892 transitions. [2024-11-17 08:53:59,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:53:59,992 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2892 transitions. [2024-11-17 08:53:59,993 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:53:59,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2892 transitions. [2024-11-17 08:53:59,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:53:59,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:00,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:00,002 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,002 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,002 INFO L745 eck$LassoCheckResult]: Stem: 24731#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 24732#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 24534#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24535#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25187#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 24536#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24537#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25001#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24742#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24743#L906 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 25269#L911 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25270#L916 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 24872#L921 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24873#L926 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 25030#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24594#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 24595#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 24340#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 24341#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24903#L1258-1 assume !(0 == ~M_E~0); 24783#L1263-1 assume !(0 == ~T1_E~0); 24784#L1268-1 assume !(0 == ~T2_E~0); 25090#L1273-1 assume !(0 == ~T3_E~0); 25636#L1278-1 assume !(0 == ~T4_E~0); 25520#L1283-1 assume !(0 == ~T5_E~0); 25521#L1288-1 assume !(0 == ~T6_E~0); 25717#L1293-1 assume !(0 == ~T7_E~0); 25707#L1298-1 assume !(0 == ~T8_E~0); 25647#L1303-1 assume !(0 == ~T9_E~0); 24304#L1308-1 assume !(0 == ~T10_E~0); 24229#L1313-1 assume !(0 == ~T11_E~0); 24230#L1318-1 assume !(0 == ~T12_E~0); 24243#L1323-1 assume !(0 == ~T13_E~0); 24244#L1328-1 assume !(0 == ~E_1~0); 24424#L1333-1 assume !(0 == ~E_2~0); 25365#L1338-1 assume !(0 == ~E_3~0); 25366#L1343-1 assume !(0 == ~E_4~0); 25490#L1348-1 assume !(0 == ~E_5~0); 25742#L1353-1 assume !(0 == ~E_6~0); 25100#L1358-1 assume !(0 == ~E_7~0); 25101#L1363-1 assume !(0 == ~E_8~0); 25394#L1368-1 assume !(0 == ~E_9~0); 24028#L1373-1 assume !(0 == ~E_10~0); 24029#L1378-1 assume !(0 == ~E_11~0); 24376#L1383-1 assume !(0 == ~E_12~0); 24377#L1388-1 assume !(0 == ~E_13~0); 25482#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25613#L607-15 assume 1 == ~m_pc~0; 25667#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 25451#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25355#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25356#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24332#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24080#L626-15 assume 1 == ~t1_pc~0; 24081#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24780#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24826#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25602#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 25429#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25430#L645-15 assume 1 == ~t2_pc~0; 25181#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24181#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24182#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25547#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 24882#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23852#L664-15 assume 1 == ~t3_pc~0; 23853#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25185#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24792#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24126#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 24127#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24555#L683-15 assume 1 == ~t4_pc~0; 25081#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25041#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25042#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25311#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24945#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24946#L702-15 assume 1 == ~t5_pc~0; 25514#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24889#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25564#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25615#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 24839#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23932#L721-15 assume 1 == ~t6_pc~0; 23933#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 24160#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25674#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24748#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 24749#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23994#L740-15 assume 1 == ~t7_pc~0; 23995#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25441#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24857#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24858#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 25637#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25638#L759-15 assume 1 == ~t8_pc~0; 25518#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24546#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25598#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25351#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25352#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24100#L778-15 assume 1 == ~t9_pc~0; 24101#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24605#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24606#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24245#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 24246#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25314#L797-15 assume 1 == ~t10_pc~0; 24550#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24551#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25240#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24251#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 24252#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24836#L816-15 assume 1 == ~t11_pc~0; 24803#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 24804#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25377#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 24565#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 24566#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25388#L835-15 assume 1 == ~t12_pc~0; 25423#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 25666#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 25664#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24905#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 23878#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 23879#L854-15 assume 1 == ~t13_pc~0; 24737#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 24738#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 24207#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24208#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 24612#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24987#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 24988#L1406-1 assume !(1 == ~T1_E~0); 25241#L1411-1 assume !(1 == ~T2_E~0); 25242#L1416-1 assume !(1 == ~T3_E~0); 24912#L1421-1 assume !(1 == ~T4_E~0); 24461#L1426-1 assume !(1 == ~T5_E~0); 24462#L1431-1 assume !(1 == ~T6_E~0); 23943#L1436-1 assume !(1 == ~T7_E~0); 23944#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24773#L1446-1 assume !(1 == ~T9_E~0); 24774#L1451-1 assume !(1 == ~T10_E~0); 25488#L1456-1 assume !(1 == ~T11_E~0); 25127#L1461-1 assume !(1 == ~T12_E~0); 24684#L1466-1 assume !(1 == ~T13_E~0); 24685#L1471-1 assume !(1 == ~E_1~0); 25459#L1476-1 assume !(1 == ~E_2~0); 25460#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 25604#L1486-1 assume !(1 == ~E_4~0); 24324#L1491-1 assume !(1 == ~E_5~0); 23869#L1496-1 assume !(1 == ~E_6~0); 23870#L1501-1 assume !(1 == ~E_7~0); 24766#L1506-1 assume !(1 == ~E_8~0); 24767#L1511-1 assume !(1 == ~E_9~0); 24716#L1516-1 assume !(1 == ~E_10~0); 23825#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 23826#L1526-1 assume !(1 == ~E_12~0); 23868#L1531-1 assume !(1 == ~E_13~0); 24479#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 23931#L1892 [2024-11-17 08:54:00,003 INFO L747 eck$LassoCheckResult]: Loop: 23931#L1892 assume true; 23874#L1892-1 assume !false; 23875#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24491#L1041 assume true; 24660#L1041-1 assume !false; 24661#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25308#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24388#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25221#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23921#L1046 assume !(0 != eval_~tmp~0#1); 23923#L1049 assume true; 25498#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24279#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24280#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 24305#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24306#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24702#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24624#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24625#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24923#L1288 assume !(0 == ~T6_E~0); 24924#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24333#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24334#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25764#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25765#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24616#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24617#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25719#L1328 assume !(0 == ~E_1~0); 25720#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 24234#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 24235#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 24193#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 24194#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 24510#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 25163#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 24790#L1368 assume !(0 == ~E_9~0); 24791#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 24610#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 24611#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 25574#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 25551#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24196#L607-1 assume 1 == ~m_pc~0; 24197#L608-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 24092#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24119#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 24120#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24414#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25528#L626-1 assume 1 == ~t1_pc~0; 25315#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25316#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25118#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24567#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24568#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24043#L645-1 assume 1 == ~t2_pc~0; 24044#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24967#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23997#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23998#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25552#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24178#L664-1 assume !(1 == ~t3_pc~0); 24179#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 24308#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24309#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24907#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25282#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25381#L683-1 assume !(1 == ~t4_pc~0); 25353#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 25354#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25328#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24693#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24694#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24867#L702-1 assume 1 == ~t5_pc~0; 24420#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 24421#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24150#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24151#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25416#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25417#L721-1 assume 1 == ~t6_pc~0; 25565#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25566#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23799#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23800#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25555#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24876#L740-1 assume !(1 == ~t7_pc~0); 24877#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 25611#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23911#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23912#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25600#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25721#L759-1 assume 1 == ~t8_pc~0; 25722#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24019#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24020#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25541#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25275#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24728#L778-1 assume 1 == ~t9_pc~0; 24729#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25143#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25360#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 24633#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 24378#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23981#L797-1 assume 1 == ~t10_pc~0; 23982#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 24519#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24520#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25654#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24480#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 24481#L816-1 assume 1 == ~t11_pc~0; 25492#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23814#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23815#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23865#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24007#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24008#L835-1 assume 1 == ~t12_pc~0; 25470#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 24384#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24385#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24089#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 24090#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 24240#L854-1 assume 1 == ~t13_pc~0; 24241#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25408#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 24819#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24820#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 25208#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25540#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 24691#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24692#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25025#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24409#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24262#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24263#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24911#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25164#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24489#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24490#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24349#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24350#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 25729#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25649#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 25288#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 25289#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 25723#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 25491#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 23979#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 23980#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 24452#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 24453#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 23821#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 23822#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 25680#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 24293#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 24294#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25505#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24076#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24077#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 24787#L1911 assume !(0 == start_simulation_~tmp~3#1); 24747#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25038#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24098#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24099#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 24048#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24049#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24322#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24323#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 23931#L1892 [2024-11-17 08:54:00,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,004 INFO L85 PathProgramCache]: Analyzing trace with hash -2072675702, now seen corresponding path program 1 times [2024-11-17 08:54:00,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [930798830] [2024-11-17 08:54:00,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,005 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,051 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,051 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [930798830] [2024-11-17 08:54:00,051 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [930798830] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,051 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,051 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:00,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117890170] [2024-11-17 08:54:00,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,052 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:00,052 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,052 INFO L85 PathProgramCache]: Analyzing trace with hash -1362642920, now seen corresponding path program 1 times [2024-11-17 08:54:00,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536644145] [2024-11-17 08:54:00,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,165 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,165 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536644145] [2024-11-17 08:54:00,165 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [536644145] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,165 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,166 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:00,166 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2049683398] [2024-11-17 08:54:00,166 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,166 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:00,167 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:00,167 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:00,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:00,168 INFO L87 Difference]: Start difference. First operand 1976 states and 2892 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:00,209 INFO L93 Difference]: Finished difference Result 1976 states and 2891 transitions. [2024-11-17 08:54:00,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2891 transitions. [2024-11-17 08:54:00,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:00,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2891 transitions. [2024-11-17 08:54:00,231 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:54:00,233 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:54:00,233 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2891 transitions. [2024-11-17 08:54:00,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:00,237 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2891 transitions. [2024-11-17 08:54:00,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2891 transitions. [2024-11-17 08:54:00,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:54:00,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.4630566801619433) internal successors, (2891), 1975 states have internal predecessors, (2891), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2891 transitions. [2024-11-17 08:54:00,277 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2891 transitions. [2024-11-17 08:54:00,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:00,280 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2891 transitions. [2024-11-17 08:54:00,280 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:54:00,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2891 transitions. [2024-11-17 08:54:00,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:00,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:00,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:00,291 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,291 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,292 INFO L745 eck$LassoCheckResult]: Stem: 28692#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 28693#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28495#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28496#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29148#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 28497#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28498#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28962#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28703#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28704#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29230#L911 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 29231#L916 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 28833#L921 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28834#L926 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 28991#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28555#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28556#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28301#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 28302#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28864#L1258-1 assume !(0 == ~M_E~0); 28744#L1263-1 assume !(0 == ~T1_E~0); 28745#L1268-1 assume !(0 == ~T2_E~0); 29051#L1273-1 assume !(0 == ~T3_E~0); 29597#L1278-1 assume !(0 == ~T4_E~0); 29481#L1283-1 assume !(0 == ~T5_E~0); 29482#L1288-1 assume !(0 == ~T6_E~0); 29678#L1293-1 assume !(0 == ~T7_E~0); 29668#L1298-1 assume !(0 == ~T8_E~0); 29608#L1303-1 assume !(0 == ~T9_E~0); 28265#L1308-1 assume !(0 == ~T10_E~0); 28190#L1313-1 assume !(0 == ~T11_E~0); 28191#L1318-1 assume !(0 == ~T12_E~0); 28204#L1323-1 assume !(0 == ~T13_E~0); 28205#L1328-1 assume !(0 == ~E_1~0); 28385#L1333-1 assume !(0 == ~E_2~0); 29326#L1338-1 assume !(0 == ~E_3~0); 29327#L1343-1 assume !(0 == ~E_4~0); 29451#L1348-1 assume !(0 == ~E_5~0); 29703#L1353-1 assume !(0 == ~E_6~0); 29061#L1358-1 assume !(0 == ~E_7~0); 29062#L1363-1 assume !(0 == ~E_8~0); 29355#L1368-1 assume !(0 == ~E_9~0); 27989#L1373-1 assume !(0 == ~E_10~0); 27990#L1378-1 assume !(0 == ~E_11~0); 28337#L1383-1 assume !(0 == ~E_12~0); 28338#L1388-1 assume !(0 == ~E_13~0); 29443#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29574#L607-15 assume 1 == ~m_pc~0; 29628#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29412#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29316#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29317#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28293#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28041#L626-15 assume 1 == ~t1_pc~0; 28042#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28741#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28787#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29563#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 29390#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29391#L645-15 assume 1 == ~t2_pc~0; 29142#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28142#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28143#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29508#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 28843#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27813#L664-15 assume 1 == ~t3_pc~0; 27814#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29146#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28753#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28087#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 28088#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28516#L683-15 assume 1 == ~t4_pc~0; 29042#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29002#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29003#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29272#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28906#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28907#L702-15 assume 1 == ~t5_pc~0; 29475#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28850#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29525#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29576#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 28800#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27893#L721-15 assume 1 == ~t6_pc~0; 27894#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28121#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29635#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28709#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 28710#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27955#L740-15 assume 1 == ~t7_pc~0; 27956#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29402#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28818#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28819#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 29598#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29599#L759-15 assume 1 == ~t8_pc~0; 29479#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28507#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29559#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29312#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29313#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28061#L778-15 assume 1 == ~t9_pc~0; 28062#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28566#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28567#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28206#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 28207#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29275#L797-15 assume 1 == ~t10_pc~0; 28511#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28512#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29201#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28212#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 28213#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28797#L816-15 assume 1 == ~t11_pc~0; 28764#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28765#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29338#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28526#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 28527#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29349#L835-15 assume 1 == ~t12_pc~0; 29384#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 29627#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 29625#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28866#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 27839#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 27840#L854-15 assume 1 == ~t13_pc~0; 28698#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 28699#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 28168#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28169#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 28573#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28948#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 28949#L1406-1 assume !(1 == ~T1_E~0); 29202#L1411-1 assume !(1 == ~T2_E~0); 29203#L1416-1 assume !(1 == ~T3_E~0); 28873#L1421-1 assume !(1 == ~T4_E~0); 28422#L1426-1 assume !(1 == ~T5_E~0); 28423#L1431-1 assume !(1 == ~T6_E~0); 27904#L1436-1 assume !(1 == ~T7_E~0); 27905#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28734#L1446-1 assume !(1 == ~T9_E~0); 28735#L1451-1 assume !(1 == ~T10_E~0); 29449#L1456-1 assume !(1 == ~T11_E~0); 29088#L1461-1 assume !(1 == ~T12_E~0); 28645#L1466-1 assume !(1 == ~T13_E~0); 28646#L1471-1 assume !(1 == ~E_1~0); 29420#L1476-1 assume !(1 == ~E_2~0); 29421#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 29565#L1486-1 assume !(1 == ~E_4~0); 28285#L1491-1 assume !(1 == ~E_5~0); 27830#L1496-1 assume !(1 == ~E_6~0); 27831#L1501-1 assume !(1 == ~E_7~0); 28727#L1506-1 assume !(1 == ~E_8~0); 28728#L1511-1 assume !(1 == ~E_9~0); 28677#L1516-1 assume !(1 == ~E_10~0); 27786#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 27787#L1526-1 assume !(1 == ~E_12~0); 27829#L1531-1 assume !(1 == ~E_13~0); 28440#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 27892#L1892 [2024-11-17 08:54:00,293 INFO L747 eck$LassoCheckResult]: Loop: 27892#L1892 assume true; 27835#L1892-1 assume !false; 27836#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28452#L1041 assume true; 28621#L1041-1 assume !false; 28622#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29269#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28349#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29182#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27882#L1046 assume !(0 != eval_~tmp~0#1); 27884#L1049 assume true; 29459#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28240#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28241#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 28266#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28267#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28663#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28585#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28586#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28884#L1288 assume !(0 == ~T6_E~0); 28885#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28294#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28295#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29725#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29726#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28577#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28578#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29680#L1328 assume !(0 == ~E_1~0); 29681#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 28195#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 28196#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 28154#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 28155#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 28471#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 29124#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 28751#L1368 assume !(0 == ~E_9~0); 28752#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 28571#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 28572#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 29535#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 29512#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28157#L607-1 assume !(1 == ~m_pc~0); 28052#L617-1 is_master_triggered_~__retres1~0#1 := 0; 28053#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28080#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 28081#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 28375#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29489#L626-1 assume 1 == ~t1_pc~0; 29276#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29277#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29079#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 28528#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28529#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28004#L645-1 assume 1 == ~t2_pc~0; 28005#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28928#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27958#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27959#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29513#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28139#L664-1 assume !(1 == ~t3_pc~0); 28140#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 28269#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28270#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28868#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29243#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29342#L683-1 assume !(1 == ~t4_pc~0); 29314#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 29315#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29289#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28654#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 28655#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28828#L702-1 assume 1 == ~t5_pc~0; 28381#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28382#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28111#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28112#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29377#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29378#L721-1 assume 1 == ~t6_pc~0; 29526#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29527#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27760#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27761#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29516#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28837#L740-1 assume !(1 == ~t7_pc~0); 28838#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 29572#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27872#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27873#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29561#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29682#L759-1 assume 1 == ~t8_pc~0; 29683#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27980#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27981#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29502#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29236#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28689#L778-1 assume 1 == ~t9_pc~0; 28690#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29104#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29321#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28594#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28339#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27942#L797-1 assume 1 == ~t10_pc~0; 27943#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28480#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28481#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29615#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28441#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28442#L816-1 assume !(1 == ~t11_pc~0); 29352#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 27775#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27776#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 27826#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 27968#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 27969#L835-1 assume 1 == ~t12_pc~0; 29431#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 28345#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28346#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28050#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 28051#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 28201#L854-1 assume 1 == ~t13_pc~0; 28202#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29369#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 28780#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28781#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 29169#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29501#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 28652#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28653#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28986#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28370#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28223#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28224#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28872#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29125#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28450#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28451#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28310#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28311#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 29690#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29610#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 29249#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 29250#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 29684#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 29452#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 27940#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 27941#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 28413#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 28414#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 27782#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 27783#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 29641#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 28254#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 28255#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29466#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28037#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28038#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 28748#L1911 assume !(0 == start_simulation_~tmp~3#1); 28708#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28999#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28059#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28060#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 28009#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28010#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28283#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28284#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 27892#L1892 [2024-11-17 08:54:00,293 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,294 INFO L85 PathProgramCache]: Analyzing trace with hash 536391659, now seen corresponding path program 1 times [2024-11-17 08:54:00,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,294 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [641256789] [2024-11-17 08:54:00,295 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,353 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [641256789] [2024-11-17 08:54:00,353 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [641256789] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,356 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,356 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:00,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141750970] [2024-11-17 08:54:00,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,357 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:00,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,358 INFO L85 PathProgramCache]: Analyzing trace with hash -647526638, now seen corresponding path program 2 times [2024-11-17 08:54:00,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321808023] [2024-11-17 08:54:00,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321808023] [2024-11-17 08:54:00,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321808023] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:00,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476868359] [2024-11-17 08:54:00,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,461 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:00,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:00,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:00,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:00,461 INFO L87 Difference]: Start difference. First operand 1976 states and 2891 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:00,498 INFO L93 Difference]: Finished difference Result 1976 states and 2890 transitions. [2024-11-17 08:54:00,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2890 transitions. [2024-11-17 08:54:00,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:00,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2890 transitions. [2024-11-17 08:54:00,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:54:00,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:54:00,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2890 transitions. [2024-11-17 08:54:00,524 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:00,524 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2890 transitions. [2024-11-17 08:54:00,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2890 transitions. [2024-11-17 08:54:00,550 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:54:00,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.4625506072874495) internal successors, (2890), 1975 states have internal predecessors, (2890), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2890 transitions. [2024-11-17 08:54:00,559 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2890 transitions. [2024-11-17 08:54:00,559 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:00,560 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2890 transitions. [2024-11-17 08:54:00,560 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:54:00,560 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2890 transitions. [2024-11-17 08:54:00,566 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:00,567 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:00,567 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:00,569 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,569 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,570 INFO L745 eck$LassoCheckResult]: Stem: 32653#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 32654#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 32456#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32457#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33109#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 32458#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32459#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32923#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32664#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32665#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33191#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33192#L916 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 32794#L921 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 32795#L926 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 32952#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 32516#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32517#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32262#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 32263#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32825#L1258-1 assume !(0 == ~M_E~0); 32705#L1263-1 assume !(0 == ~T1_E~0); 32706#L1268-1 assume !(0 == ~T2_E~0); 33012#L1273-1 assume !(0 == ~T3_E~0); 33558#L1278-1 assume !(0 == ~T4_E~0); 33442#L1283-1 assume !(0 == ~T5_E~0); 33443#L1288-1 assume !(0 == ~T6_E~0); 33639#L1293-1 assume !(0 == ~T7_E~0); 33629#L1298-1 assume !(0 == ~T8_E~0); 33569#L1303-1 assume !(0 == ~T9_E~0); 32226#L1308-1 assume !(0 == ~T10_E~0); 32151#L1313-1 assume !(0 == ~T11_E~0); 32152#L1318-1 assume !(0 == ~T12_E~0); 32165#L1323-1 assume !(0 == ~T13_E~0); 32166#L1328-1 assume !(0 == ~E_1~0); 32346#L1333-1 assume !(0 == ~E_2~0); 33287#L1338-1 assume !(0 == ~E_3~0); 33288#L1343-1 assume !(0 == ~E_4~0); 33412#L1348-1 assume !(0 == ~E_5~0); 33664#L1353-1 assume !(0 == ~E_6~0); 33022#L1358-1 assume !(0 == ~E_7~0); 33023#L1363-1 assume !(0 == ~E_8~0); 33316#L1368-1 assume !(0 == ~E_9~0); 31950#L1373-1 assume !(0 == ~E_10~0); 31951#L1378-1 assume !(0 == ~E_11~0); 32298#L1383-1 assume !(0 == ~E_12~0); 32299#L1388-1 assume !(0 == ~E_13~0); 33404#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33535#L607-15 assume 1 == ~m_pc~0; 33589#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33373#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33277#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33278#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32254#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32002#L626-15 assume 1 == ~t1_pc~0; 32003#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32702#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32748#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33524#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 33351#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33352#L645-15 assume 1 == ~t2_pc~0; 33103#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32103#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32104#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33469#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 32804#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31774#L664-15 assume 1 == ~t3_pc~0; 31775#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33107#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32714#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32048#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 32049#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32477#L683-15 assume 1 == ~t4_pc~0; 33003#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32963#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32964#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33233#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32867#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32868#L702-15 assume 1 == ~t5_pc~0; 33436#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32811#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33486#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 33537#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 32761#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31854#L721-15 assume 1 == ~t6_pc~0; 31855#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32082#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33596#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32670#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 32671#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31916#L740-15 assume 1 == ~t7_pc~0; 31917#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33363#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32779#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32780#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 33559#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33560#L759-15 assume 1 == ~t8_pc~0; 33440#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32468#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33520#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33273#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33274#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32022#L778-15 assume 1 == ~t9_pc~0; 32023#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32527#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32528#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32167#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 32168#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 33236#L797-15 assume 1 == ~t10_pc~0; 32472#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32473#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 33162#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32173#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 32174#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32758#L816-15 assume 1 == ~t11_pc~0; 32725#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32726#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 33299#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32487#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 32488#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33310#L835-15 assume 1 == ~t12_pc~0; 33345#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 33588#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 33586#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32827#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 31800#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 31801#L854-15 assume 1 == ~t13_pc~0; 32659#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 32660#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 32129#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32130#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 32534#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32909#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 32910#L1406-1 assume !(1 == ~T1_E~0); 33163#L1411-1 assume !(1 == ~T2_E~0); 33164#L1416-1 assume !(1 == ~T3_E~0); 32834#L1421-1 assume !(1 == ~T4_E~0); 32383#L1426-1 assume !(1 == ~T5_E~0); 32384#L1431-1 assume !(1 == ~T6_E~0); 31865#L1436-1 assume !(1 == ~T7_E~0); 31866#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32695#L1446-1 assume !(1 == ~T9_E~0); 32696#L1451-1 assume !(1 == ~T10_E~0); 33410#L1456-1 assume !(1 == ~T11_E~0); 33049#L1461-1 assume !(1 == ~T12_E~0); 32606#L1466-1 assume !(1 == ~T13_E~0); 32607#L1471-1 assume !(1 == ~E_1~0); 33381#L1476-1 assume !(1 == ~E_2~0); 33382#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 33526#L1486-1 assume !(1 == ~E_4~0); 32246#L1491-1 assume !(1 == ~E_5~0); 31791#L1496-1 assume !(1 == ~E_6~0); 31792#L1501-1 assume !(1 == ~E_7~0); 32688#L1506-1 assume !(1 == ~E_8~0); 32689#L1511-1 assume !(1 == ~E_9~0); 32638#L1516-1 assume !(1 == ~E_10~0); 31747#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 31748#L1526-1 assume !(1 == ~E_12~0); 31790#L1531-1 assume !(1 == ~E_13~0); 32401#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 31853#L1892 [2024-11-17 08:54:00,570 INFO L747 eck$LassoCheckResult]: Loop: 31853#L1892 assume true; 31796#L1892-1 assume !false; 31797#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32413#L1041 assume true; 32582#L1041-1 assume !false; 32583#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33230#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32310#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33143#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31843#L1046 assume !(0 != eval_~tmp~0#1); 31845#L1049 assume true; 33420#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32201#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32202#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 32227#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32228#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32624#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32546#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32547#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32845#L1288 assume !(0 == ~T6_E~0); 32846#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32255#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32256#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33686#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33687#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32538#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32539#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33641#L1328 assume !(0 == ~E_1~0); 33642#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 32156#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 32157#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 32115#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 32116#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 32432#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 33085#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 32712#L1368 assume !(0 == ~E_9~0); 32713#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 32532#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 32533#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 33496#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 33473#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32118#L607-1 assume 1 == ~m_pc~0; 32119#L608-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 32014#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32041#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32042#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 32336#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33450#L626-1 assume 1 == ~t1_pc~0; 33237#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33238#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33040#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 32489#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32490#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31965#L645-1 assume 1 == ~t2_pc~0; 31966#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32889#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31919#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31920#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 33474#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32100#L664-1 assume !(1 == ~t3_pc~0); 32101#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 32230#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32231#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32829#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33204#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33303#L683-1 assume !(1 == ~t4_pc~0); 33275#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 33276#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33250#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32615#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32616#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32789#L702-1 assume 1 == ~t5_pc~0; 32342#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32343#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32072#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32073#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33338#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33339#L721-1 assume !(1 == ~t6_pc~0); 33489#L731-1 is_transmit6_triggered_~__retres1~6#1 := 0; 33488#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31721#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31722#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 33477#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32798#L740-1 assume 1 == ~t7_pc~0; 32800#L741-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 33533#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31833#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31834#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33522#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33643#L759-1 assume !(1 == ~t8_pc~0); 33568#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 31941#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31942#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33463#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33197#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32650#L778-1 assume 1 == ~t9_pc~0; 32651#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 33065#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33282#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32555#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32300#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31903#L797-1 assume 1 == ~t10_pc~0; 31904#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32441#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32442#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33576#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32402#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32403#L816-1 assume !(1 == ~t11_pc~0); 33313#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 31736#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31737#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31787#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31929#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31930#L835-1 assume 1 == ~t12_pc~0; 33392#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 32306#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32307#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32011#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 32012#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 32162#L854-1 assume 1 == ~t13_pc~0; 32163#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33330#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 32741#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32742#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 33130#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33462#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 32613#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32614#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32947#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32331#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32184#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32185#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32833#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33086#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32411#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32412#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32271#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32272#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 33651#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 33571#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 33210#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 33211#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 33645#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 33413#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 31901#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 31902#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 32374#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 32375#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 31743#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 31744#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 33602#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 32215#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 32216#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33427#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 31998#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 31999#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32709#L1911 assume !(0 == start_simulation_~tmp~3#1); 32669#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 32960#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32020#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32021#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 31970#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31971#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32244#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32245#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 31853#L1892 [2024-11-17 08:54:00,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,571 INFO L85 PathProgramCache]: Analyzing trace with hash 343460458, now seen corresponding path program 1 times [2024-11-17 08:54:00,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856135963] [2024-11-17 08:54:00,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,618 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856135963] [2024-11-17 08:54:00,618 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856135963] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:00,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810436593] [2024-11-17 08:54:00,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,619 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:00,620 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,620 INFO L85 PathProgramCache]: Analyzing trace with hash -489305262, now seen corresponding path program 1 times [2024-11-17 08:54:00,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306087109] [2024-11-17 08:54:00,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,697 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,698 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,698 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1306087109] [2024-11-17 08:54:00,698 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1306087109] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,698 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,698 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:00,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1935664624] [2024-11-17 08:54:00,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,699 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:00,699 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:00,699 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:00,699 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:00,700 INFO L87 Difference]: Start difference. First operand 1976 states and 2890 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:00,731 INFO L93 Difference]: Finished difference Result 1976 states and 2889 transitions. [2024-11-17 08:54:00,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2889 transitions. [2024-11-17 08:54:00,739 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:00,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2889 transitions. [2024-11-17 08:54:00,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:54:00,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:54:00,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2889 transitions. [2024-11-17 08:54:00,750 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:00,750 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2889 transitions. [2024-11-17 08:54:00,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2889 transitions. [2024-11-17 08:54:00,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:54:00,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.4620445344129556) internal successors, (2889), 1975 states have internal predecessors, (2889), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2889 transitions. [2024-11-17 08:54:00,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2889 transitions. [2024-11-17 08:54:00,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:00,807 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2889 transitions. [2024-11-17 08:54:00,807 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:54:00,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2889 transitions. [2024-11-17 08:54:00,813 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:00,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:00,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:00,815 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,815 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,816 INFO L745 eck$LassoCheckResult]: Stem: 36614#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 36615#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 36417#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36418#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37070#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 36419#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36420#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36884#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36625#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36626#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37152#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37153#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 36755#L921 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 36756#L926 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 36913#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 36477#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36478#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36223#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 36224#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 36786#L1258-1 assume !(0 == ~M_E~0); 36666#L1263-1 assume !(0 == ~T1_E~0); 36667#L1268-1 assume !(0 == ~T2_E~0); 36973#L1273-1 assume !(0 == ~T3_E~0); 37519#L1278-1 assume !(0 == ~T4_E~0); 37403#L1283-1 assume !(0 == ~T5_E~0); 37404#L1288-1 assume !(0 == ~T6_E~0); 37600#L1293-1 assume !(0 == ~T7_E~0); 37590#L1298-1 assume !(0 == ~T8_E~0); 37530#L1303-1 assume !(0 == ~T9_E~0); 36187#L1308-1 assume !(0 == ~T10_E~0); 36112#L1313-1 assume !(0 == ~T11_E~0); 36113#L1318-1 assume !(0 == ~T12_E~0); 36126#L1323-1 assume !(0 == ~T13_E~0); 36127#L1328-1 assume !(0 == ~E_1~0); 36307#L1333-1 assume !(0 == ~E_2~0); 37248#L1338-1 assume !(0 == ~E_3~0); 37249#L1343-1 assume !(0 == ~E_4~0); 37373#L1348-1 assume !(0 == ~E_5~0); 37625#L1353-1 assume !(0 == ~E_6~0); 36983#L1358-1 assume !(0 == ~E_7~0); 36984#L1363-1 assume !(0 == ~E_8~0); 37277#L1368-1 assume !(0 == ~E_9~0); 35911#L1373-1 assume !(0 == ~E_10~0); 35912#L1378-1 assume !(0 == ~E_11~0); 36259#L1383-1 assume !(0 == ~E_12~0); 36260#L1388-1 assume !(0 == ~E_13~0); 37365#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37496#L607-15 assume 1 == ~m_pc~0; 37550#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 37334#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37238#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 37239#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36215#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35963#L626-15 assume 1 == ~t1_pc~0; 35964#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36663#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36709#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37485#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 37312#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37313#L645-15 assume 1 == ~t2_pc~0; 37064#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36064#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36065#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37430#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 36765#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35735#L664-15 assume 1 == ~t3_pc~0; 35736#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37068#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36675#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36009#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 36010#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36438#L683-15 assume 1 == ~t4_pc~0; 36964#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 36924#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36925#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37194#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36828#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36829#L702-15 assume 1 == ~t5_pc~0; 37397#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36772#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37447#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37498#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 36722#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35815#L721-15 assume 1 == ~t6_pc~0; 35816#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 36043#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37557#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 36631#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 36632#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35877#L740-15 assume 1 == ~t7_pc~0; 35878#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37324#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36740#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36741#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 37520#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37521#L759-15 assume 1 == ~t8_pc~0; 37401#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 36429#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37481#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37234#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37235#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35983#L778-15 assume 1 == ~t9_pc~0; 35984#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36488#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36489#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36128#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 36129#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 37197#L797-15 assume 1 == ~t10_pc~0; 36433#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36434#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 37123#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36134#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 36135#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36719#L816-15 assume 1 == ~t11_pc~0; 36686#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 36687#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37260#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36448#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 36449#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37271#L835-15 assume 1 == ~t12_pc~0; 37306#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 37549#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 37547#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36788#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 35761#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 35762#L854-15 assume 1 == ~t13_pc~0; 36620#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 36621#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 36090#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36091#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 36495#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36870#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 36871#L1406-1 assume !(1 == ~T1_E~0); 37124#L1411-1 assume !(1 == ~T2_E~0); 37125#L1416-1 assume !(1 == ~T3_E~0); 36795#L1421-1 assume !(1 == ~T4_E~0); 36344#L1426-1 assume !(1 == ~T5_E~0); 36345#L1431-1 assume !(1 == ~T6_E~0); 35826#L1436-1 assume !(1 == ~T7_E~0); 35827#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36656#L1446-1 assume !(1 == ~T9_E~0); 36657#L1451-1 assume !(1 == ~T10_E~0); 37371#L1456-1 assume !(1 == ~T11_E~0); 37010#L1461-1 assume !(1 == ~T12_E~0); 36567#L1466-1 assume !(1 == ~T13_E~0); 36568#L1471-1 assume !(1 == ~E_1~0); 37342#L1476-1 assume !(1 == ~E_2~0); 37343#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 37487#L1486-1 assume !(1 == ~E_4~0); 36207#L1491-1 assume !(1 == ~E_5~0); 35752#L1496-1 assume !(1 == ~E_6~0); 35753#L1501-1 assume !(1 == ~E_7~0); 36649#L1506-1 assume !(1 == ~E_8~0); 36650#L1511-1 assume !(1 == ~E_9~0); 36599#L1516-1 assume !(1 == ~E_10~0); 35708#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 35709#L1526-1 assume !(1 == ~E_12~0); 35751#L1531-1 assume !(1 == ~E_13~0); 36362#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 35814#L1892 [2024-11-17 08:54:00,816 INFO L747 eck$LassoCheckResult]: Loop: 35814#L1892 assume true; 35757#L1892-1 assume !false; 35758#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 36374#L1041 assume true; 36543#L1041-1 assume !false; 36544#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37191#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36271#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37104#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35804#L1046 assume !(0 != eval_~tmp~0#1); 35806#L1049 assume true; 37381#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36162#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36163#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 36188#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36189#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36585#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36507#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36508#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36806#L1288 assume !(0 == ~T6_E~0); 36807#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36216#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36217#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37647#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37648#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 36499#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36500#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37602#L1328 assume !(0 == ~E_1~0); 37603#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 36117#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 36118#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 36076#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 36077#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 36393#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 37046#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 36673#L1368 assume !(0 == ~E_9~0); 36674#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 36493#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 36494#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 37457#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 37434#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36079#L607-1 assume 1 == ~m_pc~0; 36080#L608-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35975#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36002#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36003#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 36297#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37411#L626-1 assume !(1 == ~t1_pc~0); 37200#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 37199#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37001#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36450#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36451#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35926#L645-1 assume 1 == ~t2_pc~0; 35927#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36850#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35880#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35881#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37435#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36061#L664-1 assume !(1 == ~t3_pc~0); 36062#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 36191#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36192#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36790#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37165#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37264#L683-1 assume !(1 == ~t4_pc~0); 37236#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 37237#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37211#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36576#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36577#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36750#L702-1 assume !(1 == ~t5_pc~0); 36305#L712-1 is_transmit5_triggered_~__retres1~5#1 := 0; 36304#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36033#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36034#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37299#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37300#L721-1 assume 1 == ~t6_pc~0; 37448#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37449#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35682#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35683#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37438#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36759#L740-1 assume !(1 == ~t7_pc~0); 36760#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 37494#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35794#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35795#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37483#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 37604#L759-1 assume 1 == ~t8_pc~0; 37605#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35902#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35903#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37424#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37158#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 36611#L778-1 assume 1 == ~t9_pc~0; 36612#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37026#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 37243#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36516#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 36261#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35864#L797-1 assume 1 == ~t10_pc~0; 35865#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 36402#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36403#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37537#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 36363#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36364#L816-1 assume !(1 == ~t11_pc~0); 37274#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 35697#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35698#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35748#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35890#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35891#L835-1 assume 1 == ~t12_pc~0; 37353#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 36267#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36268#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35972#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 35973#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 36123#L854-1 assume 1 == ~t13_pc~0; 36124#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37291#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 36702#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36703#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 37091#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 37423#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 36574#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36575#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36908#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36292#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36145#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36146#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36794#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37047#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36372#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36373#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36232#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36233#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37612#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 37532#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 37171#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 37172#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 37606#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 37374#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 35862#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 35863#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 36335#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 36336#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 35704#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 35705#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 37563#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 36176#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 36177#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37388#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35959#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35960#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 36670#L1911 assume !(0 == start_simulation_~tmp~3#1); 36630#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 36921#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 35981#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 35982#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 35931#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35932#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 36205#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 36206#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 35814#L1892 [2024-11-17 08:54:00,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,817 INFO L85 PathProgramCache]: Analyzing trace with hash 475784203, now seen corresponding path program 1 times [2024-11-17 08:54:00,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683615929] [2024-11-17 08:54:00,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,862 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,862 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,862 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683615929] [2024-11-17 08:54:00,862 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683615929] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,863 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,863 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:00,863 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [730425999] [2024-11-17 08:54:00,863 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,863 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:00,864 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,864 INFO L85 PathProgramCache]: Analyzing trace with hash -1531909265, now seen corresponding path program 1 times [2024-11-17 08:54:00,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,864 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805800328] [2024-11-17 08:54:00,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805800328] [2024-11-17 08:54:00,969 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [805800328] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,969 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,969 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:00,969 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1656066572] [2024-11-17 08:54:00,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,970 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:00,970 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:00,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:00,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:00,971 INFO L87 Difference]: Start difference. First operand 1976 states and 2889 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:01,003 INFO L93 Difference]: Finished difference Result 1976 states and 2888 transitions. [2024-11-17 08:54:01,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2888 transitions. [2024-11-17 08:54:01,011 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:01,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2888 transitions. [2024-11-17 08:54:01,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:54:01,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:54:01,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2888 transitions. [2024-11-17 08:54:01,031 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:01,031 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2888 transitions. [2024-11-17 08:54:01,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2888 transitions. [2024-11-17 08:54:01,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:54:01,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.4615384615384615) internal successors, (2888), 1975 states have internal predecessors, (2888), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2888 transitions. [2024-11-17 08:54:01,071 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2888 transitions. [2024-11-17 08:54:01,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:01,072 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2888 transitions. [2024-11-17 08:54:01,072 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:54:01,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2888 transitions. [2024-11-17 08:54:01,078 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:01,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:01,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:01,081 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,081 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,081 INFO L745 eck$LassoCheckResult]: Stem: 40575#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 40576#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 40378#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40379#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41031#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 40380#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40381#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40845#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40586#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40587#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41113#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41114#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40716#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40717#L926 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 40874#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 40438#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 40439#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40184#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 40185#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40747#L1258-1 assume !(0 == ~M_E~0); 40627#L1263-1 assume !(0 == ~T1_E~0); 40628#L1268-1 assume !(0 == ~T2_E~0); 40934#L1273-1 assume !(0 == ~T3_E~0); 41480#L1278-1 assume !(0 == ~T4_E~0); 41364#L1283-1 assume !(0 == ~T5_E~0); 41365#L1288-1 assume !(0 == ~T6_E~0); 41561#L1293-1 assume !(0 == ~T7_E~0); 41551#L1298-1 assume !(0 == ~T8_E~0); 41491#L1303-1 assume !(0 == ~T9_E~0); 40148#L1308-1 assume !(0 == ~T10_E~0); 40073#L1313-1 assume !(0 == ~T11_E~0); 40074#L1318-1 assume !(0 == ~T12_E~0); 40087#L1323-1 assume !(0 == ~T13_E~0); 40088#L1328-1 assume !(0 == ~E_1~0); 40268#L1333-1 assume !(0 == ~E_2~0); 41209#L1338-1 assume !(0 == ~E_3~0); 41210#L1343-1 assume !(0 == ~E_4~0); 41334#L1348-1 assume !(0 == ~E_5~0); 41586#L1353-1 assume !(0 == ~E_6~0); 40944#L1358-1 assume !(0 == ~E_7~0); 40945#L1363-1 assume !(0 == ~E_8~0); 41238#L1368-1 assume !(0 == ~E_9~0); 39872#L1373-1 assume !(0 == ~E_10~0); 39873#L1378-1 assume !(0 == ~E_11~0); 40220#L1383-1 assume !(0 == ~E_12~0); 40221#L1388-1 assume !(0 == ~E_13~0); 41326#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41457#L607-15 assume 1 == ~m_pc~0; 41511#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 41295#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41199#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 41200#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40176#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39924#L626-15 assume 1 == ~t1_pc~0; 39925#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40624#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40670#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41446#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 41273#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41274#L645-15 assume 1 == ~t2_pc~0; 41025#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40025#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40026#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41391#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 40726#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39696#L664-15 assume 1 == ~t3_pc~0; 39697#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 41029#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40636#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39970#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 39971#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40399#L683-15 assume 1 == ~t4_pc~0; 40925#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40885#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40886#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41155#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40789#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40790#L702-15 assume 1 == ~t5_pc~0; 41358#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40733#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41408#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41459#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 40683#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39776#L721-15 assume 1 == ~t6_pc~0; 39777#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 40004#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41518#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 40592#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 40593#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39838#L740-15 assume 1 == ~t7_pc~0; 39839#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41285#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 40701#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40702#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 41481#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41482#L759-15 assume 1 == ~t8_pc~0; 41362#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 40390#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41442#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41195#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41196#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39944#L778-15 assume 1 == ~t9_pc~0; 39945#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40449#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40450#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40089#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 40090#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41158#L797-15 assume 1 == ~t10_pc~0; 40394#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40395#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41084#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 40095#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 40096#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40680#L816-15 assume 1 == ~t11_pc~0; 40647#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 40648#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41221#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 40409#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 40410#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41232#L835-15 assume 1 == ~t12_pc~0; 41267#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 41510#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 41508#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 40749#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39722#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39723#L854-15 assume 1 == ~t13_pc~0; 40581#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 40582#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 40051#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40052#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 40456#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40831#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 40832#L1406-1 assume !(1 == ~T1_E~0); 41085#L1411-1 assume !(1 == ~T2_E~0); 41086#L1416-1 assume !(1 == ~T3_E~0); 40756#L1421-1 assume !(1 == ~T4_E~0); 40305#L1426-1 assume !(1 == ~T5_E~0); 40306#L1431-1 assume !(1 == ~T6_E~0); 39787#L1436-1 assume !(1 == ~T7_E~0); 39788#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40617#L1446-1 assume !(1 == ~T9_E~0); 40618#L1451-1 assume !(1 == ~T10_E~0); 41332#L1456-1 assume !(1 == ~T11_E~0); 40971#L1461-1 assume !(1 == ~T12_E~0); 40528#L1466-1 assume !(1 == ~T13_E~0); 40529#L1471-1 assume !(1 == ~E_1~0); 41303#L1476-1 assume !(1 == ~E_2~0); 41304#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 41448#L1486-1 assume !(1 == ~E_4~0); 40168#L1491-1 assume !(1 == ~E_5~0); 39713#L1496-1 assume !(1 == ~E_6~0); 39714#L1501-1 assume !(1 == ~E_7~0); 40610#L1506-1 assume !(1 == ~E_8~0); 40611#L1511-1 assume !(1 == ~E_9~0); 40560#L1516-1 assume !(1 == ~E_10~0); 39669#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 39670#L1526-1 assume !(1 == ~E_12~0); 39712#L1531-1 assume !(1 == ~E_13~0); 40323#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 39775#L1892 [2024-11-17 08:54:01,082 INFO L747 eck$LassoCheckResult]: Loop: 39775#L1892 assume true; 39718#L1892-1 assume !false; 39719#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40335#L1041 assume true; 40504#L1041-1 assume !false; 40505#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41152#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40232#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41065#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39765#L1046 assume !(0 != eval_~tmp~0#1); 39767#L1049 assume true; 41342#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40123#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40124#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 40149#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40150#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40546#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40468#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 40469#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40767#L1288 assume !(0 == ~T6_E~0); 40768#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 40177#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40178#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41608#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41609#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 40460#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40461#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41563#L1328 assume !(0 == ~E_1~0); 41564#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 40078#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 40079#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 40037#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 40038#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 40354#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 41007#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 40634#L1368 assume !(0 == ~E_9~0); 40635#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 40454#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 40455#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 41418#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 41395#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40040#L607-1 assume 1 == ~m_pc~0; 40041#L608-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39936#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39963#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39964#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40258#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41372#L626-1 assume 1 == ~t1_pc~0; 41159#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41160#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40962#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40411#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 40412#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39887#L645-1 assume 1 == ~t2_pc~0; 39888#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 40811#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39841#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 39842#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41396#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40022#L664-1 assume !(1 == ~t3_pc~0); 40023#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 40152#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40153#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 40751#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41126#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41225#L683-1 assume !(1 == ~t4_pc~0); 41197#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 41198#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41172#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 40537#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 40538#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40711#L702-1 assume 1 == ~t5_pc~0; 40264#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 40265#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39994#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39995#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 41260#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41261#L721-1 assume 1 == ~t6_pc~0; 41409#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41410#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39643#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39644#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41399#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 40720#L740-1 assume !(1 == ~t7_pc~0); 40721#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 41455#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39755#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39756#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41444#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41565#L759-1 assume !(1 == ~t8_pc~0); 41490#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 39863#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39864#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41385#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41119#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 40572#L778-1 assume 1 == ~t9_pc~0; 40573#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40987#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41204#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40477#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40222#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39825#L797-1 assume 1 == ~t10_pc~0; 39826#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 40363#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 40364#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41498#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 40324#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40325#L816-1 assume !(1 == ~t11_pc~0); 41235#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 39658#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39659#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39709#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39851#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39852#L835-1 assume 1 == ~t12_pc~0; 41314#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40228#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40229#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39933#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39934#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 40084#L854-1 assume 1 == ~t13_pc~0; 40085#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41252#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 40663#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40664#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 41052#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41384#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 40535#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40536#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40869#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40253#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40106#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40107#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40755#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41008#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 40333#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40334#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40193#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40194#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41573#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 41493#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 41132#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 41133#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 41567#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 41335#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 39823#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 39824#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 40296#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 40297#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 39665#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 39666#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 41524#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 40137#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 40138#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41349#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39920#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39921#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 40631#L1911 assume !(0 == start_simulation_~tmp~3#1); 40591#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 40882#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 39942#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 39943#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 39892#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39893#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40166#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 40167#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 39775#L1892 [2024-11-17 08:54:01,082 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,083 INFO L85 PathProgramCache]: Analyzing trace with hash -489778614, now seen corresponding path program 1 times [2024-11-17 08:54:01,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093221461] [2024-11-17 08:54:01,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093221461] [2024-11-17 08:54:01,130 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093221461] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,130 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,130 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:01,130 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1168030466] [2024-11-17 08:54:01,130 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,131 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:01,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,131 INFO L85 PathProgramCache]: Analyzing trace with hash -884501230, now seen corresponding path program 1 times [2024-11-17 08:54:01,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822107316] [2024-11-17 08:54:01,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,210 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822107316] [2024-11-17 08:54:01,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [822107316] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,211 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,211 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:01,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1103051899] [2024-11-17 08:54:01,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,211 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:01,212 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:01,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:01,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:01,212 INFO L87 Difference]: Start difference. First operand 1976 states and 2888 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:01,245 INFO L93 Difference]: Finished difference Result 1976 states and 2887 transitions. [2024-11-17 08:54:01,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2887 transitions. [2024-11-17 08:54:01,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:01,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2887 transitions. [2024-11-17 08:54:01,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:54:01,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:54:01,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2887 transitions. [2024-11-17 08:54:01,264 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:01,264 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2887 transitions. [2024-11-17 08:54:01,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2887 transitions. [2024-11-17 08:54:01,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:54:01,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.4610323886639676) internal successors, (2887), 1975 states have internal predecessors, (2887), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2887 transitions. [2024-11-17 08:54:01,298 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2887 transitions. [2024-11-17 08:54:01,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:01,299 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2887 transitions. [2024-11-17 08:54:01,299 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:54:01,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2887 transitions. [2024-11-17 08:54:01,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:01,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:01,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:01,308 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,309 INFO L745 eck$LassoCheckResult]: Stem: 44536#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 44537#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 44339#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 44340#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44992#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 44341#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44342#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44806#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44547#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44548#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45074#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45075#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44677#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44678#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44835#L931 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 44399#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 44400#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 44145#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 44146#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44708#L1258-1 assume !(0 == ~M_E~0); 44588#L1263-1 assume !(0 == ~T1_E~0); 44589#L1268-1 assume !(0 == ~T2_E~0); 44895#L1273-1 assume !(0 == ~T3_E~0); 45441#L1278-1 assume !(0 == ~T4_E~0); 45325#L1283-1 assume !(0 == ~T5_E~0); 45326#L1288-1 assume !(0 == ~T6_E~0); 45522#L1293-1 assume !(0 == ~T7_E~0); 45512#L1298-1 assume !(0 == ~T8_E~0); 45452#L1303-1 assume !(0 == ~T9_E~0); 44109#L1308-1 assume !(0 == ~T10_E~0); 44034#L1313-1 assume !(0 == ~T11_E~0); 44035#L1318-1 assume !(0 == ~T12_E~0); 44048#L1323-1 assume !(0 == ~T13_E~0); 44049#L1328-1 assume !(0 == ~E_1~0); 44229#L1333-1 assume !(0 == ~E_2~0); 45170#L1338-1 assume !(0 == ~E_3~0); 45171#L1343-1 assume !(0 == ~E_4~0); 45295#L1348-1 assume !(0 == ~E_5~0); 45547#L1353-1 assume !(0 == ~E_6~0); 44905#L1358-1 assume !(0 == ~E_7~0); 44906#L1363-1 assume !(0 == ~E_8~0); 45199#L1368-1 assume !(0 == ~E_9~0); 43833#L1373-1 assume !(0 == ~E_10~0); 43834#L1378-1 assume !(0 == ~E_11~0); 44181#L1383-1 assume !(0 == ~E_12~0); 44182#L1388-1 assume !(0 == ~E_13~0); 45287#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45418#L607-15 assume 1 == ~m_pc~0; 45472#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 45256#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45160#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 45161#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44137#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43885#L626-15 assume 1 == ~t1_pc~0; 43886#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 44585#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44631#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45407#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 45234#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45235#L645-15 assume 1 == ~t2_pc~0; 44986#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43986#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43987#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45352#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 44687#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43657#L664-15 assume 1 == ~t3_pc~0; 43658#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44990#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44597#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43931#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 43932#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44360#L683-15 assume 1 == ~t4_pc~0; 44886#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 44846#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44847#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45116#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44750#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44751#L702-15 assume 1 == ~t5_pc~0; 45319#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44694#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45369#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45420#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 44644#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43737#L721-15 assume 1 == ~t6_pc~0; 43738#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43965#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45479#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 44553#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 44554#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43799#L740-15 assume 1 == ~t7_pc~0; 43800#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45246#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 44662#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 44663#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 45442#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45443#L759-15 assume 1 == ~t8_pc~0; 45323#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 44351#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45403#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45156#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45157#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43905#L778-15 assume 1 == ~t9_pc~0; 43906#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44410#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 44411#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44050#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 44051#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45119#L797-15 assume 1 == ~t10_pc~0; 44355#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44356#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45045#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 44056#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 44057#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44641#L816-15 assume 1 == ~t11_pc~0; 44608#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 44609#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45182#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 44370#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 44371#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45193#L835-15 assume 1 == ~t12_pc~0; 45228#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 45471#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 45469#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 44710#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43683#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43684#L854-15 assume 1 == ~t13_pc~0; 44542#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 44543#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 44012#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44013#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 44417#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44792#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 44793#L1406-1 assume !(1 == ~T1_E~0); 45046#L1411-1 assume !(1 == ~T2_E~0); 45047#L1416-1 assume !(1 == ~T3_E~0); 44717#L1421-1 assume !(1 == ~T4_E~0); 44266#L1426-1 assume !(1 == ~T5_E~0); 44267#L1431-1 assume !(1 == ~T6_E~0); 43748#L1436-1 assume !(1 == ~T7_E~0); 43749#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44578#L1446-1 assume !(1 == ~T9_E~0); 44579#L1451-1 assume !(1 == ~T10_E~0); 45293#L1456-1 assume !(1 == ~T11_E~0); 44932#L1461-1 assume !(1 == ~T12_E~0); 44489#L1466-1 assume !(1 == ~T13_E~0); 44490#L1471-1 assume !(1 == ~E_1~0); 45264#L1476-1 assume !(1 == ~E_2~0); 45265#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 45409#L1486-1 assume !(1 == ~E_4~0); 44129#L1491-1 assume !(1 == ~E_5~0); 43674#L1496-1 assume !(1 == ~E_6~0); 43675#L1501-1 assume !(1 == ~E_7~0); 44571#L1506-1 assume !(1 == ~E_8~0); 44572#L1511-1 assume !(1 == ~E_9~0); 44521#L1516-1 assume !(1 == ~E_10~0); 43630#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 43631#L1526-1 assume !(1 == ~E_12~0); 43673#L1531-1 assume !(1 == ~E_13~0); 44284#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 43736#L1892 [2024-11-17 08:54:01,309 INFO L747 eck$LassoCheckResult]: Loop: 43736#L1892 assume true; 43679#L1892-1 assume !false; 43680#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 44296#L1041 assume true; 44465#L1041-1 assume !false; 44466#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45113#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44193#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45026#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43726#L1046 assume !(0 != eval_~tmp~0#1); 43728#L1049 assume true; 45303#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 44084#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 44085#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 44110#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44111#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44507#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44429#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44430#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44728#L1288 assume !(0 == ~T6_E~0); 44729#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 44138#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44139#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45569#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45570#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 44421#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44422#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45524#L1328 assume !(0 == ~E_1~0); 45525#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 44039#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 44040#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 43998#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 43999#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 44315#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 44968#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 44595#L1368 assume !(0 == ~E_9~0); 44596#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 44415#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 44416#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 45379#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 45356#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44001#L607-1 assume 1 == ~m_pc~0; 44002#L608-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43897#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43924#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 43925#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44219#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45333#L626-1 assume 1 == ~t1_pc~0; 45120#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45121#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44923#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44372#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44373#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43848#L645-1 assume 1 == ~t2_pc~0; 43849#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 44772#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43802#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 43803#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45357#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43983#L664-1 assume !(1 == ~t3_pc~0); 43984#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 44113#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44114#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44712#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45087#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45186#L683-1 assume !(1 == ~t4_pc~0); 45158#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 45159#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45133#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44498#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44499#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44672#L702-1 assume 1 == ~t5_pc~0; 44225#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44226#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43955#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43956#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 45221#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45222#L721-1 assume 1 == ~t6_pc~0; 45370#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45371#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43604#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43605#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 45360#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 44681#L740-1 assume !(1 == ~t7_pc~0); 44682#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 45416#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 43716#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43717#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45405#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45526#L759-1 assume 1 == ~t8_pc~0; 45527#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43824#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43825#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45346#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45080#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 44533#L778-1 assume 1 == ~t9_pc~0; 44534#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 44948#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45165#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44438#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44183#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 43786#L797-1 assume 1 == ~t10_pc~0; 43787#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 44324#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44325#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45459#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 44285#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44286#L816-1 assume 1 == ~t11_pc~0; 45297#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43619#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 43620#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43670#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43812#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43813#L835-1 assume 1 == ~t12_pc~0; 45275#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44189#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44190#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43894#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43895#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 44045#L854-1 assume 1 == ~t13_pc~0; 44046#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45213#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 44624#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44625#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 45013#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45345#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 44496#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44497#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44830#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44214#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44067#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44068#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44716#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 44969#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44294#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44295#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44154#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44155#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45534#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 45454#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 45093#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 45094#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 45528#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 45296#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 43784#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 43785#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 44257#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 44258#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 43626#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 43627#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 45485#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 44098#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 44099#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45310#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43881#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43882#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 44592#L1911 assume !(0 == start_simulation_~tmp~3#1); 44552#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 44843#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 43903#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 43904#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 43853#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43854#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 44127#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 44128#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 43736#L1892 [2024-11-17 08:54:01,310 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,310 INFO L85 PathProgramCache]: Analyzing trace with hash 171810859, now seen corresponding path program 1 times [2024-11-17 08:54:01,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,312 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668190344] [2024-11-17 08:54:01,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,312 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,380 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668190344] [2024-11-17 08:54:01,381 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1668190344] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,381 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,381 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:01,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597497741] [2024-11-17 08:54:01,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,382 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:01,382 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,382 INFO L85 PathProgramCache]: Analyzing trace with hash -1362642920, now seen corresponding path program 2 times [2024-11-17 08:54:01,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,382 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435723896] [2024-11-17 08:54:01,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,464 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,465 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435723896] [2024-11-17 08:54:01,465 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435723896] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,465 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,465 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:01,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [936992387] [2024-11-17 08:54:01,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,466 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:01,466 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:01,466 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:01,466 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:01,466 INFO L87 Difference]: Start difference. First operand 1976 states and 2887 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:01,499 INFO L93 Difference]: Finished difference Result 1976 states and 2886 transitions. [2024-11-17 08:54:01,499 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2886 transitions. [2024-11-17 08:54:01,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:01,512 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2886 transitions. [2024-11-17 08:54:01,512 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:54:01,514 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:54:01,514 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2886 transitions. [2024-11-17 08:54:01,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:01,517 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2886 transitions. [2024-11-17 08:54:01,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2886 transitions. [2024-11-17 08:54:01,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:54:01,551 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.4605263157894737) internal successors, (2886), 1975 states have internal predecessors, (2886), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2886 transitions. [2024-11-17 08:54:01,556 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2886 transitions. [2024-11-17 08:54:01,557 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:01,557 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2886 transitions. [2024-11-17 08:54:01,557 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:54:01,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2886 transitions. [2024-11-17 08:54:01,566 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:01,566 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:01,566 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:01,568 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,569 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,569 INFO L745 eck$LassoCheckResult]: Stem: 48497#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 48498#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 48300#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48301#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48953#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 48302#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48303#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48767#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48508#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48509#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49035#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49036#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48638#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48639#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48796#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 48360#L936 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 48361#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 48106#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 48107#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48669#L1258-1 assume !(0 == ~M_E~0); 48549#L1263-1 assume !(0 == ~T1_E~0); 48550#L1268-1 assume !(0 == ~T2_E~0); 48856#L1273-1 assume !(0 == ~T3_E~0); 49402#L1278-1 assume !(0 == ~T4_E~0); 49286#L1283-1 assume !(0 == ~T5_E~0); 49287#L1288-1 assume !(0 == ~T6_E~0); 49483#L1293-1 assume !(0 == ~T7_E~0); 49473#L1298-1 assume !(0 == ~T8_E~0); 49413#L1303-1 assume !(0 == ~T9_E~0); 48070#L1308-1 assume !(0 == ~T10_E~0); 47995#L1313-1 assume !(0 == ~T11_E~0); 47996#L1318-1 assume !(0 == ~T12_E~0); 48009#L1323-1 assume !(0 == ~T13_E~0); 48010#L1328-1 assume !(0 == ~E_1~0); 48190#L1333-1 assume !(0 == ~E_2~0); 49131#L1338-1 assume !(0 == ~E_3~0); 49132#L1343-1 assume !(0 == ~E_4~0); 49256#L1348-1 assume !(0 == ~E_5~0); 49508#L1353-1 assume !(0 == ~E_6~0); 48866#L1358-1 assume !(0 == ~E_7~0); 48867#L1363-1 assume !(0 == ~E_8~0); 49160#L1368-1 assume !(0 == ~E_9~0); 47794#L1373-1 assume !(0 == ~E_10~0); 47795#L1378-1 assume !(0 == ~E_11~0); 48142#L1383-1 assume !(0 == ~E_12~0); 48143#L1388-1 assume !(0 == ~E_13~0); 49248#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49379#L607-15 assume 1 == ~m_pc~0; 49433#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49217#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49121#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49122#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48098#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47846#L626-15 assume 1 == ~t1_pc~0; 47847#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48546#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48592#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49368#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 49195#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49196#L645-15 assume 1 == ~t2_pc~0; 48947#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47947#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47948#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49313#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 48648#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47618#L664-15 assume 1 == ~t3_pc~0; 47619#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48951#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48558#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47892#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 47893#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48321#L683-15 assume 1 == ~t4_pc~0; 48847#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48807#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48808#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49077#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48711#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48712#L702-15 assume 1 == ~t5_pc~0; 49280#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48655#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49330#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49381#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 48605#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47698#L721-15 assume 1 == ~t6_pc~0; 47699#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47926#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49440#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48514#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 48515#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47760#L740-15 assume 1 == ~t7_pc~0; 47761#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49207#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48623#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48624#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 49403#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49404#L759-15 assume 1 == ~t8_pc~0; 49284#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48312#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49364#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49117#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49118#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47866#L778-15 assume 1 == ~t9_pc~0; 47867#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 48371#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48372#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48011#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 48012#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49080#L797-15 assume 1 == ~t10_pc~0; 48316#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48317#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49006#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48017#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 48018#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48602#L816-15 assume 1 == ~t11_pc~0; 48569#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 48570#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49143#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 48331#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 48332#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49154#L835-15 assume 1 == ~t12_pc~0; 49189#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 49432#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 49430#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48671#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47644#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47645#L854-15 assume 1 == ~t13_pc~0; 48503#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 48504#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 47973#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47974#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 48378#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48753#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 48754#L1406-1 assume !(1 == ~T1_E~0); 49007#L1411-1 assume !(1 == ~T2_E~0); 49008#L1416-1 assume !(1 == ~T3_E~0); 48678#L1421-1 assume !(1 == ~T4_E~0); 48227#L1426-1 assume !(1 == ~T5_E~0); 48228#L1431-1 assume !(1 == ~T6_E~0); 47709#L1436-1 assume !(1 == ~T7_E~0); 47710#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48539#L1446-1 assume !(1 == ~T9_E~0); 48540#L1451-1 assume !(1 == ~T10_E~0); 49254#L1456-1 assume !(1 == ~T11_E~0); 48893#L1461-1 assume !(1 == ~T12_E~0); 48450#L1466-1 assume !(1 == ~T13_E~0); 48451#L1471-1 assume !(1 == ~E_1~0); 49225#L1476-1 assume !(1 == ~E_2~0); 49226#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 49370#L1486-1 assume !(1 == ~E_4~0); 48090#L1491-1 assume !(1 == ~E_5~0); 47635#L1496-1 assume !(1 == ~E_6~0); 47636#L1501-1 assume !(1 == ~E_7~0); 48532#L1506-1 assume !(1 == ~E_8~0); 48533#L1511-1 assume !(1 == ~E_9~0); 48482#L1516-1 assume !(1 == ~E_10~0); 47591#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 47592#L1526-1 assume !(1 == ~E_12~0); 47634#L1531-1 assume !(1 == ~E_13~0); 48245#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 47697#L1892 [2024-11-17 08:54:01,570 INFO L747 eck$LassoCheckResult]: Loop: 47697#L1892 assume true; 47640#L1892-1 assume !false; 47641#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48257#L1041 assume true; 48426#L1041-1 assume !false; 48427#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49074#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48154#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48987#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 47687#L1046 assume !(0 != eval_~tmp~0#1); 47689#L1049 assume true; 49264#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48045#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48046#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 48071#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48072#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48468#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48390#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48391#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48689#L1288 assume !(0 == ~T6_E~0); 48690#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 48099#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48100#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49530#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49531#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 48382#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 48383#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49485#L1328 assume !(0 == ~E_1~0); 49486#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 48000#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 48001#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 47959#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 47960#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 48276#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 48929#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 48556#L1368 assume !(0 == ~E_9~0); 48557#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 48376#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 48377#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 49340#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 49317#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47962#L607-1 assume !(1 == ~m_pc~0); 47857#L617-1 is_master_triggered_~__retres1~0#1 := 0; 47858#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47885#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47886#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48180#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49294#L626-1 assume 1 == ~t1_pc~0; 49081#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49082#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48884#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48333#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 48334#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47809#L645-1 assume 1 == ~t2_pc~0; 47810#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48733#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47763#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47764#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49318#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47944#L664-1 assume !(1 == ~t3_pc~0); 47945#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 48074#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48075#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48673#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49048#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49147#L683-1 assume 1 == ~t4_pc~0; 49457#L684-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 49120#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49094#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48459#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 48460#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48633#L702-1 assume 1 == ~t5_pc~0; 48186#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 48187#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47916#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47917#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49182#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49183#L721-1 assume 1 == ~t6_pc~0; 49331#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49332#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47565#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47566#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49321#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48642#L740-1 assume !(1 == ~t7_pc~0); 48643#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 49377#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47677#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47678#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49366#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49487#L759-1 assume 1 == ~t8_pc~0; 49488#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47785#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47786#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49307#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49041#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48494#L778-1 assume !(1 == ~t9_pc~0); 48496#L788-1 is_transmit9_triggered_~__retres1~9#1 := 0; 48909#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49126#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48399#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 48144#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47747#L797-1 assume 1 == ~t10_pc~0; 47748#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 48285#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48286#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49420#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 48246#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48247#L816-1 assume !(1 == ~t11_pc~0); 49157#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 47580#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47581#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47631#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47773#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 47774#L835-1 assume 1 == ~t12_pc~0; 49236#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48150#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48151#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47855#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47856#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 48006#L854-1 assume 1 == ~t13_pc~0; 48007#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49174#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 48585#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48586#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 48974#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49306#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 48457#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 48458#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48791#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48175#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48028#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48029#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48677#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 48930#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 48255#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48256#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48115#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48116#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49495#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 49415#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 49054#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 49055#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 49489#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 49257#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 47745#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 47746#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 48218#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 48219#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 47587#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 47588#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 49446#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 48059#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 48060#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49271#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47842#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47843#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 48553#L1911 assume !(0 == start_simulation_~tmp~3#1); 48513#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 48804#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 47864#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 47865#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47814#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47815#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48088#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 48089#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 47697#L1892 [2024-11-17 08:54:01,570 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,571 INFO L85 PathProgramCache]: Analyzing trace with hash -776678870, now seen corresponding path program 1 times [2024-11-17 08:54:01,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356917372] [2024-11-17 08:54:01,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,617 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,617 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1356917372] [2024-11-17 08:54:01,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1356917372] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,618 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,618 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:01,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1321513076] [2024-11-17 08:54:01,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,619 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:01,620 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,620 INFO L85 PathProgramCache]: Analyzing trace with hash -1265862702, now seen corresponding path program 1 times [2024-11-17 08:54:01,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101541590] [2024-11-17 08:54:01,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,621 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1101541590] [2024-11-17 08:54:01,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1101541590] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,707 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,707 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:01,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [218649256] [2024-11-17 08:54:01,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,708 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:01,708 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:01,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:01,709 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:01,710 INFO L87 Difference]: Start difference. First operand 1976 states and 2886 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:01,746 INFO L93 Difference]: Finished difference Result 1976 states and 2885 transitions. [2024-11-17 08:54:01,746 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2885 transitions. [2024-11-17 08:54:01,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:01,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2885 transitions. [2024-11-17 08:54:01,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:54:01,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:54:01,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2885 transitions. [2024-11-17 08:54:01,776 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:01,776 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2885 transitions. [2024-11-17 08:54:01,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2885 transitions. [2024-11-17 08:54:01,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:54:01,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.4600202429149798) internal successors, (2885), 1975 states have internal predecessors, (2885), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2885 transitions. [2024-11-17 08:54:01,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2885 transitions. [2024-11-17 08:54:01,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:01,810 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2885 transitions. [2024-11-17 08:54:01,810 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:54:01,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2885 transitions. [2024-11-17 08:54:01,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:01,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:01,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:01,821 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,822 INFO L745 eck$LassoCheckResult]: Stem: 52458#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 52459#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 52261#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52262#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52914#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 52263#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52264#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52728#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52469#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52470#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52996#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52997#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52599#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 52600#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52757#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 52321#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 52322#L941 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 52067#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 52068#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52630#L1258-1 assume !(0 == ~M_E~0); 52510#L1263-1 assume !(0 == ~T1_E~0); 52511#L1268-1 assume !(0 == ~T2_E~0); 52817#L1273-1 assume !(0 == ~T3_E~0); 53363#L1278-1 assume !(0 == ~T4_E~0); 53247#L1283-1 assume !(0 == ~T5_E~0); 53248#L1288-1 assume !(0 == ~T6_E~0); 53444#L1293-1 assume !(0 == ~T7_E~0); 53434#L1298-1 assume !(0 == ~T8_E~0); 53374#L1303-1 assume !(0 == ~T9_E~0); 52031#L1308-1 assume !(0 == ~T10_E~0); 51956#L1313-1 assume !(0 == ~T11_E~0); 51957#L1318-1 assume !(0 == ~T12_E~0); 51970#L1323-1 assume !(0 == ~T13_E~0); 51971#L1328-1 assume !(0 == ~E_1~0); 52151#L1333-1 assume !(0 == ~E_2~0); 53092#L1338-1 assume !(0 == ~E_3~0); 53093#L1343-1 assume !(0 == ~E_4~0); 53217#L1348-1 assume !(0 == ~E_5~0); 53469#L1353-1 assume !(0 == ~E_6~0); 52827#L1358-1 assume !(0 == ~E_7~0); 52828#L1363-1 assume !(0 == ~E_8~0); 53121#L1368-1 assume !(0 == ~E_9~0); 51755#L1373-1 assume !(0 == ~E_10~0); 51756#L1378-1 assume !(0 == ~E_11~0); 52103#L1383-1 assume !(0 == ~E_12~0); 52104#L1388-1 assume !(0 == ~E_13~0); 53209#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53340#L607-15 assume 1 == ~m_pc~0; 53394#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 53178#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53082#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53083#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52059#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51807#L626-15 assume 1 == ~t1_pc~0; 51808#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52507#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52553#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53329#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 53156#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53157#L645-15 assume 1 == ~t2_pc~0; 52908#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 51908#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51909#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53274#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 52609#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51579#L664-15 assume 1 == ~t3_pc~0; 51580#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52912#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52519#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 51853#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 51854#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52282#L683-15 assume 1 == ~t4_pc~0; 52808#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 52768#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52769#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 53038#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52672#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52673#L702-15 assume 1 == ~t5_pc~0; 53241#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 52616#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53291#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53342#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 52566#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51659#L721-15 assume 1 == ~t6_pc~0; 51660#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 51887#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53401#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52475#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 52476#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51721#L740-15 assume 1 == ~t7_pc~0; 51722#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 53168#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 52584#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52585#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 53364#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53365#L759-15 assume 1 == ~t8_pc~0; 53245#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52273#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53325#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53078#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53079#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51827#L778-15 assume 1 == ~t9_pc~0; 51828#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52332#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52333#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51972#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 51973#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53041#L797-15 assume 1 == ~t10_pc~0; 52277#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52278#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52967#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 51978#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 51979#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52563#L816-15 assume 1 == ~t11_pc~0; 52530#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 52531#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53104#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52292#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 52293#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53115#L835-15 assume 1 == ~t12_pc~0; 53150#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 53393#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53391#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52632#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51605#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51606#L854-15 assume 1 == ~t13_pc~0; 52464#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 52465#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 51934#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51935#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 52339#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52714#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 52715#L1406-1 assume !(1 == ~T1_E~0); 52968#L1411-1 assume !(1 == ~T2_E~0); 52969#L1416-1 assume !(1 == ~T3_E~0); 52639#L1421-1 assume !(1 == ~T4_E~0); 52188#L1426-1 assume !(1 == ~T5_E~0); 52189#L1431-1 assume !(1 == ~T6_E~0); 51670#L1436-1 assume !(1 == ~T7_E~0); 51671#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52500#L1446-1 assume !(1 == ~T9_E~0); 52501#L1451-1 assume !(1 == ~T10_E~0); 53215#L1456-1 assume !(1 == ~T11_E~0); 52854#L1461-1 assume !(1 == ~T12_E~0); 52411#L1466-1 assume !(1 == ~T13_E~0); 52412#L1471-1 assume !(1 == ~E_1~0); 53186#L1476-1 assume !(1 == ~E_2~0); 53187#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 53331#L1486-1 assume !(1 == ~E_4~0); 52051#L1491-1 assume !(1 == ~E_5~0); 51596#L1496-1 assume !(1 == ~E_6~0); 51597#L1501-1 assume !(1 == ~E_7~0); 52493#L1506-1 assume !(1 == ~E_8~0); 52494#L1511-1 assume !(1 == ~E_9~0); 52443#L1516-1 assume !(1 == ~E_10~0); 51552#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 51553#L1526-1 assume !(1 == ~E_12~0); 51595#L1531-1 assume !(1 == ~E_13~0); 52206#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 51658#L1892 [2024-11-17 08:54:01,822 INFO L747 eck$LassoCheckResult]: Loop: 51658#L1892 assume true; 51601#L1892-1 assume !false; 51602#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 52218#L1041 assume true; 52387#L1041-1 assume !false; 52388#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53035#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52115#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 52948#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 51648#L1046 assume !(0 != eval_~tmp~0#1); 51650#L1049 assume true; 53225#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 52006#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 52007#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 52032#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52033#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 52429#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 52351#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52352#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52650#L1288 assume !(0 == ~T6_E~0); 52651#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 52060#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52061#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 53491#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53492#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 52343#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52344#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53446#L1328 assume !(0 == ~E_1~0); 53447#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 51961#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 51962#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 51920#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 51921#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 52237#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 52890#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 52517#L1368 assume !(0 == ~E_9~0); 52518#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 52337#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 52338#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 53301#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 53278#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51923#L607-1 assume 1 == ~m_pc~0; 51924#L608-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51819#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51846#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 51847#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52141#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53255#L626-1 assume 1 == ~t1_pc~0; 53042#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53043#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52845#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52294#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 52295#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 51770#L645-1 assume 1 == ~t2_pc~0; 51771#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52694#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 51724#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51725#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 53279#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51905#L664-1 assume !(1 == ~t3_pc~0); 51906#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 52035#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52036#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52634#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 53009#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53108#L683-1 assume !(1 == ~t4_pc~0); 53080#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 53081#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53055#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52420#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52421#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52594#L702-1 assume 1 == ~t5_pc~0; 52147#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 52148#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51877#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 51878#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 53143#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53144#L721-1 assume 1 == ~t6_pc~0; 53292#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53293#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51526#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51527#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 53282#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 52603#L740-1 assume !(1 == ~t7_pc~0); 52604#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 53338#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51638#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51639#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53327#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53448#L759-1 assume 1 == ~t8_pc~0; 53449#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 51746#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51747#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53268#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53002#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52455#L778-1 assume 1 == ~t9_pc~0; 52456#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 52870#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53087#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52360#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52105#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 51708#L797-1 assume 1 == ~t10_pc~0; 51709#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 52246#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52247#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53381#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52207#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52208#L816-1 assume 1 == ~t11_pc~0; 53219#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51541#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51542#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51592#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 51734#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 51735#L835-1 assume 1 == ~t12_pc~0; 53197#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52111#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52112#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51816#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51817#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51967#L854-1 assume 1 == ~t13_pc~0; 51968#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53135#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 52546#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52547#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 52935#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53267#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 52418#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 52419#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52752#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 52136#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51989#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 51990#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 52638#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 52891#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52216#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52217#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52076#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52077#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53456#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 53376#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 53015#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 53016#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 53450#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 53218#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 51706#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 51707#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 52179#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 52180#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 51548#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 51549#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 53407#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 52020#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 52021#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53232#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51803#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51804#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 52514#L1911 assume !(0 == start_simulation_~tmp~3#1); 52474#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 52765#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 51825#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 51826#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 51775#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51776#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 52049#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 52050#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 51658#L1892 [2024-11-17 08:54:01,823 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,823 INFO L85 PathProgramCache]: Analyzing trace with hash -945822645, now seen corresponding path program 1 times [2024-11-17 08:54:01,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277212351] [2024-11-17 08:54:01,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,878 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277212351] [2024-11-17 08:54:01,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277212351] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,879 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:01,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [626154455] [2024-11-17 08:54:01,879 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,880 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:01,880 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,880 INFO L85 PathProgramCache]: Analyzing trace with hash -1362642920, now seen corresponding path program 3 times [2024-11-17 08:54:01,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002790155] [2024-11-17 08:54:01,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,956 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,956 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2002790155] [2024-11-17 08:54:01,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2002790155] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,956 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:01,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [959548169] [2024-11-17 08:54:01,957 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,957 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:01,957 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:01,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:01,958 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:01,958 INFO L87 Difference]: Start difference. First operand 1976 states and 2885 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:02,015 INFO L93 Difference]: Finished difference Result 1976 states and 2884 transitions. [2024-11-17 08:54:02,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2884 transitions. [2024-11-17 08:54:02,022 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:02,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2884 transitions. [2024-11-17 08:54:02,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:54:02,028 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:54:02,028 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2884 transitions. [2024-11-17 08:54:02,031 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:02,031 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2884 transitions. [2024-11-17 08:54:02,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2884 transitions. [2024-11-17 08:54:02,055 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:54:02,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.459514170040486) internal successors, (2884), 1975 states have internal predecessors, (2884), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2884 transitions. [2024-11-17 08:54:02,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2884 transitions. [2024-11-17 08:54:02,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:02,063 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2884 transitions. [2024-11-17 08:54:02,063 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:54:02,064 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2884 transitions. [2024-11-17 08:54:02,070 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:02,070 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:02,070 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:02,072 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,072 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,073 INFO L745 eck$LassoCheckResult]: Stem: 56419#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 56420#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56222#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56223#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56875#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 56224#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56225#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56689#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56430#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56431#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 56957#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 56958#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 56560#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 56561#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56718#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 56282#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56283#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56028#L946 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 56029#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56591#L1258-1 assume !(0 == ~M_E~0); 56471#L1263-1 assume !(0 == ~T1_E~0); 56472#L1268-1 assume !(0 == ~T2_E~0); 56778#L1273-1 assume !(0 == ~T3_E~0); 57324#L1278-1 assume !(0 == ~T4_E~0); 57208#L1283-1 assume !(0 == ~T5_E~0); 57209#L1288-1 assume !(0 == ~T6_E~0); 57405#L1293-1 assume !(0 == ~T7_E~0); 57395#L1298-1 assume !(0 == ~T8_E~0); 57335#L1303-1 assume !(0 == ~T9_E~0); 55992#L1308-1 assume !(0 == ~T10_E~0); 55917#L1313-1 assume !(0 == ~T11_E~0); 55918#L1318-1 assume !(0 == ~T12_E~0); 55931#L1323-1 assume !(0 == ~T13_E~0); 55932#L1328-1 assume !(0 == ~E_1~0); 56112#L1333-1 assume !(0 == ~E_2~0); 57053#L1338-1 assume !(0 == ~E_3~0); 57054#L1343-1 assume !(0 == ~E_4~0); 57178#L1348-1 assume !(0 == ~E_5~0); 57430#L1353-1 assume !(0 == ~E_6~0); 56788#L1358-1 assume !(0 == ~E_7~0); 56789#L1363-1 assume !(0 == ~E_8~0); 57082#L1368-1 assume !(0 == ~E_9~0); 55716#L1373-1 assume !(0 == ~E_10~0); 55717#L1378-1 assume !(0 == ~E_11~0); 56064#L1383-1 assume !(0 == ~E_12~0); 56065#L1388-1 assume !(0 == ~E_13~0); 57170#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57301#L607-15 assume 1 == ~m_pc~0; 57355#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 57139#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57043#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 57044#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56020#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55768#L626-15 assume 1 == ~t1_pc~0; 55769#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 56468#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56514#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57290#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 57117#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57118#L645-15 assume 1 == ~t2_pc~0; 56869#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55869#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55870#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57235#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 56570#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55540#L664-15 assume 1 == ~t3_pc~0; 55541#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56873#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56480#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 55814#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 55815#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56243#L683-15 assume 1 == ~t4_pc~0; 56769#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 56729#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56730#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56999#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56633#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56634#L702-15 assume 1 == ~t5_pc~0; 57202#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56577#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57252#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57303#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 56527#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55620#L721-15 assume 1 == ~t6_pc~0; 55621#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55848#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57362#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56436#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 56437#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55682#L740-15 assume 1 == ~t7_pc~0; 55683#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57129#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56545#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 56546#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 57325#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57326#L759-15 assume 1 == ~t8_pc~0; 57206#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56234#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57286#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57039#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57040#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 55788#L778-15 assume 1 == ~t9_pc~0; 55789#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56293#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56294#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55933#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 55934#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57002#L797-15 assume 1 == ~t10_pc~0; 56238#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56239#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56928#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55939#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 55940#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56524#L816-15 assume 1 == ~t11_pc~0; 56491#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 56492#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57065#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56253#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 56254#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 57076#L835-15 assume 1 == ~t12_pc~0; 57111#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 57354#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57352#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 56593#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 55566#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 55567#L854-15 assume 1 == ~t13_pc~0; 56425#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 56426#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55895#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55896#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 56300#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56675#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 56676#L1406-1 assume !(1 == ~T1_E~0); 56929#L1411-1 assume !(1 == ~T2_E~0); 56930#L1416-1 assume !(1 == ~T3_E~0); 56600#L1421-1 assume !(1 == ~T4_E~0); 56149#L1426-1 assume !(1 == ~T5_E~0); 56150#L1431-1 assume !(1 == ~T6_E~0); 55631#L1436-1 assume !(1 == ~T7_E~0); 55632#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56461#L1446-1 assume !(1 == ~T9_E~0); 56462#L1451-1 assume !(1 == ~T10_E~0); 57176#L1456-1 assume !(1 == ~T11_E~0); 56815#L1461-1 assume !(1 == ~T12_E~0); 56372#L1466-1 assume !(1 == ~T13_E~0); 56373#L1471-1 assume !(1 == ~E_1~0); 57147#L1476-1 assume !(1 == ~E_2~0); 57148#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 57292#L1486-1 assume !(1 == ~E_4~0); 56012#L1491-1 assume !(1 == ~E_5~0); 55557#L1496-1 assume !(1 == ~E_6~0); 55558#L1501-1 assume !(1 == ~E_7~0); 56454#L1506-1 assume !(1 == ~E_8~0); 56455#L1511-1 assume !(1 == ~E_9~0); 56404#L1516-1 assume !(1 == ~E_10~0); 55513#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 55514#L1526-1 assume !(1 == ~E_12~0); 55556#L1531-1 assume !(1 == ~E_13~0); 56167#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 55619#L1892 [2024-11-17 08:54:02,073 INFO L747 eck$LassoCheckResult]: Loop: 55619#L1892 assume true; 55562#L1892-1 assume !false; 55563#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56179#L1041 assume true; 56348#L1041-1 assume !false; 56349#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56996#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 56076#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 56909#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 55609#L1046 assume !(0 != eval_~tmp~0#1); 55611#L1049 assume true; 57186#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55967#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55968#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 55993#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55994#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56390#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 56312#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56313#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 56611#L1288 assume !(0 == ~T6_E~0); 56612#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 56021#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 56022#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 57452#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 57453#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 56304#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56305#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 57407#L1328 assume !(0 == ~E_1~0); 57408#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 55922#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 55923#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 55881#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 55882#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 56198#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 56851#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 56478#L1368 assume !(0 == ~E_9~0); 56479#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 56298#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 56299#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 57262#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 57239#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55884#L607-1 assume !(1 == ~m_pc~0); 55779#L617-1 is_master_triggered_~__retres1~0#1 := 0; 55780#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55807#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55808#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 56102#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57216#L626-1 assume 1 == ~t1_pc~0; 57003#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 57004#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56806#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56255#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 56256#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55731#L645-1 assume 1 == ~t2_pc~0; 55732#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56655#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55685#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55686#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57240#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55866#L664-1 assume !(1 == ~t3_pc~0); 55867#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 55996#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55997#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56595#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56970#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57069#L683-1 assume !(1 == ~t4_pc~0); 57041#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 57042#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57016#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56381#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56382#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56555#L702-1 assume 1 == ~t5_pc~0; 56108#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56109#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55838#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55839#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57104#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57105#L721-1 assume 1 == ~t6_pc~0; 57253#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57254#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55487#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55488#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 57243#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56564#L740-1 assume !(1 == ~t7_pc~0); 56565#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 57299#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55599#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55600#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57288#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 57409#L759-1 assume 1 == ~t8_pc~0; 57410#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 55707#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55708#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57229#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56963#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56416#L778-1 assume 1 == ~t9_pc~0; 56417#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 56831#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57048#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56321#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 56066#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55669#L797-1 assume 1 == ~t10_pc~0; 55670#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 56207#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56208#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57342#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 56168#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56169#L816-1 assume !(1 == ~t11_pc~0); 57079#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 55502#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55503#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55553#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 55695#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 55696#L835-1 assume 1 == ~t12_pc~0; 57158#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 56072#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 56073#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55777#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 55778#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 55928#L854-1 assume 1 == ~t13_pc~0; 55929#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 57096#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56507#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 56508#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 56896#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57228#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 56379#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56380#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56713#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56097#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55950#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55951#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 56599#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56852#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56177#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 56178#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 56037#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56038#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 57417#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 57337#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 56976#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 56977#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 57411#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 57179#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 55667#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 55668#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 56140#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 56141#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 55509#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 55510#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 57368#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 55981#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 55982#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 57193#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 55764#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 55765#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 56475#L1911 assume !(0 == start_simulation_~tmp~3#1); 56435#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 56726#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 55786#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 55787#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 55736#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55737#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56010#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 56011#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 55619#L1892 [2024-11-17 08:54:02,074 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,074 INFO L85 PathProgramCache]: Analyzing trace with hash 988383754, now seen corresponding path program 1 times [2024-11-17 08:54:02,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,074 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399279043] [2024-11-17 08:54:02,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,118 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,119 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399279043] [2024-11-17 08:54:02,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1399279043] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,119 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:02,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986391164] [2024-11-17 08:54:02,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,120 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:02,120 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,120 INFO L85 PathProgramCache]: Analyzing trace with hash -647526638, now seen corresponding path program 3 times [2024-11-17 08:54:02,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047063641] [2024-11-17 08:54:02,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,189 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,189 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1047063641] [2024-11-17 08:54:02,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1047063641] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,190 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:02,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [913056719] [2024-11-17 08:54:02,190 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,191 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:02,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:02,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:02,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:02,191 INFO L87 Difference]: Start difference. First operand 1976 states and 2884 transitions. cyclomatic complexity: 909 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:02,221 INFO L93 Difference]: Finished difference Result 1976 states and 2883 transitions. [2024-11-17 08:54:02,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1976 states and 2883 transitions. [2024-11-17 08:54:02,228 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:02,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1976 states to 1976 states and 2883 transitions. [2024-11-17 08:54:02,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1976 [2024-11-17 08:54:02,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1976 [2024-11-17 08:54:02,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1976 states and 2883 transitions. [2024-11-17 08:54:02,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:02,236 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2883 transitions. [2024-11-17 08:54:02,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1976 states and 2883 transitions. [2024-11-17 08:54:02,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1976 to 1976. [2024-11-17 08:54:02,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1976 states, 1976 states have (on average 1.459008097165992) internal successors, (2883), 1975 states have internal predecessors, (2883), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,266 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1976 states to 1976 states and 2883 transitions. [2024-11-17 08:54:02,266 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1976 states and 2883 transitions. [2024-11-17 08:54:02,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:02,267 INFO L425 stractBuchiCegarLoop]: Abstraction has 1976 states and 2883 transitions. [2024-11-17 08:54:02,267 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:54:02,267 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1976 states and 2883 transitions. [2024-11-17 08:54:02,273 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1803 [2024-11-17 08:54:02,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:02,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:02,275 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,275 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,276 INFO L745 eck$LassoCheckResult]: Stem: 60380#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 60381#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60183#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60184#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60836#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 60185#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60186#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60650#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60391#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60392#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60918#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60919#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60521#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 60522#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60679#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 60243#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 60244#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59989#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59990#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60552#L1258-1 assume !(0 == ~M_E~0); 60432#L1263-1 assume !(0 == ~T1_E~0); 60433#L1268-1 assume !(0 == ~T2_E~0); 60739#L1273-1 assume !(0 == ~T3_E~0); 61285#L1278-1 assume !(0 == ~T4_E~0); 61169#L1283-1 assume !(0 == ~T5_E~0); 61170#L1288-1 assume !(0 == ~T6_E~0); 61366#L1293-1 assume !(0 == ~T7_E~0); 61356#L1298-1 assume !(0 == ~T8_E~0); 61296#L1303-1 assume !(0 == ~T9_E~0); 59953#L1308-1 assume !(0 == ~T10_E~0); 59878#L1313-1 assume !(0 == ~T11_E~0); 59879#L1318-1 assume !(0 == ~T12_E~0); 59892#L1323-1 assume !(0 == ~T13_E~0); 59893#L1328-1 assume !(0 == ~E_1~0); 60073#L1333-1 assume !(0 == ~E_2~0); 61014#L1338-1 assume !(0 == ~E_3~0); 61015#L1343-1 assume !(0 == ~E_4~0); 61139#L1348-1 assume !(0 == ~E_5~0); 61391#L1353-1 assume !(0 == ~E_6~0); 60749#L1358-1 assume !(0 == ~E_7~0); 60750#L1363-1 assume !(0 == ~E_8~0); 61043#L1368-1 assume !(0 == ~E_9~0); 59677#L1373-1 assume !(0 == ~E_10~0); 59678#L1378-1 assume !(0 == ~E_11~0); 60025#L1383-1 assume !(0 == ~E_12~0); 60026#L1388-1 assume !(0 == ~E_13~0); 61131#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61262#L607-15 assume 1 == ~m_pc~0; 61316#L608-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 61100#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61004#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61005#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59981#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59729#L626-15 assume 1 == ~t1_pc~0; 59730#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 60429#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60475#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61251#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 61078#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61079#L645-15 assume 1 == ~t2_pc~0; 60830#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59830#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59831#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61196#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 60531#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59501#L664-15 assume 1 == ~t3_pc~0; 59502#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60834#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60441#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59775#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 59776#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60204#L683-15 assume 1 == ~t4_pc~0; 60730#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 60690#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60691#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60960#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60594#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60595#L702-15 assume 1 == ~t5_pc~0; 61163#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60538#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61213#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 61264#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 60488#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59581#L721-15 assume 1 == ~t6_pc~0; 59582#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59809#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61323#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60397#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 60398#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59643#L740-15 assume 1 == ~t7_pc~0; 59644#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 61090#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60506#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60507#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 61286#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61287#L759-15 assume 1 == ~t8_pc~0; 61167#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60195#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61247#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61000#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61001#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59749#L778-15 assume 1 == ~t9_pc~0; 59750#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60254#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60255#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59894#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 59895#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60963#L797-15 assume 1 == ~t10_pc~0; 60199#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 60200#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60889#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59900#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 59901#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60485#L816-15 assume 1 == ~t11_pc~0; 60452#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60453#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61026#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60214#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 60215#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 61037#L835-15 assume 1 == ~t12_pc~0; 61072#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61315#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61313#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60554#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 59527#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59528#L854-15 assume 1 == ~t13_pc~0; 60386#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 60387#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59856#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59857#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 60261#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60636#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 60637#L1406-1 assume !(1 == ~T1_E~0); 60890#L1411-1 assume !(1 == ~T2_E~0); 60891#L1416-1 assume !(1 == ~T3_E~0); 60561#L1421-1 assume !(1 == ~T4_E~0); 60110#L1426-1 assume !(1 == ~T5_E~0); 60111#L1431-1 assume !(1 == ~T6_E~0); 59592#L1436-1 assume !(1 == ~T7_E~0); 59593#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60422#L1446-1 assume !(1 == ~T9_E~0); 60423#L1451-1 assume !(1 == ~T10_E~0); 61137#L1456-1 assume !(1 == ~T11_E~0); 60776#L1461-1 assume !(1 == ~T12_E~0); 60333#L1466-1 assume !(1 == ~T13_E~0); 60334#L1471-1 assume !(1 == ~E_1~0); 61108#L1476-1 assume !(1 == ~E_2~0); 61109#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 61253#L1486-1 assume !(1 == ~E_4~0); 59973#L1491-1 assume !(1 == ~E_5~0); 59518#L1496-1 assume !(1 == ~E_6~0); 59519#L1501-1 assume !(1 == ~E_7~0); 60415#L1506-1 assume !(1 == ~E_8~0); 60416#L1511-1 assume !(1 == ~E_9~0); 60365#L1516-1 assume !(1 == ~E_10~0); 59474#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 59475#L1526-1 assume !(1 == ~E_12~0); 59517#L1531-1 assume !(1 == ~E_13~0); 60128#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 59580#L1892 [2024-11-17 08:54:02,276 INFO L747 eck$LassoCheckResult]: Loop: 59580#L1892 assume true; 59523#L1892-1 assume !false; 59524#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60140#L1041 assume true; 60309#L1041-1 assume !false; 60310#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60957#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 60037#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60870#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 59570#L1046 assume !(0 != eval_~tmp~0#1); 59572#L1049 assume true; 61147#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59928#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59929#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 59954#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59955#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60351#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60273#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60274#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60572#L1288 assume !(0 == ~T6_E~0); 60573#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59982#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59983#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 61413#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 61414#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 60265#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 60266#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 61368#L1328 assume !(0 == ~E_1~0); 61369#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 59883#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 59884#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 59842#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 59843#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 60159#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 60812#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 60439#L1368 assume !(0 == ~E_9~0); 60440#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 60259#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 60260#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 61223#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 61200#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59845#L607-1 assume 1 == ~m_pc~0; 59846#L608-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 59741#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59768#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59769#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60063#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61177#L626-1 assume 1 == ~t1_pc~0; 60964#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 60965#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60767#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60216#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60217#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59692#L645-1 assume 1 == ~t2_pc~0; 59693#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60616#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59646#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59647#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61201#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59827#L664-1 assume !(1 == ~t3_pc~0); 59828#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 59957#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59958#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60556#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60931#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61030#L683-1 assume !(1 == ~t4_pc~0); 61002#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 61003#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60977#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60342#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60343#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60516#L702-1 assume 1 == ~t5_pc~0; 60069#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60070#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59799#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59800#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 61065#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61066#L721-1 assume !(1 == ~t6_pc~0); 61216#L731-1 is_transmit6_triggered_~__retres1~6#1 := 0; 61215#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59448#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59449#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 61204#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60525#L740-1 assume !(1 == ~t7_pc~0); 60526#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 61260#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59560#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59561#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 61249#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 61370#L759-1 assume 1 == ~t8_pc~0; 61371#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59668#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59669#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 61190#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60924#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60377#L778-1 assume 1 == ~t9_pc~0; 60378#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 60792#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 61009#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60282#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60027#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59630#L797-1 assume !(1 == ~t10_pc~0); 59632#L807-1 is_transmit10_triggered_~__retres1~10#1 := 0; 60168#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60169#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 61303#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 60129#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60130#L816-1 assume !(1 == ~t11_pc~0); 61040#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 59463#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59464#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59514#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59656#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59657#L835-1 assume !(1 == ~t12_pc~0); 61120#L845-1 is_transmit12_triggered_~__retres1~12#1 := 0; 60033#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60034#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59738#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 59739#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59889#L854-1 assume 1 == ~t13_pc~0; 59890#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 61057#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60468#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60469#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 60857#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61189#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 60340#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60341#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60674#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60058#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 59911#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 59912#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60560#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60813#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60138#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60139#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59998#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59999#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 61378#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 61298#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 60937#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 60938#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 61372#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 61140#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 59628#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 59629#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 60101#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 60102#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 59470#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 59471#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 61329#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 59942#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 59943#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 61154#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59725#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 59726#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 60436#L1911 assume !(0 == start_simulation_~tmp~3#1); 60396#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60687#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59747#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 59748#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 59697#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 59698#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 59971#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 59972#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 59580#L1892 [2024-11-17 08:54:02,277 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,277 INFO L85 PathProgramCache]: Analyzing trace with hash -888885141, now seen corresponding path program 1 times [2024-11-17 08:54:02,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,277 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387828439] [2024-11-17 08:54:02,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [387828439] [2024-11-17 08:54:02,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [387828439] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,337 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:02,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1152294326] [2024-11-17 08:54:02,337 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,337 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:02,338 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,338 INFO L85 PathProgramCache]: Analyzing trace with hash -1277293620, now seen corresponding path program 1 times [2024-11-17 08:54:02,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250667838] [2024-11-17 08:54:02,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,406 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,406 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250667838] [2024-11-17 08:54:02,407 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250667838] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,407 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,407 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:02,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [403544721] [2024-11-17 08:54:02,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,407 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:02,408 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:02,408 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:02,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:02,408 INFO L87 Difference]: Start difference. First operand 1976 states and 2883 transitions. cyclomatic complexity: 908 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:02,555 INFO L93 Difference]: Finished difference Result 3760 states and 5445 transitions. [2024-11-17 08:54:02,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3760 states and 5445 transitions. [2024-11-17 08:54:02,607 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3586 [2024-11-17 08:54:02,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3760 states to 3760 states and 5445 transitions. [2024-11-17 08:54:02,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3760 [2024-11-17 08:54:02,622 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3760 [2024-11-17 08:54:02,622 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3760 states and 5445 transitions. [2024-11-17 08:54:02,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:02,628 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3760 states and 5445 transitions. [2024-11-17 08:54:02,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3760 states and 5445 transitions. [2024-11-17 08:54:02,684 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3760 to 3660. [2024-11-17 08:54:02,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3660 states, 3660 states have (on average 1.4494535519125684) internal successors, (5305), 3659 states have internal predecessors, (5305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3660 states to 3660 states and 5305 transitions. [2024-11-17 08:54:02,699 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3660 states and 5305 transitions. [2024-11-17 08:54:02,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:02,700 INFO L425 stractBuchiCegarLoop]: Abstraction has 3660 states and 5305 transitions. [2024-11-17 08:54:02,700 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:54:02,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3660 states and 5305 transitions. [2024-11-17 08:54:02,713 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3486 [2024-11-17 08:54:02,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:02,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:02,716 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,716 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,716 INFO L745 eck$LassoCheckResult]: Stem: 66126#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 66127#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 65929#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65930#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66583#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 65931#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65932#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66396#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66137#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66138#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 66668#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 66669#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 66267#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 66268#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 66425#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 65989#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 65990#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 65735#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 65736#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66298#L1258-1 assume !(0 == ~M_E~0); 66178#L1263-1 assume !(0 == ~T1_E~0); 66179#L1268-1 assume !(0 == ~T2_E~0); 66485#L1273-1 assume !(0 == ~T3_E~0); 67048#L1278-1 assume !(0 == ~T4_E~0); 66930#L1283-1 assume !(0 == ~T5_E~0); 66931#L1288-1 assume !(0 == ~T6_E~0); 67143#L1293-1 assume !(0 == ~T7_E~0); 67131#L1298-1 assume !(0 == ~T8_E~0); 67061#L1303-1 assume !(0 == ~T9_E~0); 65699#L1308-1 assume !(0 == ~T10_E~0); 65621#L1313-1 assume !(0 == ~T11_E~0); 65622#L1318-1 assume !(0 == ~T12_E~0); 65635#L1323-1 assume !(0 == ~T13_E~0); 65636#L1328-1 assume !(0 == ~E_1~0); 65820#L1333-1 assume !(0 == ~E_2~0); 66770#L1338-1 assume !(0 == ~E_3~0); 66771#L1343-1 assume !(0 == ~E_4~0); 66900#L1348-1 assume !(0 == ~E_5~0); 67168#L1353-1 assume !(0 == ~E_6~0); 66495#L1358-1 assume !(0 == ~E_7~0); 66496#L1363-1 assume !(0 == ~E_8~0); 66799#L1368-1 assume !(0 == ~E_9~0); 65421#L1373-1 assume !(0 == ~E_10~0); 65422#L1378-1 assume !(0 == ~E_11~0); 65772#L1383-1 assume !(0 == ~E_12~0); 65773#L1388-1 assume !(0 == ~E_13~0); 66892#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 67025#L607-15 assume !(1 == ~m_pc~0); 66858#L617-15 is_master_triggered_~__retres1~0#1 := 0; 66859#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66759#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 66760#L1560-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65727#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65473#L626-15 assume 1 == ~t1_pc~0; 65474#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 66175#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66221#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 67014#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 66837#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66838#L645-15 assume 1 == ~t2_pc~0; 66577#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65574#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65575#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 66959#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 66277#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65246#L664-15 assume 1 == ~t3_pc~0; 65247#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 66581#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66187#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65519#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 65520#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65950#L683-15 assume 1 == ~t4_pc~0; 66476#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 66436#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66437#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66715#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66340#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66341#L702-15 assume 1 == ~t5_pc~0; 66924#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 66284#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 66976#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 67027#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 66234#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 65324#L721-15 assume 1 == ~t6_pc~0; 65325#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65553#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 67093#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 66143#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 66144#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 65387#L740-15 assume 1 == ~t7_pc~0; 65388#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 66849#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 66252#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 66253#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 67049#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67050#L759-15 assume 1 == ~t8_pc~0; 66928#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 65941#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 67010#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66755#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66756#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65493#L778-15 assume 1 == ~t9_pc~0; 65494#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 66000#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66001#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65637#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 65638#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 66718#L797-15 assume 1 == ~t10_pc~0; 65945#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 65946#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 66640#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65643#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 65644#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 66231#L816-15 assume 1 == ~t11_pc~0; 66198#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 66199#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 66782#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65960#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 65961#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 66793#L835-15 assume 1 == ~t12_pc~0; 66830#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 67085#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 67083#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 66300#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 65272#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 65273#L854-15 assume 1 == ~t13_pc~0; 66132#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 66133#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 65599#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 65600#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 66007#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66382#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 66383#L1406-1 assume !(1 == ~T1_E~0); 66641#L1411-1 assume !(1 == ~T2_E~0); 66642#L1416-1 assume !(1 == ~T3_E~0); 66307#L1421-1 assume !(1 == ~T4_E~0); 65856#L1426-1 assume !(1 == ~T5_E~0); 65857#L1431-1 assume !(1 == ~T6_E~0); 65335#L1436-1 assume !(1 == ~T7_E~0); 65336#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 66168#L1446-1 assume !(1 == ~T9_E~0); 66169#L1451-1 assume !(1 == ~T10_E~0); 66898#L1456-1 assume !(1 == ~T11_E~0); 66523#L1461-1 assume !(1 == ~T12_E~0); 66079#L1466-1 assume !(1 == ~T13_E~0); 66080#L1471-1 assume !(1 == ~E_1~0); 66868#L1476-1 assume !(1 == ~E_2~0); 66869#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 67016#L1486-1 assume !(1 == ~E_4~0); 65719#L1491-1 assume !(1 == ~E_5~0); 65263#L1496-1 assume !(1 == ~E_6~0); 65264#L1501-1 assume !(1 == ~E_7~0); 66161#L1506-1 assume !(1 == ~E_8~0); 66162#L1511-1 assume !(1 == ~E_9~0); 66111#L1516-1 assume !(1 == ~E_10~0); 65219#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 65220#L1526-1 assume !(1 == ~E_12~0); 65262#L1531-1 assume !(1 == ~E_13~0); 65874#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 65323#L1892 [2024-11-17 08:54:02,717 INFO L747 eck$LassoCheckResult]: Loop: 65323#L1892 assume true; 65268#L1892-1 assume !false; 65269#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65886#L1041 assume true; 66055#L1041-1 assume !false; 66056#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 66711#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 65784#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 66620#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 65313#L1046 assume !(0 != eval_~tmp~0#1); 65315#L1049 assume true; 66908#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65671#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65672#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 65700#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65701#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66097#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66019#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66020#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 66318#L1288 assume !(0 == ~T6_E~0); 66319#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 65728#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 65729#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67195#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67196#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 66011#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 66012#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 67145#L1328 assume !(0 == ~E_1~0); 67146#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 65626#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 65627#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 65586#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 65587#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 65905#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 66559#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 66185#L1368 assume !(0 == ~E_9~0); 66186#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 66005#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 66006#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 66986#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 66963#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65589#L607-1 assume !(1 == ~m_pc~0); 65484#L617-1 is_master_triggered_~__retres1~0#1 := 0; 65485#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65512#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65513#L1560-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65810#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66939#L626-1 assume !(1 == ~t1_pc~0); 66721#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 66720#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66514#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65962#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65963#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65436#L645-1 assume 1 == ~t2_pc~0; 65437#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 66362#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65390#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65391#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66964#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65571#L664-1 assume 1 == ~t3_pc~0; 65573#L665-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 65703#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65704#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 66302#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66685#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66786#L683-1 assume !(1 == ~t4_pc~0); 66757#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 66758#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66732#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 66088#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66089#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 66262#L702-1 assume 1 == ~t5_pc~0; 65816#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65817#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65543#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 65544#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 66823#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 66824#L721-1 assume 1 == ~t6_pc~0; 66977#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66978#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65193#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65194#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 66967#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 66271#L740-1 assume 1 == ~t7_pc~0; 66273#L741-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 67023#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 65303#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65304#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 67012#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 67147#L759-1 assume !(1 == ~t8_pc~0); 67060#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 65412#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65413#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 66952#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 66673#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 66123#L778-1 assume !(1 == ~t9_pc~0); 66125#L788-1 is_transmit9_triggered_~__retres1~9#1 := 0; 66539#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 66764#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 66028#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65774#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65374#L797-1 assume !(1 == ~t10_pc~0); 65376#L807-1 is_transmit10_triggered_~__retres1~10#1 := 0; 65914#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65915#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 67069#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 65875#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65876#L816-1 assume 1 == ~t11_pc~0; 66902#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 65208#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65209#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 65259#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65400#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65401#L835-1 assume !(1 == ~t12_pc~0); 66880#L845-1 is_transmit12_triggered_~__retres1~12#1 := 0; 65780#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65781#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65482#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 65483#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 65632#L854-1 assume 1 == ~t13_pc~0; 65633#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 66815#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 66214#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 66215#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 66607#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66951#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 66086#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 66087#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66420#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65805#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65654#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65655#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 66306#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 66560#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65884#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65885#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65744#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65745#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 67155#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 67064#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 66691#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 66692#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 67149#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 66901#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 65372#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 65373#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 65847#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 65848#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 65215#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 65216#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 67101#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 65688#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 65689#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 66915#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 65469#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 65470#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 66182#L1911 assume !(0 == start_simulation_~tmp~3#1); 66142#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 66433#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 65491#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 65492#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 65441#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65442#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65717#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 65718#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 65323#L1892 [2024-11-17 08:54:02,718 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,718 INFO L85 PathProgramCache]: Analyzing trace with hash 994155976, now seen corresponding path program 1 times [2024-11-17 08:54:02,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347768219] [2024-11-17 08:54:02,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,816 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [347768219] [2024-11-17 08:54:02,816 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [347768219] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,816 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,817 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:02,817 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058394777] [2024-11-17 08:54:02,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,817 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:02,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,818 INFO L85 PathProgramCache]: Analyzing trace with hash -499289076, now seen corresponding path program 1 times [2024-11-17 08:54:02,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722881914] [2024-11-17 08:54:02,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,904 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,904 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722881914] [2024-11-17 08:54:02,905 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1722881914] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,905 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,905 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:02,905 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495166059] [2024-11-17 08:54:02,905 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,906 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:02,906 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:02,906 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:54:02,906 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:54:02,906 INFO L87 Difference]: Start difference. First operand 3660 states and 5305 transitions. cyclomatic complexity: 1647 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:03,223 INFO L93 Difference]: Finished difference Result 3705 states and 5335 transitions. [2024-11-17 08:54:03,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3705 states and 5335 transitions. [2024-11-17 08:54:03,240 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3531 [2024-11-17 08:54:03,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3705 states to 3705 states and 5335 transitions. [2024-11-17 08:54:03,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3705 [2024-11-17 08:54:03,253 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3705 [2024-11-17 08:54:03,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3705 states and 5335 transitions. [2024-11-17 08:54:03,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:03,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3705 states and 5335 transitions. [2024-11-17 08:54:03,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3705 states and 5335 transitions. [2024-11-17 08:54:03,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3705 to 3705. [2024-11-17 08:54:03,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3705 states, 3705 states have (on average 1.4399460188933872) internal successors, (5335), 3704 states have internal predecessors, (5335), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3705 states to 3705 states and 5335 transitions. [2024-11-17 08:54:03,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3705 states and 5335 transitions. [2024-11-17 08:54:03,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:54:03,329 INFO L425 stractBuchiCegarLoop]: Abstraction has 3705 states and 5335 transitions. [2024-11-17 08:54:03,329 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:54:03,329 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3705 states and 5335 transitions. [2024-11-17 08:54:03,342 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3531 [2024-11-17 08:54:03,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:03,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:03,344 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,345 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,345 INFO L745 eck$LassoCheckResult]: Stem: 73509#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 73510#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 73309#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 73310#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73968#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 73311#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 73312#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73780#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73520#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73521#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74054#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74055#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 73650#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 73651#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 73809#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 73369#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 73370#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 73113#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 73114#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73681#L1258-1 assume !(0 == ~M_E~0); 73561#L1263-1 assume !(0 == ~T1_E~0); 73562#L1268-1 assume !(0 == ~T2_E~0); 73869#L1273-1 assume !(0 == ~T3_E~0); 74445#L1278-1 assume !(0 == ~T4_E~0); 74323#L1283-1 assume !(0 == ~T5_E~0); 74324#L1288-1 assume !(0 == ~T6_E~0); 74549#L1293-1 assume !(0 == ~T7_E~0); 74539#L1298-1 assume !(0 == ~T8_E~0); 74458#L1303-1 assume !(0 == ~T9_E~0); 73077#L1308-1 assume !(0 == ~T10_E~0); 72998#L1313-1 assume !(0 == ~T11_E~0); 72999#L1318-1 assume !(0 == ~T12_E~0); 73012#L1323-1 assume !(0 == ~T13_E~0); 73013#L1328-1 assume !(0 == ~E_1~0); 73199#L1333-1 assume !(0 == ~E_2~0); 74159#L1338-1 assume !(0 == ~E_3~0); 74160#L1343-1 assume !(0 == ~E_4~0); 74290#L1348-1 assume !(0 == ~E_5~0); 74578#L1353-1 assume !(0 == ~E_6~0); 73880#L1358-1 assume !(0 == ~E_7~0); 73881#L1363-1 assume !(0 == ~E_8~0); 74187#L1368-1 assume !(0 == ~E_9~0); 72797#L1373-1 assume !(0 == ~E_10~0); 72798#L1378-1 assume !(0 == ~E_11~0); 73150#L1383-1 assume !(0 == ~E_12~0); 73151#L1388-1 assume !(0 == ~E_13~0); 74282#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74421#L607-15 assume !(1 == ~m_pc~0); 74247#L617-15 is_master_triggered_~__retres1~0#1 := 0; 74248#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74149#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 74150#L1560-15 assume !(0 != activate_threads_~tmp~1#1); 73105#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 72849#L626-15 assume 1 == ~t1_pc~0; 72850#L627-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 73558#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73604#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 74408#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 74225#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74226#L645-15 assume 1 == ~t2_pc~0; 73962#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 72950#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72951#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74351#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 73660#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72622#L664-15 assume 1 == ~t3_pc~0; 72623#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 73966#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73570#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 72895#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 72896#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73330#L683-15 assume 1 == ~t4_pc~0; 73860#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73820#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73821#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74101#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 73723#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73724#L702-15 assume 1 == ~t5_pc~0; 74316#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 73667#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74369#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 74424#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 73617#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72700#L721-15 assume 1 == ~t6_pc~0; 72701#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 72929#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 74490#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 73526#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 73527#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72763#L740-15 assume 1 == ~t7_pc~0; 72764#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 74238#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73635#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 73636#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 74446#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 74447#L759-15 assume 1 == ~t8_pc~0; 74320#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 73321#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74404#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74145#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 74146#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 72869#L778-15 assume 1 == ~t9_pc~0; 72870#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 73380#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73381#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 73014#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 73015#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74105#L797-15 assume 1 == ~t10_pc~0; 73325#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 73326#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74025#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 73020#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 73021#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 73614#L816-15 assume 1 == ~t11_pc~0; 73581#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 73582#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 74171#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73340#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 73341#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 74181#L835-15 assume 1 == ~t12_pc~0; 74219#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 74483#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 74481#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 73683#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 72648#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 72649#L854-15 assume 1 == ~t13_pc~0; 73515#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 73516#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 72976#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 72977#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 73387#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73766#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 73767#L1406-1 assume !(1 == ~T1_E~0); 74026#L1411-1 assume !(1 == ~T2_E~0); 74027#L1416-1 assume !(1 == ~T3_E~0); 73690#L1421-1 assume !(1 == ~T4_E~0); 73235#L1426-1 assume !(1 == ~T5_E~0); 73236#L1431-1 assume !(1 == ~T6_E~0); 72711#L1436-1 assume !(1 == ~T7_E~0); 72712#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 73551#L1446-1 assume !(1 == ~T9_E~0); 73552#L1451-1 assume !(1 == ~T10_E~0); 74288#L1456-1 assume !(1 == ~T11_E~0); 73908#L1461-1 assume !(1 == ~T12_E~0); 73461#L1466-1 assume !(1 == ~T13_E~0); 73462#L1471-1 assume !(1 == ~E_1~0); 74256#L1476-1 assume !(1 == ~E_2~0); 74257#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 74410#L1486-1 assume !(1 == ~E_4~0); 73097#L1491-1 assume !(1 == ~E_5~0); 72639#L1496-1 assume !(1 == ~E_6~0); 72640#L1501-1 assume !(1 == ~E_7~0); 73544#L1506-1 assume !(1 == ~E_8~0); 73545#L1511-1 assume !(1 == ~E_9~0); 73494#L1516-1 assume !(1 == ~E_10~0); 72595#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 72596#L1526-1 assume !(1 == ~E_12~0); 72638#L1531-1 assume !(1 == ~E_13~0); 73253#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 72699#L1892 [2024-11-17 08:54:03,346 INFO L747 eck$LassoCheckResult]: Loop: 72699#L1892 assume true; 72644#L1892-1 assume !false; 72645#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 73265#L1041 assume true; 73437#L1041-1 assume !false; 73438#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74097#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 73162#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 74005#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 72689#L1046 assume !(0 != eval_~tmp~0#1); 72691#L1049 assume true; 74300#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 73049#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 73050#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 73078#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 73079#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 73480#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 73401#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 73402#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 73701#L1288 assume !(0 == ~T6_E~0); 73702#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 73106#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 73107#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 74608#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 74609#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 73391#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 73392#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 74551#L1328 assume !(0 == ~E_1~0); 74552#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 73003#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 73004#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 72962#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 72963#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 73284#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 73944#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 73568#L1368 assume !(0 == ~E_9~0); 73569#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 73385#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 73386#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 74380#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 74355#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 72965#L607-1 assume !(1 == ~m_pc~0); 72860#L617-1 is_master_triggered_~__retres1~0#1 := 0; 72861#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74497#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73188#L1560-1 assume !(0 != activate_threads_~tmp~1#1); 73189#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74331#L626-1 assume 1 == ~t1_pc~0; 74106#L627-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 74107#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73899#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73342#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 73343#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72812#L645-1 assume 1 == ~t2_pc~0; 72813#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 73745#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 72766#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72767#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 74356#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72947#L664-1 assume 1 == ~t3_pc~0; 72949#L665-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 73081#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73082#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73685#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 74071#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 74175#L683-1 assume !(1 == ~t4_pc~0); 74515#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 74322#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 74119#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74120#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76130#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76129#L702-1 assume 1 == ~t5_pc~0; 76128#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 76126#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76125#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 76124#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 76123#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76122#L721-1 assume 1 == ~t6_pc~0; 76121#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76119#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76118#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76117#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76116#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76115#L740-1 assume !(1 == ~t7_pc~0); 76113#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 76112#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76111#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76110#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 76109#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76108#L759-1 assume !(1 == ~t8_pc~0); 76107#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 76105#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76104#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76103#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 76102#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76101#L778-1 assume !(1 == ~t9_pc~0); 76099#L788-1 is_transmit9_triggered_~__retres1~9#1 := 0; 76098#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 76097#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76096#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 76095#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76094#L797-1 assume 1 == ~t10_pc~0; 76093#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 76091#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 76090#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76089#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76088#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 76087#L816-1 assume !(1 == ~t11_pc~0); 76085#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 76084#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76083#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76082#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 76081#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76080#L835-1 assume !(1 == ~t12_pc~0); 76079#L845-1 is_transmit12_triggered_~__retres1~12#1 := 0; 76077#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 76076#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76075#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 76074#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 76073#L854-1 assume !(1 == ~t13_pc~0); 76071#L864-1 is_transmit13_triggered_~__retres1~13#1 := 0; 76070#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76069#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 76068#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 76067#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76066#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 76065#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76064#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76063#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76062#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76061#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 76060#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76059#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 76058#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 76057#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 76056#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 76055#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 76054#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 76053#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 76052#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 76051#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 76050#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 76049#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 76048#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 72748#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 72749#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 73226#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 73227#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 72591#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 72592#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 74501#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 73066#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 73067#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 74307#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 72845#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 72846#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 73565#L1911 assume !(0 == start_simulation_~tmp~3#1); 73525#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 73817#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 72867#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 72868#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 72817#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 72818#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73095#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 73096#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 72699#L1892 [2024-11-17 08:54:03,346 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,346 INFO L85 PathProgramCache]: Analyzing trace with hash 7573287, now seen corresponding path program 1 times [2024-11-17 08:54:03,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558398883] [2024-11-17 08:54:03,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,347 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1558398883] [2024-11-17 08:54:03,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1558398883] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,400 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:03,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [551984446] [2024-11-17 08:54:03,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,401 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:03,401 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,402 INFO L85 PathProgramCache]: Analyzing trace with hash 778726344, now seen corresponding path program 1 times [2024-11-17 08:54:03,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394464150] [2024-11-17 08:54:03,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,473 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [394464150] [2024-11-17 08:54:03,473 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [394464150] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,473 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:03,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958051174] [2024-11-17 08:54:03,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,474 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:03,474 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:03,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:03,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:03,475 INFO L87 Difference]: Start difference. First operand 3705 states and 5335 transitions. cyclomatic complexity: 1632 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:03,652 INFO L93 Difference]: Finished difference Result 7002 states and 10030 transitions. [2024-11-17 08:54:03,652 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7002 states and 10030 transitions. [2024-11-17 08:54:03,685 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6821 [2024-11-17 08:54:03,707 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7002 states to 7002 states and 10030 transitions. [2024-11-17 08:54:03,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7002 [2024-11-17 08:54:03,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7002 [2024-11-17 08:54:03,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7002 states and 10030 transitions. [2024-11-17 08:54:03,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:03,724 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7002 states and 10030 transitions. [2024-11-17 08:54:03,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7002 states and 10030 transitions. [2024-11-17 08:54:03,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7002 to 6994. [2024-11-17 08:54:03,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6994 states, 6994 states have (on average 1.432942522161853) internal successors, (10022), 6993 states have internal predecessors, (10022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6994 states to 6994 states and 10022 transitions. [2024-11-17 08:54:03,842 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6994 states and 10022 transitions. [2024-11-17 08:54:03,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:03,843 INFO L425 stractBuchiCegarLoop]: Abstraction has 6994 states and 10022 transitions. [2024-11-17 08:54:03,844 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:54:03,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6994 states and 10022 transitions. [2024-11-17 08:54:03,867 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6813 [2024-11-17 08:54:03,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:03,867 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:03,869 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,870 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,870 INFO L745 eck$LassoCheckResult]: Stem: 84222#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 84223#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 84019#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 84020#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84692#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 84021#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84022#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84498#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84233#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84234#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84779#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 84780#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 84367#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84368#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 84528#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 84079#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 84080#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 83825#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 83826#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84398#L1258-1 assume !(0 == ~M_E~0); 84276#L1263-1 assume !(0 == ~T1_E~0); 84277#L1268-1 assume !(0 == ~T2_E~0); 84588#L1273-1 assume !(0 == ~T3_E~0); 85184#L1278-1 assume !(0 == ~T4_E~0); 85055#L1283-1 assume !(0 == ~T5_E~0); 85056#L1288-1 assume !(0 == ~T6_E~0); 85295#L1293-1 assume !(0 == ~T7_E~0); 85283#L1298-1 assume !(0 == ~T8_E~0); 85196#L1303-1 assume !(0 == ~T9_E~0); 83789#L1308-1 assume !(0 == ~T10_E~0); 83713#L1313-1 assume !(0 == ~T11_E~0); 83714#L1318-1 assume !(0 == ~T12_E~0); 83727#L1323-1 assume !(0 == ~T13_E~0); 83728#L1328-1 assume !(0 == ~E_1~0); 83910#L1333-1 assume !(0 == ~E_2~0); 84887#L1338-1 assume !(0 == ~E_3~0); 84888#L1343-1 assume !(0 == ~E_4~0); 85026#L1348-1 assume !(0 == ~E_5~0); 85344#L1353-1 assume !(0 == ~E_6~0); 84599#L1358-1 assume !(0 == ~E_7~0); 84600#L1363-1 assume !(0 == ~E_8~0); 84918#L1368-1 assume !(0 == ~E_9~0); 83513#L1373-1 assume !(0 == ~E_10~0); 83514#L1378-1 assume !(0 == ~E_11~0); 83862#L1383-1 assume !(0 == ~E_12~0); 83863#L1388-1 assume !(0 == ~E_13~0); 85015#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 85160#L607-15 assume !(1 == ~m_pc~0); 84979#L617-15 is_master_triggered_~__retres1~0#1 := 0; 84980#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84877#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 84878#L1560-15 assume !(0 != activate_threads_~tmp~1#1); 83817#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83565#L626-15 assume !(1 == ~t1_pc~0); 83566#L636-15 is_transmit1_triggered_~__retres1~1#1 := 0; 84273#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84320#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85148#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 84957#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84958#L645-15 assume 1 == ~t2_pc~0; 84686#L646-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 83665#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83666#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85088#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 84377#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83338#L664-15 assume 1 == ~t3_pc~0; 83339#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 84691#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84285#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83610#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 83611#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84040#L683-15 assume 1 == ~t4_pc~0; 84579#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 84540#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84541#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84830#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 84440#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84441#L702-15 assume 1 == ~t5_pc~0; 85049#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 84384#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 85106#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85162#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 84333#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83417#L721-15 assume 1 == ~t6_pc~0; 83418#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 83644#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85233#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 84239#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 84240#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 83479#L740-15 assume 1 == ~t7_pc~0; 83480#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 84970#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 84352#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 84353#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 85185#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85186#L759-15 assume 1 == ~t8_pc~0; 85053#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 84031#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85144#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 84873#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 84874#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83584#L778-15 assume 1 == ~t9_pc~0; 83585#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 84090#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 84091#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 83729#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 83730#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 84835#L797-15 assume 1 == ~t10_pc~0; 84035#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 84036#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 84749#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83735#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 83736#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 84332#L816-15 assume 1 == ~t11_pc~0; 84296#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 84297#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 84901#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 84050#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 84051#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 84912#L835-15 assume 1 == ~t12_pc~0; 84951#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 85224#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 85222#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 84401#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 83364#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 83365#L854-15 assume 1 == ~t13_pc~0; 84228#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 84229#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 83691#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 83692#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 84097#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84483#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 84484#L1406-1 assume !(1 == ~T1_E~0); 84750#L1411-1 assume !(1 == ~T2_E~0); 84751#L1416-1 assume !(1 == ~T3_E~0); 84407#L1421-1 assume !(1 == ~T4_E~0); 83946#L1426-1 assume !(1 == ~T5_E~0); 83947#L1431-1 assume !(1 == ~T6_E~0); 83427#L1436-1 assume !(1 == ~T7_E~0); 83428#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 84266#L1446-1 assume !(1 == ~T9_E~0); 84267#L1451-1 assume !(1 == ~T10_E~0); 85021#L1456-1 assume !(1 == ~T11_E~0); 84628#L1461-1 assume !(1 == ~T12_E~0); 84173#L1466-1 assume !(1 == ~T13_E~0); 84174#L1471-1 assume !(1 == ~E_1~0); 84990#L1476-1 assume !(1 == ~E_2~0); 84991#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 85150#L1486-1 assume !(1 == ~E_4~0); 83809#L1491-1 assume !(1 == ~E_5~0); 83355#L1496-1 assume !(1 == ~E_6~0); 83356#L1501-1 assume !(1 == ~E_7~0); 84257#L1506-1 assume !(1 == ~E_8~0); 84258#L1511-1 assume !(1 == ~E_9~0); 84207#L1516-1 assume !(1 == ~E_10~0); 83311#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 83312#L1526-1 assume !(1 == ~E_12~0); 83354#L1531-1 assume !(1 == ~E_13~0); 83964#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 83415#L1892 [2024-11-17 08:54:03,871 INFO L747 eck$LassoCheckResult]: Loop: 83415#L1892 assume true; 83362#L1892-1 assume !false; 83363#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83980#L1041 assume true; 84151#L1041-1 assume !false; 84152#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84826#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 83873#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84729#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 83405#L1046 assume !(0 != eval_~tmp~0#1); 83407#L1049 assume true; 85033#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83762#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83763#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 83792#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83793#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 84191#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 84192#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 90258#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 90257#L1288 assume !(0 == ~T6_E~0); 90256#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 90255#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 90254#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 90253#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 90252#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 90251#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 90250#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 90249#L1328 assume !(0 == ~E_1~0); 90247#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 90245#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 85264#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 83677#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 83678#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 83995#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 84665#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 84283#L1368 assume !(0 == ~E_9~0); 84284#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 84095#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 84096#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 85116#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 85091#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83680#L607-1 assume !(1 == ~m_pc~0); 83681#L617-1 is_master_triggered_~__retres1~0#1 := 0; 90248#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 90246#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 90244#L1560-1 assume !(0 != activate_threads_~tmp~1#1); 85063#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 85064#L626-1 assume !(1 == ~t1_pc~0); 85002#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 85003#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84619#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 84052#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 84053#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83528#L645-1 assume 1 == ~t2_pc~0; 83529#L646-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 84462#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83482#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 83483#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 85094#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83662#L664-1 assume 1 == ~t3_pc~0; 83664#L665-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83790#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83791#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 84402#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 84800#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84905#L683-1 assume 1 == ~t4_pc~0; 85253#L684-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 84876#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84848#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 84182#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 84183#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 84362#L702-1 assume 1 == ~t5_pc~0; 83906#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 83907#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 83634#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83635#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 84942#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 84943#L721-1 assume 1 == ~t6_pc~0; 85107#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85108#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83285#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 83286#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 85096#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 84371#L740-1 assume 1 == ~t7_pc~0; 84373#L741-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85158#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 89988#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 89987#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 89986#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 89985#L759-1 assume !(1 == ~t8_pc~0); 89984#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 89982#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 89981#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 89980#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 89979#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 89978#L778-1 assume 1 == ~t9_pc~0; 89977#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 89975#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 89974#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 89973#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 89972#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 89971#L797-1 assume !(1 == ~t10_pc~0); 89969#L807-1 is_transmit10_triggered_~__retres1~10#1 := 0; 89968#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 89967#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 89966#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 89965#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 89964#L816-1 assume 1 == ~t11_pc~0; 89963#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 89961#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 89960#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 89959#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 89958#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 89957#L835-1 assume 1 == ~t12_pc~0; 89955#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 89954#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 89953#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 89952#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 89951#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 89950#L854-1 assume 1 == ~t13_pc~0; 89949#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 89947#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 89946#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 89945#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 89944#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89943#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 89942#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89941#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 89940#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89939#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89938#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89937#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 89936#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 89935#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 89934#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 89933#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 89816#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 89813#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 89811#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 89809#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 84806#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 84807#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 85301#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 85025#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 83464#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 83465#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 83937#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 83938#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 83307#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 83308#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 88798#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 88797#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 88796#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85394#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 83561#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 83562#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 84280#L1911 assume !(0 == start_simulation_~tmp~3#1); 84238#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 84536#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 83580#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 83581#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 83533#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 83534#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83807#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 83808#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 83415#L1892 [2024-11-17 08:54:03,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,872 INFO L85 PathProgramCache]: Analyzing trace with hash 1724974660, now seen corresponding path program 1 times [2024-11-17 08:54:03,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781006921] [2024-11-17 08:54:03,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,927 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781006921] [2024-11-17 08:54:03,927 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781006921] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,927 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:03,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [125983890] [2024-11-17 08:54:03,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,928 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:03,928 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,928 INFO L85 PathProgramCache]: Analyzing trace with hash -912958060, now seen corresponding path program 1 times [2024-11-17 08:54:03,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814446099] [2024-11-17 08:54:03,928 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,000 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,000 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814446099] [2024-11-17 08:54:04,000 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814446099] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,000 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,001 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:04,001 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365858562] [2024-11-17 08:54:04,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,002 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:04,002 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:04,003 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:04,003 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:04,003 INFO L87 Difference]: Start difference. First operand 6994 states and 10022 transitions. cyclomatic complexity: 3032 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:04,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:04,161 INFO L93 Difference]: Finished difference Result 13354 states and 19051 transitions. [2024-11-17 08:54:04,161 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13354 states and 19051 transitions. [2024-11-17 08:54:04,226 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13156 [2024-11-17 08:54:04,275 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13354 states to 13354 states and 19051 transitions. [2024-11-17 08:54:04,275 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13354 [2024-11-17 08:54:04,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13354 [2024-11-17 08:54:04,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13354 states and 19051 transitions. [2024-11-17 08:54:04,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:04,306 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13354 states and 19051 transitions. [2024-11-17 08:54:04,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13354 states and 19051 transitions. [2024-11-17 08:54:04,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13354 to 13338. [2024-11-17 08:54:04,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13338 states, 13338 states have (on average 1.4271255060728745) internal successors, (19035), 13337 states have internal predecessors, (19035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:04,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13338 states to 13338 states and 19035 transitions. [2024-11-17 08:54:04,582 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13338 states and 19035 transitions. [2024-11-17 08:54:04,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:04,583 INFO L425 stractBuchiCegarLoop]: Abstraction has 13338 states and 19035 transitions. [2024-11-17 08:54:04,583 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:54:04,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13338 states and 19035 transitions. [2024-11-17 08:54:04,627 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13140 [2024-11-17 08:54:04,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:04,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:04,631 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:04,631 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:04,631 INFO L745 eck$LassoCheckResult]: Stem: 104573#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 104574#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 104372#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 104373#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105041#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 104375#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104376#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104848#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104582#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104583#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 105128#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 105129#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 104717#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 104718#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 104876#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 104431#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 104432#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 104178#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 104179#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 104748#L1258-1 assume !(0 == ~M_E~0); 104624#L1263-1 assume !(0 == ~T1_E~0); 104625#L1268-1 assume !(0 == ~T2_E~0); 104938#L1273-1 assume !(0 == ~T3_E~0); 105546#L1278-1 assume !(0 == ~T4_E~0); 105408#L1283-1 assume !(0 == ~T5_E~0); 105409#L1288-1 assume !(0 == ~T6_E~0); 105653#L1293-1 assume !(0 == ~T7_E~0); 105641#L1298-1 assume !(0 == ~T8_E~0); 105562#L1303-1 assume !(0 == ~T9_E~0); 104143#L1308-1 assume !(0 == ~T10_E~0); 104068#L1313-1 assume !(0 == ~T11_E~0); 104069#L1318-1 assume !(0 == ~T12_E~0); 104080#L1323-1 assume !(0 == ~T13_E~0); 104081#L1328-1 assume !(0 == ~E_1~0); 104263#L1333-1 assume !(0 == ~E_2~0); 105234#L1338-1 assume !(0 == ~E_3~0); 105235#L1343-1 assume !(0 == ~E_4~0); 105372#L1348-1 assume !(0 == ~E_5~0); 105695#L1353-1 assume !(0 == ~E_6~0); 104949#L1358-1 assume !(0 == ~E_7~0); 104950#L1363-1 assume !(0 == ~E_8~0); 105265#L1368-1 assume !(0 == ~E_9~0); 103869#L1373-1 assume !(0 == ~E_10~0); 103870#L1378-1 assume !(0 == ~E_11~0); 104216#L1383-1 assume !(0 == ~E_12~0); 104217#L1388-1 assume !(0 == ~E_13~0); 105361#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 105519#L607-15 assume !(1 == ~m_pc~0); 105326#L617-15 is_master_triggered_~__retres1~0#1 := 0; 105327#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 105222#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 105223#L1560-15 assume !(0 != activate_threads_~tmp~1#1); 104170#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103920#L626-15 assume !(1 == ~t1_pc~0); 103921#L636-15 is_transmit1_triggered_~__retres1~1#1 := 0; 104621#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104671#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 105503#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 105303#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105304#L645-15 assume !(1 == ~t2_pc~0); 105525#L655-15 is_transmit2_triggered_~__retres1~2#1 := 0; 104020#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104021#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 105441#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 104727#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 103694#L664-15 assume 1 == ~t3_pc~0; 103695#L665-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 105040#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104634#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103965#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 103966#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104392#L683-15 assume 1 == ~t4_pc~0; 104929#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 104888#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104889#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 105175#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 104790#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104791#L702-15 assume 1 == ~t5_pc~0; 105402#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 104735#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 105460#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 105521#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 104684#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103773#L721-15 assume 1 == ~t6_pc~0; 103774#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 103999#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 105602#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 104589#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 104590#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103839#L740-15 assume 1 == ~t7_pc~0; 103840#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 105316#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 104702#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 104703#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 105548#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 105549#L759-15 assume 1 == ~t8_pc~0; 105407#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 104384#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 105498#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 105218#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 105219#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 103939#L778-15 assume 1 == ~t9_pc~0; 103940#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 104445#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 104446#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 104082#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 104083#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 105182#L797-15 assume 1 == ~t10_pc~0; 104388#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 104389#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 105099#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104088#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 104089#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 104683#L816-15 assume 1 == ~t11_pc~0; 104647#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 104648#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 105247#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 104406#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 104407#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 105257#L835-15 assume 1 == ~t12_pc~0; 105297#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 105593#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 105591#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 104751#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 103720#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 103721#L854-15 assume 1 == ~t13_pc~0; 104577#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 104578#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 104045#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 104046#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 104449#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104833#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 104834#L1406-1 assume !(1 == ~T1_E~0); 105100#L1411-1 assume !(1 == ~T2_E~0); 105101#L1416-1 assume !(1 == ~T3_E~0); 104757#L1421-1 assume !(1 == ~T4_E~0); 104299#L1426-1 assume !(1 == ~T5_E~0); 104300#L1431-1 assume !(1 == ~T6_E~0); 103783#L1436-1 assume !(1 == ~T7_E~0); 103784#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 104618#L1446-1 assume !(1 == ~T9_E~0); 104619#L1451-1 assume !(1 == ~T10_E~0); 105367#L1456-1 assume !(1 == ~T11_E~0); 104980#L1461-1 assume !(1 == ~T12_E~0); 104526#L1466-1 assume !(1 == ~T13_E~0); 104527#L1471-1 assume !(1 == ~E_1~0); 105337#L1476-1 assume !(1 == ~E_2~0); 105338#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 105507#L1486-1 assume !(1 == ~E_4~0); 104163#L1491-1 assume !(1 == ~E_5~0); 103711#L1496-1 assume !(1 == ~E_6~0); 103712#L1501-1 assume !(1 == ~E_7~0); 104606#L1506-1 assume !(1 == ~E_8~0); 104607#L1511-1 assume !(1 == ~E_9~0); 104557#L1516-1 assume !(1 == ~E_10~0); 103670#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 103671#L1526-1 assume !(1 == ~E_12~0); 103710#L1531-1 assume !(1 == ~E_13~0); 104317#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 103771#L1892 [2024-11-17 08:54:04,632 INFO L747 eck$LassoCheckResult]: Loop: 103771#L1892 assume true; 103718#L1892-1 assume !false; 103719#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 104331#L1041 assume true; 104503#L1041-1 assume !false; 104504#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 105171#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 104227#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 105078#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 103761#L1046 assume !(0 != eval_~tmp~0#1); 103763#L1049 assume true; 116467#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 104117#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 104118#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 104146#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 104147#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 104542#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 104463#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 104464#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 104768#L1288 assume !(0 == ~T6_E~0); 104769#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 104171#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 104172#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 105739#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 105740#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 104453#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 104454#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 105657#L1328 assume !(0 == ~E_1~0); 105658#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 104066#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 104067#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 104030#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 104031#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 104348#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 105016#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 104632#L1368 assume !(0 == ~E_9~0); 104633#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 104447#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 104448#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 105472#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 105445#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104035#L607-1 assume !(1 == ~m_pc~0); 103930#L617-1 is_master_triggered_~__retres1~0#1 := 0; 103931#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103958#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 103959#L1560-1 assume !(0 != activate_threads_~tmp~1#1); 104253#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 105417#L626-1 assume !(1 == ~t1_pc~0); 105349#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 105350#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104971#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 104402#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 104403#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103882#L645-1 assume !(1 == ~t2_pc~0); 103883#L655-1 is_transmit2_triggered_~__retres1~2#1 := 0; 104812#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103837#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 103838#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 105446#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104017#L664-1 assume 1 == ~t3_pc~0; 104019#L665-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 104144#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104145#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 104752#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 105145#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 105251#L683-1 assume 1 == ~t4_pc~0; 105621#L684-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 105221#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 105194#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 104533#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 104534#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104712#L702-1 assume 1 == ~t5_pc~0; 104259#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 104260#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103989#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103990#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 105290#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 105291#L721-1 assume 1 == ~t6_pc~0; 105462#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 105463#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103642#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 103643#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 116707#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116706#L740-1 assume 1 == ~t7_pc~0; 105696#L741-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 105517#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103751#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 103752#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 105745#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 105659#L759-1 assume !(1 == ~t8_pc~0); 105661#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 103860#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 103861#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 105432#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 105133#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 104568#L778-1 assume 1 == ~t9_pc~0; 104569#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 104997#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 105227#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 105505#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 116627#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 116626#L797-1 assume 1 == ~t10_pc~0; 116625#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 116623#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 116622#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 116352#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 116351#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 116350#L816-1 assume 1 == ~t11_pc~0; 116349#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 116347#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 116345#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 116346#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 116417#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 116415#L835-1 assume 1 == ~t12_pc~0; 116413#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 116337#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 116338#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 103928#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 103929#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 116408#L854-1 assume !(1 == ~t13_pc~0); 105281#L864-1 is_transmit13_triggered_~__retres1~13#1 := 0; 105282#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 104661#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 104662#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 105065#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 105733#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 104531#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 104532#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 104871#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 104246#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 104098#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 104099#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 104756#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 105019#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 104327#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 104328#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 104187#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 104188#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 105678#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 105564#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 105151#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 105152#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 105662#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 105371#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 103820#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 103821#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 104290#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 104291#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 103664#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 103665#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 105609#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 104132#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 104133#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 105387#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 103916#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 103917#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 104628#L1911 assume !(0 == start_simulation_~tmp~3#1); 104587#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 104884#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 103935#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 103936#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 103888#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103889#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 104161#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 104162#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 103771#L1892 [2024-11-17 08:54:04,633 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:04,633 INFO L85 PathProgramCache]: Analyzing trace with hash -504801503, now seen corresponding path program 1 times [2024-11-17 08:54:04,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:04,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1954205844] [2024-11-17 08:54:04,634 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:04,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:04,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1954205844] [2024-11-17 08:54:04,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1954205844] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:04,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636574686] [2024-11-17 08:54:04,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,691 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:04,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:04,692 INFO L85 PathProgramCache]: Analyzing trace with hash 650532913, now seen corresponding path program 1 times [2024-11-17 08:54:04,692 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:04,692 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439547467] [2024-11-17 08:54:04,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:04,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:04,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,884 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439547467] [2024-11-17 08:54:04,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [439547467] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:04,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142672700] [2024-11-17 08:54:04,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,885 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:04,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:04,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:04,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:04,886 INFO L87 Difference]: Start difference. First operand 13338 states and 19035 transitions. cyclomatic complexity: 5705 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:05,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:05,096 INFO L93 Difference]: Finished difference Result 25589 states and 36376 transitions. [2024-11-17 08:54:05,096 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25589 states and 36376 transitions. [2024-11-17 08:54:05,237 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25348 [2024-11-17 08:54:05,352 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25589 states to 25589 states and 36376 transitions. [2024-11-17 08:54:05,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25589 [2024-11-17 08:54:05,384 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25589 [2024-11-17 08:54:05,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25589 states and 36376 transitions. [2024-11-17 08:54:05,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:05,411 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25589 states and 36376 transitions. [2024-11-17 08:54:05,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25589 states and 36376 transitions. [2024-11-17 08:54:05,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25589 to 25557. [2024-11-17 08:54:06,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25557 states, 25557 states have (on average 1.4220761435223226) internal successors, (36344), 25556 states have internal predecessors, (36344), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:06,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25557 states to 25557 states and 36344 transitions. [2024-11-17 08:54:06,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25557 states and 36344 transitions. [2024-11-17 08:54:06,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:06,204 INFO L425 stractBuchiCegarLoop]: Abstraction has 25557 states and 36344 transitions. [2024-11-17 08:54:06,204 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:54:06,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25557 states and 36344 transitions. [2024-11-17 08:54:06,388 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 25316 [2024-11-17 08:54:06,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:06,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:06,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:06,391 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:06,391 INFO L745 eck$LassoCheckResult]: Stem: 143511#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 143512#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 143310#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 143311#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 143975#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 143313#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143314#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143784#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 143520#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 143521#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144062#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 144063#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 143653#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 143654#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 143814#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 143369#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 143370#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 143112#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 143113#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 143684#L1258-1 assume !(0 == ~M_E~0); 143560#L1263-1 assume !(0 == ~T1_E~0); 143561#L1268-1 assume !(0 == ~T2_E~0); 143874#L1273-1 assume !(0 == ~T3_E~0); 144482#L1278-1 assume !(0 == ~T4_E~0); 144343#L1283-1 assume !(0 == ~T5_E~0); 144344#L1288-1 assume !(0 == ~T6_E~0); 144595#L1293-1 assume !(0 == ~T7_E~0); 144582#L1298-1 assume !(0 == ~T8_E~0); 144496#L1303-1 assume !(0 == ~T9_E~0); 143077#L1308-1 assume !(0 == ~T10_E~0); 143002#L1313-1 assume !(0 == ~T11_E~0); 143003#L1318-1 assume !(0 == ~T12_E~0); 143014#L1323-1 assume !(0 == ~T13_E~0); 143015#L1328-1 assume !(0 == ~E_1~0); 143201#L1333-1 assume !(0 == ~E_2~0); 144170#L1338-1 assume !(0 == ~E_3~0); 144171#L1343-1 assume !(0 == ~E_4~0); 144312#L1348-1 assume !(0 == ~E_5~0); 144631#L1353-1 assume !(0 == ~E_6~0); 143885#L1358-1 assume !(0 == ~E_7~0); 143886#L1363-1 assume !(0 == ~E_8~0); 144204#L1368-1 assume !(0 == ~E_9~0); 142804#L1373-1 assume !(0 == ~E_10~0); 142805#L1378-1 assume !(0 == ~E_11~0); 143151#L1383-1 assume !(0 == ~E_12~0); 143152#L1388-1 assume !(0 == ~E_13~0); 144303#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144455#L607-15 assume !(1 == ~m_pc~0); 144266#L617-15 is_master_triggered_~__retres1~0#1 := 0; 144267#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144158#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 144159#L1560-15 assume !(0 != activate_threads_~tmp~1#1); 143104#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 142857#L626-15 assume !(1 == ~t1_pc~0); 142858#L636-15 is_transmit1_triggered_~__retres1~1#1 := 0; 143557#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 143607#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 144442#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 144241#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144242#L645-15 assume !(1 == ~t2_pc~0); 144461#L655-15 is_transmit2_triggered_~__retres1~2#1 := 0; 142952#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 142953#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 144371#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 143663#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 142630#L664-15 assume !(1 == ~t3_pc~0); 142631#L674-15 is_transmit3_triggered_~__retres1~3#1 := 0; 143974#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 143570#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 142898#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 142899#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143330#L683-15 assume 1 == ~t4_pc~0; 143865#L684-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 143826#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143827#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 144110#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 143726#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 143727#L702-15 assume 1 == ~t5_pc~0; 144337#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 143671#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144394#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 144457#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 143620#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 142708#L721-15 assume 1 == ~t6_pc~0; 142709#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 142932#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 144538#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 143527#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 143528#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 142774#L740-15 assume 1 == ~t7_pc~0; 142775#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 144255#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 143638#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 143639#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 144484#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 144485#L759-15 assume 1 == ~t8_pc~0; 144342#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 143322#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 144435#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 144154#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 144155#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 142873#L778-15 assume 1 == ~t9_pc~0; 142874#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 143383#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 143384#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 143016#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 143017#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 144118#L797-15 assume 1 == ~t10_pc~0; 143326#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 143327#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 144033#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 143022#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 143023#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 143619#L816-15 assume 1 == ~t11_pc~0; 143584#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 143585#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 144183#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 143344#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 143345#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 144197#L835-15 assume 1 == ~t12_pc~0; 144235#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 144530#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 144526#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 143687#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 142655#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 142656#L854-15 assume 1 == ~t13_pc~0; 143515#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 143516#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 142978#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 142979#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 143387#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 143769#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 143770#L1406-1 assume !(1 == ~T1_E~0); 144034#L1411-1 assume !(1 == ~T2_E~0); 144035#L1416-1 assume !(1 == ~T3_E~0); 143693#L1421-1 assume !(1 == ~T4_E~0); 143237#L1426-1 assume !(1 == ~T5_E~0); 143238#L1431-1 assume !(1 == ~T6_E~0); 142718#L1436-1 assume !(1 == ~T7_E~0); 142719#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 143555#L1446-1 assume !(1 == ~T9_E~0); 143556#L1451-1 assume !(1 == ~T10_E~0); 144309#L1456-1 assume !(1 == ~T11_E~0); 143914#L1461-1 assume !(1 == ~T12_E~0); 143463#L1466-1 assume !(1 == ~T13_E~0); 143464#L1471-1 assume !(1 == ~E_1~0); 144278#L1476-1 assume !(1 == ~E_2~0); 144279#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 144445#L1486-1 assume !(1 == ~E_4~0); 143099#L1491-1 assume !(1 == ~E_5~0); 142646#L1496-1 assume !(1 == ~E_6~0); 142647#L1501-1 assume !(1 == ~E_7~0); 143543#L1506-1 assume !(1 == ~E_8~0); 143544#L1511-1 assume !(1 == ~E_9~0); 143494#L1516-1 assume !(1 == ~E_10~0); 142606#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 142607#L1526-1 assume !(1 == ~E_12~0); 142645#L1531-1 assume !(1 == ~E_13~0); 143255#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 144684#L1892 [2024-11-17 08:54:06,392 INFO L747 eck$LassoCheckResult]: Loop: 144684#L1892 assume true; 163887#L1892-1 assume !false; 163877#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 163870#L1041 assume true; 163865#L1041-1 assume !false; 163860#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 163581#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 163565#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 163559#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 163552#L1046 assume !(0 != eval_~tmp~0#1); 163553#L1049 assume true; 164541#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 164540#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 164539#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 164538#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 164537#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 164536#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 164535#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 164534#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 164533#L1288 assume !(0 == ~T6_E~0); 164532#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 164531#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 164530#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 164529#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 164528#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 164527#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 164526#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 164525#L1328 assume !(0 == ~E_1~0); 164524#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 164523#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 164522#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 164521#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 164520#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 164519#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 164518#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 164517#L1368 assume !(0 == ~E_9~0); 164516#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 164515#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 164514#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 164512#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 164510#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 164508#L607-1 assume !(1 == ~m_pc~0); 164506#L617-1 is_master_triggered_~__retres1~0#1 := 0; 164504#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 164502#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 164500#L1560-1 assume !(0 != activate_threads_~tmp~1#1); 164498#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 164496#L626-1 assume !(1 == ~t1_pc~0); 164494#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 164492#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 164490#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 164488#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 164486#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 164484#L645-1 assume !(1 == ~t2_pc~0); 164482#L655-1 is_transmit2_triggered_~__retres1~2#1 := 0; 164480#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 164478#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 164476#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 164474#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 164472#L664-1 assume !(1 == ~t3_pc~0); 164470#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 164468#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 164466#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 164464#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 164461#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 164459#L683-1 assume 1 == ~t4_pc~0; 164456#L684-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 164454#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 164452#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 164450#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 164447#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 164445#L702-1 assume !(1 == ~t5_pc~0); 164442#L712-1 is_transmit5_triggered_~__retres1~5#1 := 0; 164440#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164438#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 164436#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 164433#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 164431#L721-1 assume !(1 == ~t6_pc~0); 164428#L731-1 is_transmit6_triggered_~__retres1~6#1 := 0; 164426#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 164424#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 164422#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 164419#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 164417#L740-1 assume !(1 == ~t7_pc~0); 164414#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 164412#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 164410#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 164408#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 164405#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 164403#L759-1 assume 1 == ~t8_pc~0; 164400#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 164398#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 164396#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 164394#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 164391#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 164389#L778-1 assume !(1 == ~t9_pc~0); 164386#L788-1 is_transmit9_triggered_~__retres1~9#1 := 0; 164384#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 164382#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 164380#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 164377#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 164375#L797-1 assume !(1 == ~t10_pc~0); 164372#L807-1 is_transmit10_triggered_~__retres1~10#1 := 0; 164370#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 164368#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 164366#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 164363#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 164361#L816-1 assume !(1 == ~t11_pc~0); 164358#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 164356#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 164354#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 164352#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 164349#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 164347#L835-1 assume 1 == ~t12_pc~0; 164344#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 164342#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 164340#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 164338#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 164335#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 164333#L854-1 assume !(1 == ~t13_pc~0); 164330#L864-1 is_transmit13_triggered_~__retres1~13#1 := 0; 164328#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 164326#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 164324#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 164322#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 164320#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 164318#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 164316#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 164314#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 164312#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 164310#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 164308#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 164306#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 164304#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 164302#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 164300#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 164298#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 164296#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 164294#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 164292#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 164290#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 164288#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 164286#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 164284#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 164282#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 164280#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 164278#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 164276#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 164274#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 164272#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 164271#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 164270#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 164269#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 164042#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 164037#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 164035#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 164032#L1911 assume !(0 == start_simulation_~tmp~3#1); 164028#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 164016#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 164006#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 164004#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 164002#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 164000#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 163998#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 163995#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 144684#L1892 [2024-11-17 08:54:06,392 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:06,392 INFO L85 PathProgramCache]: Analyzing trace with hash -430779970, now seen corresponding path program 1 times [2024-11-17 08:54:06,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:06,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116253981] [2024-11-17 08:54:06,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:06,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:06,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:06,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:06,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:06,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2116253981] [2024-11-17 08:54:06,450 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2116253981] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:06,450 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:06,450 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:06,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1946750531] [2024-11-17 08:54:06,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:06,451 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:06,451 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:06,451 INFO L85 PathProgramCache]: Analyzing trace with hash -652056929, now seen corresponding path program 1 times [2024-11-17 08:54:06,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:06,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082822727] [2024-11-17 08:54:06,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:06,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:06,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:06,525 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:06,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:06,526 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082822727] [2024-11-17 08:54:06,527 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2082822727] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:06,527 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:06,527 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:06,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220417310] [2024-11-17 08:54:06,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:06,528 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:06,528 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:06,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:06,529 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:06,529 INFO L87 Difference]: Start difference. First operand 25557 states and 36344 transitions. cyclomatic complexity: 10803 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:06,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:06,962 INFO L93 Difference]: Finished difference Result 49128 states and 69613 transitions. [2024-11-17 08:54:06,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49128 states and 69613 transitions. [2024-11-17 08:54:07,317 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48784 [2024-11-17 08:54:07,513 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49128 states to 49128 states and 69613 transitions. [2024-11-17 08:54:07,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49128 [2024-11-17 08:54:07,551 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49128 [2024-11-17 08:54:07,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49128 states and 69613 transitions. [2024-11-17 08:54:07,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:07,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49128 states and 69613 transitions. [2024-11-17 08:54:07,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49128 states and 69613 transitions. [2024-11-17 08:54:08,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49128 to 49064. [2024-11-17 08:54:08,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49064 states, 49064 states have (on average 1.4175158976031306) internal successors, (69549), 49063 states have internal predecessors, (69549), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:08,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49064 states to 49064 states and 69549 transitions. [2024-11-17 08:54:08,474 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49064 states and 69549 transitions. [2024-11-17 08:54:08,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:08,490 INFO L425 stractBuchiCegarLoop]: Abstraction has 49064 states and 69549 transitions. [2024-11-17 08:54:08,490 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:54:08,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49064 states and 69549 transitions. [2024-11-17 08:54:08,656 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48720 [2024-11-17 08:54:08,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:08,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:08,659 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:08,660 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:08,660 INFO L745 eck$LassoCheckResult]: Stem: 218207#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 218208#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 218003#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 218004#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 218672#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 218006#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 218007#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 218481#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 218216#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 218217#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 218760#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 218761#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 218351#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 218352#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 218509#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 218063#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 218064#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 217808#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 217809#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 218382#L1258-1 assume !(0 == ~M_E~0); 218259#L1263-1 assume !(0 == ~T1_E~0); 218260#L1268-1 assume !(0 == ~T2_E~0); 218570#L1273-1 assume !(0 == ~T3_E~0); 219191#L1278-1 assume !(0 == ~T4_E~0); 219043#L1283-1 assume !(0 == ~T5_E~0); 219044#L1288-1 assume !(0 == ~T6_E~0); 219304#L1293-1 assume !(0 == ~T7_E~0); 219292#L1298-1 assume !(0 == ~T8_E~0); 219205#L1303-1 assume !(0 == ~T9_E~0); 217773#L1308-1 assume !(0 == ~T10_E~0); 217702#L1313-1 assume !(0 == ~T11_E~0); 217703#L1318-1 assume !(0 == ~T12_E~0); 217711#L1323-1 assume !(0 == ~T13_E~0); 217712#L1328-1 assume !(0 == ~E_1~0); 217893#L1333-1 assume !(0 == ~E_2~0); 218862#L1338-1 assume !(0 == ~E_3~0); 218863#L1343-1 assume !(0 == ~E_4~0); 219011#L1348-1 assume !(0 == ~E_5~0); 219348#L1353-1 assume !(0 == ~E_6~0); 218581#L1358-1 assume !(0 == ~E_7~0); 218582#L1363-1 assume !(0 == ~E_8~0); 218900#L1368-1 assume !(0 == ~E_9~0); 217499#L1373-1 assume !(0 == ~E_10~0); 217500#L1378-1 assume !(0 == ~E_11~0); 217845#L1383-1 assume !(0 == ~E_12~0); 217846#L1388-1 assume !(0 == ~E_13~0); 219000#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 219162#L607-15 assume !(1 == ~m_pc~0); 218959#L617-15 is_master_triggered_~__retres1~0#1 := 0; 218960#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 218852#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 218853#L1560-15 assume !(0 != activate_threads_~tmp~1#1); 217800#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 217553#L626-15 assume !(1 == ~t1_pc~0); 217554#L636-15 is_transmit1_triggered_~__retres1~1#1 := 0; 218256#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 218305#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 219145#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 218933#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 218934#L645-15 assume !(1 == ~t2_pc~0); 219168#L655-15 is_transmit2_triggered_~__retres1~2#1 := 0; 217650#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 217651#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 219079#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 218361#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 217325#L664-15 assume !(1 == ~t3_pc~0); 217326#L674-15 is_transmit3_triggered_~__retres1~3#1 := 0; 218671#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 218268#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 217595#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 217596#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 218024#L683-15 assume !(1 == ~t4_pc~0); 219269#L693-15 is_transmit4_triggered_~__retres1~4#1 := 0; 218521#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 218522#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 218807#L1592-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 218423#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 218424#L702-15 assume 1 == ~t5_pc~0; 219037#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 218369#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 219099#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 219164#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 218318#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 217403#L721-15 assume 1 == ~t6_pc~0; 217404#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 217629#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 219247#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 218224#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 218225#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 217469#L740-15 assume 1 == ~t7_pc~0; 217470#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 218948#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 218336#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 218337#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 219193#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 219194#L759-15 assume 1 == ~t8_pc~0; 219042#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 218015#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 219140#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 218848#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 218849#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 217569#L778-15 assume 1 == ~t9_pc~0; 217570#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 218077#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 218078#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 217713#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 217714#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 218811#L797-15 assume 1 == ~t10_pc~0; 218019#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 218020#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 218729#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 217719#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 217720#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 218317#L816-15 assume 1 == ~t11_pc~0; 218280#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 218281#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 218878#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 218038#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 218039#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 218892#L835-15 assume 1 == ~t12_pc~0; 218927#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 219240#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 219236#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 218385#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 217350#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 217351#L854-15 assume 1 == ~t13_pc~0; 218211#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 218212#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 217677#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 217678#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 218081#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 218466#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 218467#L1406-1 assume !(1 == ~T1_E~0); 218730#L1411-1 assume !(1 == ~T2_E~0); 218731#L1416-1 assume !(1 == ~T3_E~0); 218391#L1421-1 assume !(1 == ~T4_E~0); 217929#L1426-1 assume !(1 == ~T5_E~0); 217930#L1431-1 assume !(1 == ~T6_E~0); 217413#L1436-1 assume !(1 == ~T7_E~0); 217414#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 218253#L1446-1 assume !(1 == ~T9_E~0); 218254#L1451-1 assume !(1 == ~T10_E~0); 219006#L1456-1 assume !(1 == ~T11_E~0); 218613#L1461-1 assume !(1 == ~T12_E~0); 218158#L1466-1 assume !(1 == ~T13_E~0); 218159#L1471-1 assume !(1 == ~E_1~0); 218971#L1476-1 assume !(1 == ~E_2~0); 218972#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 219148#L1486-1 assume !(1 == ~E_4~0); 217793#L1491-1 assume !(1 == ~E_5~0); 217341#L1496-1 assume !(1 == ~E_6~0); 217342#L1501-1 assume !(1 == ~E_7~0); 218241#L1506-1 assume !(1 == ~E_8~0); 218242#L1511-1 assume !(1 == ~E_9~0); 218189#L1516-1 assume !(1 == ~E_10~0); 217300#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 217301#L1526-1 assume !(1 == ~E_12~0); 217340#L1531-1 assume !(1 == ~E_13~0); 217947#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 219410#L1892 [2024-11-17 08:54:08,661 INFO L747 eck$LassoCheckResult]: Loop: 219410#L1892 assume true; 232726#L1892-1 assume !false; 231874#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 231871#L1041 assume true; 231869#L1041-1 assume !false; 231867#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 231848#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 231838#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 231836#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 231833#L1046 assume !(0 != eval_~tmp~0#1); 231834#L1049 assume true; 233087#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 233085#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 233083#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 233081#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 233078#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 233076#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 233074#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 233072#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 233070#L1288 assume !(0 == ~T6_E~0); 233068#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 233065#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 233063#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 233061#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 233059#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 233057#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 233055#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 233052#L1328 assume !(0 == ~E_1~0); 233050#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 233048#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 233046#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 233044#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 233042#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 233039#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 233037#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 233035#L1368 assume !(0 == ~E_9~0); 233033#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 233031#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 233029#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 233026#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 233024#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 233022#L607-1 assume !(1 == ~m_pc~0); 233020#L617-1 is_master_triggered_~__retres1~0#1 := 0; 233018#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 233016#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 233013#L1560-1 assume !(0 != activate_threads_~tmp~1#1); 233011#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 233009#L626-1 assume !(1 == ~t1_pc~0); 233007#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 233005#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 233003#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 233001#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 232999#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 232997#L645-1 assume !(1 == ~t2_pc~0); 232995#L655-1 is_transmit2_triggered_~__retres1~2#1 := 0; 232993#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 232991#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 232989#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 232987#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 232985#L664-1 assume !(1 == ~t3_pc~0); 232983#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 232981#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 232979#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 232977#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 232975#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 232973#L683-1 assume !(1 == ~t4_pc~0); 232971#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 232969#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 232967#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 232965#L1592-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 232963#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 232961#L702-1 assume 1 == ~t5_pc~0; 232959#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 232956#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 232954#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 232952#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 232950#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 232949#L721-1 assume !(1 == ~t6_pc~0); 232947#L731-1 is_transmit6_triggered_~__retres1~6#1 := 0; 232946#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 232945#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 232944#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 232943#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 232942#L740-1 assume 1 == ~t7_pc~0; 232941#L741-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 232939#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 232938#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 232937#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 232936#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 232935#L759-1 assume !(1 == ~t8_pc~0); 232934#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 232932#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 232931#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 232930#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 232929#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 232927#L778-1 assume 1 == ~t9_pc~0; 232925#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 232922#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 232920#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 232918#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 232916#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 232914#L797-1 assume 1 == ~t10_pc~0; 232912#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 232909#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 232907#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 232905#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 232903#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 232901#L816-1 assume 1 == ~t11_pc~0; 232899#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 232896#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 232894#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 232892#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 232890#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 232888#L835-1 assume !(1 == ~t12_pc~0); 232886#L845-1 is_transmit12_triggered_~__retres1~12#1 := 0; 232883#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 232881#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 232879#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 232877#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 232875#L854-1 assume 1 == ~t13_pc~0; 232873#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 232870#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 232868#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 232866#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 232864#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 232862#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 232860#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 232858#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 232855#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 232853#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 232851#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 232849#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 232847#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 232845#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 232842#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 232840#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 232838#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 232836#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 232834#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 232832#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 232829#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 232827#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 232825#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 232823#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 232821#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 232819#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 232816#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 232814#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 232812#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 232810#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 232808#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 232806#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 232803#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 232777#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 232772#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 232770#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 232767#L1911 assume !(0 == start_simulation_~tmp~3#1); 232764#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 232751#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 232740#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 232738#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 232736#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 232734#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 232732#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 232729#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 219410#L1892 [2024-11-17 08:54:08,661 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:08,662 INFO L85 PathProgramCache]: Analyzing trace with hash 1805633051, now seen corresponding path program 1 times [2024-11-17 08:54:08,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:08,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483449123] [2024-11-17 08:54:08,662 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:08,662 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:08,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:08,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:08,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:08,750 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [483449123] [2024-11-17 08:54:08,750 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [483449123] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:08,750 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:08,750 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:08,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199510932] [2024-11-17 08:54:08,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:08,752 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:08,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:08,753 INFO L85 PathProgramCache]: Analyzing trace with hash -1340773688, now seen corresponding path program 1 times [2024-11-17 08:54:08,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:08,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364619050] [2024-11-17 08:54:08,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:08,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:08,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:08,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:08,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:08,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364619050] [2024-11-17 08:54:08,935 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364619050] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:08,935 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:08,935 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:08,935 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1323334785] [2024-11-17 08:54:08,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:08,936 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:08,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:08,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:54:08,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:54:08,937 INFO L87 Difference]: Start difference. First operand 49064 states and 69549 transitions. cyclomatic complexity: 20517 Second operand has 5 states, 5 states have (on average 31.8) internal successors, (159), 5 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:09,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:09,444 INFO L93 Difference]: Finished difference Result 49688 states and 69980 transitions. [2024-11-17 08:54:09,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49688 states and 69980 transitions. [2024-11-17 08:54:09,680 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 49344 [2024-11-17 08:54:10,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49688 states to 49688 states and 69980 transitions. [2024-11-17 08:54:10,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49688 [2024-11-17 08:54:10,118 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49688 [2024-11-17 08:54:10,119 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49688 states and 69980 transitions. [2024-11-17 08:54:10,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:10,165 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49688 states and 69980 transitions. [2024-11-17 08:54:10,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49688 states and 69980 transitions. [2024-11-17 08:54:10,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49688 to 49688. [2024-11-17 08:54:10,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49688 states, 49688 states have (on average 1.4083883432619546) internal successors, (69980), 49687 states have internal predecessors, (69980), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:11,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49688 states to 49688 states and 69980 transitions. [2024-11-17 08:54:11,015 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49688 states and 69980 transitions. [2024-11-17 08:54:11,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:54:11,016 INFO L425 stractBuchiCegarLoop]: Abstraction has 49688 states and 69980 transitions. [2024-11-17 08:54:11,016 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-17 08:54:11,016 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49688 states and 69980 transitions. [2024-11-17 08:54:11,138 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 49344 [2024-11-17 08:54:11,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:11,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:11,141 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:11,141 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:11,141 INFO L745 eck$LassoCheckResult]: Stem: 316964#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 316965#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 316766#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 316767#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 317439#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 316768#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 316769#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 317243#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 316976#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 316977#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 317526#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 317527#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 317112#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 317113#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 317272#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 316826#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 316827#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 316572#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 316573#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 317144#L1258-1 assume !(0 == ~M_E~0); 317020#L1263-1 assume !(0 == ~T1_E~0); 317021#L1268-1 assume !(0 == ~T2_E~0); 317335#L1273-1 assume !(0 == ~T3_E~0); 317934#L1278-1 assume !(0 == ~T4_E~0); 317803#L1283-1 assume !(0 == ~T5_E~0); 317804#L1288-1 assume !(0 == ~T6_E~0); 318043#L1293-1 assume !(0 == ~T7_E~0); 318033#L1298-1 assume !(0 == ~T8_E~0); 317947#L1303-1 assume !(0 == ~T9_E~0); 316536#L1308-1 assume !(0 == ~T10_E~0); 316460#L1313-1 assume !(0 == ~T11_E~0); 316461#L1318-1 assume !(0 == ~T12_E~0); 316473#L1323-1 assume !(0 == ~T13_E~0); 316474#L1328-1 assume !(0 == ~E_1~0); 316656#L1333-1 assume !(0 == ~E_2~0); 317633#L1338-1 assume !(0 == ~E_3~0); 317634#L1343-1 assume !(0 == ~E_4~0); 317774#L1348-1 assume !(0 == ~E_5~0); 318078#L1353-1 assume !(0 == ~E_6~0); 317346#L1358-1 assume !(0 == ~E_7~0); 317347#L1363-1 assume !(0 == ~E_8~0); 317666#L1368-1 assume !(0 == ~E_9~0); 316261#L1373-1 assume !(0 == ~E_10~0); 316262#L1378-1 assume !(0 == ~E_11~0); 316608#L1383-1 assume !(0 == ~E_12~0); 316609#L1388-1 assume !(0 == ~E_13~0); 317764#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 317908#L607-15 assume !(1 == ~m_pc~0); 317729#L617-15 is_master_triggered_~__retres1~0#1 := 0; 317730#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 317623#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 317624#L1560-15 assume !(0 != activate_threads_~tmp~1#1); 316564#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 316313#L626-15 assume !(1 == ~t1_pc~0); 316314#L636-15 is_transmit1_triggered_~__retres1~1#1 := 0; 317017#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 317064#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 317893#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 317705#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 317706#L645-15 assume !(1 == ~t2_pc~0); 317914#L655-15 is_transmit2_triggered_~__retres1~2#1 := 0; 316413#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 316414#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 317834#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 317122#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 316087#L664-15 assume !(1 == ~t3_pc~0); 316088#L674-15 is_transmit3_triggered_~__retres1~3#1 := 0; 317437#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 317030#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 316358#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 316359#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 316787#L683-15 assume !(1 == ~t4_pc~0); 318011#L693-15 is_transmit4_triggered_~__retres1~4#1 := 0; 317284#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 317285#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 317577#L1592-15 assume !(0 != activate_threads_~tmp___3~0#1); 317185#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 317186#L702-15 assume 1 == ~t5_pc~0; 317797#L703-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 317129#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 317850#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 317911#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 317078#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 316164#L721-15 assume 1 == ~t6_pc~0; 316165#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 316392#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 317990#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 316983#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 316984#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 316227#L740-15 assume 1 == ~t7_pc~0; 316228#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 317719#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 317097#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 317098#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 317935#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 317936#L759-15 assume 1 == ~t8_pc~0; 317801#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 316778#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 317887#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 317619#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 317620#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 316332#L778-15 assume 1 == ~t9_pc~0; 316333#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 316837#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 316838#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 316475#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 316476#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 317582#L797-15 assume 1 == ~t10_pc~0; 316782#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 316783#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 317497#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 316481#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 316482#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 317075#L816-15 assume 1 == ~t11_pc~0; 317041#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 317042#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 317649#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 316797#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 316798#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 317659#L835-15 assume 1 == ~t12_pc~0; 317699#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 317982#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 317979#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 317146#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 316112#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 316113#L854-15 assume 1 == ~t13_pc~0; 316970#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 316971#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 316438#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 316439#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 316844#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 317228#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 317229#L1406-1 assume !(1 == ~T1_E~0); 317498#L1411-1 assume !(1 == ~T2_E~0); 317499#L1416-1 assume !(1 == ~T3_E~0); 317153#L1421-1 assume !(1 == ~T4_E~0); 316692#L1426-1 assume !(1 == ~T5_E~0); 316693#L1431-1 assume !(1 == ~T6_E~0); 316175#L1436-1 assume !(1 == ~T7_E~0); 316176#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 317009#L1446-1 assume !(1 == ~T9_E~0); 317010#L1451-1 assume !(1 == ~T10_E~0); 317770#L1456-1 assume !(1 == ~T11_E~0); 317377#L1461-1 assume !(1 == ~T12_E~0); 316916#L1466-1 assume !(1 == ~T13_E~0); 316917#L1471-1 assume !(1 == ~E_1~0); 317739#L1476-1 assume !(1 == ~E_2~0); 317740#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 317895#L1486-1 assume !(1 == ~E_4~0); 316556#L1491-1 assume !(1 == ~E_5~0); 316103#L1496-1 assume !(1 == ~E_6~0); 316104#L1501-1 assume !(1 == ~E_7~0); 317002#L1506-1 assume !(1 == ~E_8~0); 317003#L1511-1 assume !(1 == ~E_9~0); 316948#L1516-1 assume !(1 == ~E_10~0); 316061#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 316062#L1526-1 assume !(1 == ~E_12~0); 316102#L1531-1 assume !(1 == ~E_13~0); 316711#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 318136#L1892 [2024-11-17 08:54:11,142 INFO L747 eck$LassoCheckResult]: Loop: 318136#L1892 assume true; 330602#L1892-1 assume !false; 330596#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 330594#L1041 assume true; 330593#L1041-1 assume !false; 330592#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 330580#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 330569#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 330567#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 330564#L1046 assume !(0 != eval_~tmp~0#1); 330565#L1049 assume true; 330969#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 330967#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 330965#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 330963#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 330960#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 330958#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 330956#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 330954#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 330952#L1288 assume !(0 == ~T6_E~0); 330950#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 330947#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 330945#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 330943#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 330941#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 330939#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 330937#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 330934#L1328 assume !(0 == ~E_1~0); 330932#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 330930#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 330928#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 330926#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 330924#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 330921#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 330919#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 330917#L1368 assume !(0 == ~E_9~0); 330915#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 330913#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 330911#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 330908#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 330906#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 330904#L607-1 assume !(1 == ~m_pc~0); 330902#L617-1 is_master_triggered_~__retres1~0#1 := 0; 330900#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 330898#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 330896#L1560-1 assume !(0 != activate_threads_~tmp~1#1); 330894#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 330892#L626-1 assume !(1 == ~t1_pc~0); 330890#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 330888#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 330886#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 330884#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 330882#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 330880#L645-1 assume !(1 == ~t2_pc~0); 330878#L655-1 is_transmit2_triggered_~__retres1~2#1 := 0; 330876#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 330874#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 330872#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 330870#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 330868#L664-1 assume !(1 == ~t3_pc~0); 330866#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 330864#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 330862#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 330860#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 330858#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 330856#L683-1 assume !(1 == ~t4_pc~0); 330854#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 330852#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 330850#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 330848#L1592-1 assume !(0 != activate_threads_~tmp___3~0#1); 330846#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 330845#L702-1 assume 1 == ~t5_pc~0; 330844#L703-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 330842#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 330841#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 330840#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 330839#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 330838#L721-1 assume 1 == ~t6_pc~0; 330837#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 330835#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 330834#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 330833#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 330832#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 330831#L740-1 assume !(1 == ~t7_pc~0); 330829#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 330828#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 330827#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 330826#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 330825#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 330824#L759-1 assume !(1 == ~t8_pc~0); 330823#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 330821#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 330819#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 330817#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 330815#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 330813#L778-1 assume 1 == ~t9_pc~0; 330811#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 330808#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 330806#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 330804#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 330802#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 330800#L797-1 assume !(1 == ~t10_pc~0); 330797#L807-1 is_transmit10_triggered_~__retres1~10#1 := 0; 330795#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 330793#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 330791#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 330789#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 330787#L816-1 assume 1 == ~t11_pc~0; 330785#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 330782#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 330780#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 330778#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 330776#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 330774#L835-1 assume !(1 == ~t12_pc~0); 330772#L845-1 is_transmit12_triggered_~__retres1~12#1 := 0; 330769#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 330767#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 330765#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 330763#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 330761#L854-1 assume 1 == ~t13_pc~0; 330759#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 330756#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 330754#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 330751#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 330749#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 330747#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 330745#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 330743#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 330741#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 330738#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 330736#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 330734#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 330732#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 330730#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 330728#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 330725#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 330723#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 330721#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 330719#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 330717#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 330715#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 330712#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 330710#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 330708#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 330706#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 330704#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 330702#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 330699#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 330697#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 330695#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 330693#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 330691#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 330689#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 330664#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 330658#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 330656#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 330653#L1911 assume !(0 == start_simulation_~tmp~3#1); 330650#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 330631#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 330621#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 330619#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 330617#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 330616#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 330613#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 330609#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 318136#L1892 [2024-11-17 08:54:11,142 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:11,143 INFO L85 PathProgramCache]: Analyzing trace with hash -1281416070, now seen corresponding path program 1 times [2024-11-17 08:54:11,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:11,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111587633] [2024-11-17 08:54:11,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:11,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:11,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:11,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:11,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:11,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111587633] [2024-11-17 08:54:11,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111587633] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:11,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:11,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:11,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570782146] [2024-11-17 08:54:11,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:11,199 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:11,199 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:11,199 INFO L85 PathProgramCache]: Analyzing trace with hash 273348548, now seen corresponding path program 1 times [2024-11-17 08:54:11,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:11,199 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1561694420] [2024-11-17 08:54:11,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:11,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:11,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:11,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:11,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:11,267 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1561694420] [2024-11-17 08:54:11,267 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1561694420] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:11,267 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:11,267 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:11,267 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283240425] [2024-11-17 08:54:11,267 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:11,268 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:11,268 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:11,268 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:11,268 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:11,268 INFO L87 Difference]: Start difference. First operand 49688 states and 69980 transitions. cyclomatic complexity: 20324 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:11,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:11,833 INFO L93 Difference]: Finished difference Result 95559 states and 134137 transitions. [2024-11-17 08:54:11,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95559 states and 134137 transitions. [2024-11-17 08:54:12,612 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 94976 [2024-11-17 08:54:12,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95559 states to 95559 states and 134137 transitions. [2024-11-17 08:54:12,939 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95559 [2024-11-17 08:54:13,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95559 [2024-11-17 08:54:13,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95559 states and 134137 transitions. [2024-11-17 08:54:13,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:13,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 95559 states and 134137 transitions. [2024-11-17 08:54:13,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95559 states and 134137 transitions. [2024-11-17 08:54:14,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95559 to 95431. [2024-11-17 08:54:14,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95431 states, 95431 states have (on average 1.4042501912376482) internal successors, (134009), 95430 states have internal predecessors, (134009), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:14,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95431 states to 95431 states and 134009 transitions. [2024-11-17 08:54:14,504 INFO L240 hiAutomatonCegarLoop]: Abstraction has 95431 states and 134009 transitions. [2024-11-17 08:54:14,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:14,505 INFO L425 stractBuchiCegarLoop]: Abstraction has 95431 states and 134009 transitions. [2024-11-17 08:54:14,505 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-17 08:54:14,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95431 states and 134009 transitions. [2024-11-17 08:54:14,734 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 94848 [2024-11-17 08:54:14,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:14,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:14,736 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:14,736 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:14,736 INFO L745 eck$LassoCheckResult]: Stem: 462226#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 462227#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 462025#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 462026#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 462701#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 462028#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 462029#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 462506#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 462235#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 462236#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 462796#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 462797#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 462373#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 462374#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 462534#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 462085#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 462086#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 461827#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 461828#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 462406#L1258-1 assume !(0 == ~M_E~0); 462279#L1263-1 assume !(0 == ~T1_E~0); 462280#L1268-1 assume !(0 == ~T2_E~0); 462591#L1273-1 assume !(0 == ~T3_E~0); 463222#L1278-1 assume !(0 == ~T4_E~0); 463079#L1283-1 assume !(0 == ~T5_E~0); 463080#L1288-1 assume !(0 == ~T6_E~0); 463338#L1293-1 assume !(0 == ~T7_E~0); 463325#L1298-1 assume !(0 == ~T8_E~0); 463238#L1303-1 assume !(0 == ~T9_E~0); 461791#L1308-1 assume !(0 == ~T10_E~0); 461718#L1313-1 assume !(0 == ~T11_E~0); 461719#L1318-1 assume !(0 == ~T12_E~0); 461727#L1323-1 assume !(0 == ~T13_E~0); 461728#L1328-1 assume !(0 == ~E_1~0); 461914#L1333-1 assume !(0 == ~E_2~0); 462904#L1338-1 assume !(0 == ~E_3~0); 462905#L1343-1 assume !(0 == ~E_4~0); 463045#L1348-1 assume !(0 == ~E_5~0); 463375#L1353-1 assume !(0 == ~E_6~0); 462603#L1358-1 assume !(0 == ~E_7~0); 462604#L1363-1 assume !(0 == ~E_8~0); 462938#L1368-1 assume !(0 == ~E_9~0); 461518#L1373-1 assume !(0 == ~E_10~0); 461519#L1378-1 assume !(0 == ~E_11~0); 461864#L1383-1 assume !(0 == ~E_12~0); 461865#L1388-1 assume !(0 == ~E_13~0); 463034#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 463199#L607-15 assume !(1 == ~m_pc~0); 462997#L617-15 is_master_triggered_~__retres1~0#1 := 0; 462998#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 462894#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 462895#L1560-15 assume !(0 != activate_threads_~tmp~1#1); 461819#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 461572#L626-15 assume !(1 == ~t1_pc~0); 461573#L636-15 is_transmit1_triggered_~__retres1~1#1 := 0; 462274#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 462325#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 463183#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 462973#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 462974#L645-15 assume !(1 == ~t2_pc~0); 463204#L655-15 is_transmit2_triggered_~__retres1~2#1 := 0; 461669#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 461670#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 463111#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 462383#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 461344#L664-15 assume !(1 == ~t3_pc~0); 461345#L674-15 is_transmit3_triggered_~__retres1~3#1 := 0; 462700#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 462288#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 461613#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 461614#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 462046#L683-15 assume !(1 == ~t4_pc~0); 463302#L693-15 is_transmit4_triggered_~__retres1~4#1 := 0; 462545#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 462546#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 462844#L1592-15 assume !(0 != activate_threads_~tmp___3~0#1); 462447#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 462448#L702-15 assume !(1 == ~t5_pc~0); 462390#L712-15 is_transmit5_triggered_~__retres1~5#1 := 0; 462391#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 463133#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 463200#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 462338#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 461422#L721-15 assume 1 == ~t6_pc~0; 461423#L722-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 461647#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 463276#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 462242#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 462243#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 461488#L740-15 assume 1 == ~t7_pc~0; 461489#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 462985#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 462356#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 462357#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 463224#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 463225#L759-15 assume 1 == ~t8_pc~0; 463077#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 462037#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 463177#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 462890#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 462891#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 461588#L778-15 assume 1 == ~t9_pc~0; 461589#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 462099#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 462100#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 461729#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 461730#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 462848#L797-15 assume 1 == ~t10_pc~0; 462041#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 462042#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 462760#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 461735#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 461736#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 462337#L816-15 assume 1 == ~t11_pc~0; 462301#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 462302#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 462917#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 462060#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 462061#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 462930#L835-15 assume 1 == ~t12_pc~0; 462967#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 463268#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 463264#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 462409#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 461369#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 461370#L854-15 assume 1 == ~t13_pc~0; 462230#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 462231#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 461692#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 461693#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 462103#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 462490#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 462491#L1406-1 assume !(1 == ~T1_E~0); 462761#L1411-1 assume !(1 == ~T2_E~0); 462762#L1416-1 assume !(1 == ~T3_E~0); 462415#L1421-1 assume !(1 == ~T4_E~0); 461950#L1426-1 assume !(1 == ~T5_E~0); 461951#L1431-1 assume !(1 == ~T6_E~0); 461432#L1436-1 assume !(1 == ~T7_E~0); 461433#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 462271#L1446-1 assume !(1 == ~T9_E~0); 462272#L1451-1 assume !(1 == ~T10_E~0); 463040#L1456-1 assume !(1 == ~T11_E~0); 462636#L1461-1 assume !(1 == ~T12_E~0); 462178#L1466-1 assume !(1 == ~T13_E~0); 462179#L1471-1 assume !(1 == ~E_1~0); 463008#L1476-1 assume !(1 == ~E_2~0); 463009#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 463186#L1486-1 assume !(1 == ~E_4~0); 461813#L1491-1 assume !(1 == ~E_5~0); 461360#L1496-1 assume !(1 == ~E_6~0); 461361#L1501-1 assume !(1 == ~E_7~0); 462259#L1506-1 assume !(1 == ~E_8~0); 462260#L1511-1 assume !(1 == ~E_9~0); 462209#L1516-1 assume !(1 == ~E_10~0); 461319#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 461320#L1526-1 assume !(1 == ~E_12~0); 461359#L1531-1 assume !(1 == ~E_13~0); 461969#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 463448#L1892 [2024-11-17 08:54:14,737 INFO L747 eck$LassoCheckResult]: Loop: 463448#L1892 assume true; 501474#L1892-1 assume !false; 501460#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 501438#L1041 assume true; 501428#L1041-1 assume !false; 501424#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 501418#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 501409#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 501408#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 501406#L1046 assume !(0 != eval_~tmp~0#1); 501407#L1049 assume true; 506389#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 506387#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 506385#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 506384#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 506383#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 506382#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 506381#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 506380#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 506379#L1288 assume !(0 == ~T6_E~0); 506378#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 506377#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 506376#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 506375#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 506374#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 506373#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 506372#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 506371#L1328 assume !(0 == ~E_1~0); 506369#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 506367#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 506365#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 506363#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 506360#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 506358#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 506356#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 506354#L1368 assume !(0 == ~E_9~0); 506352#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 506350#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 506347#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 506345#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 506343#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 506341#L607-1 assume !(1 == ~m_pc~0); 506339#L617-1 is_master_triggered_~__retres1~0#1 := 0; 506337#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 506334#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 506332#L1560-1 assume !(0 != activate_threads_~tmp~1#1); 506330#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 506328#L626-1 assume !(1 == ~t1_pc~0); 506326#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 506324#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 506321#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 506319#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 506317#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506315#L645-1 assume !(1 == ~t2_pc~0); 506313#L655-1 is_transmit2_triggered_~__retres1~2#1 := 0; 506311#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 506308#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 506306#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 506304#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 506302#L664-1 assume !(1 == ~t3_pc~0); 506300#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 506298#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 506295#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 506293#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 506291#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 506289#L683-1 assume !(1 == ~t4_pc~0); 506287#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 506285#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 506282#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 506280#L1592-1 assume !(0 != activate_threads_~tmp___3~0#1); 506278#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 506276#L702-1 assume !(1 == ~t5_pc~0); 506274#L712-1 is_transmit5_triggered_~__retres1~5#1 := 0; 506272#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 506269#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 506267#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 506265#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 506263#L721-1 assume 1 == ~t6_pc~0; 506261#L722-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 506259#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 506258#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 506256#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 506253#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 506251#L740-1 assume 1 == ~t7_pc~0; 506249#L741-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 506246#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 506244#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 506241#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 506240#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 506239#L759-1 assume !(1 == ~t8_pc~0); 506236#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 506233#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 506230#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 506227#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 506225#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 506222#L778-1 assume 1 == ~t9_pc~0; 506220#L779-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 506217#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 506215#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 506213#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 506211#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 506208#L797-1 assume 1 == ~t10_pc~0; 506206#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 506203#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 506201#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 506199#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 506197#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 506194#L816-1 assume 1 == ~t11_pc~0; 506192#L817-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 506189#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 506187#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 506185#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 506183#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 506180#L835-1 assume !(1 == ~t12_pc~0); 506178#L845-1 is_transmit12_triggered_~__retres1~12#1 := 0; 506175#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 506173#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 506171#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 506169#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 506166#L854-1 assume 1 == ~t13_pc~0; 506164#L855-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 506160#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 506158#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 506156#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 506154#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 506152#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 506150#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 506125#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 506120#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 506115#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 506107#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 506097#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 506088#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 506079#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 506070#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 506063#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 503364#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 503361#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 503359#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 503357#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 503355#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 503353#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 503351#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 503348#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 503346#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 503344#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 503315#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 503310#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 503304#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 503299#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 503294#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 503288#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 503283#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 501746#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 501738#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 501736#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 501733#L1911 assume !(0 == start_simulation_~tmp~3#1); 501730#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 501577#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 501567#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 501564#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 501562#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 501560#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 501558#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 501556#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 463448#L1892 [2024-11-17 08:54:14,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:14,738 INFO L85 PathProgramCache]: Analyzing trace with hash 559800983, now seen corresponding path program 1 times [2024-11-17 08:54:14,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:14,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [37072955] [2024-11-17 08:54:14,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:14,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:14,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:14,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:14,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:14,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [37072955] [2024-11-17 08:54:14,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [37072955] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:14,813 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:14,813 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:14,813 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267280780] [2024-11-17 08:54:14,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:14,813 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:14,814 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:14,814 INFO L85 PathProgramCache]: Analyzing trace with hash 263436519, now seen corresponding path program 1 times [2024-11-17 08:54:14,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:14,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [75958022] [2024-11-17 08:54:14,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:14,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:14,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:14,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:14,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:14,884 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [75958022] [2024-11-17 08:54:14,884 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [75958022] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:14,884 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:14,884 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:14,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769571912] [2024-11-17 08:54:14,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:14,885 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:14,885 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:14,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:14,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:14,886 INFO L87 Difference]: Start difference. First operand 95431 states and 134009 transitions. cyclomatic complexity: 38642 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:15,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:15,995 INFO L93 Difference]: Finished difference Result 183398 states and 256694 transitions. [2024-11-17 08:54:15,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 183398 states and 256694 transitions. [2024-11-17 08:54:17,203 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 182336 [2024-11-17 08:54:17,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 183398 states to 183398 states and 256694 transitions. [2024-11-17 08:54:17,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 183398 [2024-11-17 08:54:17,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 183398 [2024-11-17 08:54:17,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 183398 states and 256694 transitions. [2024-11-17 08:54:17,834 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:17,834 INFO L218 hiAutomatonCegarLoop]: Abstraction has 183398 states and 256694 transitions. [2024-11-17 08:54:17,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183398 states and 256694 transitions. [2024-11-17 08:54:20,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183398 to 183142. [2024-11-17 08:54:20,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 183142 states, 183142 states have (on average 1.400214041563377) internal successors, (256438), 183141 states have internal predecessors, (256438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:20,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183142 states to 183142 states and 256438 transitions. [2024-11-17 08:54:20,738 INFO L240 hiAutomatonCegarLoop]: Abstraction has 183142 states and 256438 transitions. [2024-11-17 08:54:20,738 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:20,739 INFO L425 stractBuchiCegarLoop]: Abstraction has 183142 states and 256438 transitions. [2024-11-17 08:54:20,739 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-17 08:54:20,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 183142 states and 256438 transitions. [2024-11-17 08:54:21,183 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 182080 [2024-11-17 08:54:21,183 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:21,183 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:21,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:21,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:21,185 INFO L745 eck$LassoCheckResult]: Stem: 741065#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 741066#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 740865#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 740866#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 741546#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 740867#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 740868#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 741349#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 741076#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 741077#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 741633#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 741634#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 741214#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 741215#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 741378#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 740927#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 740928#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 740662#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 740663#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 741249#L1258-1 assume !(0 == ~M_E~0); 741119#L1263-1 assume !(0 == ~T1_E~0); 741120#L1268-1 assume !(0 == ~T2_E~0); 741438#L1273-1 assume !(0 == ~T3_E~0); 742090#L1278-1 assume !(0 == ~T4_E~0); 741928#L1283-1 assume !(0 == ~T5_E~0); 741929#L1288-1 assume !(0 == ~T6_E~0); 742201#L1293-1 assume !(0 == ~T7_E~0); 742189#L1298-1 assume !(0 == ~T8_E~0); 742105#L1303-1 assume !(0 == ~T9_E~0); 740625#L1308-1 assume !(0 == ~T10_E~0); 740550#L1313-1 assume !(0 == ~T11_E~0); 740551#L1318-1 assume !(0 == ~T12_E~0); 740563#L1323-1 assume !(0 == ~T13_E~0); 740564#L1328-1 assume !(0 == ~E_1~0); 740750#L1333-1 assume !(0 == ~E_2~0); 741746#L1338-1 assume !(0 == ~E_3~0); 741747#L1343-1 assume !(0 == ~E_4~0); 741899#L1348-1 assume !(0 == ~E_5~0); 742239#L1353-1 assume !(0 == ~E_6~0); 741449#L1358-1 assume !(0 == ~E_7~0); 741450#L1363-1 assume !(0 == ~E_8~0); 741788#L1368-1 assume !(0 == ~E_9~0); 740352#L1373-1 assume !(0 == ~E_10~0); 740353#L1378-1 assume !(0 == ~E_11~0); 740702#L1383-1 assume !(0 == ~E_12~0); 740703#L1388-1 assume !(0 == ~E_13~0); 741888#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 742060#L607-15 assume !(1 == ~m_pc~0); 741853#L617-15 is_master_triggered_~__retres1~0#1 := 0; 741854#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 741734#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 741735#L1560-15 assume !(0 != activate_threads_~tmp~1#1); 740654#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 740404#L626-15 assume !(1 == ~t1_pc~0); 740405#L636-15 is_transmit1_triggered_~__retres1~1#1 := 0; 741114#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 741164#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 742044#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 741827#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 741828#L645-15 assume !(1 == ~t2_pc~0); 742067#L655-15 is_transmit2_triggered_~__retres1~2#1 := 0; 740502#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 740503#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 741964#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 741224#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 740182#L664-15 assume !(1 == ~t3_pc~0); 740183#L674-15 is_transmit3_triggered_~__retres1~3#1 := 0; 741544#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 741129#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 740449#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 740450#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 740888#L683-15 assume !(1 == ~t4_pc~0); 742167#L693-15 is_transmit4_triggered_~__retres1~4#1 := 0; 741389#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 741390#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 741685#L1592-15 assume !(0 != activate_threads_~tmp___3~0#1); 741291#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 741292#L702-15 assume !(1 == ~t5_pc~0); 741229#L712-15 is_transmit5_triggered_~__retres1~5#1 := 0; 741230#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 741986#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 742064#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 741179#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 740259#L721-15 assume !(1 == ~t6_pc~0); 740260#L731-15 is_transmit6_triggered_~__retres1~6#1 := 0; 740483#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 742145#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 741082#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 741083#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 740318#L740-15 assume 1 == ~t7_pc~0; 740319#L741-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 741842#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 741197#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 741198#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 742091#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 742092#L759-15 assume 1 == ~t8_pc~0; 741926#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 740879#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 742038#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 741730#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 741731#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 740423#L778-15 assume 1 == ~t9_pc~0; 740424#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 740938#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 740939#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 740565#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 740566#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 741689#L797-15 assume 1 == ~t10_pc~0; 740883#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 740884#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 741602#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 740571#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 740572#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 741176#L816-15 assume 1 == ~t11_pc~0; 741140#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 741141#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 741765#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 740898#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 740899#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 741777#L835-15 assume 1 == ~t12_pc~0; 741819#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 742135#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 742133#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 741251#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 740207#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 740208#L854-15 assume 1 == ~t13_pc~0; 741071#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 741072#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 740528#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 740529#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 740945#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 741335#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 741336#L1406-1 assume !(1 == ~T1_E~0); 741603#L1411-1 assume !(1 == ~T2_E~0); 741604#L1416-1 assume !(1 == ~T3_E~0); 741258#L1421-1 assume !(1 == ~T4_E~0); 740789#L1426-1 assume !(1 == ~T5_E~0); 740790#L1431-1 assume !(1 == ~T6_E~0); 740269#L1436-1 assume !(1 == ~T7_E~0); 740270#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 741107#L1446-1 assume !(1 == ~T9_E~0); 741108#L1451-1 assume !(1 == ~T10_E~0); 741895#L1456-1 assume !(1 == ~T11_E~0); 741478#L1461-1 assume !(1 == ~T12_E~0); 741017#L1466-1 assume !(1 == ~T13_E~0); 741018#L1471-1 assume !(1 == ~E_1~0); 741863#L1476-1 assume !(1 == ~E_2~0); 741864#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 742048#L1486-1 assume !(1 == ~E_4~0); 740647#L1491-1 assume !(1 == ~E_5~0); 740198#L1496-1 assume !(1 == ~E_6~0); 740199#L1501-1 assume !(1 == ~E_7~0); 741100#L1506-1 assume !(1 == ~E_8~0); 741101#L1511-1 assume !(1 == ~E_9~0); 741049#L1516-1 assume !(1 == ~E_10~0); 740155#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 740156#L1526-1 assume !(1 == ~E_12~0); 740197#L1531-1 assume !(1 == ~E_13~0); 740808#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 742311#L1892 [2024-11-17 08:54:21,186 INFO L747 eck$LassoCheckResult]: Loop: 742311#L1892 assume true; 829186#L1892-1 assume !false; 829178#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 829175#L1041 assume true; 829173#L1041-1 assume !false; 829170#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 829129#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 829116#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 829110#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 829103#L1046 assume !(0 != eval_~tmp~0#1); 829104#L1049 assume true; 905072#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 905070#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 905068#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 905065#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 905064#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 903567#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 903566#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 903565#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 903564#L1288 assume !(0 == ~T6_E~0); 903563#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 903561#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 903560#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 903559#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 903555#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 903553#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 903551#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 903549#L1328 assume !(0 == ~E_1~0); 903546#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 903544#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 903542#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 903539#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 903537#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 903535#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 903533#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 903531#L1368 assume !(0 == ~E_9~0); 903529#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 903528#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 903527#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 903525#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 903523#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 903521#L607-1 assume !(1 == ~m_pc~0); 903519#L617-1 is_master_triggered_~__retres1~0#1 := 0; 903517#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 903515#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 903513#L1560-1 assume !(0 != activate_threads_~tmp~1#1); 903511#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 903509#L626-1 assume !(1 == ~t1_pc~0); 903507#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 903505#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 903503#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 903501#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 903499#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 903497#L645-1 assume !(1 == ~t2_pc~0); 903495#L655-1 is_transmit2_triggered_~__retres1~2#1 := 0; 903493#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 903491#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 903489#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 903488#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 903487#L664-1 assume !(1 == ~t3_pc~0); 903485#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 903483#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 831857#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 831854#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 831852#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 831850#L683-1 assume !(1 == ~t4_pc~0); 831848#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 831846#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 831844#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 831842#L1592-1 assume !(0 != activate_threads_~tmp___3~0#1); 831840#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 831838#L702-1 assume !(1 == ~t5_pc~0); 831836#L712-1 is_transmit5_triggered_~__retres1~5#1 := 0; 831834#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 831830#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 831828#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 831826#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 831824#L721-1 assume !(1 == ~t6_pc~0); 831821#L731-1 is_transmit6_triggered_~__retres1~6#1 := 0; 831819#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 831817#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 831815#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 831813#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 831811#L740-1 assume !(1 == ~t7_pc~0); 831808#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 831806#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 831804#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 831802#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 831800#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 831798#L759-1 assume !(1 == ~t8_pc~0); 831796#L769-1 is_transmit8_triggered_~__retres1~8#1 := 0; 831793#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 831791#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 831788#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 831786#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 831784#L778-1 assume !(1 == ~t9_pc~0); 831781#L788-1 is_transmit9_triggered_~__retres1~9#1 := 0; 831779#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 831777#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 831774#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 831772#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 831770#L797-1 assume 1 == ~t10_pc~0; 831768#L798-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 831765#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 831763#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 831760#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 831758#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 831756#L816-1 assume !(1 == ~t11_pc~0); 831753#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 831751#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 831749#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 831746#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 831744#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 831742#L835-1 assume !(1 == ~t12_pc~0); 831740#L845-1 is_transmit12_triggered_~__retres1~12#1 := 0; 831737#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 831735#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 831732#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 831447#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 831441#L854-1 assume !(1 == ~t13_pc~0); 831434#L864-1 is_transmit13_triggered_~__retres1~13#1 := 0; 831424#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 831413#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 831404#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 831396#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 831389#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 831384#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 831381#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 831377#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 831373#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 831368#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 831361#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 831354#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 831347#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 831340#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 831334#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 831328#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 831321#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 831315#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 831310#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 831305#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 831300#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 831294#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 831287#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 831282#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 831277#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 831271#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 831265#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 831259#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 831252#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 831246#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 831242#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 831241#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 831230#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 831222#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 831217#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 831215#L1911 assume !(0 == start_simulation_~tmp~3#1); 830759#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 829935#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 829925#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 829923#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 829218#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 829208#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 829197#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 829193#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 742311#L1892 [2024-11-17 08:54:21,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:21,187 INFO L85 PathProgramCache]: Analyzing trace with hash -65488268, now seen corresponding path program 1 times [2024-11-17 08:54:21,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:21,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [67216088] [2024-11-17 08:54:21,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:21,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:21,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:21,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:21,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:21,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [67216088] [2024-11-17 08:54:21,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [67216088] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:21,260 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:21,260 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:21,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81939233] [2024-11-17 08:54:21,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:21,261 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:21,261 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:21,261 INFO L85 PathProgramCache]: Analyzing trace with hash 519551672, now seen corresponding path program 1 times [2024-11-17 08:54:21,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:21,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1281589628] [2024-11-17 08:54:21,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:21,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:21,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:21,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:21,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:21,327 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1281589628] [2024-11-17 08:54:21,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1281589628] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:21,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:21,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:21,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306246307] [2024-11-17 08:54:21,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:21,328 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:21,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:21,329 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:54:21,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:54:21,329 INFO L87 Difference]: Start difference. First operand 183142 states and 256438 transitions. cyclomatic complexity: 73424 Second operand has 4 states, 4 states have (on average 39.75) internal successors, (159), 3 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:24,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:24,318 INFO L93 Difference]: Finished difference Result 438661 states and 611699 transitions. [2024-11-17 08:54:24,318 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 438661 states and 611699 transitions. [2024-11-17 08:54:26,678 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 435584 [2024-11-17 08:54:27,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 438661 states to 438661 states and 611699 transitions. [2024-11-17 08:54:27,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 438661 [2024-11-17 08:54:28,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 438661 [2024-11-17 08:54:28,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 438661 states and 611699 transitions. [2024-11-17 08:54:28,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:28,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 438661 states and 611699 transitions. [2024-11-17 08:54:29,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438661 states and 611699 transitions. [2024-11-17 08:54:32,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438661 to 351269. [2024-11-17 08:54:32,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 351269 states, 351269 states have (on average 1.3966817453290783) internal successors, (490611), 351268 states have internal predecessors, (490611), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:33,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 351269 states to 351269 states and 490611 transitions. [2024-11-17 08:54:33,477 INFO L240 hiAutomatonCegarLoop]: Abstraction has 351269 states and 490611 transitions. [2024-11-17 08:54:33,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:54:33,478 INFO L425 stractBuchiCegarLoop]: Abstraction has 351269 states and 490611 transitions. [2024-11-17 08:54:33,478 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-17 08:54:33,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 351269 states and 490611 transitions. [2024-11-17 08:54:35,527 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 349312 [2024-11-17 08:54:35,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:35,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:35,530 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:35,530 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:35,530 INFO L745 eck$LassoCheckResult]: Stem: 1362886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1362887#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1362682#L1855 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1362683#L874-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1363358#L881 assume 1 == ~m_i~0;~m_st~0 := 0; 1362687#L886 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1362688#L891 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1363163#L896 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1362895#L901 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1362896#L906 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1363444#L911 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1363445#L916 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1363029#L921 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1363030#L926 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1363192#L931 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1362746#L936 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1362747#L941 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1362479#L946 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1362480#L952 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1363062#L1258-1 assume !(0 == ~M_E~0); 1362935#L1263-1 assume !(0 == ~T1_E~0); 1362936#L1268-1 assume !(0 == ~T2_E~0); 1363251#L1273-1 assume !(0 == ~T3_E~0); 1363883#L1278-1 assume !(0 == ~T4_E~0); 1363729#L1283-1 assume !(0 == ~T5_E~0); 1363730#L1288-1 assume !(0 == ~T6_E~0); 1363992#L1293-1 assume !(0 == ~T7_E~0); 1363981#L1298-1 assume !(0 == ~T8_E~0); 1363897#L1303-1 assume !(0 == ~T9_E~0); 1362439#L1308-1 assume !(0 == ~T10_E~0); 1362369#L1313-1 assume !(0 == ~T11_E~0); 1362370#L1318-1 assume !(0 == ~T12_E~0); 1362378#L1323-1 assume !(0 == ~T13_E~0); 1362379#L1328-1 assume !(0 == ~E_1~0); 1362570#L1333-1 assume !(0 == ~E_2~0); 1363549#L1338-1 assume !(0 == ~E_3~0); 1363550#L1343-1 assume !(0 == ~E_4~0); 1363696#L1348-1 assume !(0 == ~E_5~0); 1364029#L1353-1 assume !(0 == ~E_6~0); 1363263#L1358-1 assume !(0 == ~E_7~0); 1363264#L1363-1 assume !(0 == ~E_8~0); 1363586#L1368-1 assume !(0 == ~E_9~0); 1362169#L1373-1 assume !(0 == ~E_10~0); 1362170#L1378-1 assume !(0 == ~E_11~0); 1362518#L1383-1 assume !(0 == ~E_12~0); 1362519#L1388-1 assume !(0 == ~E_13~0); 1363687#L1394-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1363858#L607-15 assume !(1 == ~m_pc~0); 1363651#L617-15 is_master_triggered_~__retres1~0#1 := 0; 1363652#L610-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1363536#L619-15 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1363537#L1560-15 assume !(0 != activate_threads_~tmp~1#1); 1362471#L1566-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1362223#L626-15 assume !(1 == ~t1_pc~0); 1362224#L636-15 is_transmit1_triggered_~__retres1~1#1 := 0; 1362932#L629-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1362982#L638-15 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1363839#L1568-15 assume !(0 != activate_threads_~tmp___0~0#1); 1363622#L1574-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1363623#L645-15 assume !(1 == ~t2_pc~0); 1363864#L655-15 is_transmit2_triggered_~__retres1~2#1 := 0; 1362319#L648-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1362320#L657-15 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1363770#L1576-15 assume !(0 != activate_threads_~tmp___1~0#1); 1363038#L1582-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1361997#L664-15 assume !(1 == ~t3_pc~0); 1361998#L674-15 is_transmit3_triggered_~__retres1~3#1 := 0; 1363357#L667-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1362945#L676-15 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1362263#L1584-15 assume !(0 != activate_threads_~tmp___2~0#1); 1362264#L1590-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1362705#L683-15 assume !(1 == ~t4_pc~0); 1363960#L693-15 is_transmit4_triggered_~__retres1~4#1 := 0; 1363203#L686-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1363204#L695-15 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1363491#L1592-15 assume !(0 != activate_threads_~tmp___3~0#1); 1363104#L1598-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1363105#L702-15 assume !(1 == ~t5_pc~0); 1363044#L712-15 is_transmit5_triggered_~__retres1~5#1 := 0; 1363045#L705-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1363792#L714-15 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1363860#L1600-15 assume !(0 != activate_threads_~tmp___4~0#1); 1362995#L1606-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1362077#L721-15 assume !(1 == ~t6_pc~0); 1362078#L731-15 is_transmit6_triggered_~__retres1~6#1 := 0; 1362297#L724-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1363936#L733-15 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1362902#L1608-15 assume !(0 != activate_threads_~tmp___5~0#1); 1362903#L1614-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1362140#L740-15 assume !(1 == ~t7_pc~0); 1362141#L750-15 is_transmit7_triggered_~__retres1~7#1 := 0; 1363638#L743-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1363014#L752-15 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1363015#L1616-15 assume !(0 != activate_threads_~tmp___6~0#1); 1363885#L1622-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1363886#L759-15 assume 1 == ~t8_pc~0; 1363728#L760-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1362696#L762-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1363834#L771-15 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1363532#L1624-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1363533#L1630-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1362239#L778-15 assume 1 == ~t9_pc~0; 1362240#L779-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1362760#L781-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1362761#L790-15 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1362380#L1632-15 assume !(0 != activate_threads_~tmp___8~0#1); 1362381#L1638-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1363495#L797-15 assume 1 == ~t10_pc~0; 1362700#L798-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1362701#L800-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1363412#L809-15 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1362386#L1640-15 assume !(0 != activate_threads_~tmp___9~0#1); 1362387#L1646-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1362994#L816-15 assume 1 == ~t11_pc~0; 1362956#L817-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1362957#L819-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1363561#L828-15 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1362719#L1648-15 assume !(0 != activate_threads_~tmp___10~0#1); 1362720#L1654-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1363575#L835-15 assume 1 == ~t12_pc~0; 1363614#L836-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1363929#L838-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1363924#L847-15 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1363065#L1656-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1362022#L1662-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1362023#L854-15 assume 1 == ~t13_pc~0; 1362890#L855-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1362891#L857-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1362343#L866-15 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1362344#L1664-15 assume !(0 != activate_threads_~tmp___12~0#1); 1362764#L1670-15 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1363147#L1401-1 assume 1 == ~M_E~0;~M_E~0 := 2; 1363148#L1406-1 assume !(1 == ~T1_E~0); 1363413#L1411-1 assume !(1 == ~T2_E~0); 1363414#L1416-1 assume !(1 == ~T3_E~0); 1363071#L1421-1 assume !(1 == ~T4_E~0); 1362608#L1426-1 assume !(1 == ~T5_E~0); 1362609#L1431-1 assume !(1 == ~T6_E~0); 1362086#L1436-1 assume !(1 == ~T7_E~0); 1362087#L1441-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1362930#L1446-1 assume !(1 == ~T9_E~0); 1362931#L1451-1 assume !(1 == ~T10_E~0); 1363693#L1456-1 assume !(1 == ~T11_E~0); 1363292#L1461-1 assume !(1 == ~T12_E~0); 1362839#L1466-1 assume !(1 == ~T13_E~0); 1362840#L1471-1 assume !(1 == ~E_1~0); 1363661#L1476-1 assume !(1 == ~E_2~0); 1363662#L1481-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1363841#L1486-1 assume !(1 == ~E_4~0); 1362465#L1491-1 assume !(1 == ~E_5~0); 1362013#L1496-1 assume !(1 == ~E_6~0); 1362014#L1501-1 assume !(1 == ~E_7~0); 1362918#L1506-1 assume !(1 == ~E_8~0); 1362919#L1511-1 assume !(1 == ~E_9~0); 1362868#L1516-1 assume !(1 == ~E_10~0); 1361972#L1521-1 assume 1 == ~E_11~0;~E_11~0 := 2; 1361973#L1526-1 assume !(1 == ~E_12~0); 1362012#L1531-1 assume !(1 == ~E_13~0); 1362627#L1537-1 assume true;assume { :end_inline_reset_delta_events } true; 1364100#L1892 [2024-11-17 08:54:35,531 INFO L747 eck$LassoCheckResult]: Loop: 1364100#L1892 assume true; 1610658#L1892-1 assume !false; 1610231#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1610228#L1041 assume true; 1610226#L1041-1 assume !false; 1610224#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1570647#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1570637#L1013-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1570635#L1032-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1570632#L1046 assume !(0 != eval_~tmp~0#1); 1570633#L1049 assume true; 1611016#L1251 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1611014#L874 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1611013#L1258 assume 0 == ~M_E~0;~M_E~0 := 1; 1611011#L1263 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1611009#L1268 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1611007#L1273 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1611005#L1278 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1611003#L1283 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1611000#L1288 assume !(0 == ~T6_E~0); 1610998#L1293 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1610996#L1298 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1610994#L1303 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1610992#L1308 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1610990#L1313 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1610987#L1318 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1610985#L1323 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1610983#L1328 assume !(0 == ~E_1~0); 1610981#L1333 assume 0 == ~E_2~0;~E_2~0 := 1; 1610979#L1338 assume 0 == ~E_3~0;~E_3~0 := 1; 1610977#L1343 assume 0 == ~E_4~0;~E_4~0 := 1; 1610974#L1348 assume 0 == ~E_5~0;~E_5~0 := 1; 1610972#L1353 assume 0 == ~E_6~0;~E_6~0 := 1; 1610970#L1358 assume 0 == ~E_7~0;~E_7~0 := 1; 1610968#L1363 assume 0 == ~E_8~0;~E_8~0 := 1; 1610966#L1368 assume !(0 == ~E_9~0); 1610964#L1373 assume 0 == ~E_10~0;~E_10~0 := 1; 1610961#L1378 assume 0 == ~E_11~0;~E_11~0 := 1; 1610959#L1383 assume 0 == ~E_12~0;~E_12~0 := 1; 1610957#L1388 assume 0 == ~E_13~0;~E_13~0 := 1; 1610955#L1394 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1610953#L607-1 assume !(1 == ~m_pc~0); 1610951#L617-1 is_master_triggered_~__retres1~0#1 := 0; 1610948#L610-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1610946#L619-1 assume true;activate_threads_#t~ret19#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1610944#L1560-1 assume !(0 != activate_threads_~tmp~1#1); 1610942#L1566-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1610940#L626-1 assume !(1 == ~t1_pc~0); 1610938#L636-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1610935#L629-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1610933#L638-1 assume true;activate_threads_#t~ret20#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1610931#L1568-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1610929#L1574-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1610927#L645-1 assume !(1 == ~t2_pc~0); 1610925#L655-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1610923#L648-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1610921#L657-1 assume true;activate_threads_#t~ret21#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1610919#L1576-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1610917#L1582-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1610915#L664-1 assume !(1 == ~t3_pc~0); 1610913#L674-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1610911#L667-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1610909#L676-1 assume true;activate_threads_#t~ret22#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1610907#L1584-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1610905#L1590-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1610903#L683-1 assume !(1 == ~t4_pc~0); 1610901#L693-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1610899#L686-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1610897#L695-1 assume true;activate_threads_#t~ret23#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1610895#L1592-1 assume !(0 != activate_threads_~tmp___3~0#1); 1610893#L1598-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1610891#L702-1 assume !(1 == ~t5_pc~0); 1610889#L712-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1610887#L705-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1610885#L714-1 assume true;activate_threads_#t~ret24#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1610883#L1600-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1610881#L1606-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1610879#L721-1 assume !(1 == ~t6_pc~0); 1610877#L731-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1610875#L724-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1610873#L733-1 assume true;activate_threads_#t~ret25#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1610872#L1608-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1610871#L1614-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1610870#L740-1 assume !(1 == ~t7_pc~0); 1378673#L750-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1610869#L743-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1610868#L752-1 assume true;activate_threads_#t~ret26#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1610867#L1616-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1610866#L1622-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1610865#L759-1 assume 1 == ~t8_pc~0; 1610863#L760-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1610862#L762-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1610861#L771-1 assume true;activate_threads_#t~ret27#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1610860#L1624-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1610858#L1630-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1610856#L778-1 assume !(1 == ~t9_pc~0); 1610853#L788-1 is_transmit9_triggered_~__retres1~9#1 := 0; 1610851#L781-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1610849#L790-1 assume true;activate_threads_#t~ret28#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1610847#L1632-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1610845#L1638-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1610843#L797-1 assume !(1 == ~t10_pc~0); 1610840#L807-1 is_transmit10_triggered_~__retres1~10#1 := 0; 1610838#L800-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1610836#L809-1 assume true;activate_threads_#t~ret29#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1610834#L1640-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1610832#L1646-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1610830#L816-1 assume !(1 == ~t11_pc~0); 1610827#L826-1 is_transmit11_triggered_~__retres1~11#1 := 0; 1610825#L819-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1610823#L828-1 assume true;activate_threads_#t~ret30#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1610821#L1648-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1610819#L1654-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1610817#L835-1 assume 1 == ~t12_pc~0; 1610814#L836-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1610812#L838-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1610810#L847-1 assume true;activate_threads_#t~ret31#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1610808#L1656-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1610806#L1662-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1610804#L854-1 assume !(1 == ~t13_pc~0); 1610801#L864-1 is_transmit13_triggered_~__retres1~13#1 := 0; 1610799#L857-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1610797#L866-1 assume true;activate_threads_#t~ret32#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1610795#L1664-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1610793#L1670-1 assume true;havoc activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1610791#L1401 assume 1 == ~M_E~0;~M_E~0 := 2; 1610789#L1406 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1610787#L1411 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1610785#L1416 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1610783#L1421 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1610781#L1426 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1610779#L1431 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1610777#L1436 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1610775#L1441 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1610773#L1446 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1610771#L1451 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1610769#L1456 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1610767#L1461 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1610765#L1466 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1610764#L1471 assume 1 == ~E_1~0;~E_1~0 := 2; 1610762#L1476 assume 1 == ~E_2~0;~E_2~0 := 2; 1610760#L1481 assume 1 == ~E_3~0;~E_3~0 := 2; 1610758#L1486 assume 1 == ~E_4~0;~E_4~0 := 2; 1610756#L1491 assume 1 == ~E_5~0;~E_5~0 := 2; 1610754#L1496 assume 1 == ~E_6~0;~E_6~0 := 2; 1610751#L1501 assume 1 == ~E_7~0;~E_7~0 := 2; 1610749#L1506 assume 1 == ~E_8~0;~E_8~0 := 2; 1610747#L1511 assume 1 == ~E_9~0;~E_9~0 := 2; 1610745#L1516 assume 1 == ~E_10~0;~E_10~0 := 2; 1610743#L1521 assume 1 == ~E_11~0;~E_11~0 := 2; 1610741#L1526 assume 1 == ~E_12~0;~E_12~0 := 2; 1610738#L1531 assume 1 == ~E_13~0;~E_13~0 := 2; 1610736#L1537 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1610710#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1610705#L1013-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1610703#L1032-1 assume true;start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1610700#L1911 assume !(0 == start_simulation_~tmp~3#1); 1610696#L1922 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1610682#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1610672#L1013 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1610670#L1032 assume true;stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1610668#L1866 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1610665#L1868 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1610663#L1874 assume true;start_simulation_#t~ret35#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1610661#L1924 assume !(0 != start_simulation_~tmp___0~1#1); 1364100#L1892 [2024-11-17 08:54:35,532 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:35,532 INFO L85 PathProgramCache]: Analyzing trace with hash 1381366801, now seen corresponding path program 1 times [2024-11-17 08:54:35,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:35,532 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [248178485] [2024-11-17 08:54:35,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:35,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:35,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:35,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:35,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:35,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [248178485] [2024-11-17 08:54:35,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [248178485] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:35,605 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:35,606 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:35,606 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2057992807] [2024-11-17 08:54:35,606 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:35,606 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:35,607 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:35,607 INFO L85 PathProgramCache]: Analyzing trace with hash 884768603, now seen corresponding path program 1 times [2024-11-17 08:54:35,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:35,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500011611] [2024-11-17 08:54:35,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:35,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:35,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:35,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:35,699 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:35,699 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500011611] [2024-11-17 08:54:35,699 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500011611] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:35,699 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:35,699 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:35,699 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179583309] [2024-11-17 08:54:35,700 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:35,700 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:35,700 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:35,701 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:35,701 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:35,701 INFO L87 Difference]: Start difference. First operand 351269 states and 490611 transitions. cyclomatic complexity: 139470 Second operand has 3 states, 3 states have (on average 53.0) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:39,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:39,504 INFO L93 Difference]: Finished difference Result 673956 states and 938736 transitions. [2024-11-17 08:54:39,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 673956 states and 938736 transitions. [2024-11-17 08:54:42,756 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 669696 [2024-11-17 08:54:45,347 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 673956 states to 673956 states and 938736 transitions. [2024-11-17 08:54:45,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 673956 [2024-11-17 08:54:45,682 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 673956 [2024-11-17 08:54:45,682 INFO L73 IsDeterministic]: Start isDeterministic. Operand 673956 states and 938736 transitions.