./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 3289d67d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- This is Ultimate 0.2.5-tmp.fs.icfgbuilder-eval-3289d67-m [2024-11-17 08:53:51,763 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-17 08:53:51,829 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-17 08:53:51,837 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-17 08:53:51,839 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-17 08:53:51,839 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2024-11-17 08:53:51,864 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-17 08:53:51,865 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-17 08:53:51,865 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-17 08:53:51,866 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-17 08:53:51,866 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-17 08:53:51,869 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-17 08:53:51,869 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-17 08:53:51,873 INFO L153 SettingsManager]: * Use SBE=true [2024-11-17 08:53:51,873 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-17 08:53:51,873 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-17 08:53:51,874 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-17 08:53:51,874 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-17 08:53:51,874 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-17 08:53:51,874 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-17 08:53:51,875 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-17 08:53:51,875 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-17 08:53:51,876 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-17 08:53:51,876 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-17 08:53:51,879 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-17 08:53:51,879 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-17 08:53:51,880 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-17 08:53:51,880 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-17 08:53:51,880 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-17 08:53:51,880 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-17 08:53:51,881 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-17 08:53:51,881 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-17 08:53:51,881 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-17 08:53:51,881 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-17 08:53:51,881 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-17 08:53:51,882 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2024-11-17 08:53:51,882 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-17 08:53:51,882 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-17 08:53:51,883 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-17 08:53:51,885 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-17 08:53:51,885 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2024-11-17 08:53:52,174 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-17 08:53:52,201 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-17 08:53:52,204 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-17 08:53:52,205 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-17 08:53:52,206 INFO L274 PluginConnector]: CDTParser initialized [2024-11-17 08:53:52,207 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.16.cil.c [2024-11-17 08:53:53,716 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-17 08:53:53,953 INFO L384 CDTParser]: Found 1 translation units. [2024-11-17 08:53:53,954 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.16.cil.c [2024-11-17 08:53:53,969 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e8b457923/4d3ed6191a8241cf833cec6208176aec/FLAG21046224c [2024-11-17 08:53:54,295 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e8b457923/4d3ed6191a8241cf833cec6208176aec [2024-11-17 08:53:54,298 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-17 08:53:54,299 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-17 08:53:54,300 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:54,300 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-17 08:53:54,305 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-17 08:53:54,306 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:54,307 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5846cbff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54, skipping insertion in model container [2024-11-17 08:53:54,307 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:54,356 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-17 08:53:54,662 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:54,676 INFO L200 MainTranslator]: Completed pre-run [2024-11-17 08:53:54,789 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-17 08:53:54,819 INFO L204 MainTranslator]: Completed translation [2024-11-17 08:53:54,820 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54 WrapperNode [2024-11-17 08:53:54,820 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-17 08:53:54,821 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:54,821 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-17 08:53:54,821 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-17 08:53:54,827 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:54,845 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:54,961 INFO L138 Inliner]: procedures = 56, calls = 72, calls flagged for inlining = 67, calls inlined = 304, statements flattened = 4727 [2024-11-17 08:53:54,968 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-17 08:53:54,969 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-17 08:53:54,969 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-17 08:53:54,969 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-17 08:53:54,989 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:54,990 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:55,016 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:55,070 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-17 08:53:55,074 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:55,075 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:55,131 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:55,138 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:55,150 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:55,163 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:55,181 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-17 08:53:55,183 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2024-11-17 08:53:55,183 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2024-11-17 08:53:55,184 INFO L274 PluginConnector]: IcfgBuilder initialized [2024-11-17 08:53:55,184 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (1/1) ... [2024-11-17 08:53:55,190 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-17 08:53:55,201 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-17 08:53:55,220 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-17 08:53:55,223 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-17 08:53:55,270 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-17 08:53:55,270 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-17 08:53:55,271 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-17 08:53:55,271 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-17 08:53:55,489 INFO L256 CfgBuilder]: Building ICFG [2024-11-17 08:53:55,491 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-17 08:53:58,547 INFO L? ?]: Removed 1014 outVars from TransFormulas that were not future-live. [2024-11-17 08:53:58,547 INFO L307 CfgBuilder]: Performing block encoding [2024-11-17 08:53:58,601 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-17 08:53:58,605 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2024-11-17 08:53:58,606 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:58 BoogieIcfgContainer [2024-11-17 08:53:58,606 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2024-11-17 08:53:58,607 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-17 08:53:58,609 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-17 08:53:58,613 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-17 08:53:58,614 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:58,614 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 17.11 08:53:54" (1/3) ... [2024-11-17 08:53:58,615 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a17be7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:58, skipping insertion in model container [2024-11-17 08:53:58,615 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:58,615 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 17.11 08:53:54" (2/3) ... [2024-11-17 08:53:58,615 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2a17be7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 17.11 08:53:58, skipping insertion in model container [2024-11-17 08:53:58,615 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-17 08:53:58,615 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 17.11 08:53:58" (3/3) ... [2024-11-17 08:53:58,618 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.16.cil.c [2024-11-17 08:53:58,709 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-17 08:53:58,709 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-17 08:53:58,710 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-17 08:53:58,710 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-17 08:53:58,710 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-17 08:53:58,710 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-17 08:53:58,711 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-17 08:53:58,711 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-17 08:53:58,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2138 states, 2137 states have (on average 1.4796443612540946) internal successors, (3162), 2137 states have internal predecessors, (3162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:58,826 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1948 [2024-11-17 08:53:58,826 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:58,827 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:58,850 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:58,851 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:58,851 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-17 08:53:58,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2138 states, 2137 states have (on average 1.4796443612540946) internal successors, (3162), 2137 states have internal predecessors, (3162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:58,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1948 [2024-11-17 08:53:58,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:58,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:58,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:58,884 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:58,897 INFO L745 eck$LassoCheckResult]: Stem: 510#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1057#ULTIMATE.init_returnLabel#1true assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 992#L1980true assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 521#L932-1true assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1997#L939true assume !(1 == ~m_i~0);~m_st~0 := 2; 640#L944true assume !(1 == ~t1_i~0);~t1_st~0 := 2; 165#L949true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1034#L954true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 729#L959true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1631#L964true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 136#L969true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1598#L974true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1679#L979true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1579#L984true assume !(1 == ~t9_i~0);~t9_st~0 := 2; 418#L989true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1016#L994true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1022#L999true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1424#L1004true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 1166#L1009true assume !(1 == ~t14_i~0);~t14_st~0 := 2; 383#L1015true assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 760#L1342-1true assume !(0 == ~M_E~0); 1647#L1347-1true assume !(0 == ~T1_E~0); 1329#L1352-1true assume !(0 == ~T2_E~0); 1092#L1357-1true assume !(0 == ~T3_E~0); 459#L1362-1true assume !(0 == ~T4_E~0); 1417#L1367-1true assume !(0 == ~T5_E~0); 205#L1372-1true assume !(0 == ~T6_E~0); 574#L1377-1true assume !(0 == ~T7_E~0); 406#L1382-1true assume !(0 == ~T8_E~0); 972#L1387-1true assume !(0 == ~T9_E~0); 1555#L1392-1true assume !(0 == ~T10_E~0); 429#L1397-1true assume !(0 == ~T11_E~0); 1738#L1402-1true assume !(0 == ~T12_E~0); 210#L1407-1true assume !(0 == ~T13_E~0); 1937#L1412-1true assume !(0 == ~T14_E~0); 1216#L1417-1true assume !(0 == ~E_1~0); 2136#L1422-1true assume !(0 == ~E_2~0); 1735#L1427-1true assume !(0 == ~E_3~0); 325#L1432-1true assume !(0 == ~E_4~0); 1568#L1437-1true assume !(0 == ~E_5~0); 1140#L1442-1true assume !(0 == ~E_6~0); 1494#L1447-1true assume !(0 == ~E_7~0); 961#L1452-1true assume !(0 == ~E_8~0); 87#L1457-1true assume !(0 == ~E_9~0); 1174#L1462-1true assume !(0 == ~E_10~0); 1931#L1467-1true assume !(0 == ~E_11~0); 1190#L1472-1true assume !(0 == ~E_12~0); 1388#L1477-1true assume !(0 == ~E_13~0); 909#L1482-1true assume !(0 == ~E_14~0); 287#L1488-1true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 871#L646-15true assume 1 == ~m_pc~0; 1449#L647-15true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 465#L649-15true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 734#L658-15true assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1159#L1666-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 148#L1672-15true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1071#L665-15true assume 1 == ~t1_pc~0; 52#L666-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 524#L668-15true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1756#L677-15true assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1515#L1674-15true assume !(0 != activate_threads_~tmp___0~0#1); 1508#L1680-15true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 774#L684-15true assume 1 == ~t2_pc~0; 1608#L685-15true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 636#L687-15true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1533#L696-15true assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1241#L1682-15true assume !(0 != activate_threads_~tmp___1~0#1); 2134#L1688-15true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1236#L703-15true assume 1 == ~t3_pc~0; 812#L704-15true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 989#L706-15true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 519#L715-15true assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1824#L1690-15true assume !(0 != activate_threads_~tmp___2~0#1); 1334#L1696-15true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2060#L722-15true assume 1 == ~t4_pc~0; 536#L723-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1492#L725-15true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1772#L734-15true assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 681#L1698-15true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1673#L1704-15true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2139#L741-15true assume 1 == ~t5_pc~0; 365#L742-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 550#L744-15true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 881#L753-15true assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1550#L1706-15true assume !(0 != activate_threads_~tmp___4~0#1); 270#L1712-15true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1240#L760-15true assume 1 == ~t6_pc~0; 899#L761-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1078#L763-15true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 561#L772-15true assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 854#L1714-15true assume !(0 != activate_threads_~tmp___5~0#1); 280#L1720-15true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1198#L779-15true assume 1 == ~t7_pc~0; 988#L780-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 836#L782-15true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 202#L791-15true assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2091#L1722-15true assume !(0 != activate_threads_~tmp___6~0#1); 1908#L1728-15true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 391#L798-15true assume 1 == ~t8_pc~0; 1731#L799-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1945#L801-15true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2120#L810-15true assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1314#L1730-15true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1225#L1736-15true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 565#L817-15true assume 1 == ~t9_pc~0; 1170#L818-15true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1104#L820-15true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 938#L829-15true assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1930#L1738-15true assume !(0 != activate_threads_~tmp___8~0#1); 1610#L1744-15true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1919#L836-15true assume 1 == ~t10_pc~0; 825#L837-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 183#L839-15true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 562#L848-15true assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1696#L1746-15true assume !(0 != activate_threads_~tmp___9~0#1); 1461#L1752-15true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 516#L855-15true assume 1 == ~t11_pc~0; 533#L856-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1843#L858-15true assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1284#L867-15true assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 933#L1754-15true assume !(0 != activate_threads_~tmp___10~0#1); 959#L1760-15true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3#L874-15true assume 1 == ~t12_pc~0; 1458#L875-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1628#L877-15true assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 752#L886-15true assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1858#L1762-15true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 447#L1768-15true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13#L893-15true assume 1 == ~t13_pc~0; 312#L894-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1062#L896-15true assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 832#L905-15true assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1443#L1770-15true assume !(0 != activate_threads_~tmp___12~0#1); 850#L1776-15true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 387#L912-15true assume 1 == ~t14_pc~0; 987#L913-15true assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1972#L915-15true assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1580#L924-15true assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1718#L1778-15true assume !(0 != activate_threads_~tmp___13~0#1); 891#L1784-15true assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 392#L1495-1true assume !(1 == ~M_E~0); 1726#L1500-1true assume !(1 == ~T1_E~0); 722#L1505-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1987#L1510-1true assume !(1 == ~T3_E~0); 766#L1515-1true assume !(1 == ~T4_E~0); 1789#L1520-1true assume !(1 == ~T5_E~0); 1423#L1525-1true assume !(1 == ~T6_E~0); 1047#L1530-1true assume !(1 == ~T7_E~0); 247#L1535-1true assume !(1 == ~T8_E~0); 1910#L1540-1true assume !(1 == ~T9_E~0); 12#L1545-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 2056#L1550-1true assume !(1 == ~T11_E~0); 106#L1555-1true assume !(1 == ~T12_E~0); 277#L1560-1true assume !(1 == ~T13_E~0); 1764#L1565-1true assume !(1 == ~T14_E~0); 2005#L1570-1true assume !(1 == ~E_1~0); 927#L1575-1true assume !(1 == ~E_2~0); 462#L1580-1true assume !(1 == ~E_3~0); 780#L1585-1true assume 1 == ~E_4~0;~E_4~0 := 2; 1064#L1590-1true assume !(1 == ~E_5~0); 488#L1595-1true assume !(1 == ~E_6~0); 1967#L1600-1true assume !(1 == ~E_7~0); 727#L1605-1true assume !(1 == ~E_8~0); 1697#L1610-1true assume !(1 == ~E_9~0); 1260#L1615-1true assume !(1 == ~E_10~0); 360#L1620-1true assume !(1 == ~E_11~0); 1120#L1625-1true assume 1 == ~E_12~0;~E_12~0 := 2; 963#L1630-1true assume !(1 == ~E_13~0); 487#L1635-1true assume !(1 == ~E_14~0); 44#L1641-1true assume true;assume { :end_inline_reset_delta_events } true; 609#L2017true [2024-11-17 08:53:58,900 INFO L747 eck$LassoCheckResult]: Loop: 609#L2017true assume true; 869#L2017-1true assume !false; 339#start_simulation_while_16_continue#1true assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 962#L1110true assume !true; 1052#L1118true assume true; 1737#L1335true assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 319#L932true assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 101#L1342true assume 0 == ~M_E~0;~M_E~0 := 1; 713#L1347true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1965#L1352true assume 0 == ~T2_E~0;~T2_E~0 := 1; 223#L1357true assume !(0 == ~T3_E~0); 911#L1362true assume 0 == ~T4_E~0;~T4_E~0 := 1; 814#L1367true assume 0 == ~T5_E~0;~T5_E~0 := 1; 919#L1372true assume 0 == ~T6_E~0;~T6_E~0 := 1; 2096#L1377true assume 0 == ~T7_E~0;~T7_E~0 := 1; 526#L1382true assume 0 == ~T8_E~0;~T8_E~0 := 1; 810#L1387true assume 0 == ~T9_E~0;~T9_E~0 := 1; 266#L1392true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1994#L1397true assume !(0 == ~T11_E~0); 1218#L1402true assume 0 == ~T12_E~0;~T12_E~0 := 1; 56#L1407true assume 0 == ~T13_E~0;~T13_E~0 := 1; 284#L1412true assume 0 == ~T14_E~0;~T14_E~0 := 1; 2077#L1417true assume 0 == ~E_1~0;~E_1~0 := 1; 416#L1422true assume 0 == ~E_2~0;~E_2~0 := 1; 1990#L1427true assume 0 == ~E_3~0;~E_3~0 := 1; 1242#L1432true assume 0 == ~E_4~0;~E_4~0 := 1; 628#L1437true assume !(0 == ~E_5~0); 1432#L1442true assume 0 == ~E_6~0;~E_6~0 := 1; 1317#L1447true assume 0 == ~E_7~0;~E_7~0 := 1; 272#L1452true assume 0 == ~E_8~0;~E_8~0 := 1; 670#L1457true assume 0 == ~E_9~0;~E_9~0 := 1; 2021#L1462true assume 0 == ~E_10~0;~E_10~0 := 1; 601#L1467true assume 0 == ~E_11~0;~E_11~0 := 1; 1682#L1472true assume 0 == ~E_12~0;~E_12~0 := 1; 952#L1477true assume !(0 == ~E_13~0); 137#L1482true assume 0 == ~E_14~0;~E_14~0 := 1; 1687#L1488true assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1722#L646-1true assume !(1 == ~m_pc~0); 915#L656-1true is_master_triggered_~__retres1~0#1 := 0; 1354#L649-1true assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2000#L658-1true assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1780#L1666-1true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1818#L1672-1true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1319#L665-1true assume !(1 == ~t1_pc~0); 719#L675-1true is_transmit1_triggered_~__retres1~1#1 := 0; 616#L668-1true assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1156#L677-1true assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 218#L1674-1true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2015#L1680-1true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1664#L684-1true assume !(1 == ~t2_pc~0); 1015#L694-1true is_transmit2_triggered_~__retres1~2#1 := 0; 875#L687-1true assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 861#L696-1true assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1499#L1682-1true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 971#L1688-1true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 286#L703-1true assume 1 == ~t3_pc~0; 811#L704-1true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 944#L706-1true assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1237#L715-1true assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1897#L1690-1true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2035#L1696-1true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1326#L722-1true assume !(1 == ~t4_pc~0); 445#L732-1true is_transmit4_triggered_~__retres1~4#1 := 0; 1788#L725-1true assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2036#L734-1true assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 677#L1698-1true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1289#L1704-1true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1834#L741-1true assume !(1 == ~t5_pc~0); 126#L751-1true is_transmit5_triggered_~__retres1~5#1 := 0; 1701#L744-1true assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 219#L753-1true assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 212#L1706-1true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 637#L1712-1true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1893#L760-1true assume 1 == ~t6_pc~0; 1678#L761-1true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 900#L763-1true assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 917#L772-1true assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1584#L1714-1true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 538#L1720-1true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 816#L779-1true assume !(1 == ~t7_pc~0); 1472#L789-1true is_transmit7_triggered_~__retres1~7#1 := 0; 703#L782-1true assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32#L791-1true assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 947#L1722-1true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 699#L1728-1true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1849#L798-1true assume 1 == ~t8_pc~0; 1010#L799-1true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 425#L801-1true assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1412#L810-1true assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 135#L1730-1true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 946#L1736-1true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1490#L817-1true assume !(1 == ~t9_pc~0); 1415#L827-1true is_transmit9_triggered_~__retres1~9#1 := 0; 298#L820-1true assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1005#L829-1true assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1771#L1738-1true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1439#L1744-1true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1295#L836-1true assume 1 == ~t10_pc~0; 1611#L837-1true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1136#L839-1true assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1131#L848-1true assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 796#L1746-1true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1489#L1752-1true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2012#L855-1true assume 1 == ~t11_pc~0; 1178#L856-1true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 329#L858-1true assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 241#L867-1true assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1553#L1754-1true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 848#L1760-1true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 882#L874-1true assume 1 == ~t12_pc~0; 1411#L875-1true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1541#L877-1true assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1509#L886-1true assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 132#L1762-1true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 499#L1768-1true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 450#L893-1true assume 1 == ~t13_pc~0; 179#L894-1true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1500#L896-1true assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 303#L905-1true assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1560#L1770-1true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1476#L1776-1true assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 540#L912-1true assume 1 == ~t14_pc~0; 1622#L913-1true assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1934#L915-1true assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1268#L924-1true assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 275#L1778-1true assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 327#L1784-1true assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1367#L1495true assume 1 == ~M_E~0;~M_E~0 := 2; 170#L1500true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1706#L1505true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1565#L1510true assume 1 == ~T3_E~0;~T3_E~0 := 2; 436#L1515true assume 1 == ~T4_E~0;~T4_E~0 := 2; 667#L1520true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1465#L1525true assume 1 == ~T6_E~0;~T6_E~0 := 2; 337#L1530true assume 1 == ~T7_E~0;~T7_E~0 := 2; 627#L1535true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1614#L1540true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1960#L1545true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1861#L1550true assume 1 == ~T11_E~0;~T11_E~0 := 2; 940#L1555true assume 1 == ~T12_E~0;~T12_E~0 := 2; 724#L1560true assume 1 == ~T13_E~0;~T13_E~0 := 2; 164#L1565true assume 1 == ~T14_E~0;~T14_E~0 := 2; 577#L1570true assume 1 == ~E_1~0;~E_1~0 := 2; 646#L1575true assume 1 == ~E_2~0;~E_2~0 := 2; 317#L1580true assume 1 == ~E_3~0;~E_3~0 := 2; 2132#L1585true assume 1 == ~E_4~0;~E_4~0 := 2; 1551#L1590true assume 1 == ~E_5~0;~E_5~0 := 2; 2019#L1595true assume 1 == ~E_6~0;~E_6~0 := 2; 1486#L1600true assume 1 == ~E_7~0;~E_7~0 := 2; 1266#L1605true assume 1 == ~E_8~0;~E_8~0 := 2; 1554#L1610true assume 1 == ~E_9~0;~E_9~0 := 2; 762#L1615true assume 1 == ~E_10~0;~E_10~0 := 2; 514#L1620true assume 1 == ~E_11~0;~E_11~0 := 2; 1197#L1625true assume 1 == ~E_12~0;~E_12~0 := 2; 20#L1630true assume 1 == ~E_13~0;~E_13~0 := 2; 121#L1635true assume 1 == ~E_14~0;~E_14~0 := 2; 1459#L1641true assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 331#L1022-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1027#L1080-1true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 2047#L1101-1true assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1021#L2036true assume !(0 == start_simulation_~tmp~3#1); 305#L2047true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 2133#L1022true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1666#L1080true assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 71#L1101true assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 737#L1991true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 597#L1993true assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1760#L1999true assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1873#L2049true assume !(0 != start_simulation_~tmp___0~1#1); 609#L2017true [2024-11-17 08:53:58,917 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:58,917 INFO L85 PathProgramCache]: Analyzing trace with hash -1889461764, now seen corresponding path program 1 times [2024-11-17 08:53:58,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:58,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421877191] [2024-11-17 08:53:58,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:58,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:59,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:59,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:59,325 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421877191] [2024-11-17 08:53:59,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421877191] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:59,326 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:59,326 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:59,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1269857055] [2024-11-17 08:53:59,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:59,334 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:59,335 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,335 INFO L85 PathProgramCache]: Analyzing trace with hash 667219018, now seen corresponding path program 1 times [2024-11-17 08:53:59,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,336 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23982568] [2024-11-17 08:53:59,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:59,416 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:59,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:59,417 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23982568] [2024-11-17 08:53:59,417 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23982568] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:59,418 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:59,418 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:53:59,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [339683011] [2024-11-17 08:53:59,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:59,423 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:53:59,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:53:59,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2024-11-17 08:53:59,457 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2024-11-17 08:53:59,464 INFO L87 Difference]: Start difference. First operand has 2138 states, 2137 states have (on average 1.4796443612540946) internal successors, (3162), 2137 states have internal predecessors, (3162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 84.5) internal successors, (169), 2 states have internal predecessors, (169), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:53:59,544 INFO L93 Difference]: Finished difference Result 2120 states and 3107 transitions. [2024-11-17 08:53:59,546 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2120 states and 3107 transitions. [2024-11-17 08:53:59,564 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:53:59,582 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2120 states to 2114 states and 3101 transitions. [2024-11-17 08:53:59,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:53:59,587 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:53:59,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3101 transitions. [2024-11-17 08:53:59,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:53:59,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3101 transitions. [2024-11-17 08:53:59,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3101 transitions. [2024-11-17 08:53:59,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:53:59,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.466887417218543) internal successors, (3101), 2113 states have internal predecessors, (3101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:53:59,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3101 transitions. [2024-11-17 08:53:59,716 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3101 transitions. [2024-11-17 08:53:59,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2024-11-17 08:53:59,721 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3101 transitions. [2024-11-17 08:53:59,721 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-17 08:53:59,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3101 transitions. [2024-11-17 08:53:59,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:53:59,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:53:59,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:53:59,733 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:59,733 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:53:59,734 INFO L745 eck$LassoCheckResult]: Stem: 5224#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 5225#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 5828#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5243#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5244#L939 assume !(1 == ~m_i~0);~m_st~0 := 2; 5434#L944 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 4613#L949 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4614#L954 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5540#L959 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5541#L964 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4555#L969 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4556#L974 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6282#L979 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6273#L984 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 5075#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5076#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5851#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5855#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5982#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 5015#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5016#L1342-1 assume !(0 == ~M_E~0); 5575#L1347-1 assume !(0 == ~T1_E~0); 6128#L1352-1 assume !(0 == ~T2_E~0); 5916#L1357-1 assume !(0 == ~T3_E~0); 5141#L1362-1 assume !(0 == ~T4_E~0); 5142#L1367-1 assume !(0 == ~T5_E~0); 4697#L1372-1 assume !(0 == ~T6_E~0); 4698#L1377-1 assume !(0 == ~T7_E~0); 5056#L1382-1 assume !(0 == ~T8_E~0); 5057#L1387-1 assume !(0 == ~T9_E~0); 5802#L1392-1 assume !(0 == ~T10_E~0); 5094#L1397-1 assume !(0 == ~T11_E~0); 5095#L1402-1 assume !(0 == ~T12_E~0); 4706#L1407-1 assume !(0 == ~T13_E~0); 4707#L1412-1 assume !(0 == ~T14_E~0); 6027#L1417-1 assume !(0 == ~E_1~0); 6028#L1422-1 assume !(0 == ~E_2~0); 6326#L1427-1 assume !(0 == ~E_3~0); 4912#L1432-1 assume !(0 == ~E_4~0); 4913#L1437-1 assume !(0 == ~E_5~0); 5959#L1442-1 assume !(0 == ~E_6~0); 5960#L1447-1 assume !(0 == ~E_7~0); 5794#L1452-1 assume !(0 == ~E_8~0); 4453#L1457-1 assume !(0 == ~E_9~0); 4454#L1462-1 assume !(0 == ~E_10~0); 5990#L1467-1 assume !(0 == ~E_11~0); 6005#L1472-1 assume !(0 == ~E_12~0); 6006#L1477-1 assume !(0 == ~E_13~0); 5753#L1482-1 assume !(0 == ~E_14~0); 4847#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4848#L646-15 assume 1 == ~m_pc~0; 5709#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5153#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5154#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5546#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4577#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4578#L665-15 assume 1 == ~t1_pc~0; 4378#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4379#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5249#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6242#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 6236#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5591#L684-15 assume 1 == ~t2_pc~0; 5592#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5428#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5429#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6048#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 6049#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6045#L703-15 assume 1 == ~t3_pc~0; 5641#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5642#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5238#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5239#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 6132#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6133#L722-15 assume 1 == ~t4_pc~0; 5259#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5260#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6230#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5485#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5486#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6303#L741-15 assume 1 == ~t5_pc~0; 4981#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4982#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5283#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5721#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 4819#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4820#L760-15 assume 1 == ~t6_pc~0; 5741#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5742#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5303#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5304#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 4835#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4836#L779-15 assume 1 == ~t7_pc~0; 5825#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4562#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4693#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4694#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 6363#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5030#L798-15 assume 1 == ~t8_pc~0; 5031#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5507#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6367#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6115#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6033#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5308#L817-15 assume 1 == ~t9_pc~0; 5309#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4550#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5774#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5775#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 6288#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6289#L836-15 assume 1 == ~t10_pc~0; 5661#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4651#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4652#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5305#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 6212#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5233#L855-15 assume 1 == ~t11_pc~0; 5234#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5257#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6092#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5770#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 5771#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4270#L874-15 assume 1 == ~t12_pc~0; 4271#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 6086#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5564#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5565#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5123#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4293#L893-15 assume 1 == ~t13_pc~0; 4294#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4889#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5668#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5669#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 5689#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 5024#L912-15 assume 1 == ~t14_pc~0; 5025#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 5824#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 6274#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 6275#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 5731#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5033#L1495-1 assume !(1 == ~M_E~0); 5034#L1500-1 assume !(1 == ~T1_E~0); 5530#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5531#L1510-1 assume !(1 == ~T3_E~0); 5583#L1515-1 assume !(1 == ~T4_E~0); 5584#L1520-1 assume !(1 == ~T5_E~0); 6191#L1525-1 assume !(1 == ~T6_E~0); 5887#L1530-1 assume !(1 == ~T7_E~0); 4777#L1535-1 assume !(1 == ~T8_E~0); 4778#L1540-1 assume !(1 == ~T9_E~0); 4291#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4292#L1550-1 assume !(1 == ~T11_E~0); 4491#L1555-1 assume !(1 == ~T12_E~0); 4492#L1560-1 assume !(1 == ~T13_E~0); 4830#L1565-1 assume !(1 == ~T14_E~0); 6335#L1570-1 assume !(1 == ~E_1~0); 5766#L1575-1 assume !(1 == ~E_2~0); 5146#L1580-1 assume !(1 == ~E_3~0); 5147#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5603#L1590-1 assume !(1 == ~E_5~0); 5188#L1595-1 assume !(1 == ~E_6~0); 5189#L1600-1 assume !(1 == ~E_7~0); 5537#L1605-1 assume !(1 == ~E_8~0); 5538#L1610-1 assume !(1 == ~E_9~0); 6069#L1615-1 assume !(1 == ~E_10~0); 4972#L1620-1 assume !(1 == ~E_11~0); 4973#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 5795#L1630-1 assume !(1 == ~E_13~0); 5187#L1635-1 assume !(1 == ~E_14~0); 4361#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 4362#L2017 [2024-11-17 08:53:59,742 INFO L747 eck$LassoCheckResult]: Loop: 4362#L2017 assume true; 5383#L2017-1 assume !false; 4936#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4740#L1110 assume true; 4446#L1110-1 assume !false; 4447#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 6246#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 5160#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 6156#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5820#L1115 assume !(0 != eval_~tmp~0#1); 5821#L1118 assume true; 5891#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4903#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4481#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 4482#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5522#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4728#L1357 assume !(0 == ~T3_E~0); 4729#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5645#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5646#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5760#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5250#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5251#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4814#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4815#L1397 assume !(0 == ~T11_E~0); 6030#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4390#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4391#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 4840#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 5071#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 5072#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 6050#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 5413#L1437 assume !(0 == ~E_5~0); 5414#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 6117#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 4823#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 4824#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 5477#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 5369#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 5370#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 5785#L1477 assume !(0 == ~E_13~0); 4559#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 4560#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6310#L646-1 assume 1 == ~m_pc~0; 5996#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5757#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6148#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6338#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6339#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6119#L665-1 assume 1 == ~t1_pc~0; 6120#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5393#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5394#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4721#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4722#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6300#L684-1 assume !(1 == ~t2_pc~0); 5712#L694-1 is_transmit2_triggered_~__retres1~2#1 := 0; 5713#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5700#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5701#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5801#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4844#L703-1 assume 1 == ~t3_pc~0; 4845#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5640#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5779#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6046#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6359#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6125#L722-1 assume !(1 == ~t4_pc~0); 5121#L732-1 is_transmit4_triggered_~__retres1~4#1 := 0; 5122#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6342#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5481#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5482#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6096#L741-1 assume !(1 == ~t5_pc~0); 4534#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 4535#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4723#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4710#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4711#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5430#L760-1 assume 1 == ~t6_pc~0; 6307#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5744#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5745#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5759#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5266#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5267#L779-1 assume 1 == ~t7_pc~0; 5435#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5436#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4339#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4340#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5505#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5506#L798-1 assume !(1 == ~t8_pc~0); 5539#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 5088#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5089#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4553#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4554#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5781#L817-1 assume 1 == ~t9_pc~0; 6229#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4864#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4865#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5839#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6197#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6100#L836-1 assume !(1 == ~t10_pc~0); 4545#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 4546#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5949#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5620#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5621#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6228#L855-1 assume !(1 == ~t11_pc~0); 5826#L865-1 is_transmit11_triggered_~__retres1~11#1 := 0; 4918#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4769#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4770#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5686#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5687#L874-1 assume 1 == ~t12_pc~0; 5722#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 6145#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 6237#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4547#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4548#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5127#L893-1 assume 1 == ~t13_pc~0; 4642#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4643#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4871#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4872#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 6220#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 5268#L912-1 assume 1 == ~t14_pc~0; 5269#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 5666#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 6075#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 4826#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 4827#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4916#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 4624#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4625#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6268#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5105#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5106#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5470#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4932#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4933#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5412#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6292#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6352#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5776#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5532#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4611#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 4612#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 5328#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 4898#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 4899#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 6261#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 6262#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 6227#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 6072#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 6073#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 5576#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 5229#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 5230#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 4311#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 4312#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 4529#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4921#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4475#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 5861#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5854#L2036 assume !(0 == start_simulation_~tmp~3#1); 4876#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 4877#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 4303#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 4421#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 4422#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5362#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5363#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 6334#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 4362#L2017 [2024-11-17 08:53:59,743 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,743 INFO L85 PathProgramCache]: Analyzing trace with hash -1889461764, now seen corresponding path program 2 times [2024-11-17 08:53:59,743 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,743 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166687908] [2024-11-17 08:53:59,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:53:59,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:53:59,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:53:59,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166687908] [2024-11-17 08:53:59,897 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [166687908] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:53:59,897 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:53:59,897 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:53:59,897 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1762100289] [2024-11-17 08:53:59,897 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:53:59,898 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:53:59,901 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:53:59,901 INFO L85 PathProgramCache]: Analyzing trace with hash -587304748, now seen corresponding path program 1 times [2024-11-17 08:53:59,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:53:59,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513853997] [2024-11-17 08:53:59,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:53:59,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:53:59,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,083 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1513853997] [2024-11-17 08:54:00,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1513853997] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,086 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,086 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:00,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432481201] [2024-11-17 08:54:00,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,087 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:00,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:00,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:00,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:00,088 INFO L87 Difference]: Start difference. First operand 2114 states and 3101 transitions. cyclomatic complexity: 988 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:00,133 INFO L93 Difference]: Finished difference Result 2114 states and 3100 transitions. [2024-11-17 08:54:00,133 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3100 transitions. [2024-11-17 08:54:00,143 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:00,153 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3100 transitions. [2024-11-17 08:54:00,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:00,157 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:00,157 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3100 transitions. [2024-11-17 08:54:00,162 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:00,162 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3100 transitions. [2024-11-17 08:54:00,165 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3100 transitions. [2024-11-17 08:54:00,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:00,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4664143803216652) internal successors, (3100), 2113 states have internal predecessors, (3100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3100 transitions. [2024-11-17 08:54:00,200 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3100 transitions. [2024-11-17 08:54:00,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:00,203 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3100 transitions. [2024-11-17 08:54:00,203 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-17 08:54:00,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3100 transitions. [2024-11-17 08:54:00,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:00,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:00,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:00,216 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,216 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,218 INFO L745 eck$LassoCheckResult]: Stem: 9461#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 9462#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 10065#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9480#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9481#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 9671#L944 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 8850#L949 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 8851#L954 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9777#L959 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9778#L964 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8792#L969 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8793#L974 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10519#L979 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10510#L984 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 9312#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9313#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10088#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 10092#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 10219#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 9252#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9253#L1342-1 assume !(0 == ~M_E~0); 9813#L1347-1 assume !(0 == ~T1_E~0); 10365#L1352-1 assume !(0 == ~T2_E~0); 10153#L1357-1 assume !(0 == ~T3_E~0); 9378#L1362-1 assume !(0 == ~T4_E~0); 9379#L1367-1 assume !(0 == ~T5_E~0); 8934#L1372-1 assume !(0 == ~T6_E~0); 8935#L1377-1 assume !(0 == ~T7_E~0); 9293#L1382-1 assume !(0 == ~T8_E~0); 9294#L1387-1 assume !(0 == ~T9_E~0); 10039#L1392-1 assume !(0 == ~T10_E~0); 9331#L1397-1 assume !(0 == ~T11_E~0); 9332#L1402-1 assume !(0 == ~T12_E~0); 8943#L1407-1 assume !(0 == ~T13_E~0); 8944#L1412-1 assume !(0 == ~T14_E~0); 10264#L1417-1 assume !(0 == ~E_1~0); 10265#L1422-1 assume !(0 == ~E_2~0); 10563#L1427-1 assume !(0 == ~E_3~0); 9149#L1432-1 assume !(0 == ~E_4~0); 9150#L1437-1 assume !(0 == ~E_5~0); 10196#L1442-1 assume !(0 == ~E_6~0); 10197#L1447-1 assume !(0 == ~E_7~0); 10031#L1452-1 assume !(0 == ~E_8~0); 8690#L1457-1 assume !(0 == ~E_9~0); 8691#L1462-1 assume !(0 == ~E_10~0); 10227#L1467-1 assume !(0 == ~E_11~0); 10242#L1472-1 assume !(0 == ~E_12~0); 10243#L1477-1 assume !(0 == ~E_13~0); 9990#L1482-1 assume !(0 == ~E_14~0); 9084#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9085#L646-15 assume 1 == ~m_pc~0; 9946#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9390#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9391#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9783#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8814#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8815#L665-15 assume 1 == ~t1_pc~0; 8615#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8616#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9486#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10479#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 10474#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9828#L684-15 assume 1 == ~t2_pc~0; 9829#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9665#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9666#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10285#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 10286#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10282#L703-15 assume 1 == ~t3_pc~0; 9878#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9879#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9475#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9476#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 10369#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10370#L722-15 assume 1 == ~t4_pc~0; 9496#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9497#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10467#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9722#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9723#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10540#L741-15 assume 1 == ~t5_pc~0; 9218#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9219#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9520#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9960#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 9056#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9057#L760-15 assume 1 == ~t6_pc~0; 9978#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9979#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9540#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9541#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 9072#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9073#L779-15 assume 1 == ~t7_pc~0; 10062#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8799#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8930#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8931#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 10600#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9267#L798-15 assume 1 == ~t8_pc~0; 9268#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9744#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10604#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10352#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10271#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9545#L817-15 assume 1 == ~t9_pc~0; 9546#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8787#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10011#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10012#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 10525#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10526#L836-15 assume 1 == ~t10_pc~0; 9898#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8888#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8889#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9542#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 10449#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9470#L855-15 assume 1 == ~t11_pc~0; 9471#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9494#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10329#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10007#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 10008#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8507#L874-15 assume 1 == ~t12_pc~0; 8508#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10323#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9801#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9802#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9360#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8530#L893-15 assume 1 == ~t13_pc~0; 8531#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9126#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9905#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9906#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 9926#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 9261#L912-15 assume 1 == ~t14_pc~0; 9262#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 10061#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 10511#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 10512#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 9968#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9270#L1495-1 assume !(1 == ~M_E~0); 9271#L1500-1 assume !(1 == ~T1_E~0); 9767#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9768#L1510-1 assume !(1 == ~T3_E~0); 9820#L1515-1 assume !(1 == ~T4_E~0); 9821#L1520-1 assume !(1 == ~T5_E~0); 10428#L1525-1 assume !(1 == ~T6_E~0); 10124#L1530-1 assume !(1 == ~T7_E~0); 9014#L1535-1 assume !(1 == ~T8_E~0); 9015#L1540-1 assume !(1 == ~T9_E~0); 8528#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8529#L1550-1 assume !(1 == ~T11_E~0); 8728#L1555-1 assume !(1 == ~T12_E~0); 8729#L1560-1 assume !(1 == ~T13_E~0); 9069#L1565-1 assume !(1 == ~T14_E~0); 10572#L1570-1 assume !(1 == ~E_1~0); 10003#L1575-1 assume !(1 == ~E_2~0); 9383#L1580-1 assume !(1 == ~E_3~0); 9384#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 9840#L1590-1 assume !(1 == ~E_5~0); 9425#L1595-1 assume !(1 == ~E_6~0); 9426#L1600-1 assume !(1 == ~E_7~0); 9774#L1605-1 assume !(1 == ~E_8~0); 9775#L1610-1 assume !(1 == ~E_9~0); 10306#L1615-1 assume !(1 == ~E_10~0); 9209#L1620-1 assume !(1 == ~E_11~0); 9210#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 10032#L1630-1 assume !(1 == ~E_13~0); 9424#L1635-1 assume !(1 == ~E_14~0); 8598#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 8599#L2017 [2024-11-17 08:54:00,218 INFO L747 eck$LassoCheckResult]: Loop: 8599#L2017 assume true; 9620#L2017-1 assume !false; 9173#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8977#L1110 assume true; 8683#L1110-1 assume !false; 8684#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 10483#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 9397#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 10393#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10057#L1115 assume !(0 != eval_~tmp~0#1); 10058#L1118 assume true; 10128#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9140#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8718#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 8719#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9759#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8965#L1357 assume !(0 == ~T3_E~0); 8966#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9882#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9883#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9997#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9487#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9488#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9051#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9052#L1397 assume !(0 == ~T11_E~0); 10267#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8627#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8628#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 9077#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 9308#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 9309#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 10287#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 9650#L1437 assume !(0 == ~E_5~0); 9651#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 10354#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 9060#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 9061#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 9714#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 9606#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 9607#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 10022#L1477 assume !(0 == ~E_13~0); 8796#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 8797#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10547#L646-1 assume 1 == ~m_pc~0; 10233#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9994#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10385#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10575#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10576#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10356#L665-1 assume 1 == ~t1_pc~0; 10357#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9630#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9631#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8958#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8959#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10537#L684-1 assume 1 == ~t2_pc~0; 9948#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9950#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9937#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9938#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10038#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9081#L703-1 assume 1 == ~t3_pc~0; 9082#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9877#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10016#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10283#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10596#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10362#L722-1 assume 1 == ~t4_pc~0; 10363#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9359#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10579#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9718#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9719#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10333#L741-1 assume !(1 == ~t5_pc~0); 8771#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 8772#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8960#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8947#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8948#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9669#L760-1 assume 1 == ~t6_pc~0; 10544#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9981#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9982#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9996#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9503#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9504#L779-1 assume 1 == ~t7_pc~0; 9672#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9673#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8576#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8577#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9742#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9743#L798-1 assume !(1 == ~t8_pc~0); 9776#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 9325#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9326#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8790#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8791#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10018#L817-1 assume 1 == ~t9_pc~0; 10466#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9101#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9102#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10076#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10434#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10337#L836-1 assume !(1 == ~t10_pc~0); 8784#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 8785#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10186#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9857#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9858#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10465#L855-1 assume 1 == ~t11_pc~0; 10232#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9154#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9002#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9003#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9923#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9924#L874-1 assume 1 == ~t12_pc~0; 9958#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 10380#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 10473#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8779#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8780#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9363#L893-1 assume !(1 == ~t13_pc~0); 8881#L903-1 is_transmit13_triggered_~__retres1~13#1 := 0; 8880#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9108#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9109#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 10457#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 9505#L912-1 assume 1 == ~t14_pc~0; 9506#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 9903#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 10312#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 9063#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 9064#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9151#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 8861#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8862#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10504#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9342#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9343#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9707#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9169#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9170#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9649#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10528#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10589#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10013#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9769#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8848#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 8849#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 9565#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 9135#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 9136#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 10498#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 10499#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 10463#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 10309#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 10310#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 9812#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 9466#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 9467#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 8548#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 8549#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 8761#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9158#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8712#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 10095#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 10091#L2036 assume !(0 == start_simulation_~tmp~3#1); 9113#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 9114#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 8540#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 8658#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 8659#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9599#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9600#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 10571#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 8599#L2017 [2024-11-17 08:54:00,221 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,221 INFO L85 PathProgramCache]: Analyzing trace with hash -2143851171, now seen corresponding path program 1 times [2024-11-17 08:54:00,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828752187] [2024-11-17 08:54:00,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828752187] [2024-11-17 08:54:00,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828752187] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:00,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1292271267] [2024-11-17 08:54:00,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,292 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:00,292 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,292 INFO L85 PathProgramCache]: Analyzing trace with hash 490442778, now seen corresponding path program 1 times [2024-11-17 08:54:00,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,293 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [524277842] [2024-11-17 08:54:00,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,294 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,424 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [524277842] [2024-11-17 08:54:00,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [524277842] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:00,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127642995] [2024-11-17 08:54:00,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,425 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:00,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:00,426 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:00,426 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:00,427 INFO L87 Difference]: Start difference. First operand 2114 states and 3100 transitions. cyclomatic complexity: 987 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:00,471 INFO L93 Difference]: Finished difference Result 2114 states and 3099 transitions. [2024-11-17 08:54:00,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3099 transitions. [2024-11-17 08:54:00,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:00,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3099 transitions. [2024-11-17 08:54:00,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:00,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:00,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3099 transitions. [2024-11-17 08:54:00,498 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:00,498 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3099 transitions. [2024-11-17 08:54:00,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3099 transitions. [2024-11-17 08:54:00,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:00,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4659413434247872) internal successors, (3099), 2113 states have internal predecessors, (3099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3099 transitions. [2024-11-17 08:54:00,538 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3099 transitions. [2024-11-17 08:54:00,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:00,539 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3099 transitions. [2024-11-17 08:54:00,539 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-17 08:54:00,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3099 transitions. [2024-11-17 08:54:00,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:00,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:00,549 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:00,552 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,552 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,552 INFO L745 eck$LassoCheckResult]: Stem: 13698#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 13699#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 14302#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13717#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13718#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 13908#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13087#L949 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 13088#L954 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 14014#L959 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 14015#L964 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13029#L969 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13030#L974 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14756#L979 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14747#L984 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 13549#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13550#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 14325#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 14329#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 14456#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 13489#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13490#L1342-1 assume !(0 == ~M_E~0); 14050#L1347-1 assume !(0 == ~T1_E~0); 14602#L1352-1 assume !(0 == ~T2_E~0); 14390#L1357-1 assume !(0 == ~T3_E~0); 13615#L1362-1 assume !(0 == ~T4_E~0); 13616#L1367-1 assume !(0 == ~T5_E~0); 13171#L1372-1 assume !(0 == ~T6_E~0); 13172#L1377-1 assume !(0 == ~T7_E~0); 13530#L1382-1 assume !(0 == ~T8_E~0); 13531#L1387-1 assume !(0 == ~T9_E~0); 14276#L1392-1 assume !(0 == ~T10_E~0); 13568#L1397-1 assume !(0 == ~T11_E~0); 13569#L1402-1 assume !(0 == ~T12_E~0); 13180#L1407-1 assume !(0 == ~T13_E~0); 13181#L1412-1 assume !(0 == ~T14_E~0); 14501#L1417-1 assume !(0 == ~E_1~0); 14502#L1422-1 assume !(0 == ~E_2~0); 14800#L1427-1 assume !(0 == ~E_3~0); 13386#L1432-1 assume !(0 == ~E_4~0); 13387#L1437-1 assume !(0 == ~E_5~0); 14433#L1442-1 assume !(0 == ~E_6~0); 14434#L1447-1 assume !(0 == ~E_7~0); 14268#L1452-1 assume !(0 == ~E_8~0); 12927#L1457-1 assume !(0 == ~E_9~0); 12928#L1462-1 assume !(0 == ~E_10~0); 14464#L1467-1 assume !(0 == ~E_11~0); 14479#L1472-1 assume !(0 == ~E_12~0); 14480#L1477-1 assume !(0 == ~E_13~0); 14227#L1482-1 assume !(0 == ~E_14~0); 13321#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13322#L646-15 assume 1 == ~m_pc~0; 14183#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13627#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13628#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14020#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13051#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13052#L665-15 assume 1 == ~t1_pc~0; 12852#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12853#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13723#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14716#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 14711#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14065#L684-15 assume 1 == ~t2_pc~0; 14066#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13902#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13903#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14522#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 14523#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14519#L703-15 assume 1 == ~t3_pc~0; 14115#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14116#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13712#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13713#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 14606#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14607#L722-15 assume 1 == ~t4_pc~0; 13733#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13734#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14704#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13959#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13960#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14777#L741-15 assume 1 == ~t5_pc~0; 13455#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13456#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13757#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14197#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 13293#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13294#L760-15 assume 1 == ~t6_pc~0; 14215#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14216#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13777#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13778#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 13309#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13310#L779-15 assume 1 == ~t7_pc~0; 14299#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13036#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13167#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13168#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 14837#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13504#L798-15 assume 1 == ~t8_pc~0; 13505#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13981#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14841#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14589#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14508#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13782#L817-15 assume 1 == ~t9_pc~0; 13783#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13024#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14248#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14249#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 14762#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14763#L836-15 assume 1 == ~t10_pc~0; 14135#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13125#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13126#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13779#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 14686#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13707#L855-15 assume 1 == ~t11_pc~0; 13708#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13731#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14566#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14244#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 14245#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12744#L874-15 assume 1 == ~t12_pc~0; 12745#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 14560#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14038#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14039#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13597#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12767#L893-15 assume 1 == ~t13_pc~0; 12768#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13363#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 14142#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 14143#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 14163#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 13498#L912-15 assume 1 == ~t14_pc~0; 13499#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 14298#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 14748#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 14749#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 14205#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13507#L1495-1 assume !(1 == ~M_E~0); 13508#L1500-1 assume !(1 == ~T1_E~0); 14004#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14005#L1510-1 assume !(1 == ~T3_E~0); 14057#L1515-1 assume !(1 == ~T4_E~0); 14058#L1520-1 assume !(1 == ~T5_E~0); 14665#L1525-1 assume !(1 == ~T6_E~0); 14361#L1530-1 assume !(1 == ~T7_E~0); 13251#L1535-1 assume !(1 == ~T8_E~0); 13252#L1540-1 assume !(1 == ~T9_E~0); 12765#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12766#L1550-1 assume !(1 == ~T11_E~0); 12965#L1555-1 assume !(1 == ~T12_E~0); 12966#L1560-1 assume !(1 == ~T13_E~0); 13306#L1565-1 assume !(1 == ~T14_E~0); 14809#L1570-1 assume !(1 == ~E_1~0); 14240#L1575-1 assume !(1 == ~E_2~0); 13620#L1580-1 assume !(1 == ~E_3~0); 13621#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 14077#L1590-1 assume !(1 == ~E_5~0); 13662#L1595-1 assume !(1 == ~E_6~0); 13663#L1600-1 assume !(1 == ~E_7~0); 14011#L1605-1 assume !(1 == ~E_8~0); 14012#L1610-1 assume !(1 == ~E_9~0); 14543#L1615-1 assume !(1 == ~E_10~0); 13446#L1620-1 assume !(1 == ~E_11~0); 13447#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 14269#L1630-1 assume !(1 == ~E_13~0); 13661#L1635-1 assume !(1 == ~E_14~0); 12835#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 12836#L2017 [2024-11-17 08:54:00,553 INFO L747 eck$LassoCheckResult]: Loop: 12836#L2017 assume true; 13857#L2017-1 assume !false; 13410#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13214#L1110 assume true; 12920#L1110-1 assume !false; 12921#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 14720#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 13634#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 14630#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14294#L1115 assume !(0 != eval_~tmp~0#1); 14295#L1118 assume true; 14365#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13377#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12955#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 12956#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13996#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13202#L1357 assume !(0 == ~T3_E~0); 13203#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14119#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14120#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14234#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13724#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13725#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13288#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13289#L1397 assume !(0 == ~T11_E~0); 14504#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12864#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12865#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 13317#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 13545#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 13546#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 14524#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 13887#L1437 assume !(0 == ~E_5~0); 13888#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 14591#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 13297#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 13298#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 13951#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 13843#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 13844#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 14259#L1477 assume !(0 == ~E_13~0); 13033#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 13034#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14784#L646-1 assume 1 == ~m_pc~0; 14470#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 14231#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14622#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14812#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14813#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14593#L665-1 assume 1 == ~t1_pc~0; 14594#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13867#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13868#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13195#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13196#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14774#L684-1 assume 1 == ~t2_pc~0; 14185#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14187#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14174#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14175#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14275#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13318#L703-1 assume 1 == ~t3_pc~0; 13319#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14114#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14253#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14520#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14833#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14599#L722-1 assume 1 == ~t4_pc~0; 14600#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13596#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14816#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13956#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13957#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14570#L741-1 assume !(1 == ~t5_pc~0); 13008#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 13009#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13197#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13184#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13185#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13906#L760-1 assume 1 == ~t6_pc~0; 14781#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14218#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14219#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14233#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13740#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13741#L779-1 assume 1 == ~t7_pc~0; 13909#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13910#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12813#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12814#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13979#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13980#L798-1 assume 1 == ~t8_pc~0; 14322#L799-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13562#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13563#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13027#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13028#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14255#L817-1 assume !(1 == ~t9_pc~0); 14659#L827-1 is_transmit9_triggered_~__retres1~9#1 := 0; 13336#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13337#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14313#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 14671#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 14574#L836-1 assume !(1 == ~t10_pc~0); 13016#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 13017#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14423#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14094#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 14095#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14702#L855-1 assume 1 == ~t11_pc~0; 14469#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13391#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13239#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13240#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 14160#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 14161#L874-1 assume 1 == ~t12_pc~0; 14195#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 14617#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 14710#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13018#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13019#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13600#L893-1 assume 1 == ~t13_pc~0; 13116#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13117#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13345#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13346#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 14694#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 13742#L912-1 assume !(1 == ~t14_pc~0); 13744#L922-1 is_transmit14_triggered_~__retres1~14#1 := 0; 14140#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 14549#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 13300#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 13301#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13388#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 13098#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13099#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14741#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13579#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13580#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13944#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13406#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13407#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13886#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14765#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14826#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14250#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 14006#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13085#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 13086#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 13802#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 13372#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 13373#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 14735#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 14736#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 14700#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 14546#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 14547#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 14049#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 13703#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 13704#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 12785#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 12786#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 12998#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13395#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12949#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 14332#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 14328#L2036 assume !(0 == start_simulation_~tmp~3#1); 13350#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 13351#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 12777#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 12895#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 12896#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13836#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13837#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 14808#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 12836#L2017 [2024-11-17 08:54:00,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,554 INFO L85 PathProgramCache]: Analyzing trace with hash -1182225956, now seen corresponding path program 1 times [2024-11-17 08:54:00,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,555 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600397871] [2024-11-17 08:54:00,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,620 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600397871] [2024-11-17 08:54:00,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600397871] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:00,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173280232] [2024-11-17 08:54:00,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,621 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:00,622 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,622 INFO L85 PathProgramCache]: Analyzing trace with hash -1966574694, now seen corresponding path program 1 times [2024-11-17 08:54:00,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,622 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287690709] [2024-11-17 08:54:00,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,727 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,727 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287690709] [2024-11-17 08:54:00,728 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1287690709] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:00,728 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [226591078] [2024-11-17 08:54:00,728 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,728 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:00,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:00,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:00,729 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:00,729 INFO L87 Difference]: Start difference. First operand 2114 states and 3099 transitions. cyclomatic complexity: 986 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:00,768 INFO L93 Difference]: Finished difference Result 2114 states and 3098 transitions. [2024-11-17 08:54:00,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3098 transitions. [2024-11-17 08:54:00,781 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:00,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3098 transitions. [2024-11-17 08:54:00,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:00,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:00,791 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3098 transitions. [2024-11-17 08:54:00,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:00,793 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3098 transitions. [2024-11-17 08:54:00,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3098 transitions. [2024-11-17 08:54:00,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:00,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4654683065279093) internal successors, (3098), 2113 states have internal predecessors, (3098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:00,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3098 transitions. [2024-11-17 08:54:00,830 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3098 transitions. [2024-11-17 08:54:00,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:00,832 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3098 transitions. [2024-11-17 08:54:00,832 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-17 08:54:00,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3098 transitions. [2024-11-17 08:54:00,840 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:00,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:00,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:00,844 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,844 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:00,845 INFO L745 eck$LassoCheckResult]: Stem: 17935#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 17936#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 18539#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17954#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17955#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 18145#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17324#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17325#L954 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 18251#L959 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 18252#L964 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17266#L969 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17267#L974 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 18993#L979 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18984#L984 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 17786#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17787#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 18562#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 18566#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 18693#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 17726#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17727#L1342-1 assume !(0 == ~M_E~0); 18287#L1347-1 assume !(0 == ~T1_E~0); 18839#L1352-1 assume !(0 == ~T2_E~0); 18627#L1357-1 assume !(0 == ~T3_E~0); 17852#L1362-1 assume !(0 == ~T4_E~0); 17853#L1367-1 assume !(0 == ~T5_E~0); 17408#L1372-1 assume !(0 == ~T6_E~0); 17409#L1377-1 assume !(0 == ~T7_E~0); 17769#L1382-1 assume !(0 == ~T8_E~0); 17770#L1387-1 assume !(0 == ~T9_E~0); 18513#L1392-1 assume !(0 == ~T10_E~0); 17805#L1397-1 assume !(0 == ~T11_E~0); 17806#L1402-1 assume !(0 == ~T12_E~0); 17417#L1407-1 assume !(0 == ~T13_E~0); 17418#L1412-1 assume !(0 == ~T14_E~0); 18738#L1417-1 assume !(0 == ~E_1~0); 18739#L1422-1 assume !(0 == ~E_2~0); 19037#L1427-1 assume !(0 == ~E_3~0); 17623#L1432-1 assume !(0 == ~E_4~0); 17624#L1437-1 assume !(0 == ~E_5~0); 18670#L1442-1 assume !(0 == ~E_6~0); 18671#L1447-1 assume !(0 == ~E_7~0); 18505#L1452-1 assume !(0 == ~E_8~0); 17164#L1457-1 assume !(0 == ~E_9~0); 17165#L1462-1 assume !(0 == ~E_10~0); 18701#L1467-1 assume !(0 == ~E_11~0); 18716#L1472-1 assume !(0 == ~E_12~0); 18717#L1477-1 assume !(0 == ~E_13~0); 18464#L1482-1 assume !(0 == ~E_14~0); 17558#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17559#L646-15 assume 1 == ~m_pc~0; 18420#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17864#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17865#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18257#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17288#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17289#L665-15 assume 1 == ~t1_pc~0; 17089#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17090#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17960#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18953#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 18948#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18302#L684-15 assume 1 == ~t2_pc~0; 18303#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18139#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18140#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18759#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 18760#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18756#L703-15 assume 1 == ~t3_pc~0; 18352#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18353#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17949#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17950#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 18843#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18844#L722-15 assume 1 == ~t4_pc~0; 17972#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17973#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18941#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18196#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18197#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19014#L741-15 assume 1 == ~t5_pc~0; 17692#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17693#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17994#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18434#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 17530#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17531#L760-15 assume 1 == ~t6_pc~0; 18452#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18453#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18014#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18015#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 17546#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17547#L779-15 assume 1 == ~t7_pc~0; 18536#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17273#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17404#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17405#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 19074#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17741#L798-15 assume 1 == ~t8_pc~0; 17742#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18218#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19078#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18826#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18745#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18019#L817-15 assume 1 == ~t9_pc~0; 18020#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 17261#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18485#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18486#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 18999#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19000#L836-15 assume 1 == ~t10_pc~0; 18372#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 17362#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17363#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18016#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 18923#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17944#L855-15 assume 1 == ~t11_pc~0; 17945#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17968#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18803#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 18481#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 18482#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16981#L874-15 assume 1 == ~t12_pc~0; 16982#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18797#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18275#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 18276#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17834#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17004#L893-15 assume 1 == ~t13_pc~0; 17005#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17600#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 18379#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18380#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 18400#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 17735#L912-15 assume 1 == ~t14_pc~0; 17736#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 18535#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 18985#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 18986#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 18442#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17744#L1495-1 assume !(1 == ~M_E~0); 17745#L1500-1 assume !(1 == ~T1_E~0); 18241#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18242#L1510-1 assume !(1 == ~T3_E~0); 18294#L1515-1 assume !(1 == ~T4_E~0); 18295#L1520-1 assume !(1 == ~T5_E~0); 18902#L1525-1 assume !(1 == ~T6_E~0); 18598#L1530-1 assume !(1 == ~T7_E~0); 17488#L1535-1 assume !(1 == ~T8_E~0); 17489#L1540-1 assume !(1 == ~T9_E~0); 17002#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17003#L1550-1 assume !(1 == ~T11_E~0); 17202#L1555-1 assume !(1 == ~T12_E~0); 17203#L1560-1 assume !(1 == ~T13_E~0); 17543#L1565-1 assume !(1 == ~T14_E~0); 19046#L1570-1 assume !(1 == ~E_1~0); 18477#L1575-1 assume !(1 == ~E_2~0); 17857#L1580-1 assume !(1 == ~E_3~0); 17858#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18314#L1590-1 assume !(1 == ~E_5~0); 17899#L1595-1 assume !(1 == ~E_6~0); 17900#L1600-1 assume !(1 == ~E_7~0); 18249#L1605-1 assume !(1 == ~E_8~0); 18250#L1610-1 assume !(1 == ~E_9~0); 18780#L1615-1 assume !(1 == ~E_10~0); 17683#L1620-1 assume !(1 == ~E_11~0); 17684#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 18506#L1630-1 assume !(1 == ~E_13~0); 17898#L1635-1 assume !(1 == ~E_14~0); 17073#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 17074#L2017 [2024-11-17 08:54:00,845 INFO L747 eck$LassoCheckResult]: Loop: 17074#L2017 assume true; 18094#L2017-1 assume !false; 17647#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17451#L1110 assume true; 17157#L1110-1 assume !false; 17158#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 18957#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 17871#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 18867#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18531#L1115 assume !(0 != eval_~tmp~0#1); 18532#L1118 assume true; 18602#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17614#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17192#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 17193#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18233#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17439#L1357 assume !(0 == ~T3_E~0); 17440#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18356#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18357#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18471#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17961#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17962#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17525#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17526#L1397 assume !(0 == ~T11_E~0); 18741#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17101#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17102#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 17554#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 17782#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 17783#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 18761#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 18124#L1437 assume !(0 == ~E_5~0); 18125#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 18828#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 17534#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 17535#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 18188#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 18080#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 18081#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 18496#L1477 assume !(0 == ~E_13~0); 17270#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 17271#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19021#L646-1 assume 1 == ~m_pc~0; 18707#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18468#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18859#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19049#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19050#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18830#L665-1 assume !(1 == ~t1_pc~0); 18240#L675-1 is_transmit1_triggered_~__retres1~1#1 := 0; 18104#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18105#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17432#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17433#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19011#L684-1 assume 1 == ~t2_pc~0; 18422#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18424#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18411#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18412#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 18512#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17555#L703-1 assume 1 == ~t3_pc~0; 17556#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18351#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18491#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18757#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19070#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18836#L722-1 assume 1 == ~t4_pc~0; 18837#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17833#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19053#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18193#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18194#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18807#L741-1 assume 1 == ~t5_pc~0; 19062#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17246#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17434#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17421#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17422#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18143#L760-1 assume 1 == ~t6_pc~0; 19018#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18455#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18456#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18470#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17977#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17978#L779-1 assume 1 == ~t7_pc~0; 18146#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18147#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17050#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17051#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18216#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18217#L798-1 assume !(1 == ~t8_pc~0); 18248#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 17795#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17796#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17262#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17263#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18490#L817-1 assume !(1 == ~t9_pc~0); 18896#L827-1 is_transmit9_triggered_~__retres1~9#1 := 0; 17575#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17576#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 18550#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 18908#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18811#L836-1 assume !(1 == ~t10_pc~0); 17253#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 17254#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18660#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 18331#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18332#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 18939#L855-1 assume 1 == ~t11_pc~0; 18706#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17628#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17476#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17477#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 18397#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 18398#L874-1 assume 1 == ~t12_pc~0; 18432#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 18854#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 18947#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17255#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17256#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17837#L893-1 assume 1 == ~t13_pc~0; 17353#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17354#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17582#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17583#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 18931#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 17979#L912-1 assume 1 == ~t14_pc~0; 17980#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 18377#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 18786#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 17537#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 17538#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17625#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 17335#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17336#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18978#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17816#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17817#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18181#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17643#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17644#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18123#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19002#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19063#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 18487#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 18243#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 17322#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 17323#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 18039#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 17609#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 17610#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 18972#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 18973#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 18937#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 18783#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 18784#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 18286#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 17940#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 17941#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 17022#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 17023#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 17235#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17632#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 17186#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 18569#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 18565#L2036 assume !(0 == start_simulation_~tmp~3#1); 17587#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 17588#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 17014#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 17132#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 17133#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18073#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18074#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 19045#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 17074#L2017 [2024-11-17 08:54:00,846 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,846 INFO L85 PathProgramCache]: Analyzing trace with hash -319921795, now seen corresponding path program 1 times [2024-11-17 08:54:00,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1504396815] [2024-11-17 08:54:00,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:00,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:00,898 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:00,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1504396815] [2024-11-17 08:54:00,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1504396815] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:00,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:00,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:00,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465978019] [2024-11-17 08:54:00,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:00,899 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:00,900 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:00,900 INFO L85 PathProgramCache]: Analyzing trace with hash 1006764570, now seen corresponding path program 1 times [2024-11-17 08:54:00,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:00,900 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873648767] [2024-11-17 08:54:00,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:00,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:00,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,017 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [873648767] [2024-11-17 08:54:01,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [873648767] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,018 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:01,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1207938211] [2024-11-17 08:54:01,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,019 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:01,019 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:01,019 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:01,019 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:01,020 INFO L87 Difference]: Start difference. First operand 2114 states and 3098 transitions. cyclomatic complexity: 985 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:01,054 INFO L93 Difference]: Finished difference Result 2114 states and 3097 transitions. [2024-11-17 08:54:01,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3097 transitions. [2024-11-17 08:54:01,062 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:01,070 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3097 transitions. [2024-11-17 08:54:01,070 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:01,071 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:01,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3097 transitions. [2024-11-17 08:54:01,074 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:01,074 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3097 transitions. [2024-11-17 08:54:01,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3097 transitions. [2024-11-17 08:54:01,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:01,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4649952696310313) internal successors, (3097), 2113 states have internal predecessors, (3097), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3097 transitions. [2024-11-17 08:54:01,106 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3097 transitions. [2024-11-17 08:54:01,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:01,108 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3097 transitions. [2024-11-17 08:54:01,108 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-17 08:54:01,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3097 transitions. [2024-11-17 08:54:01,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:01,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:01,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:01,117 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,117 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,117 INFO L745 eck$LassoCheckResult]: Stem: 22172#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 22173#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 22776#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22193#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22194#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 22385#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21561#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21562#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22488#L959 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 22489#L964 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21503#L969 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21504#L974 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23230#L979 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23221#L984 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 22023#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22024#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22799#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 22803#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 22930#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 21963#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21964#L1342-1 assume !(0 == ~M_E~0); 22524#L1347-1 assume !(0 == ~T1_E~0); 23076#L1352-1 assume !(0 == ~T2_E~0); 22864#L1357-1 assume !(0 == ~T3_E~0); 22089#L1362-1 assume !(0 == ~T4_E~0); 22090#L1367-1 assume !(0 == ~T5_E~0); 21645#L1372-1 assume !(0 == ~T6_E~0); 21646#L1377-1 assume !(0 == ~T7_E~0); 22006#L1382-1 assume !(0 == ~T8_E~0); 22007#L1387-1 assume !(0 == ~T9_E~0); 22750#L1392-1 assume !(0 == ~T10_E~0); 22042#L1397-1 assume !(0 == ~T11_E~0); 22043#L1402-1 assume !(0 == ~T12_E~0); 21654#L1407-1 assume !(0 == ~T13_E~0); 21655#L1412-1 assume !(0 == ~T14_E~0); 22975#L1417-1 assume !(0 == ~E_1~0); 22976#L1422-1 assume !(0 == ~E_2~0); 23274#L1427-1 assume !(0 == ~E_3~0); 21860#L1432-1 assume !(0 == ~E_4~0); 21861#L1437-1 assume !(0 == ~E_5~0); 22907#L1442-1 assume !(0 == ~E_6~0); 22908#L1447-1 assume !(0 == ~E_7~0); 22742#L1452-1 assume !(0 == ~E_8~0); 21401#L1457-1 assume !(0 == ~E_9~0); 21402#L1462-1 assume !(0 == ~E_10~0); 22938#L1467-1 assume !(0 == ~E_11~0); 22953#L1472-1 assume !(0 == ~E_12~0); 22954#L1477-1 assume !(0 == ~E_13~0); 22701#L1482-1 assume !(0 == ~E_14~0); 21795#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21796#L646-15 assume 1 == ~m_pc~0; 22657#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22101#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22102#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22494#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21525#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21526#L665-15 assume 1 == ~t1_pc~0; 21326#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21327#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22197#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 23190#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 23185#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22539#L684-15 assume 1 == ~t2_pc~0; 22540#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22376#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22377#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22996#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 22997#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22993#L703-15 assume 1 == ~t3_pc~0; 22589#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22590#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22186#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22187#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 23080#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23081#L722-15 assume 1 == ~t4_pc~0; 22209#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22210#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23178#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22433#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22434#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23251#L741-15 assume 1 == ~t5_pc~0; 21929#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21930#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22231#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22671#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 21767#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21768#L760-15 assume 1 == ~t6_pc~0; 22689#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22690#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22251#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22252#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 21783#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21784#L779-15 assume 1 == ~t7_pc~0; 22773#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 21510#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21641#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21642#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 23311#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21978#L798-15 assume 1 == ~t8_pc~0; 21979#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22455#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23315#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23063#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22982#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22256#L817-15 assume 1 == ~t9_pc~0; 22257#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21498#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22722#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22723#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 23236#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23237#L836-15 assume 1 == ~t10_pc~0; 22609#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21599#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21600#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22253#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 23160#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22181#L855-15 assume 1 == ~t11_pc~0; 22182#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22205#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23040#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22718#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 22719#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21218#L874-15 assume 1 == ~t12_pc~0; 21219#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23034#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22512#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22513#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 22071#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21241#L893-15 assume 1 == ~t13_pc~0; 21242#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21837#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 22616#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22617#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 22637#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 21972#L912-15 assume 1 == ~t14_pc~0; 21973#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 22772#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 23222#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 23223#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 22679#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21981#L1495-1 assume !(1 == ~M_E~0); 21982#L1500-1 assume !(1 == ~T1_E~0); 22478#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22479#L1510-1 assume !(1 == ~T3_E~0); 22531#L1515-1 assume !(1 == ~T4_E~0); 22532#L1520-1 assume !(1 == ~T5_E~0); 23139#L1525-1 assume !(1 == ~T6_E~0); 22835#L1530-1 assume !(1 == ~T7_E~0); 21725#L1535-1 assume !(1 == ~T8_E~0); 21726#L1540-1 assume !(1 == ~T9_E~0); 21239#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21240#L1550-1 assume !(1 == ~T11_E~0); 21439#L1555-1 assume !(1 == ~T12_E~0); 21440#L1560-1 assume !(1 == ~T13_E~0); 21780#L1565-1 assume !(1 == ~T14_E~0); 23283#L1570-1 assume !(1 == ~E_1~0); 22714#L1575-1 assume !(1 == ~E_2~0); 22094#L1580-1 assume !(1 == ~E_3~0); 22095#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 22551#L1590-1 assume !(1 == ~E_5~0); 22136#L1595-1 assume !(1 == ~E_6~0); 22137#L1600-1 assume !(1 == ~E_7~0); 22486#L1605-1 assume !(1 == ~E_8~0); 22487#L1610-1 assume !(1 == ~E_9~0); 23017#L1615-1 assume !(1 == ~E_10~0); 21920#L1620-1 assume !(1 == ~E_11~0); 21921#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 22743#L1630-1 assume !(1 == ~E_13~0); 22135#L1635-1 assume !(1 == ~E_14~0); 21310#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 21311#L2017 [2024-11-17 08:54:01,119 INFO L747 eck$LassoCheckResult]: Loop: 21311#L2017 assume true; 22331#L2017-1 assume !false; 21884#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21688#L1110 assume true; 21394#L1110-1 assume !false; 21395#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 23194#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 22111#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 23104#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22768#L1115 assume !(0 != eval_~tmp~0#1); 22769#L1118 assume true; 22839#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21851#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21429#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 21430#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22470#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21676#L1357 assume !(0 == ~T3_E~0); 21677#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22593#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22594#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22708#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22198#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22199#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21762#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21763#L1397 assume !(0 == ~T11_E~0); 22978#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21338#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21339#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 21791#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 22019#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 22020#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 22998#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 22363#L1437 assume !(0 == ~E_5~0); 22364#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 23065#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 21771#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 21772#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 22425#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 22317#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 22318#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 22733#L1477 assume !(0 == ~E_13~0); 21507#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 21508#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23258#L646-1 assume 1 == ~m_pc~0; 22944#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 22705#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23096#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23286#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 23287#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23067#L665-1 assume 1 == ~t1_pc~0; 23068#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22341#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22342#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21669#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21670#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23248#L684-1 assume 1 == ~t2_pc~0; 22659#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22661#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22648#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22649#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22749#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21792#L703-1 assume 1 == ~t3_pc~0; 21793#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22588#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22728#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22994#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23307#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23073#L722-1 assume 1 == ~t4_pc~0; 23074#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22070#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23290#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22430#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22431#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23044#L741-1 assume 1 == ~t5_pc~0; 23299#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 21483#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21671#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21658#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21659#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22380#L760-1 assume 1 == ~t6_pc~0; 23255#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 22692#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22693#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22707#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22214#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22215#L779-1 assume !(1 == ~t7_pc~0); 22384#L789-1 is_transmit7_triggered_~__retres1~7#1 := 0; 22383#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21287#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21288#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22453#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22454#L798-1 assume !(1 == ~t8_pc~0); 22485#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 22032#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22033#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21499#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21500#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22727#L817-1 assume 1 == ~t9_pc~0; 23177#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21812#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21813#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22787#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 23145#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23048#L836-1 assume !(1 == ~t10_pc~0); 21490#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 21491#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22897#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22568#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22569#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23176#L855-1 assume !(1 == ~t11_pc~0); 22774#L865-1 is_transmit11_triggered_~__retres1~11#1 := 0; 21865#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 21713#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21714#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22634#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 22635#L874-1 assume 1 == ~t12_pc~0; 22669#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 23091#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 23184#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 21492#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21493#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22074#L893-1 assume 1 == ~t13_pc~0; 21590#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21591#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21819#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21820#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 23168#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 22216#L912-1 assume 1 == ~t14_pc~0; 22217#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 22614#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 23023#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 21774#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 21775#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21862#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 21572#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21573#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23215#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22053#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22054#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22418#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21880#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21881#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22360#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 23239#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 23300#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22724#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 22480#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 21559#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 21560#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 22276#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 21846#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 21847#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 23209#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 23210#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 23174#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 23020#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 23021#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 22523#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 22177#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 22178#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 21259#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 21260#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 21472#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 21869#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 21423#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 22807#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 22802#L2036 assume !(0 == start_simulation_~tmp~3#1); 21824#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 21825#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 21251#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 21369#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 21370#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22310#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22311#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 23282#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 21311#L2017 [2024-11-17 08:54:01,120 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,120 INFO L85 PathProgramCache]: Analyzing trace with hash -569200196, now seen corresponding path program 1 times [2024-11-17 08:54:01,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983368935] [2024-11-17 08:54:01,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,121 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1983368935] [2024-11-17 08:54:01,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1983368935] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,181 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,181 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:01,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [913378673] [2024-11-17 08:54:01,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,182 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:01,182 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,182 INFO L85 PathProgramCache]: Analyzing trace with hash 1004523546, now seen corresponding path program 1 times [2024-11-17 08:54:01,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002123486] [2024-11-17 08:54:01,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2002123486] [2024-11-17 08:54:01,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2002123486] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,274 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,274 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:01,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667046022] [2024-11-17 08:54:01,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,276 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:01,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:01,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:01,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:01,277 INFO L87 Difference]: Start difference. First operand 2114 states and 3097 transitions. cyclomatic complexity: 984 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:01,312 INFO L93 Difference]: Finished difference Result 2114 states and 3096 transitions. [2024-11-17 08:54:01,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3096 transitions. [2024-11-17 08:54:01,320 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:01,328 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3096 transitions. [2024-11-17 08:54:01,328 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:01,330 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:01,330 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3096 transitions. [2024-11-17 08:54:01,332 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:01,332 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3096 transitions. [2024-11-17 08:54:01,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3096 transitions. [2024-11-17 08:54:01,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:01,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4645222327341532) internal successors, (3096), 2113 states have internal predecessors, (3096), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3096 transitions. [2024-11-17 08:54:01,371 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3096 transitions. [2024-11-17 08:54:01,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:01,373 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3096 transitions. [2024-11-17 08:54:01,373 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-17 08:54:01,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3096 transitions. [2024-11-17 08:54:01,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:01,381 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:01,381 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:01,383 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,384 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,385 INFO L745 eck$LassoCheckResult]: Stem: 26409#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 26410#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 27013#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26430#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26431#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 26622#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25798#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25799#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26725#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26726#L964 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 25740#L969 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25741#L974 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 27467#L979 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 27458#L984 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 26260#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26261#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27036#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 27040#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 27167#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 26200#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26201#L1342-1 assume !(0 == ~M_E~0); 26761#L1347-1 assume !(0 == ~T1_E~0); 27313#L1352-1 assume !(0 == ~T2_E~0); 27101#L1357-1 assume !(0 == ~T3_E~0); 26326#L1362-1 assume !(0 == ~T4_E~0); 26327#L1367-1 assume !(0 == ~T5_E~0); 25882#L1372-1 assume !(0 == ~T6_E~0); 25883#L1377-1 assume !(0 == ~T7_E~0); 26243#L1382-1 assume !(0 == ~T8_E~0); 26244#L1387-1 assume !(0 == ~T9_E~0); 26987#L1392-1 assume !(0 == ~T10_E~0); 26279#L1397-1 assume !(0 == ~T11_E~0); 26280#L1402-1 assume !(0 == ~T12_E~0); 25891#L1407-1 assume !(0 == ~T13_E~0); 25892#L1412-1 assume !(0 == ~T14_E~0); 27212#L1417-1 assume !(0 == ~E_1~0); 27213#L1422-1 assume !(0 == ~E_2~0); 27511#L1427-1 assume !(0 == ~E_3~0); 26097#L1432-1 assume !(0 == ~E_4~0); 26098#L1437-1 assume !(0 == ~E_5~0); 27144#L1442-1 assume !(0 == ~E_6~0); 27145#L1447-1 assume !(0 == ~E_7~0); 26979#L1452-1 assume !(0 == ~E_8~0); 25638#L1457-1 assume !(0 == ~E_9~0); 25639#L1462-1 assume !(0 == ~E_10~0); 27175#L1467-1 assume !(0 == ~E_11~0); 27190#L1472-1 assume !(0 == ~E_12~0); 27191#L1477-1 assume !(0 == ~E_13~0); 26938#L1482-1 assume !(0 == ~E_14~0); 26033#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26034#L646-15 assume 1 == ~m_pc~0; 26894#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 26338#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26339#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26731#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25764#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25765#L665-15 assume 1 == ~t1_pc~0; 25563#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25564#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26434#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27427#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 27422#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26776#L684-15 assume 1 == ~t2_pc~0; 26777#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26613#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26614#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27233#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 27234#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27230#L703-15 assume 1 == ~t3_pc~0; 26826#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26827#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26423#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26424#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 27317#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27318#L722-15 assume 1 == ~t4_pc~0; 26446#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26447#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27415#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26670#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26671#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27488#L741-15 assume 1 == ~t5_pc~0; 26166#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 26167#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26468#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26908#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 26004#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26005#L760-15 assume 1 == ~t6_pc~0; 26926#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26927#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26488#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26489#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 26020#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26021#L779-15 assume 1 == ~t7_pc~0; 27010#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25747#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25878#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25879#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 27548#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26215#L798-15 assume 1 == ~t8_pc~0; 26216#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 26692#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27552#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 27300#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27219#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26493#L817-15 assume 1 == ~t9_pc~0; 26494#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25735#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26959#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26960#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 27473#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27474#L836-15 assume 1 == ~t10_pc~0; 26846#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25836#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25837#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26490#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 27398#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26418#L855-15 assume 1 == ~t11_pc~0; 26419#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26442#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 27277#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26955#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 26956#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25455#L874-15 assume 1 == ~t12_pc~0; 25456#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27271#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26749#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26750#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 26308#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25478#L893-15 assume 1 == ~t13_pc~0; 25479#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 26074#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 26853#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26854#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 26874#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 26209#L912-15 assume 1 == ~t14_pc~0; 26210#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 27009#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 27459#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 27460#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 26916#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26218#L1495-1 assume !(1 == ~M_E~0); 26219#L1500-1 assume !(1 == ~T1_E~0); 26715#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26716#L1510-1 assume !(1 == ~T3_E~0); 26768#L1515-1 assume !(1 == ~T4_E~0); 26769#L1520-1 assume !(1 == ~T5_E~0); 27376#L1525-1 assume !(1 == ~T6_E~0); 27072#L1530-1 assume !(1 == ~T7_E~0); 25962#L1535-1 assume !(1 == ~T8_E~0); 25963#L1540-1 assume !(1 == ~T9_E~0); 25476#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25477#L1550-1 assume !(1 == ~T11_E~0); 25676#L1555-1 assume !(1 == ~T12_E~0); 25677#L1560-1 assume !(1 == ~T13_E~0); 26017#L1565-1 assume !(1 == ~T14_E~0); 27520#L1570-1 assume !(1 == ~E_1~0); 26951#L1575-1 assume !(1 == ~E_2~0); 26331#L1580-1 assume !(1 == ~E_3~0); 26332#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26788#L1590-1 assume !(1 == ~E_5~0); 26373#L1595-1 assume !(1 == ~E_6~0); 26374#L1600-1 assume !(1 == ~E_7~0); 26723#L1605-1 assume !(1 == ~E_8~0); 26724#L1610-1 assume !(1 == ~E_9~0); 27254#L1615-1 assume !(1 == ~E_10~0); 26157#L1620-1 assume !(1 == ~E_11~0); 26158#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 26980#L1630-1 assume !(1 == ~E_13~0); 26372#L1635-1 assume !(1 == ~E_14~0); 25547#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 25548#L2017 [2024-11-17 08:54:01,385 INFO L747 eck$LassoCheckResult]: Loop: 25548#L2017 assume true; 26568#L2017-1 assume !false; 26123#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25925#L1110 assume true; 25631#L1110-1 assume !false; 25632#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 27431#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 26348#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 27341#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27005#L1115 assume !(0 != eval_~tmp~0#1); 27006#L1118 assume true; 27076#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26088#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25666#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 25667#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26707#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25913#L1357 assume !(0 == ~T3_E~0); 25914#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26830#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26831#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26945#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26435#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26436#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25999#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26000#L1397 assume !(0 == ~T11_E~0); 27215#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25575#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25576#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 26028#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 26256#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 26257#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 27235#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 26602#L1437 assume !(0 == ~E_5~0); 26603#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 27302#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 26008#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 26009#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 26662#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 26554#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 26555#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 26970#L1477 assume !(0 == ~E_13~0); 25744#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 25745#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27495#L646-1 assume 1 == ~m_pc~0; 27181#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 26942#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27333#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27523#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27524#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27304#L665-1 assume 1 == ~t1_pc~0; 27305#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26578#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26579#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25907#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25908#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27485#L684-1 assume 1 == ~t2_pc~0; 26896#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26898#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26885#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26886#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26986#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26029#L703-1 assume 1 == ~t3_pc~0; 26030#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 26825#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26966#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27231#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27544#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27310#L722-1 assume !(1 == ~t4_pc~0); 26306#L732-1 is_transmit4_triggered_~__retres1~4#1 := 0; 26307#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27527#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26667#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26668#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27281#L741-1 assume 1 == ~t5_pc~0; 27536#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25720#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25906#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25895#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25896#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26615#L760-1 assume 1 == ~t6_pc~0; 27492#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26929#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26930#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26944#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26451#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26452#L779-1 assume 1 == ~t7_pc~0; 26619#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26620#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25524#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25525#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 26690#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26691#L798-1 assume !(1 == ~t8_pc~0); 26722#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 26269#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26270#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25736#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 25737#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26965#L817-1 assume 1 == ~t9_pc~0; 27414#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 26049#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26050#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 27024#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 27382#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 27285#L836-1 assume !(1 == ~t10_pc~0); 25730#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 25731#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27134#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26805#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26806#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 27413#L855-1 assume !(1 == ~t11_pc~0); 27011#L865-1 is_transmit11_triggered_~__retres1~11#1 := 0; 26102#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25950#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25951#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 26871#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 26872#L874-1 assume 1 == ~t12_pc~0; 26906#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 27328#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 27421#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25732#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25733#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26311#L893-1 assume 1 == ~t13_pc~0; 25827#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25828#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 26056#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26057#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 27405#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 26453#L912-1 assume 1 == ~t14_pc~0; 26454#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 26851#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 27260#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 26011#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 26012#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26099#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 25809#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25810#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27452#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26290#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26291#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26655#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26117#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26118#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26597#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27477#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 27537#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26961#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26717#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 25796#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 25797#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 26513#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 26083#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 26084#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 27446#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 27447#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 27411#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 27257#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 27258#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 26760#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 26414#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 26415#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 25496#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 25497#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 25709#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26106#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 25660#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 27044#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 27039#L2036 assume !(0 == start_simulation_~tmp~3#1); 26061#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 26062#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 25488#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 25606#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 25607#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26547#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26548#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 27519#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 25548#L2017 [2024-11-17 08:54:01,386 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,386 INFO L85 PathProgramCache]: Analyzing trace with hash -854336099, now seen corresponding path program 1 times [2024-11-17 08:54:01,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1439790177] [2024-11-17 08:54:01,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,464 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1439790177] [2024-11-17 08:54:01,464 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1439790177] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:01,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647764033] [2024-11-17 08:54:01,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,465 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:01,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,466 INFO L85 PathProgramCache]: Analyzing trace with hash 450536154, now seen corresponding path program 1 times [2024-11-17 08:54:01,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574665996] [2024-11-17 08:54:01,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574665996] [2024-11-17 08:54:01,563 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1574665996] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,563 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,563 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:01,563 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317442830] [2024-11-17 08:54:01,563 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,564 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:01,564 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:01,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:01,565 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:01,565 INFO L87 Difference]: Start difference. First operand 2114 states and 3096 transitions. cyclomatic complexity: 983 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:01,600 INFO L93 Difference]: Finished difference Result 2114 states and 3095 transitions. [2024-11-17 08:54:01,600 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3095 transitions. [2024-11-17 08:54:01,608 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:01,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3095 transitions. [2024-11-17 08:54:01,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:01,621 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:01,621 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3095 transitions. [2024-11-17 08:54:01,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:01,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3095 transitions. [2024-11-17 08:54:01,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3095 transitions. [2024-11-17 08:54:01,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:01,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4640491958372752) internal successors, (3095), 2113 states have internal predecessors, (3095), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3095 transitions. [2024-11-17 08:54:01,665 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3095 transitions. [2024-11-17 08:54:01,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:01,666 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3095 transitions. [2024-11-17 08:54:01,666 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-17 08:54:01,666 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3095 transitions. [2024-11-17 08:54:01,674 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:01,674 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:01,674 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:01,676 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,677 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:01,677 INFO L745 eck$LassoCheckResult]: Stem: 30646#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 30647#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 31250#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30667#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30668#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 30859#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30035#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30036#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30962#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30963#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29977#L969 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 29978#L974 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 31704#L979 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 31695#L984 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 30497#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 30498#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31273#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31277#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 31404#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 30437#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30438#L1342-1 assume !(0 == ~M_E~0); 30998#L1347-1 assume !(0 == ~T1_E~0); 31550#L1352-1 assume !(0 == ~T2_E~0); 31338#L1357-1 assume !(0 == ~T3_E~0); 30563#L1362-1 assume !(0 == ~T4_E~0); 30564#L1367-1 assume !(0 == ~T5_E~0); 30119#L1372-1 assume !(0 == ~T6_E~0); 30120#L1377-1 assume !(0 == ~T7_E~0); 30480#L1382-1 assume !(0 == ~T8_E~0); 30481#L1387-1 assume !(0 == ~T9_E~0); 31224#L1392-1 assume !(0 == ~T10_E~0); 30516#L1397-1 assume !(0 == ~T11_E~0); 30517#L1402-1 assume !(0 == ~T12_E~0); 30128#L1407-1 assume !(0 == ~T13_E~0); 30129#L1412-1 assume !(0 == ~T14_E~0); 31449#L1417-1 assume !(0 == ~E_1~0); 31450#L1422-1 assume !(0 == ~E_2~0); 31748#L1427-1 assume !(0 == ~E_3~0); 30334#L1432-1 assume !(0 == ~E_4~0); 30335#L1437-1 assume !(0 == ~E_5~0); 31381#L1442-1 assume !(0 == ~E_6~0); 31382#L1447-1 assume !(0 == ~E_7~0); 31216#L1452-1 assume !(0 == ~E_8~0); 29875#L1457-1 assume !(0 == ~E_9~0); 29876#L1462-1 assume !(0 == ~E_10~0); 31412#L1467-1 assume !(0 == ~E_11~0); 31427#L1472-1 assume !(0 == ~E_12~0); 31428#L1477-1 assume !(0 == ~E_13~0); 31175#L1482-1 assume !(0 == ~E_14~0); 30270#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30271#L646-15 assume 1 == ~m_pc~0; 31131#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30575#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30576#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30968#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30001#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30002#L665-15 assume 1 == ~t1_pc~0; 29800#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29801#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30671#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31664#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 31659#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31013#L684-15 assume 1 == ~t2_pc~0; 31014#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 30850#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30851#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31470#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 31471#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31468#L703-15 assume 1 == ~t3_pc~0; 31063#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31064#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30660#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30661#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 31554#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31555#L722-15 assume 1 == ~t4_pc~0; 30683#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30684#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31652#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30907#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30908#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31725#L741-15 assume 1 == ~t5_pc~0; 30405#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30406#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30705#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31145#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 30241#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30242#L760-15 assume 1 == ~t6_pc~0; 31163#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31164#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30725#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 30726#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 30257#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30258#L779-15 assume 1 == ~t7_pc~0; 31247#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29984#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30115#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 30116#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 31785#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30452#L798-15 assume 1 == ~t8_pc~0; 30453#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30929#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31789#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31537#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 31456#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 30730#L817-15 assume 1 == ~t9_pc~0; 30731#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29972#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31196#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31197#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 31710#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31711#L836-15 assume 1 == ~t10_pc~0; 31083#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 30073#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30074#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 30727#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 31635#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30655#L855-15 assume 1 == ~t11_pc~0; 30656#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 30679#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31514#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31192#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 31193#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29692#L874-15 assume 1 == ~t12_pc~0; 29693#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31508#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30986#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30987#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 30545#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29715#L893-15 assume 1 == ~t13_pc~0; 29716#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30311#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 31090#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 31091#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 31111#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 30448#L912-15 assume 1 == ~t14_pc~0; 30449#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 31246#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 31696#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 31697#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 31155#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30455#L1495-1 assume !(1 == ~M_E~0); 30456#L1500-1 assume !(1 == ~T1_E~0); 30952#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30953#L1510-1 assume !(1 == ~T3_E~0); 31005#L1515-1 assume !(1 == ~T4_E~0); 31006#L1520-1 assume !(1 == ~T5_E~0); 31613#L1525-1 assume !(1 == ~T6_E~0); 31309#L1530-1 assume !(1 == ~T7_E~0); 30199#L1535-1 assume !(1 == ~T8_E~0); 30200#L1540-1 assume !(1 == ~T9_E~0); 29713#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29714#L1550-1 assume !(1 == ~T11_E~0); 29913#L1555-1 assume !(1 == ~T12_E~0); 29914#L1560-1 assume !(1 == ~T13_E~0); 30254#L1565-1 assume !(1 == ~T14_E~0); 31757#L1570-1 assume !(1 == ~E_1~0); 31188#L1575-1 assume !(1 == ~E_2~0); 30568#L1580-1 assume !(1 == ~E_3~0); 30569#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 31025#L1590-1 assume !(1 == ~E_5~0); 30610#L1595-1 assume !(1 == ~E_6~0); 30611#L1600-1 assume !(1 == ~E_7~0); 30960#L1605-1 assume !(1 == ~E_8~0); 30961#L1610-1 assume !(1 == ~E_9~0); 31491#L1615-1 assume !(1 == ~E_10~0); 30394#L1620-1 assume !(1 == ~E_11~0); 30395#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 31217#L1630-1 assume !(1 == ~E_13~0); 30609#L1635-1 assume !(1 == ~E_14~0); 29784#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 29785#L2017 [2024-11-17 08:54:01,678 INFO L747 eck$LassoCheckResult]: Loop: 29785#L2017 assume true; 30805#L2017-1 assume !false; 30360#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30162#L1110 assume true; 29868#L1110-1 assume !false; 29869#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 31668#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 30586#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 31578#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31242#L1115 assume !(0 != eval_~tmp~0#1); 31243#L1118 assume true; 31313#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30326#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29905#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 29906#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30944#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30150#L1357 assume !(0 == ~T3_E~0); 30151#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31067#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31068#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31182#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30672#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30673#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30236#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 30237#L1397 assume !(0 == ~T11_E~0); 31452#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29812#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29813#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 30265#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 30493#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 30494#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 31472#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 30839#L1437 assume !(0 == ~E_5~0); 30840#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 31539#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 30245#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 30246#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 30899#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 30791#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 30792#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 31209#L1477 assume !(0 == ~E_13~0); 29981#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 29982#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31732#L646-1 assume 1 == ~m_pc~0; 31418#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 31179#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31570#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 31760#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31761#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31541#L665-1 assume 1 == ~t1_pc~0; 31542#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 30815#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30816#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30144#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30145#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31722#L684-1 assume 1 == ~t2_pc~0; 31133#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31135#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31122#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31123#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31223#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30266#L703-1 assume 1 == ~t3_pc~0; 30267#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31062#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31201#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31467#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31781#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31547#L722-1 assume 1 == ~t4_pc~0; 31548#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30544#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31764#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30902#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30903#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31518#L741-1 assume !(1 == ~t5_pc~0); 29956#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 29957#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30143#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 30132#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30133#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30852#L760-1 assume 1 == ~t6_pc~0; 31729#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31166#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31167#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31181#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30688#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30689#L779-1 assume 1 == ~t7_pc~0; 30856#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 30857#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29761#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29762#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30927#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30928#L798-1 assume 1 == ~t8_pc~0; 31268#L799-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 30506#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 30507#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29973#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29974#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31203#L817-1 assume 1 == ~t9_pc~0; 31651#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 30286#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30287#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31261#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 31619#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31522#L836-1 assume 1 == ~t10_pc~0; 31523#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 29968#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31371#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31042#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31043#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 31650#L855-1 assume !(1 == ~t11_pc~0); 31248#L865-1 is_transmit11_triggered_~__retres1~11#1 := 0; 30339#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30187#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 30188#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31108#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 31109#L874-1 assume 1 == ~t12_pc~0; 31143#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 31565#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 31658#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29969#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29970#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30548#L893-1 assume 1 == ~t13_pc~0; 30064#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 30065#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 30293#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30294#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 31642#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 30690#L912-1 assume 1 == ~t14_pc~0; 30691#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 31088#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 31497#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 30248#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 30249#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30336#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 30046#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30047#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31689#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30527#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30528#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30892#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30354#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30355#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30834#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31714#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 31774#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31198#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30954#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 30033#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 30034#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 30750#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 30320#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 30321#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 31683#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 31684#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 31648#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 31494#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 31495#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 30997#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 30651#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 30652#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 29733#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 29734#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 29946#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30343#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29897#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 31281#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 31276#L2036 assume !(0 == start_simulation_~tmp~3#1); 30298#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 30299#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 29725#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 29843#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 29844#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30784#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30785#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 31756#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 29785#L2017 [2024-11-17 08:54:01,678 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,679 INFO L85 PathProgramCache]: Analyzing trace with hash -1556270692, now seen corresponding path program 1 times [2024-11-17 08:54:01,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854599568] [2024-11-17 08:54:01,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,740 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,741 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854599568] [2024-11-17 08:54:01,743 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854599568] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,743 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,743 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:01,744 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1105021063] [2024-11-17 08:54:01,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,744 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:01,744 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:01,744 INFO L85 PathProgramCache]: Analyzing trace with hash 927667040, now seen corresponding path program 1 times [2024-11-17 08:54:01,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:01,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251781702] [2024-11-17 08:54:01,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:01,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:01,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:01,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:01,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:01,848 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1251781702] [2024-11-17 08:54:01,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1251781702] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:01,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:01,849 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:01,849 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1494959495] [2024-11-17 08:54:01,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:01,849 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:01,850 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:01,850 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:01,850 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:01,850 INFO L87 Difference]: Start difference. First operand 2114 states and 3095 transitions. cyclomatic complexity: 982 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:01,901 INFO L93 Difference]: Finished difference Result 2114 states and 3094 transitions. [2024-11-17 08:54:01,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3094 transitions. [2024-11-17 08:54:01,908 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:01,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3094 transitions. [2024-11-17 08:54:01,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:01,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:01,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3094 transitions. [2024-11-17 08:54:01,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:01,921 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3094 transitions. [2024-11-17 08:54:01,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3094 transitions. [2024-11-17 08:54:01,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:01,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4635761589403973) internal successors, (3094), 2113 states have internal predecessors, (3094), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:01,990 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3094 transitions. [2024-11-17 08:54:01,991 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3094 transitions. [2024-11-17 08:54:01,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:01,993 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3094 transitions. [2024-11-17 08:54:01,993 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-17 08:54:01,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3094 transitions. [2024-11-17 08:54:02,000 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:02,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:02,001 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:02,003 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,003 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,003 INFO L745 eck$LassoCheckResult]: Stem: 34883#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 34884#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 35487#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34904#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34905#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 35096#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34272#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34273#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35199#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35200#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34214#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34215#L974 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 35941#L979 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 35932#L984 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 34734#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 34735#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35510#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35514#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 35641#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 34674#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34675#L1342-1 assume !(0 == ~M_E~0); 35235#L1347-1 assume !(0 == ~T1_E~0); 35787#L1352-1 assume !(0 == ~T2_E~0); 35575#L1357-1 assume !(0 == ~T3_E~0); 34800#L1362-1 assume !(0 == ~T4_E~0); 34801#L1367-1 assume !(0 == ~T5_E~0); 34356#L1372-1 assume !(0 == ~T6_E~0); 34357#L1377-1 assume !(0 == ~T7_E~0); 34717#L1382-1 assume !(0 == ~T8_E~0); 34718#L1387-1 assume !(0 == ~T9_E~0); 35461#L1392-1 assume !(0 == ~T10_E~0); 34753#L1397-1 assume !(0 == ~T11_E~0); 34754#L1402-1 assume !(0 == ~T12_E~0); 34365#L1407-1 assume !(0 == ~T13_E~0); 34366#L1412-1 assume !(0 == ~T14_E~0); 35686#L1417-1 assume !(0 == ~E_1~0); 35687#L1422-1 assume !(0 == ~E_2~0); 35985#L1427-1 assume !(0 == ~E_3~0); 34571#L1432-1 assume !(0 == ~E_4~0); 34572#L1437-1 assume !(0 == ~E_5~0); 35618#L1442-1 assume !(0 == ~E_6~0); 35619#L1447-1 assume !(0 == ~E_7~0); 35453#L1452-1 assume !(0 == ~E_8~0); 34112#L1457-1 assume !(0 == ~E_9~0); 34113#L1462-1 assume !(0 == ~E_10~0); 35649#L1467-1 assume !(0 == ~E_11~0); 35664#L1472-1 assume !(0 == ~E_12~0); 35665#L1477-1 assume !(0 == ~E_13~0); 35412#L1482-1 assume !(0 == ~E_14~0); 34507#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34508#L646-15 assume 1 == ~m_pc~0; 35368#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 34812#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34813#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35205#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34238#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34239#L665-15 assume 1 == ~t1_pc~0; 34037#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34038#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34908#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35901#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 35896#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35250#L684-15 assume 1 == ~t2_pc~0; 35251#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35087#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35088#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35707#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 35708#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35705#L703-15 assume 1 == ~t3_pc~0; 35300#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35301#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34897#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34898#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 35791#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35792#L722-15 assume 1 == ~t4_pc~0; 34920#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34921#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35889#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35144#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35145#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35962#L741-15 assume 1 == ~t5_pc~0; 34642#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34643#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34942#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35382#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 34478#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34479#L760-15 assume 1 == ~t6_pc~0; 35400#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35401#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34962#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34963#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 34494#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34495#L779-15 assume 1 == ~t7_pc~0; 35484#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34221#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34352#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34353#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 36022#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34689#L798-15 assume 1 == ~t8_pc~0; 34690#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35166#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36026#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35774#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35693#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34967#L817-15 assume 1 == ~t9_pc~0; 34968#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34209#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35433#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35434#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 35947#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35948#L836-15 assume 1 == ~t10_pc~0; 35320#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34310#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34311#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34964#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 35872#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34892#L855-15 assume 1 == ~t11_pc~0; 34893#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34916#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35751#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35429#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 35430#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33929#L874-15 assume 1 == ~t12_pc~0; 33930#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35745#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35223#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35224#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34782#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33952#L893-15 assume 1 == ~t13_pc~0; 33953#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 34550#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 35327#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 35328#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 35348#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 34685#L912-15 assume 1 == ~t14_pc~0; 34686#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 35483#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 35933#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 35934#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 35392#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34693#L1495-1 assume !(1 == ~M_E~0); 34694#L1500-1 assume !(1 == ~T1_E~0); 35189#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35190#L1510-1 assume !(1 == ~T3_E~0); 35242#L1515-1 assume !(1 == ~T4_E~0); 35243#L1520-1 assume !(1 == ~T5_E~0); 35850#L1525-1 assume !(1 == ~T6_E~0); 35546#L1530-1 assume !(1 == ~T7_E~0); 34436#L1535-1 assume !(1 == ~T8_E~0); 34437#L1540-1 assume !(1 == ~T9_E~0); 33950#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33951#L1550-1 assume !(1 == ~T11_E~0); 34150#L1555-1 assume !(1 == ~T12_E~0); 34151#L1560-1 assume !(1 == ~T13_E~0); 34491#L1565-1 assume !(1 == ~T14_E~0); 35994#L1570-1 assume !(1 == ~E_1~0); 35425#L1575-1 assume !(1 == ~E_2~0); 34805#L1580-1 assume !(1 == ~E_3~0); 34806#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 35262#L1590-1 assume !(1 == ~E_5~0); 34847#L1595-1 assume !(1 == ~E_6~0); 34848#L1600-1 assume !(1 == ~E_7~0); 35197#L1605-1 assume !(1 == ~E_8~0); 35198#L1610-1 assume !(1 == ~E_9~0); 35728#L1615-1 assume !(1 == ~E_10~0); 34631#L1620-1 assume !(1 == ~E_11~0); 34632#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 35454#L1630-1 assume !(1 == ~E_13~0); 34846#L1635-1 assume !(1 == ~E_14~0); 34021#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 34022#L2017 [2024-11-17 08:54:02,004 INFO L747 eck$LassoCheckResult]: Loop: 34022#L2017 assume true; 35042#L2017-1 assume !false; 34597#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34399#L1110 assume true; 34105#L1110-1 assume !false; 34106#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 35905#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 34823#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 35815#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35479#L1115 assume !(0 != eval_~tmp~0#1); 35480#L1118 assume true; 35550#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34563#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34142#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 34143#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35181#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34387#L1357 assume !(0 == ~T3_E~0); 34388#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35304#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35305#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35419#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34909#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 34910#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34473#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34474#L1397 assume !(0 == ~T11_E~0); 35689#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 34049#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34050#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 34502#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 34730#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 34731#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 35709#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 35076#L1437 assume !(0 == ~E_5~0); 35077#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 35776#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 34482#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 34483#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 35136#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 35028#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 35029#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 35446#L1477 assume !(0 == ~E_13~0); 34218#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 34219#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35969#L646-1 assume 1 == ~m_pc~0; 35655#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 35416#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35807#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 35997#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35998#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35778#L665-1 assume 1 == ~t1_pc~0; 35779#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35052#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35053#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34381#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34382#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35959#L684-1 assume 1 == ~t2_pc~0; 35370#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35372#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35359#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35360#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35460#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34503#L703-1 assume 1 == ~t3_pc~0; 34504#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35299#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35438#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35704#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36018#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35784#L722-1 assume 1 == ~t4_pc~0; 35785#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34781#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36001#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35139#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35140#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35755#L741-1 assume !(1 == ~t5_pc~0); 34193#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 34194#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34380#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34369#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34370#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35089#L760-1 assume 1 == ~t6_pc~0; 35966#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35403#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35404#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35418#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34925#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34926#L779-1 assume 1 == ~t7_pc~0; 35093#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35094#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33998#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33999#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 35164#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35165#L798-1 assume 1 == ~t8_pc~0; 35505#L799-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34746#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34747#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34212#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 34213#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35440#L817-1 assume 1 == ~t9_pc~0; 35888#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34523#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34524#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35498#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35856#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35759#L836-1 assume 1 == ~t10_pc~0; 35760#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34205#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35608#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35279#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35280#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35887#L855-1 assume 1 == ~t11_pc~0; 35654#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34576#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34424#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34425#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35345#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 35346#L874-1 assume 1 == ~t12_pc~0; 35380#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 35802#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 35895#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34206#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 34207#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34785#L893-1 assume 1 == ~t13_pc~0; 34301#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 34302#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 34530#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34531#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 35879#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 34927#L912-1 assume 1 == ~t14_pc~0; 34928#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 35325#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 35734#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 34485#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 34486#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34573#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 34283#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34284#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35926#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34764#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34765#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35129#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34591#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34592#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35071#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35951#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 36011#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35435#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 35191#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34270#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 34271#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 34987#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 34557#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 34558#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 35920#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 35921#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 35885#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 35731#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 35732#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 35234#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 34888#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 34889#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 33970#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 33971#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 34183#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34580#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 34134#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 35518#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 35513#L2036 assume !(0 == start_simulation_~tmp~3#1); 34535#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 34536#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 33962#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 34080#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 34081#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35021#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35022#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 35993#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 34022#L2017 [2024-11-17 08:54:02,005 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,006 INFO L85 PathProgramCache]: Analyzing trace with hash -1163271747, now seen corresponding path program 1 times [2024-11-17 08:54:02,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,006 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003966904] [2024-11-17 08:54:02,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,059 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,060 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1003966904] [2024-11-17 08:54:02,060 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1003966904] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,060 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,060 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:02,060 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1860816124] [2024-11-17 08:54:02,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,061 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:02,061 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,062 INFO L85 PathProgramCache]: Analyzing trace with hash 1754954563, now seen corresponding path program 1 times [2024-11-17 08:54:02,062 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,062 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1239625534] [2024-11-17 08:54:02,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,152 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,152 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1239625534] [2024-11-17 08:54:02,152 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1239625534] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,153 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,153 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:02,153 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2146594113] [2024-11-17 08:54:02,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,153 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:02,153 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:02,154 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:02,154 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:02,154 INFO L87 Difference]: Start difference. First operand 2114 states and 3094 transitions. cyclomatic complexity: 981 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:02,186 INFO L93 Difference]: Finished difference Result 2114 states and 3093 transitions. [2024-11-17 08:54:02,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3093 transitions. [2024-11-17 08:54:02,193 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:02,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3093 transitions. [2024-11-17 08:54:02,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:02,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:02,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3093 transitions. [2024-11-17 08:54:02,211 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:02,211 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3093 transitions. [2024-11-17 08:54:02,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3093 transitions. [2024-11-17 08:54:02,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:02,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4631031220435193) internal successors, (3093), 2113 states have internal predecessors, (3093), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3093 transitions. [2024-11-17 08:54:02,247 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3093 transitions. [2024-11-17 08:54:02,248 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:02,248 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3093 transitions. [2024-11-17 08:54:02,248 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-17 08:54:02,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3093 transitions. [2024-11-17 08:54:02,254 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:02,255 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:02,255 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:02,257 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,257 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,257 INFO L745 eck$LassoCheckResult]: Stem: 39120#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 39121#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 39724#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39141#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39142#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 39333#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38509#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38510#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39436#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39437#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38451#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38452#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40178#L979 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 40169#L984 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 38971#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 38972#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 39747#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39751#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 39878#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 38911#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38912#L1342-1 assume !(0 == ~M_E~0); 39472#L1347-1 assume !(0 == ~T1_E~0); 40024#L1352-1 assume !(0 == ~T2_E~0); 39812#L1357-1 assume !(0 == ~T3_E~0); 39037#L1362-1 assume !(0 == ~T4_E~0); 39038#L1367-1 assume !(0 == ~T5_E~0); 38593#L1372-1 assume !(0 == ~T6_E~0); 38594#L1377-1 assume !(0 == ~T7_E~0); 38954#L1382-1 assume !(0 == ~T8_E~0); 38955#L1387-1 assume !(0 == ~T9_E~0); 39698#L1392-1 assume !(0 == ~T10_E~0); 38990#L1397-1 assume !(0 == ~T11_E~0); 38991#L1402-1 assume !(0 == ~T12_E~0); 38602#L1407-1 assume !(0 == ~T13_E~0); 38603#L1412-1 assume !(0 == ~T14_E~0); 39923#L1417-1 assume !(0 == ~E_1~0); 39924#L1422-1 assume !(0 == ~E_2~0); 40222#L1427-1 assume !(0 == ~E_3~0); 38808#L1432-1 assume !(0 == ~E_4~0); 38809#L1437-1 assume !(0 == ~E_5~0); 39855#L1442-1 assume !(0 == ~E_6~0); 39856#L1447-1 assume !(0 == ~E_7~0); 39690#L1452-1 assume !(0 == ~E_8~0); 38349#L1457-1 assume !(0 == ~E_9~0); 38350#L1462-1 assume !(0 == ~E_10~0); 39886#L1467-1 assume !(0 == ~E_11~0); 39901#L1472-1 assume !(0 == ~E_12~0); 39902#L1477-1 assume !(0 == ~E_13~0); 39649#L1482-1 assume !(0 == ~E_14~0); 38744#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38745#L646-15 assume 1 == ~m_pc~0; 39605#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39049#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39050#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39442#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 38475#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38476#L665-15 assume 1 == ~t1_pc~0; 38277#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 38278#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39145#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 40138#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 40133#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39487#L684-15 assume 1 == ~t2_pc~0; 39488#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39324#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39325#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39944#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 39945#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39942#L703-15 assume 1 == ~t3_pc~0; 39537#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39538#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39134#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39135#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 40028#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40029#L722-15 assume 1 == ~t4_pc~0; 39157#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39158#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40126#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39381#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39382#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40199#L741-15 assume 1 == ~t5_pc~0; 38879#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38880#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39179#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 39619#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 38715#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38716#L760-15 assume 1 == ~t6_pc~0; 39637#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39638#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39199#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39200#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 38731#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38732#L779-15 assume 1 == ~t7_pc~0; 39721#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38458#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38589#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38590#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 40259#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38926#L798-15 assume 1 == ~t8_pc~0; 38927#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39403#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 40263#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 40011#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39931#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39204#L817-15 assume 1 == ~t9_pc~0; 39205#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38446#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39670#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39671#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 40184#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 40185#L836-15 assume 1 == ~t10_pc~0; 39557#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38547#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38548#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39201#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 40109#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39129#L855-15 assume 1 == ~t11_pc~0; 39130#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 39153#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39988#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39666#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 39667#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 38166#L874-15 assume 1 == ~t12_pc~0; 38167#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 39982#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 39460#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39461#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 39019#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38189#L893-15 assume 1 == ~t13_pc~0; 38190#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38787#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 39564#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 39565#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 39585#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 38923#L912-15 assume 1 == ~t14_pc~0; 38924#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 39720#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 40170#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 40171#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 39630#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38930#L1495-1 assume !(1 == ~M_E~0); 38931#L1500-1 assume !(1 == ~T1_E~0); 39426#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39427#L1510-1 assume !(1 == ~T3_E~0); 39479#L1515-1 assume !(1 == ~T4_E~0); 39480#L1520-1 assume !(1 == ~T5_E~0); 40087#L1525-1 assume !(1 == ~T6_E~0); 39783#L1530-1 assume !(1 == ~T7_E~0); 38673#L1535-1 assume !(1 == ~T8_E~0); 38674#L1540-1 assume !(1 == ~T9_E~0); 38187#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38188#L1550-1 assume !(1 == ~T11_E~0); 38387#L1555-1 assume !(1 == ~T12_E~0); 38388#L1560-1 assume !(1 == ~T13_E~0); 38728#L1565-1 assume !(1 == ~T14_E~0); 40231#L1570-1 assume !(1 == ~E_1~0); 39662#L1575-1 assume !(1 == ~E_2~0); 39042#L1580-1 assume !(1 == ~E_3~0); 39043#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 39499#L1590-1 assume !(1 == ~E_5~0); 39084#L1595-1 assume !(1 == ~E_6~0); 39085#L1600-1 assume !(1 == ~E_7~0); 39434#L1605-1 assume !(1 == ~E_8~0); 39435#L1610-1 assume !(1 == ~E_9~0); 39965#L1615-1 assume !(1 == ~E_10~0); 38868#L1620-1 assume !(1 == ~E_11~0); 38869#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 39691#L1630-1 assume !(1 == ~E_13~0); 39083#L1635-1 assume !(1 == ~E_14~0); 38258#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 38259#L2017 [2024-11-17 08:54:02,258 INFO L747 eck$LassoCheckResult]: Loop: 38259#L2017 assume true; 39279#L2017-1 assume !false; 38834#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38636#L1110 assume true; 38342#L1110-1 assume !false; 38343#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 40142#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 39060#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 40052#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 39716#L1115 assume !(0 != eval_~tmp~0#1); 39717#L1118 assume true; 39787#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38800#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38379#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 38380#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39418#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38624#L1357 assume !(0 == ~T3_E~0); 38625#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39541#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39542#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39656#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39146#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39147#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38710#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38711#L1397 assume !(0 == ~T11_E~0); 39926#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38286#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 38287#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 38739#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 38967#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 38968#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 39946#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 39313#L1437 assume !(0 == ~E_5~0); 39314#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 40013#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 38719#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 38720#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 39373#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 39265#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 39266#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 39683#L1477 assume !(0 == ~E_13~0); 38455#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 38456#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40206#L646-1 assume 1 == ~m_pc~0; 39892#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 39653#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40044#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 40234#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 40235#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40015#L665-1 assume 1 == ~t1_pc~0; 40016#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39289#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39290#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38617#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38618#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40196#L684-1 assume 1 == ~t2_pc~0; 39607#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 39609#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39596#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39597#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 39697#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38740#L703-1 assume 1 == ~t3_pc~0; 38741#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39536#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39675#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39941#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 40255#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40021#L722-1 assume 1 == ~t4_pc~0; 40022#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 39018#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40238#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39377#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39378#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39992#L741-1 assume 1 == ~t5_pc~0; 40247#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38431#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38619#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38606#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38607#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39326#L760-1 assume 1 == ~t6_pc~0; 40203#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 39640#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 39641#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39655#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 39162#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39163#L779-1 assume 1 == ~t7_pc~0; 39330#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 39331#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38235#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38236#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 39401#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39402#L798-1 assume !(1 == ~t8_pc~0); 39433#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 38983#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38984#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38449#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38450#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39677#L817-1 assume !(1 == ~t9_pc~0); 40082#L827-1 is_transmit9_triggered_~__retres1~9#1 := 0; 38760#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38761#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39735#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 40093#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39996#L836-1 assume !(1 == ~t10_pc~0); 38441#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 38442#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39845#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39516#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 39517#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 40124#L855-1 assume 1 == ~t11_pc~0; 39891#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38813#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38661#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38662#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 39582#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 39583#L874-1 assume 1 == ~t12_pc~0; 39617#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 40039#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40132#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38443#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 38444#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 39022#L893-1 assume 1 == ~t13_pc~0; 38538#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 38539#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 38767#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38768#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 40116#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 39164#L912-1 assume 1 == ~t14_pc~0; 39165#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 39562#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 39971#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 38722#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 38723#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38810#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 38520#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38521#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40163#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39001#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39002#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39366#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38828#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38829#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39308#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40188#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 40248#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 39672#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 39428#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38507#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 38508#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 39224#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 38794#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 38795#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 40157#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 40158#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 40122#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 39968#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 39969#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 39471#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 39125#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 39126#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 38207#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 38208#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 38420#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38817#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 38371#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 39755#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 39750#L2036 assume !(0 == start_simulation_~tmp~3#1); 38772#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 38773#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 38199#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 38317#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 38318#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39258#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39259#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 40230#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 38259#L2017 [2024-11-17 08:54:02,259 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,259 INFO L85 PathProgramCache]: Analyzing trace with hash 650520956, now seen corresponding path program 1 times [2024-11-17 08:54:02,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455327640] [2024-11-17 08:54:02,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,305 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,305 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455327640] [2024-11-17 08:54:02,305 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [455327640] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,306 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,306 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:02,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [176130619] [2024-11-17 08:54:02,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,306 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:02,307 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,307 INFO L85 PathProgramCache]: Analyzing trace with hash 514997117, now seen corresponding path program 1 times [2024-11-17 08:54:02,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,307 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77215024] [2024-11-17 08:54:02,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,387 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,388 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77215024] [2024-11-17 08:54:02,388 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77215024] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,388 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,388 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:02,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [291683427] [2024-11-17 08:54:02,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,389 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:02,389 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:02,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:02,390 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:02,390 INFO L87 Difference]: Start difference. First operand 2114 states and 3093 transitions. cyclomatic complexity: 980 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:02,468 INFO L93 Difference]: Finished difference Result 2114 states and 3092 transitions. [2024-11-17 08:54:02,468 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3092 transitions. [2024-11-17 08:54:02,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:02,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3092 transitions. [2024-11-17 08:54:02,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:02,491 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:02,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3092 transitions. [2024-11-17 08:54:02,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:02,494 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3092 transitions. [2024-11-17 08:54:02,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3092 transitions. [2024-11-17 08:54:02,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:02,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4626300851466414) internal successors, (3092), 2113 states have internal predecessors, (3092), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3092 transitions. [2024-11-17 08:54:02,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3092 transitions. [2024-11-17 08:54:02,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:02,540 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3092 transitions. [2024-11-17 08:54:02,540 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-17 08:54:02,540 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3092 transitions. [2024-11-17 08:54:02,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:02,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:02,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:02,551 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,551 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,552 INFO L745 eck$LassoCheckResult]: Stem: 43357#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 43358#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 43961#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43378#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43379#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 43570#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42746#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42747#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43673#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43674#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42688#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42689#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 44415#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44406#L984 assume !(1 == ~t9_i~0);~t9_st~0 := 2; 43208#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 43209#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 43984#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 43988#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 44115#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 43148#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43149#L1342-1 assume !(0 == ~M_E~0); 43709#L1347-1 assume !(0 == ~T1_E~0); 44261#L1352-1 assume !(0 == ~T2_E~0); 44049#L1357-1 assume !(0 == ~T3_E~0); 43274#L1362-1 assume !(0 == ~T4_E~0); 43275#L1367-1 assume !(0 == ~T5_E~0); 42830#L1372-1 assume !(0 == ~T6_E~0); 42831#L1377-1 assume !(0 == ~T7_E~0); 43191#L1382-1 assume !(0 == ~T8_E~0); 43192#L1387-1 assume !(0 == ~T9_E~0); 43935#L1392-1 assume !(0 == ~T10_E~0); 43227#L1397-1 assume !(0 == ~T11_E~0); 43228#L1402-1 assume !(0 == ~T12_E~0); 42839#L1407-1 assume !(0 == ~T13_E~0); 42840#L1412-1 assume !(0 == ~T14_E~0); 44160#L1417-1 assume !(0 == ~E_1~0); 44161#L1422-1 assume !(0 == ~E_2~0); 44459#L1427-1 assume !(0 == ~E_3~0); 43045#L1432-1 assume !(0 == ~E_4~0); 43046#L1437-1 assume !(0 == ~E_5~0); 44092#L1442-1 assume !(0 == ~E_6~0); 44093#L1447-1 assume !(0 == ~E_7~0); 43927#L1452-1 assume !(0 == ~E_8~0); 42586#L1457-1 assume !(0 == ~E_9~0); 42587#L1462-1 assume !(0 == ~E_10~0); 44123#L1467-1 assume !(0 == ~E_11~0); 44138#L1472-1 assume !(0 == ~E_12~0); 44139#L1477-1 assume !(0 == ~E_13~0); 43886#L1482-1 assume !(0 == ~E_14~0); 42981#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42982#L646-15 assume 1 == ~m_pc~0; 43842#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43286#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43287#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 43679#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42712#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42713#L665-15 assume 1 == ~t1_pc~0; 42514#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42515#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43382#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 44375#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 44370#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43724#L684-15 assume 1 == ~t2_pc~0; 43725#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43561#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43562#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 44181#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 44182#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44179#L703-15 assume 1 == ~t3_pc~0; 43774#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43775#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43371#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 43372#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 44265#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44266#L722-15 assume 1 == ~t4_pc~0; 43394#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43395#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44363#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43618#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43619#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44436#L741-15 assume 1 == ~t5_pc~0; 43116#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 43117#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43416#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 43856#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 42952#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42953#L760-15 assume 1 == ~t6_pc~0; 43874#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43875#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43436#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43437#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 42968#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42969#L779-15 assume 1 == ~t7_pc~0; 43958#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 42695#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42826#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42827#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 44496#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43163#L798-15 assume 1 == ~t8_pc~0; 43164#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 43640#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 44500#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 44248#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 44168#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43441#L817-15 assume 1 == ~t9_pc~0; 43442#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42683#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 43907#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43908#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 44421#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44422#L836-15 assume 1 == ~t10_pc~0; 43794#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42784#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42785#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43438#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 44346#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 43366#L855-15 assume 1 == ~t11_pc~0; 43367#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43390#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 44225#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 43903#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 43904#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 42403#L874-15 assume 1 == ~t12_pc~0; 42404#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44219#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 43697#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 43698#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 43258#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42426#L893-15 assume 1 == ~t13_pc~0; 42427#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 43024#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 43801#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 43802#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 43822#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 43160#L912-15 assume 1 == ~t14_pc~0; 43161#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 43957#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 44407#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 44408#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 43867#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43167#L1495-1 assume !(1 == ~M_E~0); 43168#L1500-1 assume !(1 == ~T1_E~0); 43663#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43664#L1510-1 assume !(1 == ~T3_E~0); 43717#L1515-1 assume !(1 == ~T4_E~0); 43718#L1520-1 assume !(1 == ~T5_E~0); 44324#L1525-1 assume !(1 == ~T6_E~0); 44020#L1530-1 assume !(1 == ~T7_E~0); 42910#L1535-1 assume !(1 == ~T8_E~0); 42911#L1540-1 assume !(1 == ~T9_E~0); 42424#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42425#L1550-1 assume !(1 == ~T11_E~0); 42624#L1555-1 assume !(1 == ~T12_E~0); 42625#L1560-1 assume !(1 == ~T13_E~0); 42965#L1565-1 assume !(1 == ~T14_E~0); 44468#L1570-1 assume !(1 == ~E_1~0); 43899#L1575-1 assume !(1 == ~E_2~0); 43281#L1580-1 assume !(1 == ~E_3~0); 43282#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 43736#L1590-1 assume !(1 == ~E_5~0); 43321#L1595-1 assume !(1 == ~E_6~0); 43322#L1600-1 assume !(1 == ~E_7~0); 43671#L1605-1 assume !(1 == ~E_8~0); 43672#L1610-1 assume !(1 == ~E_9~0); 44202#L1615-1 assume !(1 == ~E_10~0); 43105#L1620-1 assume !(1 == ~E_11~0); 43106#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 43928#L1630-1 assume !(1 == ~E_13~0); 43320#L1635-1 assume !(1 == ~E_14~0); 42495#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 42496#L2017 [2024-11-17 08:54:02,552 INFO L747 eck$LassoCheckResult]: Loop: 42496#L2017 assume true; 43516#L2017-1 assume !false; 43071#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 42873#L1110 assume true; 42579#L1110-1 assume !false; 42580#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 44379#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 43297#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 44289#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 43953#L1115 assume !(0 != eval_~tmp~0#1); 43954#L1118 assume true; 44024#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43037#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 42616#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 42617#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43655#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 42861#L1357 assume !(0 == ~T3_E~0); 42862#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43778#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43779#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43893#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 43383#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43384#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42947#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 42948#L1397 assume !(0 == ~T11_E~0); 44163#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 42523#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 42524#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 42976#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 43204#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 43205#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 44183#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 43550#L1437 assume !(0 == ~E_5~0); 43551#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 44250#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 42956#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 42957#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 43610#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 43502#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 43503#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 43918#L1477 assume !(0 == ~E_13~0); 42692#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 42693#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44443#L646-1 assume 1 == ~m_pc~0; 44129#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 43890#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44281#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 44471#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44472#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44252#L665-1 assume 1 == ~t1_pc~0; 44253#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 43526#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43527#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42854#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42855#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44433#L684-1 assume 1 == ~t2_pc~0; 43844#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 43846#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43833#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 43834#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43934#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42977#L703-1 assume 1 == ~t3_pc~0; 42978#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 43773#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43912#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 44178#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44492#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44258#L722-1 assume 1 == ~t4_pc~0; 44259#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43255#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44475#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 43614#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43615#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44229#L741-1 assume 1 == ~t5_pc~0; 44484#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42668#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42856#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42843#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42844#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 43563#L760-1 assume 1 == ~t6_pc~0; 44440#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 43877#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 43878#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 43892#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 43399#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 43400#L779-1 assume !(1 == ~t7_pc~0); 43569#L789-1 is_transmit7_triggered_~__retres1~7#1 := 0; 43568#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42472#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42473#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 43638#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 43639#L798-1 assume !(1 == ~t8_pc~0); 43670#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 43220#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 43221#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42686#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 42687#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 43914#L817-1 assume 1 == ~t9_pc~0; 44362#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 42997#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42998#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 43972#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 44330#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 44233#L836-1 assume !(1 == ~t10_pc~0); 42678#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 42679#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 44082#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 43753#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 43754#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 44361#L855-1 assume 1 == ~t11_pc~0; 44128#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 43050#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42898#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42899#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 43819#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 43820#L874-1 assume 1 == ~t12_pc~0; 43854#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 44276#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44369#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42680#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42681#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 43259#L893-1 assume 1 == ~t13_pc~0; 42775#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 42776#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 43004#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 43005#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 44353#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 43401#L912-1 assume 1 == ~t14_pc~0; 43402#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 43799#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 44208#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 42959#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 42960#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43047#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 42757#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42758#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44400#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43238#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43239#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 43603#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 43065#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 43066#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 43545#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44425#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 44485#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43909#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 43665#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42744#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 42745#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 43461#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 43031#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 43032#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 44394#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 44395#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 44359#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 44205#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 44206#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 43708#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 43362#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 43363#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 42444#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 42445#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 42657#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 43054#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 42608#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 43992#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 43987#L2036 assume !(0 == start_simulation_~tmp~3#1); 43009#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 43010#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 42436#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 42554#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 42555#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43495#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43496#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 44467#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 42496#L2017 [2024-11-17 08:54:02,553 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,553 INFO L85 PathProgramCache]: Analyzing trace with hash -399348259, now seen corresponding path program 1 times [2024-11-17 08:54:02,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,553 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910754599] [2024-11-17 08:54:02,553 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,618 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,618 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1910754599] [2024-11-17 08:54:02,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1910754599] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:02,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491456173] [2024-11-17 08:54:02,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,620 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:02,621 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,621 INFO L85 PathProgramCache]: Analyzing trace with hash 1831811069, now seen corresponding path program 1 times [2024-11-17 08:54:02,621 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,621 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2133310549] [2024-11-17 08:54:02,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2133310549] [2024-11-17 08:54:02,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2133310549] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,717 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,717 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:02,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2122107369] [2024-11-17 08:54:02,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,717 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:02,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:02,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:02,718 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:02,718 INFO L87 Difference]: Start difference. First operand 2114 states and 3092 transitions. cyclomatic complexity: 979 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:02,751 INFO L93 Difference]: Finished difference Result 2114 states and 3091 transitions. [2024-11-17 08:54:02,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3091 transitions. [2024-11-17 08:54:02,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:02,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3091 transitions. [2024-11-17 08:54:02,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:02,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:02,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3091 transitions. [2024-11-17 08:54:02,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:02,772 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3091 transitions. [2024-11-17 08:54:02,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3091 transitions. [2024-11-17 08:54:02,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:02,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4621570482497634) internal successors, (3091), 2113 states have internal predecessors, (3091), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:02,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3091 transitions. [2024-11-17 08:54:02,803 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3091 transitions. [2024-11-17 08:54:02,803 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:02,803 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3091 transitions. [2024-11-17 08:54:02,804 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-17 08:54:02,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3091 transitions. [2024-11-17 08:54:02,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:02,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:02,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:02,812 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:02,812 INFO L745 eck$LassoCheckResult]: Stem: 47594#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 47595#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 48198#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 47615#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 47616#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 47807#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46983#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46984#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47910#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47911#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46925#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46926#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48652#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48643#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47445#L989 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 47446#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 48221#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 48225#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 48352#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 47385#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47386#L1342-1 assume !(0 == ~M_E~0); 47946#L1347-1 assume !(0 == ~T1_E~0); 48498#L1352-1 assume !(0 == ~T2_E~0); 48286#L1357-1 assume !(0 == ~T3_E~0); 47511#L1362-1 assume !(0 == ~T4_E~0); 47512#L1367-1 assume !(0 == ~T5_E~0); 47067#L1372-1 assume !(0 == ~T6_E~0); 47068#L1377-1 assume !(0 == ~T7_E~0); 47428#L1382-1 assume !(0 == ~T8_E~0); 47429#L1387-1 assume !(0 == ~T9_E~0); 48172#L1392-1 assume !(0 == ~T10_E~0); 47464#L1397-1 assume !(0 == ~T11_E~0); 47465#L1402-1 assume !(0 == ~T12_E~0); 47076#L1407-1 assume !(0 == ~T13_E~0); 47077#L1412-1 assume !(0 == ~T14_E~0); 48397#L1417-1 assume !(0 == ~E_1~0); 48398#L1422-1 assume !(0 == ~E_2~0); 48696#L1427-1 assume !(0 == ~E_3~0); 47282#L1432-1 assume !(0 == ~E_4~0); 47283#L1437-1 assume !(0 == ~E_5~0); 48329#L1442-1 assume !(0 == ~E_6~0); 48330#L1447-1 assume !(0 == ~E_7~0); 48164#L1452-1 assume !(0 == ~E_8~0); 46823#L1457-1 assume !(0 == ~E_9~0); 46824#L1462-1 assume !(0 == ~E_10~0); 48360#L1467-1 assume !(0 == ~E_11~0); 48375#L1472-1 assume !(0 == ~E_12~0); 48376#L1477-1 assume !(0 == ~E_13~0); 48123#L1482-1 assume !(0 == ~E_14~0); 47218#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47219#L646-15 assume 1 == ~m_pc~0; 48079#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 47523#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47524#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47916#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 46949#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46950#L665-15 assume 1 == ~t1_pc~0; 46751#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 46752#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47619#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48612#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 48607#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47961#L684-15 assume 1 == ~t2_pc~0; 47962#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47798#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47799#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48419#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 48420#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48416#L703-15 assume 1 == ~t3_pc~0; 48011#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48012#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47608#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47609#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 48502#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48503#L722-15 assume 1 == ~t4_pc~0; 47631#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47632#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48600#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47855#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47856#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48673#L741-15 assume 1 == ~t5_pc~0; 47353#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47354#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47653#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48093#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 47189#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47190#L760-15 assume 1 == ~t6_pc~0; 48111#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48112#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47673#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47674#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 47205#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47206#L779-15 assume 1 == ~t7_pc~0; 48195#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46932#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47063#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47064#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 48733#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47400#L798-15 assume 1 == ~t8_pc~0; 47401#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47877#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48737#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 48486#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 48405#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47678#L817-15 assume 1 == ~t9_pc~0; 47679#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46920#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48144#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48145#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 48658#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48659#L836-15 assume 1 == ~t10_pc~0; 48031#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47021#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47022#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47675#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 48583#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47603#L855-15 assume 1 == ~t11_pc~0; 47604#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 47627#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 48462#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 48140#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 48141#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 46640#L874-15 assume 1 == ~t12_pc~0; 46641#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48456#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 47934#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47935#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 47495#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46663#L893-15 assume 1 == ~t13_pc~0; 46664#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 47261#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 48038#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 48039#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 48059#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 47397#L912-15 assume 1 == ~t14_pc~0; 47398#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 48194#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 48644#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 48645#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 48104#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47404#L1495-1 assume !(1 == ~M_E~0); 47405#L1500-1 assume !(1 == ~T1_E~0); 47900#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47901#L1510-1 assume !(1 == ~T3_E~0); 47954#L1515-1 assume !(1 == ~T4_E~0); 47955#L1520-1 assume !(1 == ~T5_E~0); 48561#L1525-1 assume !(1 == ~T6_E~0); 48257#L1530-1 assume !(1 == ~T7_E~0); 47147#L1535-1 assume !(1 == ~T8_E~0); 47148#L1540-1 assume !(1 == ~T9_E~0); 46661#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46662#L1550-1 assume !(1 == ~T11_E~0); 46861#L1555-1 assume !(1 == ~T12_E~0); 46862#L1560-1 assume !(1 == ~T13_E~0); 47202#L1565-1 assume !(1 == ~T14_E~0); 48705#L1570-1 assume !(1 == ~E_1~0); 48136#L1575-1 assume !(1 == ~E_2~0); 47518#L1580-1 assume !(1 == ~E_3~0); 47519#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 47973#L1590-1 assume !(1 == ~E_5~0); 47558#L1595-1 assume !(1 == ~E_6~0); 47559#L1600-1 assume !(1 == ~E_7~0); 47908#L1605-1 assume !(1 == ~E_8~0); 47909#L1610-1 assume !(1 == ~E_9~0); 48439#L1615-1 assume !(1 == ~E_10~0); 47342#L1620-1 assume !(1 == ~E_11~0); 47343#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 48165#L1630-1 assume !(1 == ~E_13~0); 47557#L1635-1 assume !(1 == ~E_14~0); 46732#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 46733#L2017 [2024-11-17 08:54:02,813 INFO L747 eck$LassoCheckResult]: Loop: 46733#L2017 assume true; 47753#L2017-1 assume !false; 47308#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 47110#L1110 assume true; 46816#L1110-1 assume !false; 46817#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 48616#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 47534#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 48526#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 48190#L1115 assume !(0 != eval_~tmp~0#1); 48191#L1118 assume true; 48261#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47274#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 46853#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 46854#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47892#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47098#L1357 assume !(0 == ~T3_E~0); 47099#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48015#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48016#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48130#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 47620#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47621#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47184#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 47185#L1397 assume !(0 == ~T11_E~0); 48400#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 46760#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 46761#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 47213#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 47440#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 47441#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 48418#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 47783#L1437 assume !(0 == ~E_5~0); 47784#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 48487#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 47191#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 47192#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 47847#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 47739#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 47740#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 48155#L1477 assume !(0 == ~E_13~0); 46929#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 46930#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48680#L646-1 assume 1 == ~m_pc~0; 48366#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 48127#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48518#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48708#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 48709#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48489#L665-1 assume 1 == ~t1_pc~0; 48490#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47763#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47764#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47091#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47092#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48670#L684-1 assume 1 == ~t2_pc~0; 48081#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 48083#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48070#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48071#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 48171#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47214#L703-1 assume !(1 == ~t3_pc~0); 47216#L713-1 is_transmit3_triggered_~__retres1~3#1 := 0; 48010#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48149#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48415#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 48729#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48495#L722-1 assume 1 == ~t4_pc~0; 48496#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 47492#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48712#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47851#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47852#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48466#L741-1 assume 1 == ~t5_pc~0; 48721#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 46905#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47093#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47080#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47081#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47800#L760-1 assume 1 == ~t6_pc~0; 48677#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48114#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48115#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48129#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47636#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47637#L779-1 assume 1 == ~t7_pc~0; 47804#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47805#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46709#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46710#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47875#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47876#L798-1 assume !(1 == ~t8_pc~0); 47907#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 47457#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47458#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46923#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 46924#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48151#L817-1 assume 1 == ~t9_pc~0; 48599#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47234#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47235#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 48209#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 48567#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48470#L836-1 assume !(1 == ~t10_pc~0); 46915#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 46916#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48319#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47990#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47991#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 48598#L855-1 assume !(1 == ~t11_pc~0); 48196#L865-1 is_transmit11_triggered_~__retres1~11#1 := 0; 47287#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47135#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47136#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 48056#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 48057#L874-1 assume 1 == ~t12_pc~0; 48091#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 48513#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48606#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46917#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46918#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 47496#L893-1 assume 1 == ~t13_pc~0; 47012#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 47013#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 47241#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 47242#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 48590#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 47638#L912-1 assume 1 == ~t14_pc~0; 47639#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 48036#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 48445#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 47196#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 47197#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47286#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 46994#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46995#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48637#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47475#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47476#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47840#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47302#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47303#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 47782#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48662#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 48722#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48146#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 47902#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 46981#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 46982#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 47698#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 47268#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 47269#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 48631#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 48632#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 48596#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 48442#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 48443#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 47945#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 47599#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 47600#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 46681#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 46682#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 46894#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 47291#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 46845#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 48229#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 48224#L2036 assume !(0 == start_simulation_~tmp~3#1); 47246#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 47247#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 46673#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 46791#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 46792#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47732#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 47733#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 48704#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 46733#L2017 [2024-11-17 08:54:02,813 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,813 INFO L85 PathProgramCache]: Analyzing trace with hash -571762340, now seen corresponding path program 1 times [2024-11-17 08:54:02,813 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120499800] [2024-11-17 08:54:02,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,814 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,858 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,859 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1120499800] [2024-11-17 08:54:02,859 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1120499800] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,859 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,859 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:02,859 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [471424860] [2024-11-17 08:54:02,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,859 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:02,860 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:02,860 INFO L85 PathProgramCache]: Analyzing trace with hash 716540186, now seen corresponding path program 1 times [2024-11-17 08:54:02,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:02,860 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052444161] [2024-11-17 08:54:02,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:02,860 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:02,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:02,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:02,942 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:02,942 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2052444161] [2024-11-17 08:54:02,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2052444161] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:02,943 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:02,943 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:02,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [912961637] [2024-11-17 08:54:02,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:02,943 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:02,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:02,944 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:02,944 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:02,944 INFO L87 Difference]: Start difference. First operand 2114 states and 3091 transitions. cyclomatic complexity: 978 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:03,016 INFO L93 Difference]: Finished difference Result 2114 states and 3090 transitions. [2024-11-17 08:54:03,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3090 transitions. [2024-11-17 08:54:03,023 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:03,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3090 transitions. [2024-11-17 08:54:03,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:03,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:03,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3090 transitions. [2024-11-17 08:54:03,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:03,037 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3090 transitions. [2024-11-17 08:54:03,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3090 transitions. [2024-11-17 08:54:03,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:03,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4616840113528855) internal successors, (3090), 2113 states have internal predecessors, (3090), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3090 transitions. [2024-11-17 08:54:03,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3090 transitions. [2024-11-17 08:54:03,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:03,071 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3090 transitions. [2024-11-17 08:54:03,072 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-17 08:54:03,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3090 transitions. [2024-11-17 08:54:03,078 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:03,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:03,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:03,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,081 INFO L745 eck$LassoCheckResult]: Stem: 51831#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 51832#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 52435#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 51852#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 51853#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 52044#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51220#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51221#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52147#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52148#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51162#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 51163#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52889#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 52880#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 51682#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 51683#L994 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 52458#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 52462#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 52589#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 51622#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51623#L1342-1 assume !(0 == ~M_E~0); 52183#L1347-1 assume !(0 == ~T1_E~0); 52735#L1352-1 assume !(0 == ~T2_E~0); 52523#L1357-1 assume !(0 == ~T3_E~0); 51748#L1362-1 assume !(0 == ~T4_E~0); 51749#L1367-1 assume !(0 == ~T5_E~0); 51304#L1372-1 assume !(0 == ~T6_E~0); 51305#L1377-1 assume !(0 == ~T7_E~0); 51665#L1382-1 assume !(0 == ~T8_E~0); 51666#L1387-1 assume !(0 == ~T9_E~0); 52409#L1392-1 assume !(0 == ~T10_E~0); 51701#L1397-1 assume !(0 == ~T11_E~0); 51702#L1402-1 assume !(0 == ~T12_E~0); 51313#L1407-1 assume !(0 == ~T13_E~0); 51314#L1412-1 assume !(0 == ~T14_E~0); 52634#L1417-1 assume !(0 == ~E_1~0); 52635#L1422-1 assume !(0 == ~E_2~0); 52933#L1427-1 assume !(0 == ~E_3~0); 51519#L1432-1 assume !(0 == ~E_4~0); 51520#L1437-1 assume !(0 == ~E_5~0); 52566#L1442-1 assume !(0 == ~E_6~0); 52567#L1447-1 assume !(0 == ~E_7~0); 52401#L1452-1 assume !(0 == ~E_8~0); 51060#L1457-1 assume !(0 == ~E_9~0); 51061#L1462-1 assume !(0 == ~E_10~0); 52597#L1467-1 assume !(0 == ~E_11~0); 52612#L1472-1 assume !(0 == ~E_12~0); 52613#L1477-1 assume !(0 == ~E_13~0); 52360#L1482-1 assume !(0 == ~E_14~0); 51455#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51456#L646-15 assume 1 == ~m_pc~0; 52316#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 51760#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 51761#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52153#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 51186#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 51187#L665-15 assume 1 == ~t1_pc~0; 50988#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 50989#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 51856#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 52849#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 52844#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52198#L684-15 assume 1 == ~t2_pc~0; 52199#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52035#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52036#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52656#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 52657#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52653#L703-15 assume 1 == ~t3_pc~0; 52248#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52249#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 51845#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 51846#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 52739#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52740#L722-15 assume 1 == ~t4_pc~0; 51868#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 51869#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52837#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52092#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52093#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52910#L741-15 assume 1 == ~t5_pc~0; 51592#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 51593#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51890#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 52330#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 51426#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 51427#L760-15 assume 1 == ~t6_pc~0; 52348#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52349#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 51910#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 51911#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 51442#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51443#L779-15 assume 1 == ~t7_pc~0; 52432#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 51169#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 51300#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 51301#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 52970#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 51637#L798-15 assume 1 == ~t8_pc~0; 51638#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 52115#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 52974#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 52723#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 52642#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 51915#L817-15 assume 1 == ~t9_pc~0; 51916#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51157#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 52381#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52382#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 52895#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52896#L836-15 assume 1 == ~t10_pc~0; 52268#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 51258#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 51259#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 51912#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 52820#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 51840#L855-15 assume 1 == ~t11_pc~0; 51841#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 51864#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 52699#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 52377#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 52378#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50877#L874-15 assume 1 == ~t12_pc~0; 50878#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52693#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52171#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 52172#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51732#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50900#L893-15 assume 1 == ~t13_pc~0; 50901#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 51498#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 52275#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 52276#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 52298#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 51634#L912-15 assume 1 == ~t14_pc~0; 51635#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 52431#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 52881#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 52882#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 52341#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51641#L1495-1 assume !(1 == ~M_E~0); 51642#L1500-1 assume !(1 == ~T1_E~0); 52137#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52138#L1510-1 assume !(1 == ~T3_E~0); 52191#L1515-1 assume !(1 == ~T4_E~0); 52192#L1520-1 assume !(1 == ~T5_E~0); 52798#L1525-1 assume !(1 == ~T6_E~0); 52494#L1530-1 assume !(1 == ~T7_E~0); 51384#L1535-1 assume !(1 == ~T8_E~0); 51385#L1540-1 assume !(1 == ~T9_E~0); 50898#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50899#L1550-1 assume !(1 == ~T11_E~0); 51098#L1555-1 assume !(1 == ~T12_E~0); 51099#L1560-1 assume !(1 == ~T13_E~0); 51439#L1565-1 assume !(1 == ~T14_E~0); 52942#L1570-1 assume !(1 == ~E_1~0); 52373#L1575-1 assume !(1 == ~E_2~0); 51755#L1580-1 assume !(1 == ~E_3~0); 51756#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 52210#L1590-1 assume !(1 == ~E_5~0); 51795#L1595-1 assume !(1 == ~E_6~0); 51796#L1600-1 assume !(1 == ~E_7~0); 52145#L1605-1 assume !(1 == ~E_8~0); 52146#L1610-1 assume !(1 == ~E_9~0); 52676#L1615-1 assume !(1 == ~E_10~0); 51579#L1620-1 assume !(1 == ~E_11~0); 51580#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 52402#L1630-1 assume !(1 == ~E_13~0); 51794#L1635-1 assume !(1 == ~E_14~0); 50969#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 50970#L2017 [2024-11-17 08:54:03,081 INFO L747 eck$LassoCheckResult]: Loop: 50970#L2017 assume true; 51990#L2017-1 assume !false; 51545#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 51347#L1110 assume true; 51053#L1110-1 assume !false; 51054#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 52855#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 51771#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 52763#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 52429#L1115 assume !(0 != eval_~tmp~0#1); 52430#L1118 assume true; 52498#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 51513#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 51090#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 51091#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52129#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 51335#L1357 assume !(0 == ~T3_E~0); 51336#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 52252#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52253#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52367#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 51857#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 51858#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 51421#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 51422#L1397 assume !(0 == ~T11_E~0); 52637#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 50995#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50996#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 51447#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 51677#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 51678#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 52655#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 52020#L1437 assume !(0 == ~E_5~0); 52021#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 52724#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 51430#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 51431#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 52084#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 51976#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 51977#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 52392#L1477 assume !(0 == ~E_13~0); 51166#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 51167#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52917#L646-1 assume 1 == ~m_pc~0; 52603#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 52364#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52755#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 52945#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 52946#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52726#L665-1 assume 1 == ~t1_pc~0; 52727#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 52000#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52001#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 51328#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 51329#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 52907#L684-1 assume 1 == ~t2_pc~0; 52318#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 52320#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52307#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 52308#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 52408#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 51451#L703-1 assume 1 == ~t3_pc~0; 51452#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 52247#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52386#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 52652#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 52966#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 52732#L722-1 assume !(1 == ~t4_pc~0); 51728#L732-1 is_transmit4_triggered_~__retres1~4#1 := 0; 51729#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52949#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 52088#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 52089#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52703#L741-1 assume !(1 == ~t5_pc~0); 51141#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 51142#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 51330#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 51317#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 51318#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52037#L760-1 assume 1 == ~t6_pc~0; 52914#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52351#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52352#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 52366#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 51873#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 51874#L779-1 assume 1 == ~t7_pc~0; 52041#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 52042#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 50946#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50947#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 52112#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52113#L798-1 assume !(1 == ~t8_pc~0); 52144#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 51695#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 51696#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 51160#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 51161#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 52388#L817-1 assume 1 == ~t9_pc~0; 52836#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 51471#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 51472#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 52446#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 52804#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 52707#L836-1 assume !(1 == ~t10_pc~0); 51152#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 51153#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 52556#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 52227#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 52228#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 52835#L855-1 assume !(1 == ~t11_pc~0); 52433#L865-1 is_transmit11_triggered_~__retres1~11#1 := 0; 51524#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 51372#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 51373#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 52293#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 52294#L874-1 assume 1 == ~t12_pc~0; 52328#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 52752#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 52843#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 51154#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 51155#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 51733#L893-1 assume 1 == ~t13_pc~0; 51249#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 51250#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 51478#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 51479#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 52827#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 51875#L912-1 assume 1 == ~t14_pc~0; 51876#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 52273#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 52682#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 51433#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 51434#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51523#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 51231#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51232#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52874#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 51712#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 51713#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52077#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 51539#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 51540#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 52019#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52899#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 52959#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52383#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52139#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 51218#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 51219#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 51935#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 51505#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 51506#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 52868#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 52869#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 52833#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 52679#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 52680#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 52182#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 51836#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 51837#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 50918#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 50919#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 51131#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 51528#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 51082#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 52466#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 52461#L2036 assume !(0 == start_simulation_~tmp~3#1); 51483#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 51484#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 50910#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 51028#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 51029#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 51969#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 51970#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 52941#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 50970#L2017 [2024-11-17 08:54:03,082 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,082 INFO L85 PathProgramCache]: Analyzing trace with hash 1085243901, now seen corresponding path program 1 times [2024-11-17 08:54:03,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505431414] [2024-11-17 08:54:03,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,132 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,133 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,133 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [505431414] [2024-11-17 08:54:03,133 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [505431414] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:03,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1305168867] [2024-11-17 08:54:03,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,134 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:03,134 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,134 INFO L85 PathProgramCache]: Analyzing trace with hash 824324215, now seen corresponding path program 1 times [2024-11-17 08:54:03,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1575799081] [2024-11-17 08:54:03,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,225 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,225 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1575799081] [2024-11-17 08:54:03,225 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1575799081] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,225 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,225 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:03,225 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1702915289] [2024-11-17 08:54:03,226 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,226 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:03,226 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:03,227 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:03,227 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:03,228 INFO L87 Difference]: Start difference. First operand 2114 states and 3090 transitions. cyclomatic complexity: 977 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:03,262 INFO L93 Difference]: Finished difference Result 2114 states and 3089 transitions. [2024-11-17 08:54:03,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3089 transitions. [2024-11-17 08:54:03,269 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:03,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3089 transitions. [2024-11-17 08:54:03,279 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:03,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:03,282 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3089 transitions. [2024-11-17 08:54:03,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:03,285 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3089 transitions. [2024-11-17 08:54:03,287 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3089 transitions. [2024-11-17 08:54:03,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:03,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4612109744560076) internal successors, (3089), 2113 states have internal predecessors, (3089), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3089 transitions. [2024-11-17 08:54:03,316 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3089 transitions. [2024-11-17 08:54:03,316 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:03,317 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3089 transitions. [2024-11-17 08:54:03,317 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-17 08:54:03,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3089 transitions. [2024-11-17 08:54:03,322 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:03,323 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:03,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:03,325 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,325 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,325 INFO L745 eck$LassoCheckResult]: Stem: 56068#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 56069#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 56672#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56089#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56090#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 56281#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55457#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55458#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56384#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56385#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55399#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55400#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 57126#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 57117#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 55919#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 55920#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56695#L999 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 56699#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 56826#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 55859#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55860#L1342-1 assume !(0 == ~M_E~0); 56420#L1347-1 assume !(0 == ~T1_E~0); 56972#L1352-1 assume !(0 == ~T2_E~0); 56760#L1357-1 assume !(0 == ~T3_E~0); 55985#L1362-1 assume !(0 == ~T4_E~0); 55986#L1367-1 assume !(0 == ~T5_E~0); 55541#L1372-1 assume !(0 == ~T6_E~0); 55542#L1377-1 assume !(0 == ~T7_E~0); 55902#L1382-1 assume !(0 == ~T8_E~0); 55903#L1387-1 assume !(0 == ~T9_E~0); 56646#L1392-1 assume !(0 == ~T10_E~0); 55938#L1397-1 assume !(0 == ~T11_E~0); 55939#L1402-1 assume !(0 == ~T12_E~0); 55550#L1407-1 assume !(0 == ~T13_E~0); 55551#L1412-1 assume !(0 == ~T14_E~0); 56871#L1417-1 assume !(0 == ~E_1~0); 56872#L1422-1 assume !(0 == ~E_2~0); 57170#L1427-1 assume !(0 == ~E_3~0); 55756#L1432-1 assume !(0 == ~E_4~0); 55757#L1437-1 assume !(0 == ~E_5~0); 56803#L1442-1 assume !(0 == ~E_6~0); 56804#L1447-1 assume !(0 == ~E_7~0); 56638#L1452-1 assume !(0 == ~E_8~0); 55297#L1457-1 assume !(0 == ~E_9~0); 55298#L1462-1 assume !(0 == ~E_10~0); 56834#L1467-1 assume !(0 == ~E_11~0); 56849#L1472-1 assume !(0 == ~E_12~0); 56850#L1477-1 assume !(0 == ~E_13~0); 56597#L1482-1 assume !(0 == ~E_14~0); 55692#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55693#L646-15 assume 1 == ~m_pc~0; 56553#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 55997#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55998#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56390#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55423#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55424#L665-15 assume 1 == ~t1_pc~0; 55225#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55226#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56093#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57086#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 57081#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56435#L684-15 assume 1 == ~t2_pc~0; 56436#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56272#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56273#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56893#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 56894#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56890#L703-15 assume 1 == ~t3_pc~0; 56485#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56486#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56082#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56083#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 56976#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56977#L722-15 assume 1 == ~t4_pc~0; 56105#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 56106#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57074#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56329#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56330#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57147#L741-15 assume 1 == ~t5_pc~0; 55829#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55830#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56127#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 56567#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 55663#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55664#L760-15 assume 1 == ~t6_pc~0; 56585#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 56586#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56147#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 56148#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 55679#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 55680#L779-15 assume 1 == ~t7_pc~0; 56669#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55406#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55537#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55538#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 57207#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55874#L798-15 assume 1 == ~t8_pc~0; 55875#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 56352#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57211#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 56960#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56879#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56152#L817-15 assume 1 == ~t9_pc~0; 56153#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55394#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 56618#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56619#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 57132#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57133#L836-15 assume 1 == ~t10_pc~0; 56505#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55495#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55496#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56149#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 57057#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 56077#L855-15 assume 1 == ~t11_pc~0; 56078#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 56101#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 56936#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 56614#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 56615#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 55114#L874-15 assume 1 == ~t12_pc~0; 55115#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 56930#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 56408#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 56409#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 55969#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 55137#L893-15 assume 1 == ~t13_pc~0; 55138#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 55735#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 56512#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 56513#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 56535#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 55871#L912-15 assume 1 == ~t14_pc~0; 55872#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 56668#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 57118#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 57119#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 56578#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55878#L1495-1 assume !(1 == ~M_E~0); 55879#L1500-1 assume !(1 == ~T1_E~0); 56374#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56375#L1510-1 assume !(1 == ~T3_E~0); 56428#L1515-1 assume !(1 == ~T4_E~0); 56429#L1520-1 assume !(1 == ~T5_E~0); 57035#L1525-1 assume !(1 == ~T6_E~0); 56731#L1530-1 assume !(1 == ~T7_E~0); 55621#L1535-1 assume !(1 == ~T8_E~0); 55622#L1540-1 assume !(1 == ~T9_E~0); 55135#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 55136#L1550-1 assume !(1 == ~T11_E~0); 55335#L1555-1 assume !(1 == ~T12_E~0); 55336#L1560-1 assume !(1 == ~T13_E~0); 55676#L1565-1 assume !(1 == ~T14_E~0); 57179#L1570-1 assume !(1 == ~E_1~0); 56610#L1575-1 assume !(1 == ~E_2~0); 55992#L1580-1 assume !(1 == ~E_3~0); 55993#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 56447#L1590-1 assume !(1 == ~E_5~0); 56032#L1595-1 assume !(1 == ~E_6~0); 56033#L1600-1 assume !(1 == ~E_7~0); 56382#L1605-1 assume !(1 == ~E_8~0); 56383#L1610-1 assume !(1 == ~E_9~0); 56913#L1615-1 assume !(1 == ~E_10~0); 55816#L1620-1 assume !(1 == ~E_11~0); 55817#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 56639#L1630-1 assume !(1 == ~E_13~0); 56031#L1635-1 assume !(1 == ~E_14~0); 55206#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 55207#L2017 [2024-11-17 08:54:03,326 INFO L747 eck$LassoCheckResult]: Loop: 55207#L2017 assume true; 56227#L2017-1 assume !false; 55782#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55584#L1110 assume true; 55290#L1110-1 assume !false; 55291#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 57092#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 56003#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 57000#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 56666#L1115 assume !(0 != eval_~tmp~0#1); 56667#L1118 assume true; 56735#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55750#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55327#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 55328#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 56366#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 55572#L1357 assume !(0 == ~T3_E~0); 55573#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56489#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 56490#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56604#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 56094#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 56095#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 55658#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 55659#L1397 assume !(0 == ~T11_E~0); 56874#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 55232#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 55233#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 55684#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 55915#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 55916#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 56892#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 56257#L1437 assume !(0 == ~E_5~0); 56258#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 56961#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 55667#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 55668#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 56321#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 56213#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 56214#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 56629#L1477 assume !(0 == ~E_13~0); 55403#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 55404#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57154#L646-1 assume 1 == ~m_pc~0; 56840#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 56601#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56992#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57182#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57183#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56963#L665-1 assume 1 == ~t1_pc~0; 56964#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 56237#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56238#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 55565#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55566#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57144#L684-1 assume 1 == ~t2_pc~0; 56555#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 56557#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56544#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56545#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 56645#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55688#L703-1 assume 1 == ~t3_pc~0; 55689#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56484#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56623#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 56889#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57203#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56969#L722-1 assume 1 == ~t4_pc~0; 56970#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 55966#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57186#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 56325#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56326#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56940#L741-1 assume !(1 == ~t5_pc~0); 55378#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 55379#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55567#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 55554#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55555#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56274#L760-1 assume !(1 == ~t6_pc~0); 57152#L770-1 is_transmit6_triggered_~__retres1~6#1 := 0; 56588#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56589#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 56603#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56110#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56111#L779-1 assume 1 == ~t7_pc~0; 56278#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 56279#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55183#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55184#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 56349#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56350#L798-1 assume 1 == ~t8_pc~0; 56690#L799-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 55932#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55933#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55397#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 55398#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 56625#L817-1 assume 1 == ~t9_pc~0; 57073#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 55708#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55709#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 56683#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 57041#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 56944#L836-1 assume 1 == ~t10_pc~0; 56945#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 55390#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 56793#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 56464#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 56465#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 57072#L855-1 assume 1 == ~t11_pc~0; 56839#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55762#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55609#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55610#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 56530#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 56531#L874-1 assume 1 == ~t12_pc~0; 56565#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 56989#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 57080#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55391#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 55392#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 55971#L893-1 assume !(1 == ~t13_pc~0); 55488#L903-1 is_transmit13_triggered_~__retres1~13#1 := 0; 55487#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 55715#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 55716#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 57064#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 56112#L912-1 assume 1 == ~t14_pc~0; 56113#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 56510#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 56919#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 55670#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 55671#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55760#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 55468#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55469#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57112#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55949#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55950#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 56314#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55776#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55777#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56256#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57136#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 57196#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56620#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56376#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 55455#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 55456#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 56172#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 55742#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 55743#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 57105#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 57106#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 57070#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 56916#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 56917#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 56419#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 56073#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 56074#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 55155#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 55156#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 55368#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55765#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 55319#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 56703#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 56698#L2036 assume !(0 == start_simulation_~tmp~3#1); 55720#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 55721#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 55147#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 55265#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 55266#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 56206#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56207#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 57178#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 55207#L2017 [2024-11-17 08:54:03,326 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1969979708, now seen corresponding path program 1 times [2024-11-17 08:54:03,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2078599290] [2024-11-17 08:54:03,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,378 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,378 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2078599290] [2024-11-17 08:54:03,378 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2078599290] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,378 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:03,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1040600750] [2024-11-17 08:54:03,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,379 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:03,379 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,379 INFO L85 PathProgramCache]: Analyzing trace with hash -130687427, now seen corresponding path program 1 times [2024-11-17 08:54:03,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565563478] [2024-11-17 08:54:03,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,464 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,464 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565563478] [2024-11-17 08:54:03,464 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565563478] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,464 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,464 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:03,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1308791854] [2024-11-17 08:54:03,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,465 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:03,465 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:03,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:03,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:03,466 INFO L87 Difference]: Start difference. First operand 2114 states and 3089 transitions. cyclomatic complexity: 976 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:03,499 INFO L93 Difference]: Finished difference Result 2114 states and 3088 transitions. [2024-11-17 08:54:03,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3088 transitions. [2024-11-17 08:54:03,507 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:03,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3088 transitions. [2024-11-17 08:54:03,512 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:03,513 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:03,513 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3088 transitions. [2024-11-17 08:54:03,515 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:03,515 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3088 transitions. [2024-11-17 08:54:03,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3088 transitions. [2024-11-17 08:54:03,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:03,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4607379375591296) internal successors, (3088), 2113 states have internal predecessors, (3088), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3088 transitions. [2024-11-17 08:54:03,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3088 transitions. [2024-11-17 08:54:03,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:03,549 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3088 transitions. [2024-11-17 08:54:03,549 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-17 08:54:03,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3088 transitions. [2024-11-17 08:54:03,554 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:03,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:03,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:03,584 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,584 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,586 INFO L745 eck$LassoCheckResult]: Stem: 60305#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 60306#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 60909#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60326#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60327#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 60518#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59694#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59695#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60621#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60622#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59636#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59637#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61363#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 61356#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60156#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 60157#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 60932#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60936#L1004 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 61063#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 60096#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60097#L1342-1 assume !(0 == ~M_E~0); 60657#L1347-1 assume !(0 == ~T1_E~0); 61209#L1352-1 assume !(0 == ~T2_E~0); 60997#L1357-1 assume !(0 == ~T3_E~0); 60222#L1362-1 assume !(0 == ~T4_E~0); 60223#L1367-1 assume !(0 == ~T5_E~0); 59778#L1372-1 assume !(0 == ~T6_E~0); 59779#L1377-1 assume !(0 == ~T7_E~0); 60139#L1382-1 assume !(0 == ~T8_E~0); 60140#L1387-1 assume !(0 == ~T9_E~0); 60883#L1392-1 assume !(0 == ~T10_E~0); 60175#L1397-1 assume !(0 == ~T11_E~0); 60176#L1402-1 assume !(0 == ~T12_E~0); 59787#L1407-1 assume !(0 == ~T13_E~0); 59788#L1412-1 assume !(0 == ~T14_E~0); 61108#L1417-1 assume !(0 == ~E_1~0); 61109#L1422-1 assume !(0 == ~E_2~0); 61407#L1427-1 assume !(0 == ~E_3~0); 59993#L1432-1 assume !(0 == ~E_4~0); 59994#L1437-1 assume !(0 == ~E_5~0); 61040#L1442-1 assume !(0 == ~E_6~0); 61041#L1447-1 assume !(0 == ~E_7~0); 60875#L1452-1 assume !(0 == ~E_8~0); 59534#L1457-1 assume !(0 == ~E_9~0); 59535#L1462-1 assume !(0 == ~E_10~0); 61071#L1467-1 assume !(0 == ~E_11~0); 61086#L1472-1 assume !(0 == ~E_12~0); 61087#L1477-1 assume !(0 == ~E_13~0); 60834#L1482-1 assume !(0 == ~E_14~0); 59929#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59930#L646-15 assume 1 == ~m_pc~0; 60790#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 60234#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60235#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60627#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59660#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59661#L665-15 assume 1 == ~t1_pc~0; 59462#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59463#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60330#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 61323#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 61318#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60672#L684-15 assume 1 == ~t2_pc~0; 60673#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60509#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60510#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 61130#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 61131#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61127#L703-15 assume 1 == ~t3_pc~0; 60722#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60723#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60319#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60320#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 61213#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61214#L722-15 assume 1 == ~t4_pc~0; 60342#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 60343#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61311#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60566#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60567#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61384#L741-15 assume 1 == ~t5_pc~0; 60066#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 60067#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60364#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60804#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 59900#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59901#L760-15 assume 1 == ~t6_pc~0; 60822#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60823#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60385#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60386#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 59916#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59917#L779-15 assume 1 == ~t7_pc~0; 60906#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59643#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59774#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59775#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 61444#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60111#L798-15 assume 1 == ~t8_pc~0; 60112#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60589#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 61448#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 61196#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 61114#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60389#L817-15 assume 1 == ~t9_pc~0; 60390#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59631#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60855#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60856#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 61369#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61370#L836-15 assume 1 == ~t10_pc~0; 60741#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59732#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 59733#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60384#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 61293#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60314#L855-15 assume 1 == ~t11_pc~0; 60315#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60338#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 61173#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60851#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 60852#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59351#L874-15 assume 1 == ~t12_pc~0; 59352#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61167#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60645#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60646#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60204#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 59374#L893-15 assume 1 == ~t13_pc~0; 59375#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59970#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60749#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60750#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 60770#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 60103#L912-15 assume 1 == ~t14_pc~0; 60104#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 60905#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 61354#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 61355#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 60812#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60114#L1495-1 assume !(1 == ~M_E~0); 60115#L1500-1 assume !(1 == ~T1_E~0); 60611#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60612#L1510-1 assume !(1 == ~T3_E~0); 60664#L1515-1 assume !(1 == ~T4_E~0); 60665#L1520-1 assume !(1 == ~T5_E~0); 61272#L1525-1 assume !(1 == ~T6_E~0); 60968#L1530-1 assume !(1 == ~T7_E~0); 59858#L1535-1 assume !(1 == ~T8_E~0); 59859#L1540-1 assume !(1 == ~T9_E~0); 59372#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 59373#L1550-1 assume !(1 == ~T11_E~0); 59572#L1555-1 assume !(1 == ~T12_E~0); 59573#L1560-1 assume !(1 == ~T13_E~0); 59911#L1565-1 assume !(1 == ~T14_E~0); 61416#L1570-1 assume !(1 == ~E_1~0); 60847#L1575-1 assume !(1 == ~E_2~0); 60227#L1580-1 assume !(1 == ~E_3~0); 60228#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 60684#L1590-1 assume !(1 == ~E_5~0); 60269#L1595-1 assume !(1 == ~E_6~0); 60270#L1600-1 assume !(1 == ~E_7~0); 60618#L1605-1 assume !(1 == ~E_8~0); 60619#L1610-1 assume !(1 == ~E_9~0); 61150#L1615-1 assume !(1 == ~E_10~0); 60053#L1620-1 assume !(1 == ~E_11~0); 60054#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 60876#L1630-1 assume !(1 == ~E_13~0); 60268#L1635-1 assume !(1 == ~E_14~0); 59442#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 59443#L2017 [2024-11-17 08:54:03,587 INFO L747 eck$LassoCheckResult]: Loop: 59443#L2017 assume true; 60464#L2017-1 assume !false; 60017#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59821#L1110 assume true; 59527#L1110-1 assume !false; 59528#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 61327#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 60240#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 61237#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 60901#L1115 assume !(0 != eval_~tmp~0#1); 60902#L1118 assume true; 60972#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59984#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59560#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 59561#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60603#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 59809#L1357 assume !(0 == ~T3_E~0); 59810#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60726#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60727#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60841#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60331#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60332#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 59895#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 59896#L1397 assume !(0 == ~T11_E~0); 61111#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59469#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 59470#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 59921#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 60152#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 60153#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 61129#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 60494#L1437 assume !(0 == ~E_5~0); 60495#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 61198#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 59904#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 59905#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 60558#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 60450#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 60451#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 60866#L1477 assume !(0 == ~E_13~0); 59640#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 59641#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61391#L646-1 assume 1 == ~m_pc~0; 61077#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 60838#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61229#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61419#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61420#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61200#L665-1 assume 1 == ~t1_pc~0; 61201#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 60474#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60475#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59802#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 59803#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61381#L684-1 assume 1 == ~t2_pc~0; 60792#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 60794#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60781#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60782#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60882#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 59925#L703-1 assume 1 == ~t3_pc~0; 59926#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 60721#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60860#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 61126#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61440#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61206#L722-1 assume 1 == ~t4_pc~0; 61207#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 60203#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61423#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60562#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60563#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61177#L741-1 assume 1 == ~t5_pc~0; 61432#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59616#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59804#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59791#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59792#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60511#L760-1 assume 1 == ~t6_pc~0; 61388#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60825#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60826#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60840#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60347#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60348#L779-1 assume 1 == ~t7_pc~0; 60515#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 60516#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59420#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59421#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60586#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60587#L798-1 assume !(1 == ~t8_pc~0); 60620#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 60169#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60170#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59634#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 59635#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60862#L817-1 assume !(1 == ~t9_pc~0); 61267#L827-1 is_transmit9_triggered_~__retres1~9#1 := 0; 59945#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59946#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60920#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 61278#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 61181#L836-1 assume !(1 == ~t10_pc~0); 59626#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 59627#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 61030#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60701#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 60702#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 61309#L855-1 assume 1 == ~t11_pc~0; 61076#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 59999#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59846#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59847#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 60767#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 60768#L874-1 assume 1 == ~t12_pc~0; 60802#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 61226#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 61317#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 59628#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 59629#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60208#L893-1 assume 1 == ~t13_pc~0; 59723#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59724#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59952#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59953#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 61301#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 60349#L912-1 assume 1 == ~t14_pc~0; 60350#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 60747#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 61156#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 59907#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 59908#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59997#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 59705#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59706#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61349#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60186#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60187#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 60551#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60013#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60014#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60493#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61373#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61433#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 60857#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 60613#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 59692#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 59693#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 60409#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 59979#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 59980#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 61342#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 61343#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 61307#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 61153#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 61154#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 60656#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 60310#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 60311#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 59392#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 59393#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 59605#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 60002#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 59556#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 60942#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 60935#L2036 assume !(0 == start_simulation_~tmp~3#1); 59957#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 59958#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 59384#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 59502#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 59503#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60443#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60444#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 61415#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 59443#L2017 [2024-11-17 08:54:03,587 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,587 INFO L85 PathProgramCache]: Analyzing trace with hash -2019353059, now seen corresponding path program 1 times [2024-11-17 08:54:03,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949837666] [2024-11-17 08:54:03,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949837666] [2024-11-17 08:54:03,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [949837666] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,634 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,634 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:03,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [667996396] [2024-11-17 08:54:03,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,634 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:03,635 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,635 INFO L85 PathProgramCache]: Analyzing trace with hash 514997117, now seen corresponding path program 2 times [2024-11-17 08:54:03,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240812669] [2024-11-17 08:54:03,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,720 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240812669] [2024-11-17 08:54:03,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [240812669] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,721 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,721 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:03,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [478972499] [2024-11-17 08:54:03,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,721 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:03,722 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:03,722 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:03,722 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:03,722 INFO L87 Difference]: Start difference. First operand 2114 states and 3088 transitions. cyclomatic complexity: 975 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:03,756 INFO L93 Difference]: Finished difference Result 2114 states and 3087 transitions. [2024-11-17 08:54:03,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3087 transitions. [2024-11-17 08:54:03,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:03,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3087 transitions. [2024-11-17 08:54:03,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:03,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:03,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3087 transitions. [2024-11-17 08:54:03,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:03,772 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3087 transitions. [2024-11-17 08:54:03,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3087 transitions. [2024-11-17 08:54:03,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:03,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4602649006622517) internal successors, (3087), 2113 states have internal predecessors, (3087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3087 transitions. [2024-11-17 08:54:03,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3087 transitions. [2024-11-17 08:54:03,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:03,808 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3087 transitions. [2024-11-17 08:54:03,808 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-17 08:54:03,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3087 transitions. [2024-11-17 08:54:03,813 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:03,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:03,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:03,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,816 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:03,816 INFO L745 eck$LassoCheckResult]: Stem: 64542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 64543#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 65146#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 64561#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 64562#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 64752#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63931#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63932#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64858#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 64859#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63873#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63874#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65600#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 65591#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64393#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 64394#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 65169#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 65173#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 65300#L1009 assume !(1 == ~t14_i~0);~t14_st~0 := 2; 64333#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 64334#L1342-1 assume !(0 == ~M_E~0); 64893#L1347-1 assume !(0 == ~T1_E~0); 65446#L1352-1 assume !(0 == ~T2_E~0); 65234#L1357-1 assume !(0 == ~T3_E~0); 64459#L1362-1 assume !(0 == ~T4_E~0); 64460#L1367-1 assume !(0 == ~T5_E~0); 64015#L1372-1 assume !(0 == ~T6_E~0); 64016#L1377-1 assume !(0 == ~T7_E~0); 64374#L1382-1 assume !(0 == ~T8_E~0); 64375#L1387-1 assume !(0 == ~T9_E~0); 65120#L1392-1 assume !(0 == ~T10_E~0); 64412#L1397-1 assume !(0 == ~T11_E~0); 64413#L1402-1 assume !(0 == ~T12_E~0); 64024#L1407-1 assume !(0 == ~T13_E~0); 64025#L1412-1 assume !(0 == ~T14_E~0); 65345#L1417-1 assume !(0 == ~E_1~0); 65346#L1422-1 assume !(0 == ~E_2~0); 65644#L1427-1 assume !(0 == ~E_3~0); 64230#L1432-1 assume !(0 == ~E_4~0); 64231#L1437-1 assume !(0 == ~E_5~0); 65277#L1442-1 assume !(0 == ~E_6~0); 65278#L1447-1 assume !(0 == ~E_7~0); 65112#L1452-1 assume !(0 == ~E_8~0); 63771#L1457-1 assume !(0 == ~E_9~0); 63772#L1462-1 assume !(0 == ~E_10~0); 65308#L1467-1 assume !(0 == ~E_11~0); 65323#L1472-1 assume !(0 == ~E_12~0); 65324#L1477-1 assume !(0 == ~E_13~0); 65071#L1482-1 assume !(0 == ~E_14~0); 64165#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 64166#L646-15 assume 1 == ~m_pc~0; 65027#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 64471#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 64472#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 64864#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 63895#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63896#L665-15 assume 1 == ~t1_pc~0; 63696#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 63697#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64567#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 65560#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 65554#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 64909#L684-15 assume 1 == ~t2_pc~0; 64910#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 64746#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 64747#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65366#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 65367#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65363#L703-15 assume 1 == ~t3_pc~0; 64959#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64960#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 64556#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 64557#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 65450#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65451#L722-15 assume 1 == ~t4_pc~0; 64577#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64578#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65548#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64803#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64804#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65621#L741-15 assume 1 == ~t5_pc~0; 64299#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 64300#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64601#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 65039#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 64137#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64138#L760-15 assume 1 == ~t6_pc~0; 65059#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65060#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 64621#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 64622#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 64153#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64154#L779-15 assume 1 == ~t7_pc~0; 65143#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 63880#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 64008#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 64009#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 65681#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64348#L798-15 assume 1 == ~t8_pc~0; 64349#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 64825#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 65685#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 65433#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 65351#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 64626#L817-15 assume 1 == ~t9_pc~0; 64627#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 63868#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 65092#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65093#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 65606#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65607#L836-15 assume 1 == ~t10_pc~0; 64978#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 63969#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 63970#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64623#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 65530#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 64551#L855-15 assume 1 == ~t11_pc~0; 64552#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64575#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 65410#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 65088#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 65089#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 63588#L874-15 assume 1 == ~t12_pc~0; 63589#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 65404#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 64882#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 64883#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 64441#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 63611#L893-15 assume 1 == ~t13_pc~0; 63612#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 64207#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64986#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 64987#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 65007#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 64340#L912-15 assume 1 == ~t14_pc~0; 64341#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 65142#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 65592#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 65593#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 65049#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64351#L1495-1 assume !(1 == ~M_E~0); 64352#L1500-1 assume !(1 == ~T1_E~0); 64848#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 64849#L1510-1 assume !(1 == ~T3_E~0); 64901#L1515-1 assume !(1 == ~T4_E~0); 64902#L1520-1 assume !(1 == ~T5_E~0); 65509#L1525-1 assume !(1 == ~T6_E~0); 65205#L1530-1 assume !(1 == ~T7_E~0); 64095#L1535-1 assume !(1 == ~T8_E~0); 64096#L1540-1 assume !(1 == ~T9_E~0); 63609#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63610#L1550-1 assume !(1 == ~T11_E~0); 63809#L1555-1 assume !(1 == ~T12_E~0); 63810#L1560-1 assume !(1 == ~T13_E~0); 64148#L1565-1 assume !(1 == ~T14_E~0); 65653#L1570-1 assume !(1 == ~E_1~0); 65084#L1575-1 assume !(1 == ~E_2~0); 64464#L1580-1 assume !(1 == ~E_3~0); 64465#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 64921#L1590-1 assume !(1 == ~E_5~0); 64506#L1595-1 assume !(1 == ~E_6~0); 64507#L1600-1 assume !(1 == ~E_7~0); 64855#L1605-1 assume !(1 == ~E_8~0); 64856#L1610-1 assume !(1 == ~E_9~0); 65387#L1615-1 assume !(1 == ~E_10~0); 64290#L1620-1 assume !(1 == ~E_11~0); 64291#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 65113#L1630-1 assume !(1 == ~E_13~0); 64505#L1635-1 assume !(1 == ~E_14~0); 63679#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 63680#L2017 [2024-11-17 08:54:03,817 INFO L747 eck$LassoCheckResult]: Loop: 63680#L2017 assume true; 64701#L2017-1 assume !false; 64254#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 64058#L1110 assume true; 63764#L1110-1 assume !false; 63765#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 65564#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 64477#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 65474#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 65138#L1115 assume !(0 != eval_~tmp~0#1); 65139#L1118 assume true; 65209#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 64221#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 63797#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 63798#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64840#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64046#L1357 assume !(0 == ~T3_E~0); 64047#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64963#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 64964#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 65078#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64568#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64569#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64132#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 64133#L1397 assume !(0 == ~T11_E~0); 65348#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 63706#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 63707#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 64158#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 64389#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 64390#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 65368#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 64731#L1437 assume !(0 == ~E_5~0); 64732#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 65435#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 64141#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 64142#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 64795#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 64687#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 64688#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 65103#L1477 assume !(0 == ~E_13~0); 63877#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 63878#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65628#L646-1 assume 1 == ~m_pc~0; 65314#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 65075#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65466#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 65656#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65657#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65437#L665-1 assume 1 == ~t1_pc~0; 65438#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 64711#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 64712#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 64039#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 64040#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65618#L684-1 assume 1 == ~t2_pc~0; 65029#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 65031#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65018#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 65019#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65119#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 64162#L703-1 assume 1 == ~t3_pc~0; 64163#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 64958#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65097#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 65364#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 65677#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65443#L722-1 assume 1 == ~t4_pc~0; 65444#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 64440#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65660#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 64799#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 64800#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65414#L741-1 assume 1 == ~t5_pc~0; 65669#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 63853#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 64041#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 64028#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 64029#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 64748#L760-1 assume 1 == ~t6_pc~0; 65625#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 65062#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 65063#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 65077#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 64584#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 64585#L779-1 assume 1 == ~t7_pc~0; 64753#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 64754#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 63657#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 63658#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 64823#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 64824#L798-1 assume !(1 == ~t8_pc~0); 64857#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 64406#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 64407#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 63871#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 63872#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 65099#L817-1 assume !(1 == ~t9_pc~0); 65504#L827-1 is_transmit9_triggered_~__retres1~9#1 := 0; 64182#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 64183#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 65157#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 65515#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 65418#L836-1 assume !(1 == ~t10_pc~0); 63863#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 63864#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 65267#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 64938#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 64939#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 65546#L855-1 assume 1 == ~t11_pc~0; 65313#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 64236#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 64083#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 64084#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 65004#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 65005#L874-1 assume 1 == ~t12_pc~0; 65040#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 65463#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 65555#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 63865#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 63866#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 64445#L893-1 assume 1 == ~t13_pc~0; 63960#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 63961#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 64189#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 64190#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 65538#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 64586#L912-1 assume 1 == ~t14_pc~0; 64587#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 64984#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 65393#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 64144#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 64145#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 64234#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 63942#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 63943#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65586#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 64423#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64424#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 64788#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 64250#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 64251#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 64730#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65610#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65670#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 65094#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64850#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 63929#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 63930#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 64646#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 64216#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 64217#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 65579#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 65580#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 65544#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 65390#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 65391#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 64894#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 64547#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 64548#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 63629#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 63630#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 63842#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 64239#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 63793#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 65179#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 65172#L2036 assume !(0 == start_simulation_~tmp~3#1); 64194#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 64195#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 63621#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 63739#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 63740#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 64680#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 64681#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 65652#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 63680#L2017 [2024-11-17 08:54:03,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,817 INFO L85 PathProgramCache]: Analyzing trace with hash -1316757220, now seen corresponding path program 1 times [2024-11-17 08:54:03,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [287442066] [2024-11-17 08:54:03,818 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,864 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [287442066] [2024-11-17 08:54:03,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [287442066] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,865 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,865 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:03,865 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111888148] [2024-11-17 08:54:03,865 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,866 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:03,866 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:03,866 INFO L85 PathProgramCache]: Analyzing trace with hash 514997117, now seen corresponding path program 3 times [2024-11-17 08:54:03,866 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:03,866 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074891074] [2024-11-17 08:54:03,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:03,867 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:03,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:03,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:03,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:03,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074891074] [2024-11-17 08:54:03,946 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1074891074] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:03,946 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:03,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:03,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612453282] [2024-11-17 08:54:03,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:03,947 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:03,947 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:03,947 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:03,947 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:03,948 INFO L87 Difference]: Start difference. First operand 2114 states and 3087 transitions. cyclomatic complexity: 974 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:03,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:03,980 INFO L93 Difference]: Finished difference Result 2114 states and 3086 transitions. [2024-11-17 08:54:03,980 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2114 states and 3086 transitions. [2024-11-17 08:54:03,986 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:03,991 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2114 states to 2114 states and 3086 transitions. [2024-11-17 08:54:03,991 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2114 [2024-11-17 08:54:03,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2114 [2024-11-17 08:54:03,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2114 states and 3086 transitions. [2024-11-17 08:54:03,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:03,994 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3086 transitions. [2024-11-17 08:54:03,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2114 states and 3086 transitions. [2024-11-17 08:54:04,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2114 to 2114. [2024-11-17 08:54:04,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2114 states, 2114 states have (on average 1.4597918637653737) internal successors, (3086), 2113 states have internal predecessors, (3086), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:04,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2114 states to 2114 states and 3086 transitions. [2024-11-17 08:54:04,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2114 states and 3086 transitions. [2024-11-17 08:54:04,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:04,027 INFO L425 stractBuchiCegarLoop]: Abstraction has 2114 states and 3086 transitions. [2024-11-17 08:54:04,027 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-17 08:54:04,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2114 states and 3086 transitions. [2024-11-17 08:54:04,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1929 [2024-11-17 08:54:04,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:04,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:04,034 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:04,034 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:04,034 INFO L745 eck$LassoCheckResult]: Stem: 68779#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 68780#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 69383#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 68798#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68799#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 68989#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68168#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68169#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69095#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69096#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68110#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 68111#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 69837#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 69828#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 68630#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 68631#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69406#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 69410#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 69537#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 68570#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68571#L1342-1 assume !(0 == ~M_E~0); 69130#L1347-1 assume !(0 == ~T1_E~0); 69683#L1352-1 assume !(0 == ~T2_E~0); 69471#L1357-1 assume !(0 == ~T3_E~0); 68696#L1362-1 assume !(0 == ~T4_E~0); 68697#L1367-1 assume !(0 == ~T5_E~0); 68252#L1372-1 assume !(0 == ~T6_E~0); 68253#L1377-1 assume !(0 == ~T7_E~0); 68611#L1382-1 assume !(0 == ~T8_E~0); 68612#L1387-1 assume !(0 == ~T9_E~0); 69357#L1392-1 assume !(0 == ~T10_E~0); 68649#L1397-1 assume !(0 == ~T11_E~0); 68650#L1402-1 assume !(0 == ~T12_E~0); 68261#L1407-1 assume !(0 == ~T13_E~0); 68262#L1412-1 assume !(0 == ~T14_E~0); 69582#L1417-1 assume !(0 == ~E_1~0); 69583#L1422-1 assume !(0 == ~E_2~0); 69881#L1427-1 assume !(0 == ~E_3~0); 68467#L1432-1 assume !(0 == ~E_4~0); 68468#L1437-1 assume !(0 == ~E_5~0); 69514#L1442-1 assume !(0 == ~E_6~0); 69515#L1447-1 assume !(0 == ~E_7~0); 69349#L1452-1 assume !(0 == ~E_8~0); 68008#L1457-1 assume !(0 == ~E_9~0); 68009#L1462-1 assume !(0 == ~E_10~0); 69545#L1467-1 assume !(0 == ~E_11~0); 69560#L1472-1 assume !(0 == ~E_12~0); 69561#L1477-1 assume !(0 == ~E_13~0); 69308#L1482-1 assume !(0 == ~E_14~0); 68402#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 68403#L646-15 assume 1 == ~m_pc~0; 69264#L647-15 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 68708#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 68709#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69101#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68132#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 68133#L665-15 assume 1 == ~t1_pc~0; 67933#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 67934#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68804#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69797#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 69791#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69146#L684-15 assume 1 == ~t2_pc~0; 69147#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68983#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68984#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69603#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 69604#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69600#L703-15 assume 1 == ~t3_pc~0; 69196#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69197#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 68793#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 68794#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 69687#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69688#L722-15 assume 1 == ~t4_pc~0; 68814#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68815#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69785#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69040#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69041#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69858#L741-15 assume 1 == ~t5_pc~0; 68536#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 68537#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68838#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69276#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 68374#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68375#L760-15 assume 1 == ~t6_pc~0; 69296#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 69297#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68858#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 68859#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 68390#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68391#L779-15 assume 1 == ~t7_pc~0; 69380#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 68117#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68245#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68246#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 69918#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68585#L798-15 assume 1 == ~t8_pc~0; 68586#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 69062#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 69922#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69670#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 69588#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68863#L817-15 assume 1 == ~t9_pc~0; 68864#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68105#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69329#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69330#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 69843#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69844#L836-15 assume 1 == ~t10_pc~0; 69215#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 68206#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 68207#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 68860#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 69767#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 68788#L855-15 assume 1 == ~t11_pc~0; 68789#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68812#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 69647#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69325#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 69326#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 67825#L874-15 assume 1 == ~t12_pc~0; 67826#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 69641#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69119#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69120#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 68678#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 67848#L893-15 assume 1 == ~t13_pc~0; 67849#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68444#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69223#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69224#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 69244#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 68577#L912-15 assume 1 == ~t14_pc~0; 68578#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 69379#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 69829#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 69830#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 69286#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68588#L1495-1 assume !(1 == ~M_E~0); 68589#L1500-1 assume !(1 == ~T1_E~0); 69085#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69086#L1510-1 assume !(1 == ~T3_E~0); 69138#L1515-1 assume !(1 == ~T4_E~0); 69139#L1520-1 assume !(1 == ~T5_E~0); 69746#L1525-1 assume !(1 == ~T6_E~0); 69442#L1530-1 assume !(1 == ~T7_E~0); 68332#L1535-1 assume !(1 == ~T8_E~0); 68333#L1540-1 assume !(1 == ~T9_E~0); 67846#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 67847#L1550-1 assume !(1 == ~T11_E~0); 68046#L1555-1 assume !(1 == ~T12_E~0); 68047#L1560-1 assume !(1 == ~T13_E~0); 68385#L1565-1 assume !(1 == ~T14_E~0); 69890#L1570-1 assume !(1 == ~E_1~0); 69321#L1575-1 assume !(1 == ~E_2~0); 68701#L1580-1 assume !(1 == ~E_3~0); 68702#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69158#L1590-1 assume !(1 == ~E_5~0); 68743#L1595-1 assume !(1 == ~E_6~0); 68744#L1600-1 assume !(1 == ~E_7~0); 69092#L1605-1 assume !(1 == ~E_8~0); 69093#L1610-1 assume !(1 == ~E_9~0); 69624#L1615-1 assume !(1 == ~E_10~0); 68527#L1620-1 assume !(1 == ~E_11~0); 68528#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 69350#L1630-1 assume !(1 == ~E_13~0); 68742#L1635-1 assume !(1 == ~E_14~0); 67916#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 67917#L2017 [2024-11-17 08:54:04,035 INFO L747 eck$LassoCheckResult]: Loop: 67917#L2017 assume true; 68938#L2017-1 assume !false; 68491#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68295#L1110 assume true; 68001#L1110-1 assume !false; 68002#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 69801#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 68714#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 69711#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69375#L1115 assume !(0 != eval_~tmp~0#1); 69376#L1118 assume true; 69446#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68458#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68034#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 68035#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69077#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 68283#L1357 assume !(0 == ~T3_E~0); 68284#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69200#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69201#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69315#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68805#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 68806#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 68369#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 68370#L1397 assume !(0 == ~T11_E~0); 69585#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 67943#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 67944#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 68395#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 68626#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 68627#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 69605#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 68968#L1437 assume !(0 == ~E_5~0); 68969#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 69672#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 68378#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 68379#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 69032#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 68924#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 68925#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 69340#L1477 assume !(0 == ~E_13~0); 68114#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 68115#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69865#L646-1 assume 1 == ~m_pc~0; 69551#L647-1 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 69312#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69703#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69893#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69894#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69674#L665-1 assume 1 == ~t1_pc~0; 69675#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68948#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 68949#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68276#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68277#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69855#L684-1 assume !(1 == ~t2_pc~0); 69267#L694-1 is_transmit2_triggered_~__retres1~2#1 := 0; 69268#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69255#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69256#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69356#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68399#L703-1 assume !(1 == ~t3_pc~0); 68401#L713-1 is_transmit3_triggered_~__retres1~3#1 := 0; 69195#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69334#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69601#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69914#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69680#L722-1 assume 1 == ~t4_pc~0; 69681#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 68677#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69897#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69036#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 69037#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69651#L741-1 assume 1 == ~t5_pc~0; 69906#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 68090#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 68278#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68265#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 68266#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68985#L760-1 assume !(1 == ~t6_pc~0); 69863#L770-1 is_transmit6_triggered_~__retres1~6#1 := 0; 69299#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69300#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69314#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 68821#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68822#L779-1 assume !(1 == ~t7_pc~0); 68992#L789-1 is_transmit7_triggered_~__retres1~7#1 := 0; 68991#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 67894#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 67895#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 69060#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69061#L798-1 assume !(1 == ~t8_pc~0); 69094#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 68643#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68644#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 68108#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68109#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69336#L817-1 assume 1 == ~t9_pc~0; 69784#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68419#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68420#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69394#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69752#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69655#L836-1 assume !(1 == ~t10_pc~0); 68100#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 68101#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69504#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69175#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69176#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69783#L855-1 assume !(1 == ~t11_pc~0); 69381#L865-1 is_transmit11_triggered_~__retres1~11#1 := 0; 68473#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68320#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68321#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 69241#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69242#L874-1 assume 1 == ~t12_pc~0; 69277#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 69700#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69792#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68102#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 68103#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 68682#L893-1 assume 1 == ~t13_pc~0; 68197#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68198#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68426#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68427#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 69775#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 68823#L912-1 assume !(1 == ~t14_pc~0); 68825#L922-1 is_transmit14_triggered_~__retres1~14#1 := 0; 69221#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 69630#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 68381#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 68382#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68471#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 68179#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 68180#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69823#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 68660#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 68661#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 69025#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 68487#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 68488#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 68967#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69847#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69907#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69331#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 69087#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 68166#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 68167#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 68883#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 68453#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 68454#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 69816#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 69817#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 69781#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 69627#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 69628#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 69131#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 68784#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 68785#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 67866#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 67867#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 68079#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 68476#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 68030#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 69416#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 69409#L2036 assume !(0 == start_simulation_~tmp~3#1); 68431#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 68432#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 67858#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 67976#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 67977#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 68917#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 68918#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 69889#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 67917#L2017 [2024-11-17 08:54:04,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:04,035 INFO L85 PathProgramCache]: Analyzing trace with hash 2031043133, now seen corresponding path program 1 times [2024-11-17 08:54:04,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:04,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111676510] [2024-11-17 08:54:04,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:04,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:04,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,098 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,098 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [111676510] [2024-11-17 08:54:04,098 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [111676510] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,098 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,098 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:04,098 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1206293890] [2024-11-17 08:54:04,098 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,098 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:04,099 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:04,099 INFO L85 PathProgramCache]: Analyzing trace with hash 457094990, now seen corresponding path program 1 times [2024-11-17 08:54:04,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:04,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747016317] [2024-11-17 08:54:04,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:04,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:04,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,207 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [747016317] [2024-11-17 08:54:04,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [747016317] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:04,208 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342799857] [2024-11-17 08:54:04,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,208 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:04,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:04,209 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:04,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:04,209 INFO L87 Difference]: Start difference. First operand 2114 states and 3086 transitions. cyclomatic complexity: 973 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:04,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:04,367 INFO L93 Difference]: Finished difference Result 4024 states and 5832 transitions. [2024-11-17 08:54:04,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4024 states and 5832 transitions. [2024-11-17 08:54:04,382 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3838 [2024-11-17 08:54:04,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4024 states to 4024 states and 5832 transitions. [2024-11-17 08:54:04,391 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4024 [2024-11-17 08:54:04,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4024 [2024-11-17 08:54:04,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4024 states and 5832 transitions. [2024-11-17 08:54:04,398 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:04,398 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4024 states and 5832 transitions. [2024-11-17 08:54:04,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4024 states and 5832 transitions. [2024-11-17 08:54:04,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4024 to 3917. [2024-11-17 08:54:04,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3917 states, 3917 states have (on average 1.4505999489405157) internal successors, (5682), 3916 states have internal predecessors, (5682), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:04,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3917 states to 3917 states and 5682 transitions. [2024-11-17 08:54:04,462 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3917 states and 5682 transitions. [2024-11-17 08:54:04,463 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:04,464 INFO L425 stractBuchiCegarLoop]: Abstraction has 3917 states and 5682 transitions. [2024-11-17 08:54:04,464 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-17 08:54:04,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3917 states and 5682 transitions. [2024-11-17 08:54:04,474 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3731 [2024-11-17 08:54:04,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:04,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:04,477 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:04,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:04,477 INFO L745 eck$LassoCheckResult]: Stem: 74930#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 74931#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 75543#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74950#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74951#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 75145#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74315#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74316#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75252#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75253#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74256#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74257#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76014#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76005#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 74779#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 74780#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 75567#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 75572#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 75702#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 74719#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 74720#L1342-1 assume !(0 == ~M_E~0); 75288#L1347-1 assume !(0 == ~T1_E~0); 75851#L1352-1 assume !(0 == ~T2_E~0); 75633#L1357-1 assume !(0 == ~T3_E~0); 74845#L1362-1 assume !(0 == ~T4_E~0); 74846#L1367-1 assume !(0 == ~T5_E~0); 74398#L1372-1 assume !(0 == ~T6_E~0); 74399#L1377-1 assume !(0 == ~T7_E~0); 74760#L1382-1 assume !(0 == ~T8_E~0); 74761#L1387-1 assume !(0 == ~T9_E~0); 75517#L1392-1 assume !(0 == ~T10_E~0); 74798#L1397-1 assume !(0 == ~T11_E~0); 74799#L1402-1 assume !(0 == ~T12_E~0); 74407#L1407-1 assume !(0 == ~T13_E~0); 74408#L1412-1 assume !(0 == ~T14_E~0); 75750#L1417-1 assume !(0 == ~E_1~0); 75751#L1422-1 assume !(0 == ~E_2~0); 76065#L1427-1 assume !(0 == ~E_3~0); 74616#L1432-1 assume !(0 == ~E_4~0); 74617#L1437-1 assume !(0 == ~E_5~0); 75679#L1442-1 assume !(0 == ~E_6~0); 75680#L1447-1 assume !(0 == ~E_7~0); 75508#L1452-1 assume !(0 == ~E_8~0); 74155#L1457-1 assume !(0 == ~E_9~0); 74156#L1462-1 assume !(0 == ~E_10~0); 75710#L1467-1 assume !(0 == ~E_11~0); 75727#L1472-1 assume !(0 == ~E_12~0); 75728#L1477-1 assume !(0 == ~E_13~0); 75464#L1482-1 assume !(0 == ~E_14~0); 74549#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 74550#L646-15 assume !(1 == ~m_pc~0); 75421#L656-15 is_master_triggered_~__retres1~0#1 := 0; 74857#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 74858#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 75258#L1666-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 74279#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74280#L665-15 assume 1 == ~t1_pc~0; 74080#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 74081#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 74956#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 75969#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 75964#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75303#L684-15 assume 1 == ~t2_pc~0; 75304#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 75139#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75140#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75771#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 75772#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75768#L703-15 assume 1 == ~t3_pc~0; 75353#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75354#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 74945#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74946#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 75855#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75856#L722-15 assume 1 == ~t4_pc~0; 74967#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 74968#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75957#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75196#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75197#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76038#L741-15 assume 1 == ~t5_pc~0; 74685#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 74686#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74991#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 75432#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 74521#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74522#L760-15 assume 1 == ~t6_pc~0; 75452#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 75453#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75011#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75012#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 74537#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74538#L779-15 assume 1 == ~t7_pc~0; 75540#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 74263#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 74394#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74395#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 76108#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 74734#L798-15 assume 1 == ~t8_pc~0; 74735#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 75219#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76113#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 75838#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 75756#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75016#L817-15 assume 1 == ~t9_pc~0; 75017#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 74251#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75486#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75487#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 76021#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76022#L836-15 assume 1 == ~t10_pc~0; 75373#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 74353#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 74354#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75013#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 75939#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 74940#L855-15 assume 1 == ~t11_pc~0; 74941#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 74965#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 75815#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 75482#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 75483#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 73972#L874-15 assume 1 == ~t12_pc~0; 73973#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 75809#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75276#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75277#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 74827#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 73995#L893-15 assume 1 == ~t13_pc~0; 73996#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 74593#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 75380#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 75381#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 75401#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 74728#L912-15 assume 1 == ~t14_pc~0; 74729#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 75539#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 76006#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 76007#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 75442#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74737#L1495-1 assume !(1 == ~M_E~0); 74738#L1500-1 assume !(1 == ~T1_E~0); 75242#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75243#L1510-1 assume !(1 == ~T3_E~0); 75295#L1515-1 assume !(1 == ~T4_E~0); 75296#L1520-1 assume !(1 == ~T5_E~0); 75917#L1525-1 assume !(1 == ~T6_E~0); 75605#L1530-1 assume !(1 == ~T7_E~0); 74479#L1535-1 assume !(1 == ~T8_E~0); 74480#L1540-1 assume !(1 == ~T9_E~0); 73993#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 73994#L1550-1 assume !(1 == ~T11_E~0); 74192#L1555-1 assume !(1 == ~T12_E~0); 74193#L1560-1 assume !(1 == ~T13_E~0); 74532#L1565-1 assume !(1 == ~T14_E~0); 76075#L1570-1 assume !(1 == ~E_1~0); 75478#L1575-1 assume !(1 == ~E_2~0); 74850#L1580-1 assume !(1 == ~E_3~0); 74851#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 75315#L1590-1 assume !(1 == ~E_5~0); 74892#L1595-1 assume !(1 == ~E_6~0); 74893#L1600-1 assume !(1 == ~E_7~0); 75249#L1605-1 assume !(1 == ~E_8~0); 75250#L1610-1 assume !(1 == ~E_9~0); 75792#L1615-1 assume !(1 == ~E_10~0); 74676#L1620-1 assume !(1 == ~E_11~0); 74677#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 75509#L1630-1 assume !(1 == ~E_13~0); 74891#L1635-1 assume !(1 == ~E_14~0); 74063#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 74064#L2017 [2024-11-17 08:54:04,478 INFO L747 eck$LassoCheckResult]: Loop: 74064#L2017 assume true; 75091#L2017-1 assume !false; 74640#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74441#L1110 assume true; 74148#L1110-1 assume !false; 74149#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 75974#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 74864#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 75880#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 75535#L1115 assume !(0 != eval_~tmp~0#1); 75536#L1118 assume true; 75609#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 74607#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 74183#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 74184#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 75234#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 74429#L1357 assume !(0 == ~T3_E~0); 74430#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75357#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 75358#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 75471#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 74958#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 74959#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 74516#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 74517#L1397 assume !(0 == ~T11_E~0); 75753#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 74092#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 74093#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 74542#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 74775#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 74776#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 75773#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 75124#L1437 assume !(0 == ~E_5~0); 75125#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 75840#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 74525#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 74526#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 75188#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 75077#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 75078#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 75499#L1477 assume !(0 == ~E_13~0); 74260#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 74261#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76045#L646-1 assume !(1 == ~m_pc~0); 75467#L656-1 is_master_triggered_~__retres1~0#1 := 0; 75468#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75872#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76078#L1666-1 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 76079#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75842#L665-1 assume 1 == ~t1_pc~0; 75843#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 75102#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75103#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74422#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 74423#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76035#L684-1 assume !(1 == ~t2_pc~0); 75423#L694-1 is_transmit2_triggered_~__retres1~2#1 := 0; 75424#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75412#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 75413#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 75516#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74546#L703-1 assume 1 == ~t3_pc~0; 74547#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 75352#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75491#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 75769#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76104#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75848#L722-1 assume 1 == ~t4_pc~0; 75849#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 74826#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76083#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75192#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 75193#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75819#L741-1 assume !(1 == ~t5_pc~0); 74235#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 74236#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 74424#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 74411#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 74412#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 75141#L760-1 assume !(1 == ~t6_pc~0); 76043#L770-1 is_transmit6_triggered_~__retres1~6#1 := 0; 75455#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 75456#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75470#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 74974#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 74975#L779-1 assume 1 == ~t7_pc~0; 75146#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 75147#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 74041#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74042#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 75217#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75218#L798-1 assume !(1 == ~t8_pc~0); 75251#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 74792#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74793#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74254#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 74255#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 75493#L817-1 assume 1 == ~t9_pc~0; 75956#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 74566#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74567#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 75554#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 75923#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 75823#L836-1 assume 1 == ~t10_pc~0; 75824#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 74247#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 75669#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 75332#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 75333#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 75955#L855-1 assume 1 == ~t11_pc~0; 75715#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 74622#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 74471#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 74472#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 75398#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 75399#L874-1 assume 1 == ~t12_pc~0; 75433#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 75869#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75965#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 74248#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 74249#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 74831#L893-1 assume 1 == ~t13_pc~0; 74344#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 74345#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 74573#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 74574#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 75947#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 74976#L912-1 assume 1 == ~t14_pc~0; 74977#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 75378#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 75798#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 74528#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 74529#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74618#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 74326#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 74327#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75999#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 74809#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74810#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 75181#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 74636#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 74637#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 75123#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 76024#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 76095#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 75488#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 75244#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 74313#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 74314#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 75036#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 74601#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 74602#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 75993#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 75994#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 75953#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 75795#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 75796#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 75287#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 74936#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 74937#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 74013#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 74014#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 74225#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 74625#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 74177#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 75575#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 76131#L2036 assume !(0 == start_simulation_~tmp~3#1); 74578#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 74579#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 74005#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 74123#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 74124#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75072#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75073#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 76074#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 74064#L2017 [2024-11-17 08:54:04,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:04,478 INFO L85 PathProgramCache]: Analyzing trace with hash 619414170, now seen corresponding path program 1 times [2024-11-17 08:54:04,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:04,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123858581] [2024-11-17 08:54:04,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:04,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:04,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,559 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123858581] [2024-11-17 08:54:04,560 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123858581] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,560 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,560 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:04,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [790647717] [2024-11-17 08:54:04,560 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,561 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:04,561 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:04,561 INFO L85 PathProgramCache]: Analyzing trace with hash -964080969, now seen corresponding path program 1 times [2024-11-17 08:54:04,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:04,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1056603079] [2024-11-17 08:54:04,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:04,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:04,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:04,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:04,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:04,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1056603079] [2024-11-17 08:54:04,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1056603079] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:04,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:04,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:04,634 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765275325] [2024-11-17 08:54:04,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:04,634 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:04,634 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:04,635 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:54:04,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:54:04,635 INFO L87 Difference]: Start difference. First operand 3917 states and 5682 transitions. cyclomatic complexity: 1767 Second operand has 5 states, 5 states have (on average 34.0) internal successors, (170), 5 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:04,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:04,977 INFO L93 Difference]: Finished difference Result 3962 states and 5712 transitions. [2024-11-17 08:54:04,977 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3962 states and 5712 transitions. [2024-11-17 08:54:04,992 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3776 [2024-11-17 08:54:05,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3962 states to 3962 states and 5712 transitions. [2024-11-17 08:54:05,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3962 [2024-11-17 08:54:05,005 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3962 [2024-11-17 08:54:05,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3962 states and 5712 transitions. [2024-11-17 08:54:05,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:05,010 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3962 states and 5712 transitions. [2024-11-17 08:54:05,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3962 states and 5712 transitions. [2024-11-17 08:54:05,059 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3962 to 3962. [2024-11-17 08:54:05,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3962 states, 3962 states have (on average 1.441696113074205) internal successors, (5712), 3961 states have internal predecessors, (5712), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:05,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3962 states to 3962 states and 5712 transitions. [2024-11-17 08:54:05,075 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3962 states and 5712 transitions. [2024-11-17 08:54:05,075 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:54:05,076 INFO L425 stractBuchiCegarLoop]: Abstraction has 3962 states and 5712 transitions. [2024-11-17 08:54:05,076 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-17 08:54:05,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3962 states and 5712 transitions. [2024-11-17 08:54:05,089 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3776 [2024-11-17 08:54:05,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:05,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:05,092 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:05,092 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:05,093 INFO L745 eck$LassoCheckResult]: Stem: 82817#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 82818#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 83431#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82837#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82838#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 83032#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82205#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82206#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 83138#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 83139#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 82146#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 82147#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 83899#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 83890#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 82667#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 82668#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 83453#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 83458#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 83588#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 82607#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82608#L1342-1 assume !(0 == ~M_E~0); 83173#L1347-1 assume !(0 == ~T1_E~0); 83737#L1352-1 assume !(0 == ~T2_E~0); 83519#L1357-1 assume !(0 == ~T3_E~0); 82733#L1362-1 assume !(0 == ~T4_E~0); 82734#L1367-1 assume !(0 == ~T5_E~0); 82288#L1372-1 assume !(0 == ~T6_E~0); 82289#L1377-1 assume !(0 == ~T7_E~0); 82648#L1382-1 assume !(0 == ~T8_E~0); 82649#L1387-1 assume !(0 == ~T9_E~0); 83405#L1392-1 assume !(0 == ~T10_E~0); 82686#L1397-1 assume !(0 == ~T11_E~0); 82687#L1402-1 assume !(0 == ~T12_E~0); 82297#L1407-1 assume !(0 == ~T13_E~0); 82298#L1412-1 assume !(0 == ~T14_E~0); 83635#L1417-1 assume !(0 == ~E_1~0); 83636#L1422-1 assume !(0 == ~E_2~0); 83947#L1427-1 assume !(0 == ~E_3~0); 82504#L1432-1 assume !(0 == ~E_4~0); 82505#L1437-1 assume !(0 == ~E_5~0); 83564#L1442-1 assume !(0 == ~E_6~0); 83565#L1447-1 assume !(0 == ~E_7~0); 83396#L1452-1 assume !(0 == ~E_8~0); 82045#L1457-1 assume !(0 == ~E_9~0); 82046#L1462-1 assume !(0 == ~E_10~0); 83596#L1467-1 assume !(0 == ~E_11~0); 83613#L1472-1 assume !(0 == ~E_12~0); 83614#L1477-1 assume !(0 == ~E_13~0); 83352#L1482-1 assume !(0 == ~E_14~0); 82439#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82440#L646-15 assume !(1 == ~m_pc~0); 83308#L656-15 is_master_triggered_~__retres1~0#1 := 0; 82745#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82746#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83144#L1666-15 assume !(0 != activate_threads_~tmp~1#1); 82169#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82170#L665-15 assume 1 == ~t1_pc~0; 81970#L666-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 81971#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82843#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 83854#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 83849#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83189#L684-15 assume 1 == ~t2_pc~0; 83190#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 83026#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83027#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83656#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 83657#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83653#L703-15 assume 1 == ~t3_pc~0; 83239#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83240#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82832#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82833#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 83741#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83742#L722-15 assume 1 == ~t4_pc~0; 82854#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82855#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83842#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83083#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83084#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83920#L741-15 assume 1 == ~t5_pc~0; 82573#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82574#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82878#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 83320#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 82411#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82412#L760-15 assume 1 == ~t6_pc~0; 83340#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 83341#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82898#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82899#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 82427#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82428#L779-15 assume 1 == ~t7_pc~0; 83428#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 82153#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82282#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82283#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 83985#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82622#L798-15 assume 1 == ~t8_pc~0; 82623#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 83105#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 83989#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 83724#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 83641#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82903#L817-15 assume 1 == ~t9_pc~0; 82904#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82141#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 83374#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83375#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 83905#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 83906#L836-15 assume 1 == ~t10_pc~0; 83258#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 82243#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82244#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82900#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 83825#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82827#L855-15 assume 1 == ~t11_pc~0; 82828#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 82852#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 83701#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 83370#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 83371#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 81862#L874-15 assume 1 == ~t12_pc~0; 81863#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 83695#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83162#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 83163#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 82715#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 81885#L893-15 assume 1 == ~t13_pc~0; 81886#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 82481#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 83266#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 83267#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 83287#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 82614#L912-15 assume 1 == ~t14_pc~0; 82615#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 83427#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 83891#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 83892#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 83330#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82625#L1495-1 assume !(1 == ~M_E~0); 82626#L1500-1 assume !(1 == ~T1_E~0); 83128#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83129#L1510-1 assume !(1 == ~T3_E~0); 83181#L1515-1 assume !(1 == ~T4_E~0); 83182#L1520-1 assume !(1 == ~T5_E~0); 83803#L1525-1 assume !(1 == ~T6_E~0); 83490#L1530-1 assume !(1 == ~T7_E~0); 82368#L1535-1 assume !(1 == ~T8_E~0); 82369#L1540-1 assume !(1 == ~T9_E~0); 81883#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 81884#L1550-1 assume !(1 == ~T11_E~0); 82082#L1555-1 assume !(1 == ~T12_E~0); 82083#L1560-1 assume !(1 == ~T13_E~0); 82422#L1565-1 assume !(1 == ~T14_E~0); 83956#L1570-1 assume !(1 == ~E_1~0); 83366#L1575-1 assume !(1 == ~E_2~0); 82738#L1580-1 assume !(1 == ~E_3~0); 82739#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 83201#L1590-1 assume !(1 == ~E_5~0); 82780#L1595-1 assume !(1 == ~E_6~0); 82781#L1600-1 assume !(1 == ~E_7~0); 83135#L1605-1 assume !(1 == ~E_8~0); 83136#L1610-1 assume !(1 == ~E_9~0); 83677#L1615-1 assume !(1 == ~E_10~0); 82564#L1620-1 assume !(1 == ~E_11~0); 82565#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 83397#L1630-1 assume !(1 == ~E_13~0); 82779#L1635-1 assume !(1 == ~E_14~0); 81953#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 81954#L2017 [2024-11-17 08:54:05,094 INFO L747 eck$LassoCheckResult]: Loop: 81954#L2017 assume true; 82978#L2017-1 assume !false; 82528#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82331#L1110 assume true; 82038#L1110-1 assume !false; 82039#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 83859#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 82751#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 83766#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 83423#L1115 assume !(0 != eval_~tmp~0#1); 83424#L1118 assume true; 83494#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82495#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82071#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 82072#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83120#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 82319#L1357 assume !(0 == ~T3_E~0); 82320#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83243#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 83244#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 83359#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 82845#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 82846#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 82405#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 82406#L1397 assume !(0 == ~T11_E~0); 83638#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 81980#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 81981#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 82432#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 82663#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 82664#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 83658#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 83011#L1437 assume !(0 == ~E_5~0); 83012#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 83726#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 82415#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 82416#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 83075#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 82964#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 82965#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 83387#L1477 assume !(0 == ~E_13~0); 82150#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 82151#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83927#L646-1 assume !(1 == ~m_pc~0); 83355#L656-1 is_master_triggered_~__retres1~0#1 := 0; 83356#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83758#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 83959#L1666-1 assume !(0 != activate_threads_~tmp~1#1); 83960#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83728#L665-1 assume 1 == ~t1_pc~0; 83729#L666-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 82989#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82990#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82312#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82313#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83917#L684-1 assume 1 == ~t2_pc~0; 83309#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 83311#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83299#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 83300#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 83404#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82436#L703-1 assume 1 == ~t3_pc~0; 82437#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83238#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83379#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 83654#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 83981#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83734#L722-1 assume 1 == ~t4_pc~0; 83735#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82714#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83963#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 83079#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83080#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 83705#L741-1 assume 1 == ~t5_pc~0; 83973#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82126#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82314#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82301#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82302#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 83028#L760-1 assume !(1 == ~t6_pc~0); 83925#L770-1 is_transmit6_triggered_~__retres1~6#1 := 0; 83343#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 83344#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 83358#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 82861#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82862#L779-1 assume 1 == ~t7_pc~0; 83033#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 83034#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 81931#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 81932#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 83103#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 83104#L798-1 assume !(1 == ~t8_pc~0); 83137#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 82680#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82681#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82144#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82145#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 83381#L817-1 assume 1 == ~t9_pc~0; 83841#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82456#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82457#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 83441#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 83810#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 83709#L836-1 assume !(1 == ~t10_pc~0); 82136#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 82137#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 83554#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 83218#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 83219#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 83840#L855-1 assume 1 == ~t11_pc~0; 83601#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 82510#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 82356#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 82357#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 83284#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 83285#L874-1 assume 1 == ~t12_pc~0; 83321#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 83755#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 83850#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 82138#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 82139#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 82719#L893-1 assume 1 == ~t13_pc~0; 82234#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 82235#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 82463#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 82464#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 83832#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 82863#L912-1 assume !(1 == ~t14_pc~0); 82865#L922-1 is_transmit14_triggered_~__retres1~14#1 := 0; 83264#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 83683#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 82418#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 82419#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82508#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 82216#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 82217#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83884#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82697#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82698#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 83068#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 82524#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 82525#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 83010#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 83909#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 83974#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 83376#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 83130#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 82203#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 82204#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 82923#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 82490#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 82491#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 83877#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 83878#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 83838#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 83680#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 83681#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 83174#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 82823#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 82824#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 81903#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 81904#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 82115#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 82513#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 82067#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 83464#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 83456#L2036 assume !(0 == start_simulation_~tmp~3#1); 82468#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 82469#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 81895#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 82013#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 82014#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82957#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82958#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 83955#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 81954#L2017 [2024-11-17 08:54:05,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:05,094 INFO L85 PathProgramCache]: Analyzing trace with hash -1694391047, now seen corresponding path program 1 times [2024-11-17 08:54:05,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:05,095 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720066220] [2024-11-17 08:54:05,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:05,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:05,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:05,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:05,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:05,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720066220] [2024-11-17 08:54:05,167 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720066220] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:05,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:05,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:05,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [272622889] [2024-11-17 08:54:05,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:05,169 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:05,169 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:05,170 INFO L85 PathProgramCache]: Analyzing trace with hash -37639082, now seen corresponding path program 1 times [2024-11-17 08:54:05,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:05,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988075272] [2024-11-17 08:54:05,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:05,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:05,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:05,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:05,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:05,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988075272] [2024-11-17 08:54:05,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [988075272] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:05,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:05,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:05,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004240579] [2024-11-17 08:54:05,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:05,259 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:05,259 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:05,260 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:05,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:05,260 INFO L87 Difference]: Start difference. First operand 3962 states and 5712 transitions. cyclomatic complexity: 1752 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:05,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:05,412 INFO L93 Difference]: Finished difference Result 7490 states and 10745 transitions. [2024-11-17 08:54:05,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7490 states and 10745 transitions. [2024-11-17 08:54:05,452 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7297 [2024-11-17 08:54:05,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7490 states to 7490 states and 10745 transitions. [2024-11-17 08:54:05,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7490 [2024-11-17 08:54:05,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7490 [2024-11-17 08:54:05,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7490 states and 10745 transitions. [2024-11-17 08:54:05,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:05,496 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7490 states and 10745 transitions. [2024-11-17 08:54:05,503 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7490 states and 10745 transitions. [2024-11-17 08:54:05,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7490 to 7482. [2024-11-17 08:54:05,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7482 states, 7482 states have (on average 1.4350441058540497) internal successors, (10737), 7481 states have internal predecessors, (10737), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:05,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7482 states to 7482 states and 10737 transitions. [2024-11-17 08:54:05,615 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7482 states and 10737 transitions. [2024-11-17 08:54:05,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:05,616 INFO L425 stractBuchiCegarLoop]: Abstraction has 7482 states and 10737 transitions. [2024-11-17 08:54:05,616 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-17 08:54:05,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7482 states and 10737 transitions. [2024-11-17 08:54:05,646 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7289 [2024-11-17 08:54:05,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:05,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:05,649 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:05,649 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:05,649 INFO L745 eck$LassoCheckResult]: Stem: 94277#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 94278#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 94903#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94297#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94298#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 94495#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 93663#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 93664#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94605#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94606#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 93604#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 93605#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 95418#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 95408#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 94125#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 94126#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 94930#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 94936#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 95077#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 94065#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94066#L1342-1 assume !(0 == ~M_E~0); 94642#L1347-1 assume !(0 == ~T1_E~0); 95243#L1352-1 assume !(0 == ~T2_E~0); 95004#L1357-1 assume !(0 == ~T3_E~0); 94192#L1362-1 assume !(0 == ~T4_E~0); 94193#L1367-1 assume !(0 == ~T5_E~0); 93746#L1372-1 assume !(0 == ~T6_E~0); 93747#L1377-1 assume !(0 == ~T7_E~0); 94106#L1382-1 assume !(0 == ~T8_E~0); 94107#L1387-1 assume !(0 == ~T9_E~0); 94877#L1392-1 assume !(0 == ~T10_E~0); 94144#L1397-1 assume !(0 == ~T11_E~0); 94145#L1402-1 assume !(0 == ~T12_E~0); 93755#L1407-1 assume !(0 == ~T13_E~0); 93756#L1412-1 assume !(0 == ~T14_E~0); 95131#L1417-1 assume !(0 == ~E_1~0); 95132#L1422-1 assume !(0 == ~E_2~0); 95479#L1427-1 assume !(0 == ~E_3~0); 93962#L1432-1 assume !(0 == ~E_4~0); 93963#L1437-1 assume !(0 == ~E_5~0); 95052#L1442-1 assume !(0 == ~E_6~0); 95053#L1447-1 assume !(0 == ~E_7~0); 94867#L1452-1 assume !(0 == ~E_8~0); 93503#L1457-1 assume !(0 == ~E_9~0); 93504#L1462-1 assume !(0 == ~E_10~0); 95085#L1467-1 assume !(0 == ~E_11~0); 95105#L1472-1 assume !(0 == ~E_12~0); 95106#L1477-1 assume !(0 == ~E_13~0); 94824#L1482-1 assume !(0 == ~E_14~0); 93896#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 93897#L646-15 assume !(1 == ~m_pc~0); 94780#L656-15 is_master_triggered_~__retres1~0#1 := 0; 94204#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94205#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 94611#L1666-15 assume !(0 != activate_threads_~tmp~1#1); 93627#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 93628#L665-15 assume !(1 == ~t1_pc~0); 94258#L675-15 is_transmit1_triggered_~__retres1~1#1 := 0; 94259#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94303#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 95374#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 95368#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94658#L684-15 assume 1 == ~t2_pc~0; 94659#L685-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 94489#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94490#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 95155#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 95156#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95152#L703-15 assume 1 == ~t3_pc~0; 94710#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94711#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94292#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 94293#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 95247#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95248#L722-15 assume 1 == ~t4_pc~0; 94314#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 94315#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95361#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94548#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94549#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95446#L741-15 assume 1 == ~t5_pc~0; 94031#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 94032#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94338#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 94792#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 93868#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 93869#L760-15 assume 1 == ~t6_pc~0; 94812#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 94813#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94358#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 94359#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 93884#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 93885#L779-15 assume 1 == ~t7_pc~0; 94900#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 93611#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 93740#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93741#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 95529#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94080#L798-15 assume 1 == ~t8_pc~0; 94081#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 94570#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 95535#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 95231#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 95137#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94363#L817-15 assume 1 == ~t9_pc~0; 94364#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 93599#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 94845#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 94846#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 95424#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95425#L836-15 assume 1 == ~t10_pc~0; 94729#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 93701#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 93702#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 94360#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 95344#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 94287#L855-15 assume 1 == ~t11_pc~0; 94288#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 94312#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 95206#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 94841#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 94842#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 93323#L874-15 assume 1 == ~t12_pc~0; 93324#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 95200#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 94631#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 94632#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 94174#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 93346#L893-15 assume 1 == ~t13_pc~0; 93347#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 93939#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 94737#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 94738#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 94759#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 94072#L912-15 assume 1 == ~t14_pc~0; 94073#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 94899#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 95409#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 95410#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 94802#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94083#L1495-1 assume !(1 == ~M_E~0); 94084#L1500-1 assume !(1 == ~T1_E~0); 94595#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94596#L1510-1 assume !(1 == ~T3_E~0); 94650#L1515-1 assume !(1 == ~T4_E~0); 94651#L1520-1 assume !(1 == ~T5_E~0); 95321#L1525-1 assume !(1 == ~T6_E~0); 94971#L1530-1 assume !(1 == ~T7_E~0); 93826#L1535-1 assume !(1 == ~T8_E~0); 93827#L1540-1 assume !(1 == ~T9_E~0); 93344#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 93345#L1550-1 assume !(1 == ~T11_E~0); 93540#L1555-1 assume !(1 == ~T12_E~0); 93541#L1560-1 assume !(1 == ~T13_E~0); 93879#L1565-1 assume !(1 == ~T14_E~0); 95490#L1570-1 assume !(1 == ~E_1~0); 94837#L1575-1 assume !(1 == ~E_2~0); 94197#L1580-1 assume !(1 == ~E_3~0); 94198#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 94670#L1590-1 assume !(1 == ~E_5~0); 94239#L1595-1 assume !(1 == ~E_6~0); 94240#L1600-1 assume !(1 == ~E_7~0); 94602#L1605-1 assume !(1 == ~E_8~0); 94603#L1610-1 assume !(1 == ~E_9~0); 95180#L1615-1 assume !(1 == ~E_10~0); 94022#L1620-1 assume !(1 == ~E_11~0); 94023#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 94868#L1630-1 assume !(1 == ~E_13~0); 94238#L1635-1 assume !(1 == ~E_14~0); 93414#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 93415#L2017 [2024-11-17 08:54:05,650 INFO L747 eck$LassoCheckResult]: Loop: 93415#L2017 assume true; 97999#L2017-1 assume !false; 97946#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97942#L1110 assume true; 97939#L1110-1 assume !false; 97937#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 97924#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 97914#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 97912#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 94895#L1115 assume !(0 != eval_~tmp~0#1); 94896#L1118 assume true; 100581#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 100580#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100579#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 94585#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 94586#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 93777#L1357 assume !(0 == ~T3_E~0); 93778#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 94714#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94715#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 94831#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 94305#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 94306#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 93863#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 93864#L1397 assume !(0 == ~T11_E~0); 95134#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 93438#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 93439#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 93889#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 94121#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 94122#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 95157#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 95158#L1437 assume !(0 == ~E_5~0); 95326#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 95233#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 93872#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 93873#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 94540#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 94425#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 94426#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 94858#L1477 assume !(0 == ~E_13~0); 93608#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 93609#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95454#L646-1 assume !(1 == ~m_pc~0); 94827#L656-1 is_master_triggered_~__retres1~0#1 := 0; 94828#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95263#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 95493#L1666-1 assume !(0 != activate_threads_~tmp~1#1); 95494#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95235#L665-1 assume !(1 == ~t1_pc~0); 94594#L675-1 is_transmit1_triggered_~__retres1~1#1 := 0; 94452#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94453#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 93770#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 93771#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95443#L684-1 assume 1 == ~t2_pc~0; 94781#L685-1 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 94783#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94771#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 94772#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 94876#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 93893#L703-1 assume !(1 == ~t3_pc~0); 93895#L713-1 is_transmit3_triggered_~__retres1~3#1 := 0; 94709#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94850#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 95153#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 95523#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95240#L722-1 assume 1 == ~t4_pc~0; 95241#L723-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 94172#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95497#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94543#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94544#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95210#L741-1 assume 1 == ~t5_pc~0; 95510#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 93584#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 93772#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 93759#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 93760#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 94491#L760-1 assume 1 == ~t6_pc~0; 95451#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 94815#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 94816#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 94830#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 94321#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 94322#L779-1 assume 1 == ~t7_pc~0; 94496#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 94497#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 93392#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 93393#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 94568#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 94569#L798-1 assume 1 == ~t8_pc~0; 94925#L799-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 94138#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 94139#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 93602#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 93603#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 94852#L817-1 assume 1 == ~t9_pc~0; 95360#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 93914#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 93915#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 94918#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 95328#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 95215#L836-1 assume 1 == ~t10_pc~0; 95216#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 93595#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 95042#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 94687#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 94688#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 95359#L855-1 assume 1 == ~t11_pc~0; 95090#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 93968#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 93814#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 93815#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 94756#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 94757#L874-1 assume 1 == ~t12_pc~0; 94793#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 95260#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 95369#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 93596#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 93597#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 94178#L893-1 assume 1 == ~t13_pc~0; 93692#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 93693#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 93921#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 93922#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 95351#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 94323#L912-1 assume !(1 == ~t14_pc~0); 94325#L922-1 is_transmit14_triggered_~__retres1~14#1 := 0; 94735#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 95186#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 93875#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 93876#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93966#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 93674#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 93675#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 95402#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94155#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94156#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94533#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 93982#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 93983#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 94473#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 95428#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 95513#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 94847#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 94597#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 93661#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 93662#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 94384#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 93948#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 93949#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 95395#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 95396#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 95357#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 95183#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 95184#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 94643#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 94283#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 94284#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 93364#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 93365#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 93573#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 93971#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 93525#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 94942#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 94934#L2036 assume !(0 == start_simulation_~tmp~3#1); 94935#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 98025#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 98014#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 98012#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 98009#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98007#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98005#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 98002#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 93415#L2017 [2024-11-17 08:54:05,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:05,651 INFO L85 PathProgramCache]: Analyzing trace with hash -273109226, now seen corresponding path program 1 times [2024-11-17 08:54:05,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:05,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1438697167] [2024-11-17 08:54:05,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:05,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:05,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:05,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:05,707 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:05,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1438697167] [2024-11-17 08:54:05,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1438697167] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:05,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:05,708 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:05,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988347784] [2024-11-17 08:54:05,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:05,708 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:05,709 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:05,709 INFO L85 PathProgramCache]: Analyzing trace with hash 718814329, now seen corresponding path program 1 times [2024-11-17 08:54:05,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:05,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985751765] [2024-11-17 08:54:05,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:05,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:05,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:05,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:05,777 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:05,777 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985751765] [2024-11-17 08:54:05,777 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985751765] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:05,777 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:05,777 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:05,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960861894] [2024-11-17 08:54:05,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:05,778 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:05,778 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:05,778 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:05,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:05,779 INFO L87 Difference]: Start difference. First operand 7482 states and 10737 transitions. cyclomatic complexity: 3259 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:05,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:05,991 INFO L93 Difference]: Finished difference Result 14290 states and 20422 transitions. [2024-11-17 08:54:05,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14290 states and 20422 transitions. [2024-11-17 08:54:06,060 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14080 [2024-11-17 08:54:06,109 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14290 states to 14290 states and 20422 transitions. [2024-11-17 08:54:06,109 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14290 [2024-11-17 08:54:06,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14290 [2024-11-17 08:54:06,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14290 states and 20422 transitions. [2024-11-17 08:54:06,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:06,143 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14290 states and 20422 transitions. [2024-11-17 08:54:06,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14290 states and 20422 transitions. [2024-11-17 08:54:06,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14290 to 14274. [2024-11-17 08:54:06,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14274 states, 14274 states have (on average 1.4295922656578395) internal successors, (20406), 14273 states have internal predecessors, (20406), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:06,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14274 states to 14274 states and 20406 transitions. [2024-11-17 08:54:06,350 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14274 states and 20406 transitions. [2024-11-17 08:54:06,351 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:06,351 INFO L425 stractBuchiCegarLoop]: Abstraction has 14274 states and 20406 transitions. [2024-11-17 08:54:06,351 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-17 08:54:06,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14274 states and 20406 transitions. [2024-11-17 08:54:06,398 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14064 [2024-11-17 08:54:06,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:06,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:06,401 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:06,401 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:06,402 INFO L745 eck$LassoCheckResult]: Stem: 116062#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 116063#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 116694#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 116081#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 116082#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 116280#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 115445#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 115446#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 116390#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 116391#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 115386#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 115387#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 117222#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 117209#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 115909#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 115910#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 116718#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 116723#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 116867#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 115848#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 115849#L1342-1 assume !(0 == ~M_E~0); 116427#L1347-1 assume !(0 == ~T1_E~0); 117025#L1352-1 assume !(0 == ~T2_E~0); 116792#L1357-1 assume !(0 == ~T3_E~0); 115974#L1362-1 assume !(0 == ~T4_E~0); 115975#L1367-1 assume !(0 == ~T5_E~0); 115529#L1372-1 assume !(0 == ~T6_E~0); 115530#L1377-1 assume !(0 == ~T7_E~0); 115890#L1382-1 assume !(0 == ~T8_E~0); 115891#L1387-1 assume !(0 == ~T9_E~0); 116668#L1392-1 assume !(0 == ~T10_E~0); 115928#L1397-1 assume !(0 == ~T11_E~0); 115929#L1402-1 assume !(0 == ~T12_E~0); 115538#L1407-1 assume !(0 == ~T13_E~0); 115539#L1412-1 assume !(0 == ~T14_E~0); 116917#L1417-1 assume !(0 == ~E_1~0); 116918#L1422-1 assume !(0 == ~E_2~0); 117288#L1427-1 assume !(0 == ~E_3~0); 115744#L1432-1 assume !(0 == ~E_4~0); 115745#L1437-1 assume !(0 == ~E_5~0); 116841#L1442-1 assume !(0 == ~E_6~0); 116842#L1447-1 assume !(0 == ~E_7~0); 116659#L1452-1 assume !(0 == ~E_8~0); 115283#L1457-1 assume !(0 == ~E_9~0); 115284#L1462-1 assume !(0 == ~E_10~0); 116875#L1467-1 assume !(0 == ~E_11~0); 116891#L1472-1 assume !(0 == ~E_12~0); 116892#L1477-1 assume !(0 == ~E_13~0); 116614#L1482-1 assume !(0 == ~E_14~0); 115679#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 115680#L646-15 assume !(1 == ~m_pc~0); 116567#L656-15 is_master_triggered_~__retres1~0#1 := 0; 115986#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 115987#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 116396#L1666-15 assume !(0 != activate_threads_~tmp~1#1); 115409#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 115410#L665-15 assume !(1 == ~t1_pc~0); 116043#L675-15 is_transmit1_triggered_~__retres1~1#1 := 0; 116044#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116087#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 117166#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 117160#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 116444#L684-15 assume !(1 == ~t2_pc~0); 116445#L694-15 is_transmit2_triggered_~__retres1~2#1 := 0; 116274#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116275#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 116938#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 116939#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116935#L703-15 assume 1 == ~t3_pc~0; 116495#L704-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 116496#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116076#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 116077#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 117030#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117031#L722-15 assume 1 == ~t4_pc~0; 116100#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 116101#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117152#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 116334#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 116335#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117255#L741-15 assume 1 == ~t5_pc~0; 115813#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 115814#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 116126#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 116580#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 115650#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 115651#L760-15 assume 1 == ~t6_pc~0; 116601#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 116602#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116145#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116146#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 115667#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 115668#L779-15 assume 1 == ~t7_pc~0; 116691#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 115393#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 115523#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 115524#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 117354#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 115864#L798-15 assume 1 == ~t8_pc~0; 115865#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 116355#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 117368#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 117012#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 116923#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 116150#L817-15 assume 1 == ~t9_pc~0; 116151#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 115381#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 116637#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 116638#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 117230#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 117231#L836-15 assume 1 == ~t10_pc~0; 116513#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 115483#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 115484#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 116147#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 117130#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 116071#L855-15 assume 1 == ~t11_pc~0; 116072#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 116098#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 116985#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 116633#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 116634#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 115104#L874-15 assume 1 == ~t12_pc~0; 115105#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 116979#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 116416#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 116417#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 115956#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 115127#L893-15 assume 1 == ~t13_pc~0; 115128#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 115722#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 116524#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 116525#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 116545#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 115856#L912-15 assume 1 == ~t14_pc~0; 115857#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 116690#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 117210#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 117211#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 116591#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115867#L1495-1 assume !(1 == ~M_E~0); 115868#L1500-1 assume !(1 == ~T1_E~0); 116380#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116381#L1510-1 assume !(1 == ~T3_E~0); 116436#L1515-1 assume !(1 == ~T4_E~0); 116437#L1520-1 assume !(1 == ~T5_E~0); 117104#L1525-1 assume !(1 == ~T6_E~0); 116759#L1530-1 assume !(1 == ~T7_E~0); 115609#L1535-1 assume !(1 == ~T8_E~0); 115610#L1540-1 assume !(1 == ~T9_E~0); 115125#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 115126#L1550-1 assume !(1 == ~T11_E~0); 115322#L1555-1 assume !(1 == ~T12_E~0); 115323#L1560-1 assume !(1 == ~T13_E~0); 115662#L1565-1 assume !(1 == ~T14_E~0); 117303#L1570-1 assume !(1 == ~E_1~0); 116629#L1575-1 assume !(1 == ~E_2~0); 115979#L1580-1 assume !(1 == ~E_3~0); 115980#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 116457#L1590-1 assume !(1 == ~E_5~0); 116023#L1595-1 assume !(1 == ~E_6~0); 116024#L1600-1 assume !(1 == ~E_7~0); 116387#L1605-1 assume !(1 == ~E_8~0); 116388#L1610-1 assume !(1 == ~E_9~0); 116961#L1615-1 assume !(1 == ~E_10~0); 115804#L1620-1 assume !(1 == ~E_11~0); 115805#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 116660#L1630-1 assume !(1 == ~E_13~0); 116022#L1635-1 assume !(1 == ~E_14~0); 115195#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 115196#L2017 [2024-11-17 08:54:06,402 INFO L747 eck$LassoCheckResult]: Loop: 115196#L2017 assume true; 116226#L2017-1 assume !false; 115768#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 115572#L1110 assume true; 115276#L1110-1 assume !false; 115277#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 117171#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 115992#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 117063#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 116686#L1115 assume !(0 != eval_~tmp~0#1); 116687#L1118 assume true; 128968#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 128966#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 128964#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 128962#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 128960#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 128958#L1357 assume !(0 == ~T3_E~0); 128956#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 128954#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 128952#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 128950#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 128948#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 128946#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 128944#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 128942#L1397 assume !(0 == ~T11_E~0); 128940#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 128938#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 128936#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 128934#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 128932#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 128930#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 128928#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 128926#L1437 assume !(0 == ~E_5~0); 128924#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 128922#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 128920#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 128918#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 128916#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 128914#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 128912#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 128910#L1477 assume !(0 == ~E_13~0); 128908#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 128906#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 128904#L646-1 assume !(1 == ~m_pc~0); 128901#L656-1 is_master_triggered_~__retres1~0#1 := 0; 128899#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128897#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 128896#L1666-1 assume !(0 != activate_threads_~tmp~1#1); 117326#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 117016#L665-1 assume !(1 == ~t1_pc~0); 116379#L675-1 is_transmit1_triggered_~__retres1~1#1 := 0; 116237#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116238#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 115553#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 115554#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117252#L684-1 assume !(1 == ~t2_pc~0); 116717#L694-1 is_transmit2_triggered_~__retres1~2#1 := 0; 116572#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116557#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 116558#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 116667#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 115676#L703-1 assume 1 == ~t3_pc~0; 115677#L704-1 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 116494#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116642#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 116936#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 117349#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117022#L722-1 assume !(1 == ~t4_pc~0); 115954#L732-1 is_transmit4_triggered_~__retres1~4#1 := 0; 115955#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 117313#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 116326#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 116327#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 116989#L741-1 assume 1 == ~t5_pc~0; 117329#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 115366#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 115555#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 115542#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 115543#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116276#L760-1 assume 1 == ~t6_pc~0; 117259#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 116604#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116605#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 116621#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 116107#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 116108#L779-1 assume 1 == ~t7_pc~0; 116281#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 116282#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 115173#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 115174#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 116353#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 116354#L798-1 assume !(1 == ~t8_pc~0); 116389#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 115922#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 115923#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 115384#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 115385#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 116644#L817-1 assume 1 == ~t9_pc~0; 117149#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 129178#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 129177#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 129176#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 129175#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 129174#L836-1 assume 1 == ~t10_pc~0; 129173#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 129171#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 129170#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 129169#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 129167#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 117386#L855-1 assume !(1 == ~t11_pc~0); 116692#L865-1 is_transmit11_triggered_~__retres1~11#1 := 0; 115750#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 115597#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 115598#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 116542#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 116543#L874-1 assume 1 == ~t12_pc~0; 116581#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 117048#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 117161#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 115378#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 115379#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 115960#L893-1 assume 1 == ~t13_pc~0; 115474#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 115475#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 115704#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 115705#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 117138#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 116109#L912-1 assume !(1 == ~t14_pc~0); 116111#L922-1 is_transmit14_triggered_~__retres1~14#1 := 0; 116519#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 116968#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 115658#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 115659#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115748#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 115456#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 115457#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117199#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 115939#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 115940#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 116316#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 115764#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 115765#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 116257#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 117234#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 117335#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 117336#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 128859#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 128858#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 128857#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 128856#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 128855#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 128854#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 128853#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 128852#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 128851#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 128850#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 128849#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 128848#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 116067#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 116068#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 115145#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 115146#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 115355#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 115753#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 115306#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 116729#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 116722#L2036 assume !(0 == start_simulation_~tmp~3#1); 116029#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 117415#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 115137#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 115251#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 115252#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 116205#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 116206#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 117301#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 115196#L2017 [2024-11-17 08:54:06,404 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:06,404 INFO L85 PathProgramCache]: Analyzing trace with hash 882168563, now seen corresponding path program 1 times [2024-11-17 08:54:06,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:06,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893131865] [2024-11-17 08:54:06,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:06,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:06,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:06,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:06,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:06,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893131865] [2024-11-17 08:54:06,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893131865] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:06,457 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:06,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:06,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1633745957] [2024-11-17 08:54:06,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:06,458 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:06,458 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:06,459 INFO L85 PathProgramCache]: Analyzing trace with hash -1903044208, now seen corresponding path program 1 times [2024-11-17 08:54:06,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:06,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926752319] [2024-11-17 08:54:06,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:06,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:06,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:06,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:06,528 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:06,528 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1926752319] [2024-11-17 08:54:06,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1926752319] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:06,528 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:06,528 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:06,528 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [740840413] [2024-11-17 08:54:06,529 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:06,529 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:06,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:06,529 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:06,530 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:06,530 INFO L87 Difference]: Start difference. First operand 14274 states and 20406 transitions. cyclomatic complexity: 6140 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:06,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:06,736 INFO L93 Difference]: Finished difference Result 27393 states and 39019 transitions. [2024-11-17 08:54:06,736 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27393 states and 39019 transitions. [2024-11-17 08:54:06,978 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27140 [2024-11-17 08:54:07,073 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27393 states to 27393 states and 39019 transitions. [2024-11-17 08:54:07,074 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27393 [2024-11-17 08:54:07,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27393 [2024-11-17 08:54:07,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27393 states and 39019 transitions. [2024-11-17 08:54:07,127 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:07,127 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27393 states and 39019 transitions. [2024-11-17 08:54:07,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27393 states and 39019 transitions. [2024-11-17 08:54:07,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27393 to 27361. [2024-11-17 08:54:07,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27361 states, 27361 states have (on average 1.4249113701984577) internal successors, (38987), 27360 states have internal predecessors, (38987), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:07,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27361 states to 27361 states and 38987 transitions. [2024-11-17 08:54:07,529 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27361 states and 38987 transitions. [2024-11-17 08:54:07,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:07,530 INFO L425 stractBuchiCegarLoop]: Abstraction has 27361 states and 38987 transitions. [2024-11-17 08:54:07,531 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-17 08:54:07,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27361 states and 38987 transitions. [2024-11-17 08:54:07,627 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27108 [2024-11-17 08:54:07,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:07,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:07,630 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:07,630 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:07,631 INFO L745 eck$LassoCheckResult]: Stem: 157745#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 157746#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 158386#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 157768#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 157769#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 157971#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 157121#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157122#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 158081#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 158082#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 157062#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 157063#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 158923#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 158911#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 157590#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 157591#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 158412#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 158418#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 158565#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 157528#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 157529#L1342-1 assume !(0 == ~M_E~0); 158124#L1347-1 assume !(0 == ~T1_E~0); 158721#L1352-1 assume !(0 == ~T2_E~0); 158488#L1357-1 assume !(0 == ~T3_E~0); 157657#L1362-1 assume !(0 == ~T4_E~0); 157658#L1367-1 assume !(0 == ~T5_E~0); 157204#L1372-1 assume !(0 == ~T6_E~0); 157205#L1377-1 assume !(0 == ~T7_E~0); 157573#L1382-1 assume !(0 == ~T8_E~0); 157574#L1387-1 assume !(0 == ~T9_E~0); 158358#L1392-1 assume !(0 == ~T10_E~0); 157608#L1397-1 assume !(0 == ~T11_E~0); 157609#L1402-1 assume !(0 == ~T12_E~0); 157213#L1407-1 assume !(0 == ~T13_E~0); 157214#L1412-1 assume !(0 == ~T14_E~0); 158616#L1417-1 assume !(0 == ~E_1~0); 158617#L1422-1 assume !(0 == ~E_2~0); 158990#L1427-1 assume !(0 == ~E_3~0); 157421#L1432-1 assume !(0 == ~E_4~0); 157422#L1437-1 assume !(0 == ~E_5~0); 158536#L1442-1 assume !(0 == ~E_6~0); 158537#L1447-1 assume !(0 == ~E_7~0); 158349#L1452-1 assume !(0 == ~E_8~0); 156960#L1457-1 assume !(0 == ~E_9~0); 156961#L1462-1 assume !(0 == ~E_10~0); 158573#L1467-1 assume !(0 == ~E_11~0); 158589#L1472-1 assume !(0 == ~E_12~0); 158590#L1477-1 assume !(0 == ~E_13~0); 158305#L1482-1 assume !(0 == ~E_14~0); 157358#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157359#L646-15 assume !(1 == ~m_pc~0); 158260#L656-15 is_master_triggered_~__retres1~0#1 := 0; 157669#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 157670#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 158087#L1666-15 assume !(0 != activate_threads_~tmp~1#1); 157087#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 157088#L665-15 assume !(1 == ~t1_pc~0); 157726#L675-15 is_transmit1_triggered_~__retres1~1#1 := 0; 157727#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 157772#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 158865#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 158861#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 158140#L684-15 assume !(1 == ~t2_pc~0); 158141#L694-15 is_transmit2_triggered_~__retres1~2#1 := 0; 157962#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157963#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 158637#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 158638#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 158634#L703-15 assume !(1 == ~t3_pc~0); 158506#L713-15 is_transmit3_triggered_~__retres1~3#1 := 0; 158383#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 157761#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 157762#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 158726#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 158727#L722-15 assume 1 == ~t4_pc~0; 157786#L723-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 157787#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 158850#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 158020#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 158021#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 158954#L741-15 assume 1 == ~t5_pc~0; 157497#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 157498#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 157808#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 158273#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 157328#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 157329#L760-15 assume 1 == ~t6_pc~0; 158293#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 158294#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 157828#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 157829#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 157344#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 157345#L779-15 assume 1 == ~t7_pc~0; 158382#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 157069#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 157200#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 157201#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 159068#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 157543#L798-15 assume 1 == ~t8_pc~0; 157544#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 158044#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 159082#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 158708#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 158624#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 157834#L817-15 assume 1 == ~t9_pc~0; 157835#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 157057#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 158327#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 158328#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 158931#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 158932#L836-15 assume 1 == ~t10_pc~0; 158204#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 157160#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 157161#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 157830#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 158827#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 157754#L855-15 assume 1 == ~t11_pc~0; 157755#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 157781#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 158681#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 158323#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 158324#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 156780#L874-15 assume 1 == ~t12_pc~0; 156781#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 158675#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 158111#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 158112#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 157639#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 156803#L893-15 assume 1 == ~t13_pc~0; 156804#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 157401#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 158215#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 158216#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 158240#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 157540#L912-15 assume 1 == ~t14_pc~0; 157541#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 158381#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 158912#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 158913#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 158286#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 157548#L1495-1 assume !(1 == ~M_E~0); 157549#L1500-1 assume !(1 == ~T1_E~0); 158069#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 158070#L1510-1 assume !(1 == ~T3_E~0); 158133#L1515-1 assume !(1 == ~T4_E~0); 158134#L1520-1 assume !(1 == ~T5_E~0); 158800#L1525-1 assume !(1 == ~T6_E~0); 158454#L1530-1 assume !(1 == ~T7_E~0); 157285#L1535-1 assume !(1 == ~T8_E~0); 157286#L1540-1 assume !(1 == ~T9_E~0); 156801#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 156802#L1550-1 assume !(1 == ~T11_E~0); 156998#L1555-1 assume !(1 == ~T12_E~0); 156999#L1560-1 assume !(1 == ~T13_E~0); 157341#L1565-1 assume !(1 == ~T14_E~0); 159004#L1570-1 assume !(1 == ~E_1~0); 158318#L1575-1 assume !(1 == ~E_2~0); 157664#L1580-1 assume !(1 == ~E_3~0); 157665#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 158151#L1590-1 assume !(1 == ~E_5~0); 157707#L1595-1 assume !(1 == ~E_6~0); 157708#L1600-1 assume !(1 == ~E_7~0); 158079#L1605-1 assume !(1 == ~E_8~0); 158080#L1610-1 assume !(1 == ~E_9~0); 158658#L1615-1 assume !(1 == ~E_10~0); 157483#L1620-1 assume !(1 == ~E_11~0); 157484#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 158350#L1630-1 assume !(1 == ~E_13~0); 157706#L1635-1 assume !(1 == ~E_14~0); 156872#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 156873#L2017 [2024-11-17 08:54:07,748 INFO L747 eck$LassoCheckResult]: Loop: 156873#L2017 assume true; 165027#L2017-1 assume !false; 165000#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164996#L1110 assume true; 164994#L1110-1 assume !false; 164991#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 164969#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 164959#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 164957#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 164954#L1115 assume !(0 != eval_~tmp~0#1); 164955#L1118 assume true; 165472#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 165470#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 165468#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 165466#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 165464#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 165462#L1357 assume !(0 == ~T3_E~0); 165459#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 165457#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 165455#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 165453#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 165451#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 165449#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 165446#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 165444#L1397 assume !(0 == ~T11_E~0); 165442#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 165440#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 165438#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 165436#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 165433#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 165431#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 165429#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 165427#L1437 assume !(0 == ~E_5~0); 165425#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 165422#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 165420#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 165418#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 165416#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 165414#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 165411#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 165407#L1477 assume !(0 == ~E_13~0); 165403#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 165402#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 165401#L646-1 assume !(1 == ~m_pc~0); 165400#L656-1 is_master_triggered_~__retres1~0#1 := 0; 165399#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 165398#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 165397#L1666-1 assume !(0 != activate_threads_~tmp~1#1); 165396#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 165395#L665-1 assume !(1 == ~t1_pc~0); 165394#L675-1 is_transmit1_triggered_~__retres1~1#1 := 0; 165393#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 165392#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 165391#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 165389#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 165387#L684-1 assume !(1 == ~t2_pc~0); 165385#L694-1 is_transmit2_triggered_~__retres1~2#1 := 0; 165383#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 165381#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 165379#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 165377#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 165375#L703-1 assume !(1 == ~t3_pc~0); 165373#L713-1 is_transmit3_triggered_~__retres1~3#1 := 0; 165371#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 165369#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 165367#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 165365#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 165363#L722-1 assume !(1 == ~t4_pc~0); 165360#L732-1 is_transmit4_triggered_~__retres1~4#1 := 0; 165358#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 165356#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 165354#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 165352#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 165350#L741-1 assume !(1 == ~t5_pc~0); 165347#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 165345#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 165343#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 165341#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 165339#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 165336#L760-1 assume 1 == ~t6_pc~0; 165334#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 165331#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 165329#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 165327#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 165325#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 165322#L779-1 assume !(1 == ~t7_pc~0); 165319#L789-1 is_transmit7_triggered_~__retres1~7#1 := 0; 165317#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 165315#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 165313#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 165311#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 165308#L798-1 assume 1 == ~t8_pc~0; 165306#L799-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 165303#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 165301#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 165299#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 165297#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 165294#L817-1 assume !(1 == ~t9_pc~0); 165291#L827-1 is_transmit9_triggered_~__retres1~9#1 := 0; 165289#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 165287#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 165285#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 165283#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 165280#L836-1 assume 1 == ~t10_pc~0; 165278#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 165275#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 165273#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 165271#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 165269#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 165266#L855-1 assume 1 == ~t11_pc~0; 165264#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 165261#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 165259#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 165257#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 165255#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 165252#L874-1 assume 1 == ~t12_pc~0; 165250#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 165247#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 165245#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 165243#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 165241#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 165238#L893-1 assume !(1 == ~t13_pc~0); 165235#L903-1 is_transmit13_triggered_~__retres1~13#1 := 0; 165232#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 165229#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 165226#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 165223#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 165219#L912-1 assume 1 == ~t14_pc~0; 165216#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 165212#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 165208#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 165205#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 165202#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 165198#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 165195#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 165192#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 165189#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 165186#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 165183#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 165179#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 165176#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 165173#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 165170#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 165167#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 165164#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 165161#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 165158#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 165155#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 165151#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 165148#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 165145#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 165142#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 165139#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 165136#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 165132#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 165129#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 165126#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 165123#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 165120#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 165117#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 165113#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 165110#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 165107#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 165086#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 165070#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 165067#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 165063#L2036 assume !(0 == start_simulation_~tmp~3#1); 165060#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 165053#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 165041#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 165039#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 165037#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 165035#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 165033#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 165031#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 156873#L2017 [2024-11-17 08:54:07,749 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:07,749 INFO L85 PathProgramCache]: Analyzing trace with hash 1255956624, now seen corresponding path program 1 times [2024-11-17 08:54:07,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:07,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793117314] [2024-11-17 08:54:07,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:07,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:07,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:07,821 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:07,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:07,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793117314] [2024-11-17 08:54:07,822 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793117314] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:07,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:07,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:07,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1444187576] [2024-11-17 08:54:07,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:07,824 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:07,824 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:07,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1609407050, now seen corresponding path program 1 times [2024-11-17 08:54:07,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:07,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [480635614] [2024-11-17 08:54:07,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:07,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:07,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:07,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:07,901 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:07,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [480635614] [2024-11-17 08:54:07,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [480635614] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:07,901 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:07,901 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:07,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327283186] [2024-11-17 08:54:07,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:07,902 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:07,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:07,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:07,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:07,903 INFO L87 Difference]: Start difference. First operand 27361 states and 38987 transitions. cyclomatic complexity: 11642 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:08,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:08,167 INFO L93 Difference]: Finished difference Result 52612 states and 74720 transitions. [2024-11-17 08:54:08,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52612 states and 74720 transitions. [2024-11-17 08:54:08,625 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52256 [2024-11-17 08:54:08,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52612 states to 52612 states and 74720 transitions. [2024-11-17 08:54:08,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52612 [2024-11-17 08:54:09,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52612 [2024-11-17 08:54:09,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52612 states and 74720 transitions. [2024-11-17 08:54:09,057 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:09,059 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52612 states and 74720 transitions. [2024-11-17 08:54:09,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52612 states and 74720 transitions. [2024-11-17 08:54:09,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52612 to 52548. [2024-11-17 08:54:09,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52548 states, 52548 states have (on average 1.4207201035243968) internal successors, (74656), 52547 states have internal predecessors, (74656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:09,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52548 states to 52548 states and 74656 transitions. [2024-11-17 08:54:09,975 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52548 states and 74656 transitions. [2024-11-17 08:54:09,976 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:09,976 INFO L425 stractBuchiCegarLoop]: Abstraction has 52548 states and 74656 transitions. [2024-11-17 08:54:09,977 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-17 08:54:09,977 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52548 states and 74656 transitions. [2024-11-17 08:54:10,244 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52192 [2024-11-17 08:54:10,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:10,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:10,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:10,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:10,248 INFO L745 eck$LassoCheckResult]: Stem: 237714#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 237715#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 238346#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 237735#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 237736#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 237930#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 237100#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 237101#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 238049#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 238050#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 237043#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 237044#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 238875#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 238863#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 237565#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 237566#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 238370#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 238377#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 238526#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 237501#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 237502#L1342-1 assume !(0 == ~M_E~0); 238087#L1347-1 assume !(0 == ~T1_E~0); 238687#L1352-1 assume !(0 == ~T2_E~0); 238450#L1357-1 assume !(0 == ~T3_E~0); 237629#L1362-1 assume !(0 == ~T4_E~0); 237630#L1367-1 assume !(0 == ~T5_E~0); 237184#L1372-1 assume !(0 == ~T6_E~0); 237185#L1377-1 assume !(0 == ~T7_E~0); 237545#L1382-1 assume !(0 == ~T8_E~0); 237546#L1387-1 assume !(0 == ~T9_E~0); 238319#L1392-1 assume !(0 == ~T10_E~0); 237583#L1397-1 assume !(0 == ~T11_E~0); 237584#L1402-1 assume !(0 == ~T12_E~0); 237193#L1407-1 assume !(0 == ~T13_E~0); 237194#L1412-1 assume !(0 == ~T14_E~0); 238576#L1417-1 assume !(0 == ~E_1~0); 238577#L1422-1 assume !(0 == ~E_2~0); 238946#L1427-1 assume !(0 == ~E_3~0); 237398#L1432-1 assume !(0 == ~E_4~0); 237399#L1437-1 assume !(0 == ~E_5~0); 238500#L1442-1 assume !(0 == ~E_6~0); 238501#L1447-1 assume !(0 == ~E_7~0); 238311#L1452-1 assume !(0 == ~E_8~0); 236941#L1457-1 assume !(0 == ~E_9~0); 236942#L1462-1 assume !(0 == ~E_10~0); 238535#L1467-1 assume !(0 == ~E_11~0); 238550#L1472-1 assume !(0 == ~E_12~0); 238551#L1477-1 assume !(0 == ~E_13~0); 238267#L1482-1 assume !(0 == ~E_14~0); 237333#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 237334#L646-15 assume !(1 == ~m_pc~0); 238222#L656-15 is_master_triggered_~__retres1~0#1 := 0; 237641#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 237642#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 238055#L1666-15 assume !(0 != activate_threads_~tmp~1#1); 237064#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 237065#L665-15 assume !(1 == ~t1_pc~0); 237696#L675-15 is_transmit1_triggered_~__retres1~1#1 := 0; 237697#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 237741#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 238821#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 238816#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 238103#L684-15 assume !(1 == ~t2_pc~0); 238104#L694-15 is_transmit2_triggered_~__retres1~2#1 := 0; 237924#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 237925#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 238597#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 238598#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 238594#L703-15 assume !(1 == ~t3_pc~0); 238468#L713-15 is_transmit3_triggered_~__retres1~3#1 := 0; 238343#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 237730#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 237731#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 238692#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 238693#L722-15 assume !(1 == ~t4_pc~0); 238159#L732-15 is_transmit4_triggered_~__retres1~4#1 := 0; 238160#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 238809#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 237988#L1698-15 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 237989#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 238913#L741-15 assume 1 == ~t5_pc~0; 237467#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 237468#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 237777#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 238233#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 237306#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 237307#L760-15 assume 1 == ~t6_pc~0; 238254#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 238255#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 237796#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 237797#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 237322#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 237323#L779-15 assume 1 == ~t7_pc~0; 238342#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 237050#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 237177#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 237178#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 239013#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 237517#L798-15 assume 1 == ~t8_pc~0; 237518#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 238014#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 239024#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 238675#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 238582#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 237801#L817-15 assume 1 == ~t9_pc~0; 237802#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 237038#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 238288#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 238289#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 238881#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 238882#L836-15 assume 1 == ~t10_pc~0; 238172#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 237138#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 237139#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 237798#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 238789#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 237724#L855-15 assume 1 == ~t11_pc~0; 237725#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 237751#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 238648#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 238284#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 238285#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 236762#L874-15 assume 1 == ~t12_pc~0; 236763#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 238643#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 238074#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 238075#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 237611#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 236785#L893-15 assume 1 == ~t13_pc~0; 236786#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 237375#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 238180#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 238181#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 238201#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 237508#L912-15 assume 1 == ~t14_pc~0; 237509#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 238341#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 238864#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 238865#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 238244#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 237520#L1495-1 assume !(1 == ~M_E~0); 237521#L1500-1 assume !(1 == ~T1_E~0); 238039#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 238040#L1510-1 assume !(1 == ~T3_E~0); 238095#L1515-1 assume !(1 == ~T4_E~0); 238096#L1520-1 assume !(1 == ~T5_E~0); 238764#L1525-1 assume !(1 == ~T6_E~0); 238414#L1530-1 assume !(1 == ~T7_E~0); 237265#L1535-1 assume !(1 == ~T8_E~0); 237266#L1540-1 assume !(1 == ~T9_E~0); 236783#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 236784#L1550-1 assume !(1 == ~T11_E~0); 236979#L1555-1 assume !(1 == ~T12_E~0); 236980#L1560-1 assume !(1 == ~T13_E~0); 237317#L1565-1 assume !(1 == ~T14_E~0); 238962#L1570-1 assume !(1 == ~E_1~0); 238280#L1575-1 assume !(1 == ~E_2~0); 237634#L1580-1 assume !(1 == ~E_3~0); 237635#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 238114#L1590-1 assume !(1 == ~E_5~0); 237677#L1595-1 assume !(1 == ~E_6~0); 237678#L1600-1 assume !(1 == ~E_7~0); 238046#L1605-1 assume !(1 == ~E_8~0); 238047#L1610-1 assume !(1 == ~E_9~0); 238621#L1615-1 assume !(1 == ~E_10~0); 237457#L1620-1 assume !(1 == ~E_11~0); 237458#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 238312#L1630-1 assume !(1 == ~E_13~0); 237676#L1635-1 assume !(1 == ~E_14~0); 236854#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 236855#L2017 [2024-11-17 08:54:10,249 INFO L747 eck$LassoCheckResult]: Loop: 236855#L2017 assume true; 247631#L2017-1 assume !false; 247627#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 247624#L1110 assume true; 247623#L1110-1 assume !false; 247622#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 247614#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 247605#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 247604#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 247601#L1115 assume !(0 != eval_~tmp~0#1); 247602#L1118 assume true; 247971#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 247970#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 247969#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 247968#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 247967#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 247966#L1357 assume !(0 == ~T3_E~0); 247965#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 247964#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 247963#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 247962#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 247961#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 247960#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 247959#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 247958#L1397 assume !(0 == ~T11_E~0); 247957#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 247956#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 247955#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 247954#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 247953#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 247952#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 247951#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 247950#L1437 assume !(0 == ~E_5~0); 247949#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 247948#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 247947#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 247946#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 247945#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 247944#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 247943#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 247942#L1477 assume !(0 == ~E_13~0); 247941#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 247940#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 247939#L646-1 assume !(1 == ~m_pc~0); 247938#L656-1 is_master_triggered_~__retres1~0#1 := 0; 247937#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 247936#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 247935#L1666-1 assume !(0 != activate_threads_~tmp~1#1); 247933#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 247931#L665-1 assume !(1 == ~t1_pc~0); 247929#L675-1 is_transmit1_triggered_~__retres1~1#1 := 0; 247927#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 247925#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 247923#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 247921#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 247919#L684-1 assume !(1 == ~t2_pc~0); 247917#L694-1 is_transmit2_triggered_~__retres1~2#1 := 0; 247915#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 247913#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 247911#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 247909#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 247907#L703-1 assume !(1 == ~t3_pc~0); 247905#L713-1 is_transmit3_triggered_~__retres1~3#1 := 0; 247903#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247901#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 247899#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 247897#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 247895#L722-1 assume !(1 == ~t4_pc~0); 247893#L732-1 is_transmit4_triggered_~__retres1~4#1 := 0; 247891#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 247889#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 247887#L1698-1 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 247885#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 247883#L741-1 assume 1 == ~t5_pc~0; 247881#L742-1 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 247878#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 247876#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 247874#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 247872#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 247869#L760-1 assume 1 == ~t6_pc~0; 247867#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 247864#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 247862#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 247860#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 247858#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 247855#L779-1 assume 1 == ~t7_pc~0; 247853#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 247850#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 247848#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 247846#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 247844#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 247841#L798-1 assume 1 == ~t8_pc~0; 247839#L799-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 247836#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 247834#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 247832#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 247830#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 247827#L817-1 assume 1 == ~t9_pc~0; 247825#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 247822#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 247820#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 247818#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 247816#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 247813#L836-1 assume 1 == ~t10_pc~0; 247811#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 247808#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 247806#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 247804#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 247802#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 247799#L855-1 assume 1 == ~t11_pc~0; 247797#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 247794#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 247792#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 247790#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 247788#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 247785#L874-1 assume 1 == ~t12_pc~0; 247783#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 247780#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 247778#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 247776#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 247774#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 247771#L893-1 assume 1 == ~t13_pc~0; 247769#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 247766#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 247764#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 247762#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 247760#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 247757#L912-1 assume 1 == ~t14_pc~0; 247755#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 247752#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 247750#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 247748#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 247746#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 247743#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 247741#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 247739#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 247737#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 247735#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 247733#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 247731#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 247729#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 247727#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 247725#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 247723#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 247721#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 247719#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 247717#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 247715#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 247713#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 247711#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 247709#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 247707#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 247705#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 247703#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 247701#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 247699#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 247697#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 247695#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 247693#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 247691#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 247689#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 247687#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 247685#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 247681#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 247666#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 247664#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 247662#L2036 assume !(0 == start_simulation_~tmp~3#1); 247660#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 247654#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 247644#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 247643#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 247641#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 247638#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 247636#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 247634#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 236855#L2017 [2024-11-17 08:54:10,249 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:10,250 INFO L85 PathProgramCache]: Analyzing trace with hash -623794195, now seen corresponding path program 1 times [2024-11-17 08:54:10,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:10,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685974618] [2024-11-17 08:54:10,250 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:10,250 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:10,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:10,341 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:10,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:10,342 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685974618] [2024-11-17 08:54:10,342 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [685974618] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:10,342 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:10,342 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:10,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2140340771] [2024-11-17 08:54:10,342 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:10,343 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:10,343 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:10,343 INFO L85 PathProgramCache]: Analyzing trace with hash -860206250, now seen corresponding path program 1 times [2024-11-17 08:54:10,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:10,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095873316] [2024-11-17 08:54:10,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:10,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:10,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:10,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:10,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:10,431 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095873316] [2024-11-17 08:54:10,432 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095873316] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:10,432 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:10,432 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:10,432 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1847001098] [2024-11-17 08:54:10,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:10,433 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:10,433 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:10,433 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-17 08:54:10,434 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-17 08:54:10,434 INFO L87 Difference]: Start difference. First operand 52548 states and 74656 transitions. cyclomatic complexity: 22140 Second operand has 5 states, 5 states have (on average 34.0) internal successors, (170), 5 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:11,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:11,009 INFO L93 Difference]: Finished difference Result 53172 states and 75087 transitions. [2024-11-17 08:54:11,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53172 states and 75087 transitions. [2024-11-17 08:54:11,229 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52816 [2024-11-17 08:54:11,666 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53172 states to 53172 states and 75087 transitions. [2024-11-17 08:54:11,666 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53172 [2024-11-17 08:54:11,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53172 [2024-11-17 08:54:11,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53172 states and 75087 transitions. [2024-11-17 08:54:11,765 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:11,765 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53172 states and 75087 transitions. [2024-11-17 08:54:11,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53172 states and 75087 transitions. [2024-11-17 08:54:12,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53172 to 53172. [2024-11-17 08:54:12,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53172 states, 53172 states have (on average 1.4121530128639133) internal successors, (75087), 53171 states have internal predecessors, (75087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:12,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53172 states to 53172 states and 75087 transitions. [2024-11-17 08:54:12,526 INFO L240 hiAutomatonCegarLoop]: Abstraction has 53172 states and 75087 transitions. [2024-11-17 08:54:12,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-17 08:54:12,528 INFO L425 stractBuchiCegarLoop]: Abstraction has 53172 states and 75087 transitions. [2024-11-17 08:54:12,528 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-17 08:54:12,528 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53172 states and 75087 transitions. [2024-11-17 08:54:12,724 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52816 [2024-11-17 08:54:12,724 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:12,724 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:12,727 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:12,727 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:12,728 INFO L745 eck$LassoCheckResult]: Stem: 343445#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 343446#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 344071#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 343464#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 343465#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 343659#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 342828#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 342829#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 343771#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 343772#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 342770#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 342771#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 344572#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 344560#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 343294#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 343295#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 344094#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 344100#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 344239#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 343231#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 343232#L1342-1 assume !(0 == ~M_E~0); 343808#L1347-1 assume !(0 == ~T1_E~0); 344393#L1352-1 assume !(0 == ~T2_E~0); 344165#L1357-1 assume !(0 == ~T3_E~0); 343359#L1362-1 assume !(0 == ~T4_E~0); 343360#L1367-1 assume !(0 == ~T5_E~0); 342912#L1372-1 assume !(0 == ~T6_E~0); 342913#L1377-1 assume !(0 == ~T7_E~0); 343275#L1382-1 assume !(0 == ~T8_E~0); 343276#L1387-1 assume !(0 == ~T9_E~0); 344040#L1392-1 assume !(0 == ~T10_E~0); 343313#L1397-1 assume !(0 == ~T11_E~0); 343314#L1402-1 assume !(0 == ~T12_E~0); 342921#L1407-1 assume !(0 == ~T13_E~0); 342922#L1412-1 assume !(0 == ~T14_E~0); 344290#L1417-1 assume !(0 == ~E_1~0); 344291#L1422-1 assume !(0 == ~E_2~0); 344632#L1427-1 assume !(0 == ~E_3~0); 343127#L1432-1 assume !(0 == ~E_4~0); 343128#L1437-1 assume !(0 == ~E_5~0); 344215#L1442-1 assume !(0 == ~E_6~0); 344216#L1447-1 assume !(0 == ~E_7~0); 344031#L1452-1 assume !(0 == ~E_8~0); 342671#L1457-1 assume !(0 == ~E_9~0); 342672#L1462-1 assume !(0 == ~E_10~0); 344248#L1467-1 assume !(0 == ~E_11~0); 344264#L1472-1 assume !(0 == ~E_12~0); 344265#L1477-1 assume !(0 == ~E_13~0); 343985#L1482-1 assume !(0 == ~E_14~0); 343062#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 343063#L646-15 assume !(1 == ~m_pc~0); 343940#L656-15 is_master_triggered_~__retres1~0#1 := 0; 343371#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 343372#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 343777#L1666-15 assume !(0 != activate_threads_~tmp~1#1); 342792#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 342793#L665-15 assume !(1 == ~t1_pc~0); 343426#L675-15 is_transmit1_triggered_~__retres1~1#1 := 0; 343427#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 343470#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 344524#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 344518#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 343824#L684-15 assume !(1 == ~t2_pc~0); 343825#L694-15 is_transmit2_triggered_~__retres1~2#1 := 0; 343653#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 343654#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 344310#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 344311#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 344307#L703-15 assume !(1 == ~t3_pc~0); 344183#L713-15 is_transmit3_triggered_~__retres1~3#1 := 0; 344068#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 343459#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 343460#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 344397#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 344398#L722-15 assume !(1 == ~t4_pc~0); 343876#L732-15 is_transmit4_triggered_~__retres1~4#1 := 0; 343877#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 344510#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 343713#L1698-15 assume !(0 != activate_threads_~tmp___3~0#1); 343714#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 344601#L741-15 assume 1 == ~t5_pc~0; 343198#L742-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 343199#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 343505#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 343951#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 343034#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 343035#L760-15 assume 1 == ~t6_pc~0; 343972#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 343973#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 343525#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 343526#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 343050#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 343051#L779-15 assume 1 == ~t7_pc~0; 344067#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 342777#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 342905#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 342906#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 344688#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 343247#L798-15 assume 1 == ~t8_pc~0; 343248#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 343737#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 344697#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 344382#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 344296#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 343530#L817-15 assume 1 == ~t9_pc~0; 343531#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 342765#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 344006#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 344007#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 344579#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 344580#L836-15 assume 1 == ~t10_pc~0; 343890#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 342866#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 342867#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 343527#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 344493#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 343454#L855-15 assume 1 == ~t11_pc~0; 343455#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 343480#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 344357#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 344002#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 344003#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 342493#L874-15 assume 1 == ~t12_pc~0; 342494#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 344352#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 343795#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 343796#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 343341#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 342516#L893-15 assume 1 == ~t13_pc~0; 342517#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 343103#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 343898#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 343899#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 343919#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 343239#L912-15 assume 1 == ~t14_pc~0; 343240#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 344066#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 344561#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 344562#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 343962#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 343250#L1495-1 assume !(1 == ~M_E~0); 343251#L1500-1 assume !(1 == ~T1_E~0); 343761#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 343762#L1510-1 assume !(1 == ~T3_E~0); 343816#L1515-1 assume !(1 == ~T4_E~0); 343817#L1520-1 assume !(1 == ~T5_E~0); 344469#L1525-1 assume !(1 == ~T6_E~0); 344134#L1530-1 assume !(1 == ~T7_E~0); 342992#L1535-1 assume !(1 == ~T8_E~0); 342993#L1540-1 assume !(1 == ~T9_E~0); 342514#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 342515#L1550-1 assume !(1 == ~T11_E~0); 342707#L1555-1 assume !(1 == ~T12_E~0); 342708#L1560-1 assume !(1 == ~T13_E~0); 343045#L1565-1 assume !(1 == ~T14_E~0); 344645#L1570-1 assume !(1 == ~E_1~0); 343998#L1575-1 assume !(1 == ~E_2~0); 343364#L1580-1 assume !(1 == ~E_3~0); 343365#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 343835#L1590-1 assume !(1 == ~E_5~0); 343407#L1595-1 assume !(1 == ~E_6~0); 343408#L1600-1 assume !(1 == ~E_7~0); 343768#L1605-1 assume !(1 == ~E_8~0); 343769#L1610-1 assume !(1 == ~E_9~0); 344333#L1615-1 assume !(1 == ~E_10~0); 343189#L1620-1 assume !(1 == ~E_11~0); 343190#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 344032#L1630-1 assume !(1 == ~E_13~0); 343406#L1635-1 assume !(1 == ~E_14~0); 342584#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 342585#L2017 [2024-11-17 08:54:12,729 INFO L747 eck$LassoCheckResult]: Loop: 342585#L2017 assume true; 350496#L2017-1 assume !false; 350468#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 350464#L1110 assume true; 350461#L1110-1 assume !false; 350459#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 350443#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 350433#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 350431#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 350408#L1115 assume !(0 != eval_~tmp~0#1); 350409#L1118 assume true; 350860#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 350859#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 350858#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 350857#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 350856#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 350855#L1357 assume !(0 == ~T3_E~0); 350854#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 350853#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 350851#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 350849#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 350847#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 350845#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 350843#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 350841#L1397 assume !(0 == ~T11_E~0); 350839#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 350837#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 350835#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 350833#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 350831#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 350829#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 350827#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 350825#L1437 assume !(0 == ~E_5~0); 350823#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 350821#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 350819#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 350817#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 350815#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 350813#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 350811#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 350809#L1477 assume !(0 == ~E_13~0); 350807#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 350805#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 350803#L646-1 assume !(1 == ~m_pc~0); 350801#L656-1 is_master_triggered_~__retres1~0#1 := 0; 350799#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 350797#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 350795#L1666-1 assume !(0 != activate_threads_~tmp~1#1); 350793#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 350791#L665-1 assume !(1 == ~t1_pc~0); 350788#L675-1 is_transmit1_triggered_~__retres1~1#1 := 0; 350786#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 350784#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 350782#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 350780#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 350778#L684-1 assume !(1 == ~t2_pc~0); 350777#L694-1 is_transmit2_triggered_~__retres1~2#1 := 0; 350774#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 350772#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 350770#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 350768#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 350766#L703-1 assume !(1 == ~t3_pc~0); 350764#L713-1 is_transmit3_triggered_~__retres1~3#1 := 0; 350761#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 350759#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 350757#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 350755#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 350753#L722-1 assume !(1 == ~t4_pc~0); 350751#L732-1 is_transmit4_triggered_~__retres1~4#1 := 0; 350748#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 350746#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 350744#L1698-1 assume !(0 != activate_threads_~tmp___3~0#1); 350742#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 350740#L741-1 assume !(1 == ~t5_pc~0); 350737#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 350734#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 350732#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 350730#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 350728#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 350726#L760-1 assume 1 == ~t6_pc~0; 350724#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 350720#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 350718#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 350716#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 350714#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 350712#L779-1 assume !(1 == ~t7_pc~0); 350709#L789-1 is_transmit7_triggered_~__retres1~7#1 := 0; 350706#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 350704#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 350702#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 350700#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 350698#L798-1 assume !(1 == ~t8_pc~0); 350695#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 350692#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 350690#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 350688#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 350686#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 350684#L817-1 assume !(1 == ~t9_pc~0); 350681#L827-1 is_transmit9_triggered_~__retres1~9#1 := 0; 350678#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 350676#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 350674#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 350672#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 350670#L836-1 assume 1 == ~t10_pc~0; 350668#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 350664#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 350662#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 350660#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 350658#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 350656#L855-1 assume !(1 == ~t11_pc~0); 350653#L865-1 is_transmit11_triggered_~__retres1~11#1 := 0; 350651#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 350649#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 350647#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 350645#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 350643#L874-1 assume 1 == ~t12_pc~0; 350641#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 350638#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 350636#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 350634#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 350632#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 350630#L893-1 assume 1 == ~t13_pc~0; 350628#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 350625#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 350623#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 350621#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 350619#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 350617#L912-1 assume 1 == ~t14_pc~0; 350615#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 350612#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 350610#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 350608#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 350606#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 350604#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 350602#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 350600#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 350598#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 350596#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 350594#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 350593#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 350592#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 350591#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 350590#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 350589#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 350588#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 350587#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 350586#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 350585#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 350584#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 350583#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 350582#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 350581#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 350580#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 350579#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 350578#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 350576#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 350574#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 350572#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 350570#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 350568#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 350566#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 350564#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 350561#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 350557#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 350542#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 350540#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 350537#L2036 assume !(0 == start_simulation_~tmp~3#1); 350534#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 350522#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 350511#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 350509#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 350507#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 350505#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 350501#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 350499#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 342585#L2017 [2024-11-17 08:54:12,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:12,730 INFO L85 PathProgramCache]: Analyzing trace with hash -638044340, now seen corresponding path program 1 times [2024-11-17 08:54:12,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:12,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351348263] [2024-11-17 08:54:12,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:12,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:12,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:12,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:12,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:12,801 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351348263] [2024-11-17 08:54:12,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [351348263] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:12,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:12,802 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:12,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1472422736] [2024-11-17 08:54:12,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:12,802 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:12,803 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:12,803 INFO L85 PathProgramCache]: Analyzing trace with hash 1365719686, now seen corresponding path program 1 times [2024-11-17 08:54:12,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:12,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4433741] [2024-11-17 08:54:12,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:12,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:12,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:12,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:12,884 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:12,884 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [4433741] [2024-11-17 08:54:12,884 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [4433741] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:12,884 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:12,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:12,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917242471] [2024-11-17 08:54:12,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:12,885 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:12,886 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:12,886 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:12,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:12,887 INFO L87 Difference]: Start difference. First operand 53172 states and 75087 transitions. cyclomatic complexity: 21947 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:13,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:13,536 INFO L93 Difference]: Finished difference Result 102291 states and 144012 transitions. [2024-11-17 08:54:13,536 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102291 states and 144012 transitions. [2024-11-17 08:54:14,194 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 101696 [2024-11-17 08:54:14,465 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102291 states to 102291 states and 144012 transitions. [2024-11-17 08:54:14,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102291 [2024-11-17 08:54:14,526 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102291 [2024-11-17 08:54:14,526 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102291 states and 144012 transitions. [2024-11-17 08:54:14,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:14,580 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102291 states and 144012 transitions. [2024-11-17 08:54:14,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102291 states and 144012 transitions. [2024-11-17 08:54:15,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102291 to 102163. [2024-11-17 08:54:15,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102163 states, 102163 states have (on average 1.4083768096081752) internal successors, (143884), 102162 states have internal predecessors, (143884), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:15,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102163 states to 102163 states and 143884 transitions. [2024-11-17 08:54:15,915 INFO L240 hiAutomatonCegarLoop]: Abstraction has 102163 states and 143884 transitions. [2024-11-17 08:54:15,915 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:15,916 INFO L425 stractBuchiCegarLoop]: Abstraction has 102163 states and 143884 transitions. [2024-11-17 08:54:15,916 INFO L332 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2024-11-17 08:54:15,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102163 states and 143884 transitions. [2024-11-17 08:54:16,221 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 101568 [2024-11-17 08:54:16,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:16,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:16,223 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:16,223 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:16,224 INFO L745 eck$LassoCheckResult]: Stem: 498918#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 498919#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 499554#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 498937#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 498938#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 499136#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 498299#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 498300#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 499254#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 499255#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 498243#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 498244#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 500100#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 500087#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 498764#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 498765#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 499583#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 499588#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 499747#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 498702#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 498703#L1342-1 assume !(0 == ~M_E~0); 499289#L1347-1 assume !(0 == ~T1_E~0); 499911#L1352-1 assume !(0 == ~T2_E~0); 499662#L1357-1 assume !(0 == ~T3_E~0); 498829#L1362-1 assume !(0 == ~T4_E~0); 498830#L1367-1 assume !(0 == ~T5_E~0); 498383#L1372-1 assume !(0 == ~T6_E~0); 498384#L1377-1 assume !(0 == ~T7_E~0); 498745#L1382-1 assume !(0 == ~T8_E~0); 498746#L1387-1 assume !(0 == ~T9_E~0); 499526#L1392-1 assume !(0 == ~T10_E~0); 498783#L1397-1 assume !(0 == ~T11_E~0); 498784#L1402-1 assume !(0 == ~T12_E~0); 498392#L1407-1 assume !(0 == ~T13_E~0); 498393#L1412-1 assume !(0 == ~T14_E~0); 499798#L1417-1 assume !(0 == ~E_1~0); 499799#L1422-1 assume !(0 == ~E_2~0); 500168#L1427-1 assume !(0 == ~E_3~0); 498598#L1432-1 assume !(0 == ~E_4~0); 498599#L1437-1 assume !(0 == ~E_5~0); 499719#L1442-1 assume !(0 == ~E_6~0); 499720#L1447-1 assume !(0 == ~E_7~0); 499517#L1452-1 assume !(0 == ~E_8~0); 498145#L1457-1 assume !(0 == ~E_9~0); 498146#L1462-1 assume !(0 == ~E_10~0); 499755#L1467-1 assume !(0 == ~E_11~0); 499772#L1472-1 assume !(0 == ~E_12~0); 499773#L1477-1 assume !(0 == ~E_13~0); 499472#L1482-1 assume !(0 == ~E_14~0); 498534#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 498535#L646-15 assume !(1 == ~m_pc~0); 499427#L656-15 is_master_triggered_~__retres1~0#1 := 0; 498841#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 498842#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 499260#L1666-15 assume !(0 != activate_threads_~tmp~1#1); 498264#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 498265#L665-15 assume !(1 == ~t1_pc~0); 498899#L675-15 is_transmit1_triggered_~__retres1~1#1 := 0; 498900#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 498943#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 500041#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 500036#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 499305#L684-15 assume !(1 == ~t2_pc~0); 499306#L694-15 is_transmit2_triggered_~__retres1~2#1 := 0; 499130#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 499131#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 499820#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 499821#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 499817#L703-15 assume !(1 == ~t3_pc~0); 499680#L713-15 is_transmit3_triggered_~__retres1~3#1 := 0; 499551#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 498932#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 498933#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 499915#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 499916#L722-15 assume !(1 == ~t4_pc~0); 499358#L732-15 is_transmit4_triggered_~__retres1~4#1 := 0; 499359#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 500030#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 499192#L1698-15 assume !(0 != activate_threads_~tmp___3~0#1); 499193#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 500135#L741-15 assume !(1 == ~t5_pc~0); 500221#L751-15 is_transmit5_triggered_~__retres1~5#1 := 0; 498978#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 498979#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 499439#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 498503#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 498504#L760-15 assume 1 == ~t6_pc~0; 499460#L761-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 499461#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 498998#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 498999#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 498522#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 498523#L779-15 assume 1 == ~t7_pc~0; 499550#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 498250#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 498376#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 498377#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 500224#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 498717#L798-15 assume 1 == ~t8_pc~0; 498718#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 499219#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 500231#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 499896#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 499804#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 499003#L817-15 assume 1 == ~t9_pc~0; 499004#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 498238#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 499494#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 499495#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 500107#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 500108#L836-15 assume 1 == ~t10_pc~0; 499371#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 498337#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 498338#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 499000#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 500012#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 498927#L855-15 assume 1 == ~t11_pc~0; 498928#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 498953#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 499870#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 499490#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 499491#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 497965#L874-15 assume 1 == ~t12_pc~0; 497966#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 499864#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 499278#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 499279#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 498811#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 497988#L893-15 assume 1 == ~t13_pc~0; 497989#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 498576#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 499382#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 499383#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 499403#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 498709#L912-15 assume 1 == ~t14_pc~0; 498710#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 499549#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 500088#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 500089#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 499450#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 498720#L1495-1 assume !(1 == ~M_E~0); 498721#L1500-1 assume !(1 == ~T1_E~0); 499244#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 499245#L1510-1 assume !(1 == ~T3_E~0); 499297#L1515-1 assume !(1 == ~T4_E~0); 499298#L1520-1 assume !(1 == ~T5_E~0); 499989#L1525-1 assume !(1 == ~T6_E~0); 499626#L1530-1 assume !(1 == ~T7_E~0); 498462#L1535-1 assume !(1 == ~T8_E~0); 498463#L1540-1 assume !(1 == ~T9_E~0); 497986#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 497987#L1550-1 assume !(1 == ~T11_E~0); 498180#L1555-1 assume !(1 == ~T12_E~0); 498181#L1560-1 assume !(1 == ~T13_E~0); 498517#L1565-1 assume !(1 == ~T14_E~0); 500182#L1570-1 assume !(1 == ~E_1~0); 499486#L1575-1 assume !(1 == ~E_2~0); 498834#L1580-1 assume !(1 == ~E_3~0); 498835#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 499316#L1590-1 assume !(1 == ~E_5~0); 498878#L1595-1 assume !(1 == ~E_6~0); 498879#L1600-1 assume !(1 == ~E_7~0); 499251#L1605-1 assume !(1 == ~E_8~0); 499252#L1610-1 assume !(1 == ~E_9~0); 499845#L1615-1 assume !(1 == ~E_10~0); 498661#L1620-1 assume !(1 == ~E_11~0); 498662#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 499518#L1630-1 assume !(1 == ~E_13~0); 498877#L1635-1 assume !(1 == ~E_14~0); 498056#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 498057#L2017 [2024-11-17 08:54:16,225 INFO L747 eck$LassoCheckResult]: Loop: 498057#L2017 assume true; 516112#L2017-1 assume !false; 516085#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 516080#L1110 assume true; 516078#L1110-1 assume !false; 516076#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 516060#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 516049#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 516047#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 516044#L1115 assume !(0 != eval_~tmp~0#1); 516045#L1118 assume true; 516476#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 516474#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 516472#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 516469#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 516467#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 516465#L1357 assume !(0 == ~T3_E~0); 516463#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 516461#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 516459#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 516456#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 516454#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 516452#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 516450#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 516448#L1397 assume !(0 == ~T11_E~0); 516446#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 516443#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 516441#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 516439#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 516437#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 516435#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 516433#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 516430#L1437 assume !(0 == ~E_5~0); 516428#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 516426#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 516424#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 516422#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 516420#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 516417#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 516415#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 516413#L1477 assume !(0 == ~E_13~0); 516411#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 516409#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 516407#L646-1 assume !(1 == ~m_pc~0); 516404#L656-1 is_master_triggered_~__retres1~0#1 := 0; 516402#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 516400#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 516398#L1666-1 assume !(0 != activate_threads_~tmp~1#1); 516396#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 516394#L665-1 assume !(1 == ~t1_pc~0); 516391#L675-1 is_transmit1_triggered_~__retres1~1#1 := 0; 516389#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 516387#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 516385#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 516383#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 516381#L684-1 assume !(1 == ~t2_pc~0); 516378#L694-1 is_transmit2_triggered_~__retres1~2#1 := 0; 516376#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 516374#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 516372#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 516370#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 516368#L703-1 assume !(1 == ~t3_pc~0); 516366#L713-1 is_transmit3_triggered_~__retres1~3#1 := 0; 516364#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 516362#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 516360#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 516358#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 516356#L722-1 assume !(1 == ~t4_pc~0); 516354#L732-1 is_transmit4_triggered_~__retres1~4#1 := 0; 516352#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 516350#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 516348#L1698-1 assume !(0 != activate_threads_~tmp___3~0#1); 516346#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 516344#L741-1 assume !(1 == ~t5_pc~0); 516342#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 516340#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 516338#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 516336#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 516334#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 516332#L760-1 assume 1 == ~t6_pc~0; 516330#L761-1 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 516327#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 516325#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 516323#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 516321#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 516319#L779-1 assume 1 == ~t7_pc~0; 516317#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 516314#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 516312#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 516310#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 516309#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 516308#L798-1 assume 1 == ~t8_pc~0; 516307#L799-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 516305#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 516304#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 516303#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 516302#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 516301#L817-1 assume 1 == ~t9_pc~0; 516300#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 516298#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 516297#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 516296#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 516295#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 516294#L836-1 assume 1 == ~t10_pc~0; 516293#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 516291#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 516290#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 516289#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 516288#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 516287#L855-1 assume 1 == ~t11_pc~0; 516286#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 516284#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 516283#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 516282#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 516281#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 516280#L874-1 assume 1 == ~t12_pc~0; 516279#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 516276#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 516274#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 516272#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 516270#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 516268#L893-1 assume 1 == ~t13_pc~0; 516266#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 516263#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 516261#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 516259#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 516256#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 516254#L912-1 assume 1 == ~t14_pc~0; 516252#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 516249#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 516247#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 516245#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 516243#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516241#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 516239#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 516237#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 516235#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 516233#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 516230#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 516228#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 516226#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 516224#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 516222#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 516220#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 516218#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 516216#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 516214#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 516212#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 516210#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 516208#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 516205#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 516203#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 516201#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 516199#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 516197#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 516195#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 516192#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 516190#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 516188#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 516186#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 516184#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 516182#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 516179#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 516175#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 516160#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 516158#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 516155#L2036 assume !(0 == start_simulation_~tmp~3#1); 516151#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 516137#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 516126#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 516124#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 516122#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 516120#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 516117#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 516115#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 498057#L2017 [2024-11-17 08:54:16,225 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:16,226 INFO L85 PathProgramCache]: Analyzing trace with hash 1071220841, now seen corresponding path program 1 times [2024-11-17 08:54:16,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:16,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556341195] [2024-11-17 08:54:16,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:16,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:16,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:16,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:16,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:16,319 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [556341195] [2024-11-17 08:54:16,319 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [556341195] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:16,319 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:16,319 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:16,319 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [77598393] [2024-11-17 08:54:16,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:16,320 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:16,320 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:16,320 INFO L85 PathProgramCache]: Analyzing trace with hash 208228818, now seen corresponding path program 1 times [2024-11-17 08:54:16,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:16,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17976774] [2024-11-17 08:54:16,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:16,322 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:16,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:16,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:16,405 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:16,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17976774] [2024-11-17 08:54:16,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17976774] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:16,405 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:16,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:16,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006699374] [2024-11-17 08:54:16,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:16,406 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:16,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:16,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:16,407 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:16,408 INFO L87 Difference]: Start difference. First operand 102163 states and 143884 transitions. cyclomatic complexity: 41785 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:17,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:17,517 INFO L93 Difference]: Finished difference Result 196402 states and 275785 transitions. [2024-11-17 08:54:17,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196402 states and 275785 transitions. [2024-11-17 08:54:18,853 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 195328 [2024-11-17 08:54:19,234 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196402 states to 196402 states and 275785 transitions. [2024-11-17 08:54:19,234 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 196402 [2024-11-17 08:54:19,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 196402 [2024-11-17 08:54:19,328 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196402 states and 275785 transitions. [2024-11-17 08:54:19,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:19,424 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196402 states and 275785 transitions. [2024-11-17 08:54:19,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196402 states and 275785 transitions. [2024-11-17 08:54:21,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196402 to 196146. [2024-11-17 08:54:21,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196146 states, 196146 states have (on average 1.404713835612248) internal successors, (275529), 196145 states have internal predecessors, (275529), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:22,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196146 states to 196146 states and 275529 transitions. [2024-11-17 08:54:22,098 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196146 states and 275529 transitions. [2024-11-17 08:54:22,099 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-17 08:54:22,099 INFO L425 stractBuchiCegarLoop]: Abstraction has 196146 states and 275529 transitions. [2024-11-17 08:54:22,099 INFO L332 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2024-11-17 08:54:22,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196146 states and 275529 transitions. [2024-11-17 08:54:23,471 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 195072 [2024-11-17 08:54:23,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:23,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:23,477 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:23,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:23,477 INFO L745 eck$LassoCheckResult]: Stem: 797496#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 797497#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 798144#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 797515#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 797516#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 797717#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 796876#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 796877#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 797832#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 797833#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 796819#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 796820#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 798698#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 798688#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 797341#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 797342#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 798172#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 798176#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 798335#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 797277#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 797278#L1342-1 assume !(0 == ~M_E~0); 797871#L1347-1 assume !(0 == ~T1_E~0); 798503#L1352-1 assume !(0 == ~T2_E~0); 798254#L1357-1 assume !(0 == ~T3_E~0); 797407#L1362-1 assume !(0 == ~T4_E~0); 797408#L1367-1 assume !(0 == ~T5_E~0); 796959#L1372-1 assume !(0 == ~T6_E~0); 796960#L1377-1 assume !(0 == ~T7_E~0); 797321#L1382-1 assume !(0 == ~T8_E~0); 797322#L1387-1 assume !(0 == ~T9_E~0); 798117#L1392-1 assume !(0 == ~T10_E~0); 797359#L1397-1 assume !(0 == ~T11_E~0); 797360#L1402-1 assume !(0 == ~T12_E~0); 796967#L1407-1 assume !(0 == ~T13_E~0); 796968#L1412-1 assume !(0 == ~T14_E~0); 798387#L1417-1 assume !(0 == ~E_1~0); 798388#L1422-1 assume !(0 == ~E_2~0); 798772#L1427-1 assume !(0 == ~E_3~0); 797174#L1432-1 assume !(0 == ~E_4~0); 797175#L1437-1 assume !(0 == ~E_5~0); 798309#L1442-1 assume !(0 == ~E_6~0); 798310#L1447-1 assume !(0 == ~E_7~0); 798108#L1452-1 assume !(0 == ~E_8~0); 796718#L1457-1 assume !(0 == ~E_9~0); 796719#L1462-1 assume !(0 == ~E_10~0); 798343#L1467-1 assume !(0 == ~E_11~0); 798361#L1472-1 assume !(0 == ~E_12~0); 798362#L1477-1 assume !(0 == ~E_13~0); 798058#L1482-1 assume !(0 == ~E_14~0); 797107#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 797108#L646-15 assume !(1 == ~m_pc~0); 798012#L656-15 is_master_triggered_~__retres1~0#1 := 0; 797420#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 797421#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 797838#L1666-15 assume !(0 != activate_threads_~tmp~1#1); 796840#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 796841#L665-15 assume !(1 == ~t1_pc~0); 797478#L675-15 is_transmit1_triggered_~__retres1~1#1 := 0; 797479#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 797521#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 798640#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 798633#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 797886#L684-15 assume !(1 == ~t2_pc~0); 797887#L694-15 is_transmit2_triggered_~__retres1~2#1 := 0; 797711#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 797712#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 798410#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 798411#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 798406#L703-15 assume !(1 == ~t3_pc~0); 798275#L713-15 is_transmit3_triggered_~__retres1~3#1 := 0; 798141#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 797510#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 797511#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 798507#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 798508#L722-15 assume !(1 == ~t4_pc~0); 797942#L732-15 is_transmit4_triggered_~__retres1~4#1 := 0; 797943#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 798622#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 797770#L1698-15 assume !(0 != activate_threads_~tmp___3~0#1); 797771#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 798734#L741-15 assume !(1 == ~t5_pc~0); 798852#L751-15 is_transmit5_triggered_~__retres1~5#1 := 0; 797556#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 797557#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 798024#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 797080#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 797081#L760-15 assume !(1 == ~t6_pc~0); 798260#L770-15 is_transmit6_triggered_~__retres1~6#1 := 0; 798233#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 797577#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 797578#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 797096#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 797097#L779-15 assume 1 == ~t7_pc~0; 798140#L780-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 796826#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 796955#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 796956#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 798855#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 797293#L798-15 assume 1 == ~t8_pc~0; 797294#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 797795#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 798866#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 798487#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 798394#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 797582#L817-15 assume 1 == ~t9_pc~0; 797583#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 796814#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 798084#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 798085#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 798706#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 798707#L836-15 assume 1 == ~t10_pc~0; 797957#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 796913#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 796914#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 797579#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 798602#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 797505#L855-15 assume 1 == ~t11_pc~0; 797506#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 797530#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 798457#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 798080#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 798081#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 796539#L874-15 assume 1 == ~t12_pc~0; 796540#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 798452#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 797858#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 797859#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 797388#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 796562#L893-15 assume 1 == ~t13_pc~0; 796563#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 797151#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 797965#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 797966#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 797987#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 797286#L912-15 assume 1 == ~t14_pc~0; 797287#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 798139#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 798689#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 798690#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 798036#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 797296#L1495-1 assume !(1 == ~M_E~0); 797297#L1500-1 assume !(1 == ~T1_E~0); 797821#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 797822#L1510-1 assume !(1 == ~T3_E~0); 797878#L1515-1 assume !(1 == ~T4_E~0); 797879#L1520-1 assume !(1 == ~T5_E~0); 798579#L1525-1 assume !(1 == ~T6_E~0); 798210#L1530-1 assume !(1 == ~T7_E~0); 797037#L1535-1 assume !(1 == ~T8_E~0); 797038#L1540-1 assume !(1 == ~T9_E~0); 796560#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 796561#L1550-1 assume !(1 == ~T11_E~0); 796756#L1555-1 assume !(1 == ~T12_E~0); 796757#L1560-1 assume !(1 == ~T13_E~0); 797091#L1565-1 assume !(1 == ~T14_E~0); 798788#L1570-1 assume !(1 == ~E_1~0); 798076#L1575-1 assume !(1 == ~E_2~0); 797413#L1580-1 assume !(1 == ~E_3~0); 797414#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 797897#L1590-1 assume !(1 == ~E_5~0); 797456#L1595-1 assume !(1 == ~E_6~0); 797457#L1600-1 assume !(1 == ~E_7~0); 797829#L1605-1 assume !(1 == ~E_8~0); 797830#L1610-1 assume !(1 == ~E_9~0); 798432#L1615-1 assume !(1 == ~E_10~0); 797236#L1620-1 assume !(1 == ~E_11~0); 797237#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 798109#L1630-1 assume !(1 == ~E_13~0); 797455#L1635-1 assume !(1 == ~E_14~0); 796630#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 796631#L2017 [2024-11-17 08:54:23,478 INFO L747 eck$LassoCheckResult]: Loop: 796631#L2017 assume true; 898998#L2017-1 assume !false; 898969#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 898965#L1110 assume true; 898963#L1110-1 assume !false; 898961#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 898939#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 898929#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 898928#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 898925#L1115 assume !(0 != eval_~tmp~0#1); 898926#L1118 assume true; 991924#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 991923#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 991922#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 991921#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 991920#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 991919#L1357 assume !(0 == ~T3_E~0); 991918#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 991917#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 991916#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 991915#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 991913#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 991910#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 991909#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 991908#L1397 assume !(0 == ~T11_E~0); 991906#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 991903#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 991901#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 991899#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 991896#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 991894#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 991892#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 991889#L1437 assume !(0 == ~E_5~0); 991887#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 991885#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 991883#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 991881#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 991879#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 991876#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 991874#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 991872#L1477 assume !(0 == ~E_13~0); 991870#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 991868#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 991866#L646-1 assume !(1 == ~m_pc~0); 991863#L656-1 is_master_triggered_~__retres1~0#1 := 0; 991861#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 991859#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 991856#L1666-1 assume !(0 != activate_threads_~tmp~1#1); 991854#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 991852#L665-1 assume !(1 == ~t1_pc~0); 991849#L675-1 is_transmit1_triggered_~__retres1~1#1 := 0; 991846#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 991842#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 991839#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 991837#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 991835#L684-1 assume !(1 == ~t2_pc~0); 991832#L694-1 is_transmit2_triggered_~__retres1~2#1 := 0; 991830#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 991828#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 991826#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 991824#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 991822#L703-1 assume !(1 == ~t3_pc~0); 991819#L713-1 is_transmit3_triggered_~__retres1~3#1 := 0; 991817#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 991815#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 991813#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 991811#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 991809#L722-1 assume !(1 == ~t4_pc~0); 991806#L732-1 is_transmit4_triggered_~__retres1~4#1 := 0; 991804#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 991802#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 991800#L1698-1 assume !(0 != activate_threads_~tmp___3~0#1); 991798#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 991796#L741-1 assume !(1 == ~t5_pc~0); 991793#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 991791#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 991789#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 991787#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 991785#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 991783#L760-1 assume !(1 == ~t6_pc~0); 991780#L770-1 is_transmit6_triggered_~__retres1~6#1 := 0; 991778#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 991776#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 991774#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 991772#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 991770#L779-1 assume 1 == ~t7_pc~0; 991767#L780-1 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 991764#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 991762#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 991760#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 991758#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 991756#L798-1 assume 1 == ~t8_pc~0; 991753#L799-1 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 991750#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 991748#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 991745#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 991742#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 991740#L817-1 assume 1 == ~t9_pc~0; 991737#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 991734#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 990783#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 990782#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 990781#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 990780#L836-1 assume 1 == ~t10_pc~0; 990778#L837-1 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 990775#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 990773#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 990069#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 987974#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 899203#L855-1 assume 1 == ~t11_pc~0; 899199#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 899197#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 899181#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 899179#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 899177#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 899173#L874-1 assume 1 == ~t12_pc~0; 899171#L875-1 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 899169#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 899168#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 899167#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 899166#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 899165#L893-1 assume 1 == ~t13_pc~0; 899164#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 899147#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 899145#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 899143#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 899141#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 899139#L912-1 assume 1 == ~t14_pc~0; 899137#L913-1 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 899134#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 899132#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 899130#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 899129#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 899128#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 899127#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 899126#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 899124#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 899121#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 899119#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 899117#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 899115#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 899113#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 899110#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 899105#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 899103#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 899101#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 899099#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 899096#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 899094#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 899092#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 899090#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 899088#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 899086#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 899084#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 899082#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 899080#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 899078#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 899076#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 899074#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 899072#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 899070#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 899068#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 899065#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 899061#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 899046#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 899044#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 899041#L2036 assume !(0 == start_simulation_~tmp~3#1); 899037#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 899023#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 899012#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 899010#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 899008#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 899006#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 899003#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 899001#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 796631#L2017 [2024-11-17 08:54:23,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:23,479 INFO L85 PathProgramCache]: Analyzing trace with hash 954282822, now seen corresponding path program 1 times [2024-11-17 08:54:23,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:23,479 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711831768] [2024-11-17 08:54:23,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:23,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:23,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:23,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:23,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:23,587 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711831768] [2024-11-17 08:54:23,587 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [711831768] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:23,587 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:23,587 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-17 08:54:23,588 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249465393] [2024-11-17 08:54:23,588 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:23,590 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:23,590 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:23,591 INFO L85 PathProgramCache]: Analyzing trace with hash -1671522001, now seen corresponding path program 1 times [2024-11-17 08:54:23,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:23,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892329156] [2024-11-17 08:54:23,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:23,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:23,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:23,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:23,655 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:23,656 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892329156] [2024-11-17 08:54:23,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [892329156] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:23,656 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:23,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:23,656 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1540635382] [2024-11-17 08:54:23,656 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:23,657 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:23,657 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:23,658 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-17 08:54:23,658 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-17 08:54:23,658 INFO L87 Difference]: Start difference. First operand 196146 states and 275529 transitions. cyclomatic complexity: 79511 Second operand has 4 states, 4 states have (on average 42.5) internal successors, (170), 3 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:26,199 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:26,199 INFO L93 Difference]: Finished difference Result 470481 states and 658438 transitions. [2024-11-17 08:54:26,199 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 470481 states and 658438 transitions. [2024-11-17 08:54:28,801 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 467392 [2024-11-17 08:54:30,541 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 470481 states to 470481 states and 658438 transitions. [2024-11-17 08:54:30,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 470481 [2024-11-17 08:54:30,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 470481 [2024-11-17 08:54:30,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 470481 states and 658438 transitions. [2024-11-17 08:54:31,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-17 08:54:31,060 INFO L218 hiAutomatonCegarLoop]: Abstraction has 470481 states and 658438 transitions. [2024-11-17 08:54:31,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 470481 states and 658438 transitions. [2024-11-17 08:54:35,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 470481 to 376369. [2024-11-17 08:54:35,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 376369 states, 376369 states have (on average 1.401534132726128) internal successors, (527494), 376368 states have internal predecessors, (527494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:36,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 376369 states to 376369 states and 527494 transitions. [2024-11-17 08:54:36,614 INFO L240 hiAutomatonCegarLoop]: Abstraction has 376369 states and 527494 transitions. [2024-11-17 08:54:36,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-17 08:54:36,615 INFO L425 stractBuchiCegarLoop]: Abstraction has 376369 states and 527494 transitions. [2024-11-17 08:54:36,615 INFO L332 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2024-11-17 08:54:36,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 376369 states and 527494 transitions. [2024-11-17 08:54:38,513 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 374400 [2024-11-17 08:54:38,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-17 08:54:38,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-17 08:54:38,516 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:38,516 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-17 08:54:38,517 INFO L745 eck$LassoCheckResult]: Stem: 1464129#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~t14_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~t14_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~t14_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~T14_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~E_14~0 := 2; 1464130#ULTIMATE.init_returnLabel#1 assume true;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~16#1;havoc main_~__retres1~16#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1;~t14_i~0 := 1; 1464781#L1980 assume true;assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret36#1, start_simulation_#t~ret37#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1464151#L932-1 assume true;assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1464152#L939 assume 1 == ~m_i~0;~m_st~0 := 0; 1464353#L944 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1463514#L949 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1463515#L954 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1464466#L959 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1464467#L964 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1463456#L969 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1463457#L974 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1465348#L979 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1465337#L984 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1463974#L989 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1463975#L994 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1464803#L999 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1464808#L1004 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1464964#L1009 assume 1 == ~t14_i~0;~t14_st~0 := 0; 1463912#L1015 assume true;assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1463913#L1342-1 assume !(0 == ~M_E~0); 1464505#L1347-1 assume !(0 == ~T1_E~0); 1465142#L1352-1 assume !(0 == ~T2_E~0); 1464885#L1357-1 assume !(0 == ~T3_E~0); 1464043#L1362-1 assume !(0 == ~T4_E~0); 1464044#L1367-1 assume !(0 == ~T5_E~0); 1463596#L1372-1 assume !(0 == ~T6_E~0); 1463597#L1377-1 assume !(0 == ~T7_E~0); 1463956#L1382-1 assume !(0 == ~T8_E~0); 1463957#L1387-1 assume !(0 == ~T9_E~0); 1464754#L1392-1 assume !(0 == ~T10_E~0); 1463993#L1397-1 assume !(0 == ~T11_E~0); 1463994#L1402-1 assume !(0 == ~T12_E~0); 1463604#L1407-1 assume !(0 == ~T13_E~0); 1463605#L1412-1 assume !(0 == ~T14_E~0); 1465018#L1417-1 assume !(0 == ~E_1~0); 1465019#L1422-1 assume !(0 == ~E_2~0); 1465421#L1427-1 assume !(0 == ~E_3~0); 1463811#L1432-1 assume !(0 == ~E_4~0); 1463812#L1437-1 assume !(0 == ~E_5~0); 1464939#L1442-1 assume !(0 == ~E_6~0); 1464940#L1447-1 assume !(0 == ~E_7~0); 1464745#L1452-1 assume !(0 == ~E_8~0); 1463356#L1457-1 assume !(0 == ~E_9~0); 1463357#L1462-1 assume !(0 == ~E_10~0); 1464972#L1467-1 assume !(0 == ~E_11~0); 1464989#L1472-1 assume !(0 == ~E_12~0); 1464990#L1477-1 assume !(0 == ~E_13~0); 1464694#L1482-1 assume !(0 == ~E_14~0); 1463748#L1488-1 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1463749#L646-15 assume !(1 == ~m_pc~0); 1464653#L656-15 is_master_triggered_~__retres1~0#1 := 0; 1464056#L649-15 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1464057#L658-15 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1464473#L1666-15 assume !(0 != activate_threads_~tmp~1#1); 1463481#L1672-15 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1463482#L665-15 assume !(1 == ~t1_pc~0); 1464111#L675-15 is_transmit1_triggered_~__retres1~1#1 := 0; 1464112#L668-15 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1464155#L677-15 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1465286#L1674-15 assume !(0 != activate_threads_~tmp___0~0#1); 1465281#L1680-15 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1464520#L684-15 assume !(1 == ~t2_pc~0); 1464521#L694-15 is_transmit2_triggered_~__retres1~2#1 := 0; 1464344#L687-15 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1464345#L696-15 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1465044#L1682-15 assume !(0 != activate_threads_~tmp___1~0#1); 1465045#L1688-15 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1465040#L703-15 assume !(1 == ~t3_pc~0); 1464904#L713-15 is_transmit3_triggered_~__retres1~3#1 := 0; 1464777#L706-15 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1464144#L715-15 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1464145#L1690-15 assume !(0 != activate_threads_~tmp___2~0#1); 1465146#L1696-15 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1465147#L722-15 assume !(1 == ~t4_pc~0); 1464579#L732-15 is_transmit4_triggered_~__retres1~4#1 := 0; 1464580#L725-15 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1465268#L734-15 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1464402#L1698-15 assume !(0 != activate_threads_~tmp___3~0#1); 1464403#L1704-15 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1465386#L741-15 assume !(1 == ~t5_pc~0); 1465497#L751-15 is_transmit5_triggered_~__retres1~5#1 := 0; 1464190#L744-15 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1464191#L753-15 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1464666#L1706-15 assume !(0 != activate_threads_~tmp___4~0#1); 1463716#L1712-15 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1463717#L760-15 assume !(1 == ~t6_pc~0); 1464891#L770-15 is_transmit6_triggered_~__retres1~6#1 := 0; 1464869#L763-15 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1464210#L772-15 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1464211#L1714-15 assume !(0 != activate_threads_~tmp___5~0#1); 1463735#L1720-15 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1463736#L779-15 assume !(1 == ~t7_pc~0); 1463462#L789-15 is_transmit7_triggered_~__retres1~7#1 := 0; 1463463#L782-15 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1463592#L791-15 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1463593#L1722-15 assume !(0 != activate_threads_~tmp___6~0#1); 1465499#L1728-15 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1463927#L798-15 assume 1 == ~t8_pc~0; 1463928#L799-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1464429#L801-15 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1465512#L810-15 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1465127#L1730-15 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1465028#L1736-15 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1464216#L817-15 assume 1 == ~t9_pc~0; 1464217#L818-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1463451#L820-15 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1464718#L829-15 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1464719#L1738-15 assume !(0 != activate_threads_~tmp___8~0#1); 1465355#L1744-15 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1465356#L836-15 assume 1 == ~t10_pc~0; 1464593#L837-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1463552#L839-15 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1463553#L848-15 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1464212#L1746-15 assume !(0 != activate_threads_~tmp___9~0#1); 1465247#L1752-15 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1464139#L855-15 assume 1 == ~t11_pc~0; 1464140#L856-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1464166#L858-15 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1465095#L867-15 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1464713#L1754-15 assume !(0 != activate_threads_~tmp___10~0#1); 1464714#L1760-15 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1463178#L874-15 assume 1 == ~t12_pc~0; 1463179#L875-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1465087#L877-15 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1464493#L886-15 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1464494#L1762-15 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1464026#L1768-15 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1463201#L893-15 assume 1 == ~t13_pc~0; 1463202#L894-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1463791#L896-15 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1464602#L905-15 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1464603#L1770-15 assume !(0 != activate_threads_~tmp___12~0#1); 1464627#L1776-15 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1463924#L912-15 assume 1 == ~t14_pc~0; 1463925#L913-15 assume 1 == ~E_14~0;is_transmit14_triggered_~__retres1~14#1 := 1; 1464776#L915-15 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1465338#L924-15 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1465339#L1778-15 assume !(0 != activate_threads_~tmp___13~0#1); 1464678#L1784-15 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1463931#L1495-1 assume !(1 == ~M_E~0); 1463932#L1500-1 assume !(1 == ~T1_E~0); 1464454#L1505-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1464455#L1510-1 assume !(1 == ~T3_E~0); 1464513#L1515-1 assume !(1 == ~T4_E~0); 1464514#L1520-1 assume !(1 == ~T5_E~0); 1465221#L1525-1 assume !(1 == ~T6_E~0); 1464846#L1530-1 assume !(1 == ~T7_E~0); 1463674#L1535-1 assume !(1 == ~T8_E~0); 1463675#L1540-1 assume !(1 == ~T9_E~0); 1463199#L1545-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1463200#L1550-1 assume !(1 == ~T11_E~0); 1463392#L1555-1 assume !(1 == ~T12_E~0); 1463393#L1560-1 assume !(1 == ~T13_E~0); 1463732#L1565-1 assume !(1 == ~T14_E~0); 1465436#L1570-1 assume !(1 == ~E_1~0); 1464708#L1575-1 assume !(1 == ~E_2~0); 1464051#L1580-1 assume !(1 == ~E_3~0); 1464052#L1585-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1464531#L1590-1 assume !(1 == ~E_5~0); 1464091#L1595-1 assume !(1 == ~E_6~0); 1464092#L1600-1 assume !(1 == ~E_7~0); 1464464#L1605-1 assume !(1 == ~E_8~0); 1464465#L1610-1 assume !(1 == ~E_9~0); 1465067#L1615-1 assume !(1 == ~E_10~0); 1463873#L1620-1 assume !(1 == ~E_11~0); 1463874#L1625-1 assume 1 == ~E_12~0;~E_12~0 := 2; 1464746#L1630-1 assume !(1 == ~E_13~0); 1464090#L1635-1 assume !(1 == ~E_14~0); 1463269#L1641-1 assume true;assume { :end_inline_reset_delta_events } true; 1463270#L2017 [2024-11-17 08:54:38,517 INFO L747 eck$LassoCheckResult]: Loop: 1463270#L2017 assume true; 1705389#L2017-1 assume !false; 1705362#start_simulation_while_16_continue#1 assume true;start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1705358#L1110 assume true; 1705356#L1110-1 assume !false; 1705353#eval_while_15_continue#1 assume true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1705333#L1022-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1705324#L1080-2 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1705321#L1101-2 assume true;eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1705319#L1115 assume !(0 != eval_~tmp~0#1); 1705320#L1118 assume true; 1706318#L1335 assume true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_14~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_15~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1706316#L932 assume true;assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1706312#L1342 assume 0 == ~M_E~0;~M_E~0 := 1; 1706310#L1347 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1706308#L1352 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1706306#L1357 assume !(0 == ~T3_E~0); 1706303#L1362 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1706301#L1367 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1706299#L1372 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1706296#L1377 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1706294#L1382 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1706292#L1387 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1706290#L1392 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1706288#L1397 assume !(0 == ~T11_E~0); 1706286#L1402 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1706284#L1407 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1706282#L1412 assume 0 == ~T14_E~0;~T14_E~0 := 1; 1706280#L1417 assume 0 == ~E_1~0;~E_1~0 := 1; 1706278#L1422 assume 0 == ~E_2~0;~E_2~0 := 1; 1706276#L1427 assume 0 == ~E_3~0;~E_3~0 := 1; 1706274#L1432 assume 0 == ~E_4~0;~E_4~0 := 1; 1706273#L1437 assume !(0 == ~E_5~0); 1706271#L1442 assume 0 == ~E_6~0;~E_6~0 := 1; 1706269#L1447 assume 0 == ~E_7~0;~E_7~0 := 1; 1706267#L1452 assume 0 == ~E_8~0;~E_8~0 := 1; 1706265#L1457 assume 0 == ~E_9~0;~E_9~0 := 1; 1706263#L1462 assume 0 == ~E_10~0;~E_10~0 := 1; 1706260#L1467 assume 0 == ~E_11~0;~E_11~0 := 1; 1706258#L1472 assume 0 == ~E_12~0;~E_12~0 := 1; 1706256#L1477 assume !(0 == ~E_13~0); 1706254#L1482 assume 0 == ~E_14~0;~E_14~0 := 1; 1706252#L1488 assume true;assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp___13~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1706250#L646-1 assume !(1 == ~m_pc~0); 1706247#L656-1 is_master_triggered_~__retres1~0#1 := 0; 1706245#L649-1 assume true;is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1706243#L658-1 assume true;activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1706241#L1666-1 assume !(0 != activate_threads_~tmp~1#1); 1706239#L1672-1 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1706237#L665-1 assume !(1 == ~t1_pc~0); 1706234#L675-1 is_transmit1_triggered_~__retres1~1#1 := 0; 1706232#L668-1 assume true;is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1706230#L677-1 assume true;activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1706228#L1674-1 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1706226#L1680-1 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1706224#L684-1 assume !(1 == ~t2_pc~0); 1706221#L694-1 is_transmit2_triggered_~__retres1~2#1 := 0; 1706219#L687-1 assume true;is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1706217#L696-1 assume true;activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1706215#L1682-1 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1706213#L1688-1 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1706211#L703-1 assume !(1 == ~t3_pc~0); 1706208#L713-1 is_transmit3_triggered_~__retres1~3#1 := 0; 1706206#L706-1 assume true;is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1706204#L715-1 assume true;activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1706202#L1690-1 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1706200#L1696-1 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1706198#L722-1 assume !(1 == ~t4_pc~0); 1705713#L732-1 is_transmit4_triggered_~__retres1~4#1 := 0; 1705712#L725-1 assume true;is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1705709#L734-1 assume true;activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1705706#L1698-1 assume !(0 != activate_threads_~tmp___3~0#1); 1705704#L1704-1 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1705702#L741-1 assume !(1 == ~t5_pc~0); 1705700#L751-1 is_transmit5_triggered_~__retres1~5#1 := 0; 1705698#L744-1 assume true;is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1705695#L753-1 assume true;activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1705691#L1706-1 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1705688#L1712-1 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1705685#L760-1 assume !(1 == ~t6_pc~0); 1705684#L770-1 is_transmit6_triggered_~__retres1~6#1 := 0; 1705642#L763-1 assume true;is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1705638#L772-1 assume true;activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1705637#L1714-1 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1705634#L1720-1 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1705632#L779-1 assume !(1 == ~t7_pc~0); 1486475#L789-1 is_transmit7_triggered_~__retres1~7#1 := 0; 1705627#L782-1 assume true;is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1705626#L791-1 assume true;activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1705623#L1722-1 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1705621#L1728-1 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1705619#L798-1 assume !(1 == ~t8_pc~0); 1705602#L808-1 is_transmit8_triggered_~__retres1~8#1 := 0; 1705600#L801-1 assume true;is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1705598#L810-1 assume true;activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1705595#L1730-1 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1705592#L1736-1 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1705589#L817-1 assume 1 == ~t9_pc~0; 1705586#L818-1 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1705584#L820-1 assume true;is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1705582#L829-1 assume true;activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1705580#L1738-1 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1705578#L1744-1 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1705576#L836-1 assume !(1 == ~t10_pc~0); 1705574#L846-1 is_transmit10_triggered_~__retres1~10#1 := 0; 1705572#L839-1 assume true;is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1705570#L848-1 assume true;activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1705569#L1746-1 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1705568#L1752-1 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1705567#L855-1 assume 1 == ~t11_pc~0; 1705566#L856-1 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1705563#L858-1 assume true;is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1705561#L867-1 assume true;activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1705559#L1754-1 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1705557#L1760-1 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1705554#L874-1 assume !(1 == ~t12_pc~0); 1705551#L884-1 is_transmit12_triggered_~__retres1~12#1 := 0; 1705549#L877-1 assume true;is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1705546#L886-1 assume true;activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1705544#L1762-1 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1705542#L1768-1 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1705540#L893-1 assume 1 == ~t13_pc~0; 1705538#L894-1 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1705535#L896-1 assume true;is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1705533#L905-1 assume true;activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1705531#L1770-1 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1705529#L1776-1 assume { :begin_inline_is_transmit14_triggered } true;havoc is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;havoc is_transmit14_triggered_~__retres1~14#1; 1705526#L912-1 assume !(1 == ~t14_pc~0); 1705523#L922-1 is_transmit14_triggered_~__retres1~14#1 := 0; 1705521#L915-1 assume true;is_transmit14_triggered_#res#1 := is_transmit14_triggered_~__retres1~14#1; 1705519#L924-1 assume true;activate_threads_#t~ret34#1 := is_transmit14_triggered_#res#1;havoc is_transmit14_triggered_~__retres1~14#1;assume { :end_inline_is_transmit14_triggered } true;activate_threads_~tmp___13~0#1 := activate_threads_#t~ret34#1;havoc activate_threads_#t~ret34#1; 1705517#L1778-1 assume 0 != activate_threads_~tmp___13~0#1;~t14_st~0 := 0; 1705515#L1784-1 assume true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_#t~ret34#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1, activate_threads_~tmp___13~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1705513#L1495 assume 1 == ~M_E~0;~M_E~0 := 2; 1705511#L1500 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1705509#L1505 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1705507#L1510 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1705505#L1515 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1705503#L1520 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1705501#L1525 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1705499#L1530 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1705497#L1535 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1705495#L1540 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1705493#L1545 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1705491#L1550 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1705489#L1555 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1705487#L1560 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1705485#L1565 assume 1 == ~T14_E~0;~T14_E~0 := 2; 1705483#L1570 assume 1 == ~E_1~0;~E_1~0 := 2; 1705481#L1575 assume 1 == ~E_2~0;~E_2~0 := 2; 1705479#L1580 assume 1 == ~E_3~0;~E_3~0 := 2; 1705477#L1585 assume 1 == ~E_4~0;~E_4~0 := 2; 1705475#L1590 assume 1 == ~E_5~0;~E_5~0 := 2; 1705473#L1595 assume 1 == ~E_6~0;~E_6~0 := 2; 1705471#L1600 assume 1 == ~E_7~0;~E_7~0 := 2; 1705469#L1605 assume 1 == ~E_8~0;~E_8~0 := 2; 1705467#L1610 assume 1 == ~E_9~0;~E_9~0 := 2; 1705466#L1615 assume 1 == ~E_10~0;~E_10~0 := 2; 1705464#L1620 assume 1 == ~E_11~0;~E_11~0 := 2; 1705462#L1625 assume 1 == ~E_12~0;~E_12~0 := 2; 1705460#L1630 assume 1 == ~E_13~0;~E_13~0 := 2; 1705458#L1635 assume 1 == ~E_14~0;~E_14~0 := 2; 1705456#L1641 assume true;assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1705451#L1022-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1705436#L1080-1 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1705434#L1101-1 assume true;start_simulation_#t~ret36#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1705431#L2036 assume !(0 == start_simulation_~tmp~3#1); 1705428#L2047 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;havoc exists_runnable_thread_~__retres1~15#1; 1705415#L1022 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~15#1 := 1; 1705403#L1080 assume true;exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~15#1; 1705401#L1101 assume true;stop_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~15#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret35#1;havoc stop_simulation_#t~ret35#1; 1705399#L1991 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1705397#L1993 assume true;stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1705395#L1999 assume true;start_simulation_#t~ret37#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret35#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret37#1;havoc start_simulation_#t~ret37#1; 1705393#L2049 assume !(0 != start_simulation_~tmp___0~1#1); 1463270#L2017 [2024-11-17 08:54:38,518 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:38,518 INFO L85 PathProgramCache]: Analyzing trace with hash 1346734051, now seen corresponding path program 1 times [2024-11-17 08:54:38,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:38,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370104232] [2024-11-17 08:54:38,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:38,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:38,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:38,588 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:38,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:38,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370104232] [2024-11-17 08:54:38,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370104232] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:38,589 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:38,589 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-17 08:54:38,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1396729480] [2024-11-17 08:54:38,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:38,589 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-17 08:54:38,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-17 08:54:38,592 INFO L85 PathProgramCache]: Analyzing trace with hash -357995840, now seen corresponding path program 1 times [2024-11-17 08:54:38,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-17 08:54:38,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071997380] [2024-11-17 08:54:38,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-17 08:54:38,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-17 08:54:38,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-17 08:54:38,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-17 08:54:38,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-17 08:54:38,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071997380] [2024-11-17 08:54:38,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2071997380] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-17 08:54:38,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-17 08:54:38,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-17 08:54:38,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1200562526] [2024-11-17 08:54:38,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-17 08:54:38,675 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-17 08:54:38,676 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-17 08:54:38,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-17 08:54:38,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-17 08:54:38,676 INFO L87 Difference]: Start difference. First operand 376369 states and 527494 transitions. cyclomatic complexity: 151253 Second operand has 3 states, 3 states have (on average 56.666666666666664) internal successors, (170), 2 states have internal predecessors, (170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-17 08:54:41,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-17 08:54:41,713 INFO L93 Difference]: Finished difference Result 722352 states and 1009923 transitions. [2024-11-17 08:54:41,713 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 722352 states and 1009923 transitions. [2024-11-17 08:54:46,083 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 718080