./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c7c6ca5d Calling Ultimate with: /root/.sdkman/candidates/java/11.0.12-open/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/token_ring.04.cil-1.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba --- Real Ultimate output --- This is Ultimate 0.2.5-?-c7c6ca5-m [2024-11-09 16:07:34,985 INFO L188 SettingsManager]: Resetting all preferences to default values... [2024-11-09 16:07:35,073 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2024-11-09 16:07:35,078 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2024-11-09 16:07:35,078 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2024-11-09 16:07:35,107 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2024-11-09 16:07:35,108 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2024-11-09 16:07:35,108 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2024-11-09 16:07:35,109 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2024-11-09 16:07:35,109 INFO L153 SettingsManager]: * Use memory slicer=true [2024-11-09 16:07:35,110 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2024-11-09 16:07:35,110 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2024-11-09 16:07:35,110 INFO L153 SettingsManager]: * Use SBE=true [2024-11-09 16:07:35,111 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2024-11-09 16:07:35,111 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2024-11-09 16:07:35,112 INFO L153 SettingsManager]: * Use old map elimination=false [2024-11-09 16:07:35,112 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2024-11-09 16:07:35,112 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2024-11-09 16:07:35,113 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2024-11-09 16:07:35,113 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2024-11-09 16:07:35,113 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2024-11-09 16:07:35,114 INFO L153 SettingsManager]: * sizeof long=4 [2024-11-09 16:07:35,114 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2024-11-09 16:07:35,115 INFO L153 SettingsManager]: * sizeof POINTER=4 [2024-11-09 16:07:35,115 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2024-11-09 16:07:35,115 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2024-11-09 16:07:35,116 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2024-11-09 16:07:35,116 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2024-11-09 16:07:35,116 INFO L153 SettingsManager]: * Allow undefined functions=false [2024-11-09 16:07:35,117 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2024-11-09 16:07:35,117 INFO L153 SettingsManager]: * sizeof long double=12 [2024-11-09 16:07:35,117 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2024-11-09 16:07:35,118 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2024-11-09 16:07:35,118 INFO L153 SettingsManager]: * Use constant arrays=true [2024-11-09 16:07:35,118 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2024-11-09 16:07:35,118 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2024-11-09 16:07:35,119 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2024-11-09 16:07:35,119 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2024-11-09 16:07:35,120 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2024-11-09 16:07:35,120 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d4710f8f3a918a0191222414f5c33a367ff98c09c2e8598fa3213223c4c35dba [2024-11-09 16:07:35,379 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2024-11-09 16:07:35,399 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2024-11-09 16:07:35,403 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2024-11-09 16:07:35,405 INFO L270 PluginConnector]: Initializing CDTParser... [2024-11-09 16:07:35,405 INFO L274 PluginConnector]: CDTParser initialized [2024-11-09 16:07:35,406 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2024-11-09 16:07:36,818 INFO L533 CDTParser]: Created temporary CDT project at NULL [2024-11-09 16:07:37,036 INFO L384 CDTParser]: Found 1 translation units. [2024-11-09 16:07:37,036 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/token_ring.04.cil-1.c [2024-11-09 16:07:37,047 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5970761d3/57e277339fb244aaac70a2812275baa6/FLAGb55dea813 [2024-11-09 16:07:37,060 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/5970761d3/57e277339fb244aaac70a2812275baa6 [2024-11-09 16:07:37,063 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2024-11-09 16:07:37,064 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2024-11-09 16:07:37,065 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2024-11-09 16:07:37,066 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2024-11-09 16:07:37,070 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2024-11-09 16:07:37,070 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,071 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1a14de7a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37, skipping insertion in model container [2024-11-09 16:07:37,071 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,104 INFO L175 MainTranslator]: Built tables and reachable declarations [2024-11-09 16:07:37,334 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:07:37,351 INFO L200 MainTranslator]: Completed pre-run [2024-11-09 16:07:37,399 INFO L210 PostProcessor]: Analyzing one entry point: main [2024-11-09 16:07:37,418 INFO L204 MainTranslator]: Completed translation [2024-11-09 16:07:37,419 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37 WrapperNode [2024-11-09 16:07:37,419 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2024-11-09 16:07:37,420 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2024-11-09 16:07:37,420 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2024-11-09 16:07:37,420 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2024-11-09 16:07:37,428 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,443 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,501 INFO L138 Inliner]: procedures = 36, calls = 44, calls flagged for inlining = 39, calls inlined = 78, statements flattened = 1073 [2024-11-09 16:07:37,502 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2024-11-09 16:07:37,503 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2024-11-09 16:07:37,503 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2024-11-09 16:07:37,503 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2024-11-09 16:07:37,518 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,519 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,523 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,557 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2024-11-09 16:07:37,558 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,558 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,579 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,591 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,594 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,597 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,603 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2024-11-09 16:07:37,604 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2024-11-09 16:07:37,604 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2024-11-09 16:07:37,604 INFO L274 PluginConnector]: RCFGBuilder initialized [2024-11-09 16:07:37,605 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (1/1) ... [2024-11-09 16:07:37,618 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2024-11-09 16:07:37,639 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2024-11-09 16:07:37,666 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2024-11-09 16:07:37,673 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2024-11-09 16:07:37,743 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2024-11-09 16:07:37,744 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2024-11-09 16:07:37,744 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2024-11-09 16:07:37,744 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2024-11-09 16:07:37,857 INFO L238 CfgBuilder]: Building ICFG [2024-11-09 16:07:37,859 INFO L264 CfgBuilder]: Building CFG for each procedure with an implementation [2024-11-09 16:07:38,757 INFO L? ?]: Removed 194 outVars from TransFormulas that were not future-live. [2024-11-09 16:07:38,757 INFO L287 CfgBuilder]: Performing block encoding [2024-11-09 16:07:38,781 INFO L311 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2024-11-09 16:07:38,781 INFO L316 CfgBuilder]: Removed 7 assume(true) statements. [2024-11-09 16:07:38,783 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:07:38 BoogieIcfgContainer [2024-11-09 16:07:38,785 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2024-11-09 16:07:38,786 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2024-11-09 16:07:38,786 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2024-11-09 16:07:38,790 INFO L274 PluginConnector]: BuchiAutomizer initialized [2024-11-09 16:07:38,790 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:07:38,791 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 04:07:37" (1/3) ... [2024-11-09 16:07:38,791 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@199c9e22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:07:38, skipping insertion in model container [2024-11-09 16:07:38,792 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:07:38,792 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 04:07:37" (2/3) ... [2024-11-09 16:07:38,792 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@199c9e22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 04:07:38, skipping insertion in model container [2024-11-09 16:07:38,792 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2024-11-09 16:07:38,792 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:07:38" (3/3) ... [2024-11-09 16:07:38,793 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-1.c [2024-11-09 16:07:38,862 INFO L300 stractBuchiCegarLoop]: Interprodecural is true [2024-11-09 16:07:38,862 INFO L301 stractBuchiCegarLoop]: Hoare is None [2024-11-09 16:07:38,862 INFO L302 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2024-11-09 16:07:38,863 INFO L303 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2024-11-09 16:07:38,863 INFO L304 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2024-11-09 16:07:38,863 INFO L305 stractBuchiCegarLoop]: Difference is false [2024-11-09 16:07:38,864 INFO L306 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2024-11-09 16:07:38,864 INFO L310 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2024-11-09 16:07:38,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 437 states, 436 states have (on average 1.525229357798165) internal successors, (665), 436 states have internal predecessors, (665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:38,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 366 [2024-11-09 16:07:38,907 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:38,907 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:38,917 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:38,917 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:38,917 INFO L332 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2024-11-09 16:07:38,919 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 437 states, 436 states have (on average 1.525229357798165) internal successors, (665), 436 states have internal predecessors, (665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:38,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 366 [2024-11-09 16:07:38,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:38,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:38,935 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:38,935 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:38,943 INFO L745 eck$LassoCheckResult]: Stem: 128#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 363#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 208#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 359#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73#L353true assume !(1 == ~m_i~0);~m_st~0 := 2; 293#L353-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 370#L358-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 43#L363-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 415#L368-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 122#L373-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 57#L514true assume !(0 == ~M_E~0); 384#L514-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 322#L519-1true assume !(0 == ~T2_E~0); 36#L524-1true assume !(0 == ~T3_E~0); 105#L529-1true assume !(0 == ~T4_E~0); 325#L534-1true assume !(0 == ~E_M~0); 259#L539-1true assume !(0 == ~E_1~0); 291#L544-1true assume !(0 == ~E_2~0); 292#L549-1true assume !(0 == ~E_3~0); 330#L554-1true assume 0 == ~E_4~0;~E_4~0 := 1; 34#L559-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174#L250true assume 1 == ~m_pc~0; 396#L251true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 323#L261true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 295#L637true assume !(0 != activate_threads_~tmp~1#1); 37#L637-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49#L269true assume !(1 == ~t1_pc~0); 102#L269-2true is_transmit1_triggered_~__retres1~1#1 := 0; 180#L280true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 324#L645true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 147#L645-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 232#L288true assume 1 == ~t2_pc~0; 355#L289true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 244#L299true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 212#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 254#L653true assume !(0 != activate_threads_~tmp___1~0#1); 306#L653-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 165#L307true assume !(1 == ~t3_pc~0); 223#L307-2true is_transmit3_triggered_~__retres1~3#1 := 0; 205#L318true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 301#L661true assume !(0 != activate_threads_~tmp___2~0#1); 127#L661-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 348#L326true assume 1 == ~t4_pc~0; 342#L327true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 163#L337true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 302#L669true assume !(0 != activate_threads_~tmp___3~0#1); 257#L669-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 297#L572true assume !(1 == ~M_E~0); 343#L572-2true assume !(1 == ~T1_E~0); 41#L577-1true assume !(1 == ~T2_E~0); 239#L582-1true assume !(1 == ~T3_E~0); 247#L587-1true assume !(1 == ~T4_E~0); 375#L592-1true assume !(1 == ~E_M~0); 11#L597-1true assume 1 == ~E_1~0;~E_1~0 := 2; 417#L602-1true assume !(1 == ~E_2~0); 140#L607-1true assume !(1 == ~E_3~0); 421#L612-1true assume !(1 == ~E_4~0); 104#L617-1true assume { :end_inline_reset_delta_events } true; 436#L803-2true [2024-11-09 16:07:38,944 INFO L747 eck$LassoCheckResult]: Loop: 436#L803-2true assume !false; 218#L804true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 188#L489-1true assume !true; 63#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 307#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 194#L514-3true assume !(0 == ~M_E~0); 154#L514-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 313#L519-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 237#L524-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 86#L529-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 172#L534-3true assume 0 == ~E_M~0;~E_M~0 := 1; 6#L539-3true assume 0 == ~E_1~0;~E_1~0 := 1; 328#L544-3true assume 0 == ~E_2~0;~E_2~0 := 1; 401#L549-3true assume !(0 == ~E_3~0); 118#L554-3true assume 0 == ~E_4~0;~E_4~0 := 1; 191#L559-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269#L250-18true assume !(1 == ~m_pc~0); 378#L250-20true is_master_triggered_~__retres1~0#1 := 0; 203#L261-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 137#is_master_triggered_returnLabel#7true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 267#L637-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 91#L637-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26#L269-18true assume 1 == ~t1_pc~0; 195#L270-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 67#L280-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 182#L645-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 285#L645-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110#L288-18true assume !(1 == ~t2_pc~0); 397#L288-20true is_transmit2_triggered_~__retres1~2#1 := 0; 10#L299-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 202#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 170#L653-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95#L653-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 310#L307-18true assume 1 == ~t3_pc~0; 141#L308-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 121#L318-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84#L661-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 346#L661-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 270#L326-18true assume 1 == ~t4_pc~0; 367#L327-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 280#L337-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 155#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4#L669-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 371#L669-20true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425#L572-3true assume 1 == ~M_E~0;~M_E~0 := 2; 93#L572-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 109#L577-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 33#L582-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 374#L587-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 190#L592-3true assume !(1 == ~E_M~0); 245#L597-3true assume 1 == ~E_1~0;~E_1~0 := 2; 132#L602-3true assume 1 == ~E_2~0;~E_2~0 := 2; 318#L607-3true assume 1 == ~E_3~0;~E_3~0 := 2; 100#L612-3true assume 1 == ~E_4~0;~E_4~0 := 2; 192#L617-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 136#L386-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 125#L413-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 185#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 164#L822true assume !(0 == start_simulation_~tmp~3#1); 265#L822-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 395#L386-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 407#L413-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 30#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 19#L777true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 198#L784true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 319#stop_simulation_returnLabel#1true start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 311#L835true assume !(0 != start_simulation_~tmp___0~1#1); 436#L803-2true [2024-11-09 16:07:38,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:38,950 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2024-11-09 16:07:38,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:38,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686557322] [2024-11-09 16:07:38,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:38,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:39,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:39,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:39,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:39,208 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686557322] [2024-11-09 16:07:39,209 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686557322] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:39,209 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:39,209 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:39,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [954508443] [2024-11-09 16:07:39,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:39,216 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:39,217 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:39,218 INFO L85 PathProgramCache]: Analyzing trace with hash 868114677, now seen corresponding path program 1 times [2024-11-09 16:07:39,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:39,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951297558] [2024-11-09 16:07:39,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:39,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:39,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:39,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:39,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:39,286 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951297558] [2024-11-09 16:07:39,286 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [951297558] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:39,286 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:39,286 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:39,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39574374] [2024-11-09 16:07:39,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:39,288 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:39,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:39,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:39,327 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:39,330 INFO L87 Difference]: Start difference. First operand has 437 states, 436 states have (on average 1.525229357798165) internal successors, (665), 436 states have internal predecessors, (665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:39,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:39,391 INFO L93 Difference]: Finished difference Result 435 states and 647 transitions. [2024-11-09 16:07:39,392 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 647 transitions. [2024-11-09 16:07:39,403 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2024-11-09 16:07:39,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 430 states and 642 transitions. [2024-11-09 16:07:39,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2024-11-09 16:07:39,417 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2024-11-09 16:07:39,417 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 642 transitions. [2024-11-09 16:07:39,419 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:39,421 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 642 transitions. [2024-11-09 16:07:39,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 642 transitions. [2024-11-09 16:07:39,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2024-11-09 16:07:39,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4930232558139536) internal successors, (642), 429 states have internal predecessors, (642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:39,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 642 transitions. [2024-11-09 16:07:39,478 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 642 transitions. [2024-11-09 16:07:39,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:39,483 INFO L425 stractBuchiCegarLoop]: Abstraction has 430 states and 642 transitions. [2024-11-09 16:07:39,483 INFO L332 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2024-11-09 16:07:39,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 642 transitions. [2024-11-09 16:07:39,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2024-11-09 16:07:39,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:39,486 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:39,488 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:39,488 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:39,489 INFO L745 eck$LassoCheckResult]: Stem: 1110#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1210#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1211#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1022#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1023#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1277#L358-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 966#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 967#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1103#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 994#L514 assume !(0 == ~M_E~0); 995#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1291#L519-1 assume !(0 == ~T2_E~0); 954#L524-1 assume !(0 == ~T3_E~0); 955#L529-1 assume !(0 == ~T4_E~0); 1079#L534-1 assume !(0 == ~E_M~0); 1255#L539-1 assume !(0 == ~E_1~0); 1256#L544-1 assume !(0 == ~E_2~0); 1275#L549-1 assume !(0 == ~E_3~0); 1276#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 949#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 950#L250 assume 1 == ~m_pc~0; 1168#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1279#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1092#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1093#L637 assume !(0 != activate_threads_~tmp~1#1); 956#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 957#L269 assume !(1 == ~t1_pc~0); 894#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 893#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 944#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 945#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1137#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1138#L288 assume 1 == ~t2_pc~0; 1231#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1134#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1215#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1216#L653 assume !(0 != activate_threads_~tmp___1~0#1); 1251#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1158#L307 assume !(1 == ~t3_pc~0); 1095#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1096#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 897#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 898#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1108#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1109#L326 assume 1 == ~t4_pc~0; 1300#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 910#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 998#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 999#L669 assume !(0 != activate_threads_~tmp___3~0#1); 1252#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1253#L572 assume !(1 == ~M_E~0); 1280#L572-2 assume !(1 == ~T1_E~0); 962#L577-1 assume !(1 == ~T2_E~0); 963#L582-1 assume !(1 == ~T3_E~0); 1235#L587-1 assume !(1 == ~T4_E~0); 1244#L592-1 assume !(1 == ~E_M~0); 901#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 902#L602-1 assume !(1 == ~E_2~0); 1130#L607-1 assume !(1 == ~E_3~0); 1131#L612-1 assume !(1 == ~E_4~0); 1077#L617-1 assume { :end_inline_reset_delta_events } true; 1078#L803-2 [2024-11-09 16:07:39,489 INFO L747 eck$LassoCheckResult]: Loop: 1078#L803-2 assume !false; 1222#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1188#L489-1 assume !false; 1189#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1159#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1008#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1074#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1224#L428 assume !(0 != eval_~tmp~0#1); 1003#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1004#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1193#L514-3 assume !(0 == ~M_E~0); 1143#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1144#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1234#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1048#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1049#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 890#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 891#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1293#L549-3 assume !(0 == ~E_3~0); 1099#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1100#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1192#L250-18 assume 1 == ~m_pc~0; 1229#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1202#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1126#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1127#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1058#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 933#L269-18 assume 1 == ~t1_pc~0; 934#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1010#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1011#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1181#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1182#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1085#L288-18 assume 1 == ~t2_pc~0; 1069#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 899#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 900#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1167#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1064#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1065#L307-18 assume !(1 == ~t3_pc~0); 1031#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1032#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1102#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1045#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1046#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1262#L326-18 assume 1 == ~t4_pc~0; 1264#L327-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1270#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1145#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 886#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 887#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1305#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1061#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1062#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 947#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 948#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1190#L592-3 assume !(1 == ~E_M~0); 1191#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1117#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1118#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1072#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1073#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1124#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1089#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1106#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 1156#L822 assume !(0 == start_simulation_~tmp~3#1); 1157#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1259#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1197#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 943#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 918#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 919#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1195#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1287#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1078#L803-2 [2024-11-09 16:07:39,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:39,490 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2024-11-09 16:07:39,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:39,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351264418] [2024-11-09 16:07:39,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:39,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:39,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:39,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:39,555 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:39,555 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351264418] [2024-11-09 16:07:39,556 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1351264418] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:39,556 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:39,556 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:39,556 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351723795] [2024-11-09 16:07:39,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:39,557 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:39,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:39,558 INFO L85 PathProgramCache]: Analyzing trace with hash -691501310, now seen corresponding path program 1 times [2024-11-09 16:07:39,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:39,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852464604] [2024-11-09 16:07:39,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:39,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:39,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:39,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:39,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:39,671 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852464604] [2024-11-09 16:07:39,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852464604] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:39,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:39,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:39,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414708367] [2024-11-09 16:07:39,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:39,672 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:39,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:39,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:39,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:39,673 INFO L87 Difference]: Start difference. First operand 430 states and 642 transitions. cyclomatic complexity: 213 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:39,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:39,733 INFO L93 Difference]: Finished difference Result 430 states and 641 transitions. [2024-11-09 16:07:39,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 641 transitions. [2024-11-09 16:07:39,736 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2024-11-09 16:07:39,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 641 transitions. [2024-11-09 16:07:39,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2024-11-09 16:07:39,770 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2024-11-09 16:07:39,770 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 641 transitions. [2024-11-09 16:07:39,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:39,774 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 641 transitions. [2024-11-09 16:07:39,774 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 641 transitions. [2024-11-09 16:07:39,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2024-11-09 16:07:39,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4906976744186047) internal successors, (641), 429 states have internal predecessors, (641), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:39,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 641 transitions. [2024-11-09 16:07:39,794 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 641 transitions. [2024-11-09 16:07:39,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:39,795 INFO L425 stractBuchiCegarLoop]: Abstraction has 430 states and 641 transitions. [2024-11-09 16:07:39,795 INFO L332 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2024-11-09 16:07:39,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 641 transitions. [2024-11-09 16:07:39,797 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2024-11-09 16:07:39,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:39,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:39,799 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:39,799 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:39,799 INFO L745 eck$LassoCheckResult]: Stem: 1977#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1978#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2077#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2078#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1889#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 1890#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2144#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1833#L363-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1834#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1970#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1861#L514 assume !(0 == ~M_E~0); 1862#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2158#L519-1 assume !(0 == ~T2_E~0); 1821#L524-1 assume !(0 == ~T3_E~0); 1822#L529-1 assume !(0 == ~T4_E~0); 1946#L534-1 assume !(0 == ~E_M~0); 2122#L539-1 assume !(0 == ~E_1~0); 2123#L544-1 assume !(0 == ~E_2~0); 2142#L549-1 assume !(0 == ~E_3~0); 2143#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1816#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1817#L250 assume 1 == ~m_pc~0; 2035#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2146#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1959#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1960#L637 assume !(0 != activate_threads_~tmp~1#1); 1823#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1824#L269 assume !(1 == ~t1_pc~0); 1761#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1760#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1811#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1812#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2004#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2005#L288 assume 1 == ~t2_pc~0; 2098#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2001#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2082#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2083#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2118#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2025#L307 assume !(1 == ~t3_pc~0); 1962#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1963#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1764#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1765#L661 assume !(0 != activate_threads_~tmp___2~0#1); 1975#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1976#L326 assume 1 == ~t4_pc~0; 2167#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1777#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1865#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1866#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2119#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2120#L572 assume !(1 == ~M_E~0); 2147#L572-2 assume !(1 == ~T1_E~0); 1829#L577-1 assume !(1 == ~T2_E~0); 1830#L582-1 assume !(1 == ~T3_E~0); 2102#L587-1 assume !(1 == ~T4_E~0); 2111#L592-1 assume !(1 == ~E_M~0); 1768#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1769#L602-1 assume !(1 == ~E_2~0); 1997#L607-1 assume !(1 == ~E_3~0); 1998#L612-1 assume !(1 == ~E_4~0); 1944#L617-1 assume { :end_inline_reset_delta_events } true; 1945#L803-2 [2024-11-09 16:07:39,800 INFO L747 eck$LassoCheckResult]: Loop: 1945#L803-2 assume !false; 2089#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2055#L489-1 assume !false; 2056#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2026#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1875#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1941#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2091#L428 assume !(0 != eval_~tmp~0#1); 1870#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1871#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2060#L514-3 assume !(0 == ~M_E~0); 2010#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2011#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2101#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1915#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1916#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1757#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1758#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2160#L549-3 assume !(0 == ~E_3~0); 1966#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1967#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2059#L250-18 assume 1 == ~m_pc~0; 2096#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2069#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1993#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1994#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1925#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1800#L269-18 assume 1 == ~t1_pc~0; 1801#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1877#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1878#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2048#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2049#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1952#L288-18 assume 1 == ~t2_pc~0; 1936#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1766#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1767#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2034#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1931#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1932#L307-18 assume !(1 == ~t3_pc~0); 1898#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 1899#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1969#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1912#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1913#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2129#L326-18 assume !(1 == ~t4_pc~0); 2130#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 2137#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2012#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1753#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1754#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2172#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1928#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1929#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1814#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1815#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2057#L592-3 assume !(1 == ~E_M~0); 2058#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1984#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1985#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1939#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1940#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1991#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1956#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1973#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2023#L822 assume !(0 == start_simulation_~tmp~3#1); 2024#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2126#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2064#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1810#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 1785#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1786#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2062#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2154#L835 assume !(0 != start_simulation_~tmp___0~1#1); 1945#L803-2 [2024-11-09 16:07:39,801 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:39,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2024-11-09 16:07:39,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:39,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703519149] [2024-11-09 16:07:39,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:39,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:39,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:39,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:39,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:39,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1703519149] [2024-11-09 16:07:39,863 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1703519149] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:39,863 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:39,864 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:39,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1257310144] [2024-11-09 16:07:39,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:39,864 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:39,864 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:39,865 INFO L85 PathProgramCache]: Analyzing trace with hash -1663175997, now seen corresponding path program 1 times [2024-11-09 16:07:39,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:39,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1956718218] [2024-11-09 16:07:39,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:39,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:39,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:39,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:39,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:39,924 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1956718218] [2024-11-09 16:07:39,924 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1956718218] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:39,924 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:39,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:39,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2021158002] [2024-11-09 16:07:39,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:39,925 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:39,925 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:39,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:39,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:39,925 INFO L87 Difference]: Start difference. First operand 430 states and 641 transitions. cyclomatic complexity: 212 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:39,938 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:39,938 INFO L93 Difference]: Finished difference Result 430 states and 640 transitions. [2024-11-09 16:07:39,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 640 transitions. [2024-11-09 16:07:39,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2024-11-09 16:07:39,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 640 transitions. [2024-11-09 16:07:39,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2024-11-09 16:07:39,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2024-11-09 16:07:39,944 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 640 transitions. [2024-11-09 16:07:39,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:39,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 640 transitions. [2024-11-09 16:07:39,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 640 transitions. [2024-11-09 16:07:39,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2024-11-09 16:07:39,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4883720930232558) internal successors, (640), 429 states have internal predecessors, (640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:39,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 640 transitions. [2024-11-09 16:07:39,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 640 transitions. [2024-11-09 16:07:39,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:39,961 INFO L425 stractBuchiCegarLoop]: Abstraction has 430 states and 640 transitions. [2024-11-09 16:07:39,962 INFO L332 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2024-11-09 16:07:39,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 640 transitions. [2024-11-09 16:07:39,963 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2024-11-09 16:07:39,964 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:39,964 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:39,967 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:39,968 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:39,969 INFO L745 eck$LassoCheckResult]: Stem: 2844#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2944#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2945#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2756#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 2757#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3011#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2700#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2701#L368-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2837#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2728#L514 assume !(0 == ~M_E~0); 2729#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3025#L519-1 assume !(0 == ~T2_E~0); 2688#L524-1 assume !(0 == ~T3_E~0); 2689#L529-1 assume !(0 == ~T4_E~0); 2813#L534-1 assume !(0 == ~E_M~0); 2989#L539-1 assume !(0 == ~E_1~0); 2990#L544-1 assume !(0 == ~E_2~0); 3009#L549-1 assume !(0 == ~E_3~0); 3010#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2683#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2684#L250 assume 1 == ~m_pc~0; 2902#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3013#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2826#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2827#L637 assume !(0 != activate_threads_~tmp~1#1); 2690#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2691#L269 assume !(1 == ~t1_pc~0); 2628#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2627#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2678#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2679#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2871#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2872#L288 assume 1 == ~t2_pc~0; 2965#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2868#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2949#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2950#L653 assume !(0 != activate_threads_~tmp___1~0#1); 2985#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2892#L307 assume !(1 == ~t3_pc~0); 2829#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2830#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2631#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2632#L661 assume !(0 != activate_threads_~tmp___2~0#1); 2842#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2843#L326 assume 1 == ~t4_pc~0; 3034#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2644#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2732#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2733#L669 assume !(0 != activate_threads_~tmp___3~0#1); 2986#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2987#L572 assume !(1 == ~M_E~0); 3014#L572-2 assume !(1 == ~T1_E~0); 2696#L577-1 assume !(1 == ~T2_E~0); 2697#L582-1 assume !(1 == ~T3_E~0); 2969#L587-1 assume !(1 == ~T4_E~0); 2978#L592-1 assume !(1 == ~E_M~0); 2635#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2636#L602-1 assume !(1 == ~E_2~0); 2864#L607-1 assume !(1 == ~E_3~0); 2865#L612-1 assume !(1 == ~E_4~0); 2811#L617-1 assume { :end_inline_reset_delta_events } true; 2812#L803-2 [2024-11-09 16:07:39,969 INFO L747 eck$LassoCheckResult]: Loop: 2812#L803-2 assume !false; 2956#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2922#L489-1 assume !false; 2923#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2893#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2742#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2808#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2958#L428 assume !(0 != eval_~tmp~0#1); 2737#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2738#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2927#L514-3 assume !(0 == ~M_E~0); 2877#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2878#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2968#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2782#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2783#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2624#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2625#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3027#L549-3 assume !(0 == ~E_3~0); 2833#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2834#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2926#L250-18 assume 1 == ~m_pc~0; 2963#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2936#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2860#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2861#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2792#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2667#L269-18 assume 1 == ~t1_pc~0; 2668#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2744#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2745#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2915#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2916#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2819#L288-18 assume 1 == ~t2_pc~0; 2803#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2633#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2634#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2901#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2798#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2799#L307-18 assume 1 == ~t3_pc~0; 2866#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2766#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2836#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2779#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2780#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2996#L326-18 assume !(1 == ~t4_pc~0); 2997#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3004#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2879#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2620#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2621#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3039#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2795#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2796#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2681#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2682#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2924#L592-3 assume !(1 == ~E_M~0); 2925#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2851#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2852#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2806#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2807#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2858#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2823#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 2890#L822 assume !(0 == start_simulation_~tmp~3#1); 2891#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2993#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2931#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2677#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 2652#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2653#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2929#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3021#L835 assume !(0 != start_simulation_~tmp___0~1#1); 2812#L803-2 [2024-11-09 16:07:39,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:39,970 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2024-11-09 16:07:39,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:39,973 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1551242085] [2024-11-09 16:07:39,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:39,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:39,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:40,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:40,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:40,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1551242085] [2024-11-09 16:07:40,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1551242085] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:40,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:40,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:40,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [376158637] [2024-11-09 16:07:40,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:40,023 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:40,023 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:40,023 INFO L85 PathProgramCache]: Analyzing trace with hash 1580342210, now seen corresponding path program 1 times [2024-11-09 16:07:40,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:40,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889248984] [2024-11-09 16:07:40,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:40,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:40,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:40,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:40,070 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:40,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889248984] [2024-11-09 16:07:40,070 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889248984] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:40,070 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:40,071 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:40,071 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [999194629] [2024-11-09 16:07:40,071 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:40,071 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:40,072 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:40,072 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:40,072 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:40,072 INFO L87 Difference]: Start difference. First operand 430 states and 640 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:40,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:40,084 INFO L93 Difference]: Finished difference Result 430 states and 639 transitions. [2024-11-09 16:07:40,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 639 transitions. [2024-11-09 16:07:40,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2024-11-09 16:07:40,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 639 transitions. [2024-11-09 16:07:40,088 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2024-11-09 16:07:40,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2024-11-09 16:07:40,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 639 transitions. [2024-11-09 16:07:40,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:40,090 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 639 transitions. [2024-11-09 16:07:40,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 639 transitions. [2024-11-09 16:07:40,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2024-11-09 16:07:40,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.486046511627907) internal successors, (639), 429 states have internal predecessors, (639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:40,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 639 transitions. [2024-11-09 16:07:40,098 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 639 transitions. [2024-11-09 16:07:40,100 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:40,100 INFO L425 stractBuchiCegarLoop]: Abstraction has 430 states and 639 transitions. [2024-11-09 16:07:40,101 INFO L332 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2024-11-09 16:07:40,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 639 transitions. [2024-11-09 16:07:40,102 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2024-11-09 16:07:40,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:40,102 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:40,107 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:40,107 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:40,108 INFO L745 eck$LassoCheckResult]: Stem: 3711#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3712#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3811#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3812#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3623#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 3624#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3879#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3567#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3568#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3704#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3597#L514 assume !(0 == ~M_E~0); 3598#L514-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3892#L519-1 assume !(0 == ~T2_E~0); 3555#L524-1 assume !(0 == ~T3_E~0); 3556#L529-1 assume !(0 == ~T4_E~0); 3680#L534-1 assume !(0 == ~E_M~0); 3856#L539-1 assume !(0 == ~E_1~0); 3857#L544-1 assume !(0 == ~E_2~0); 3876#L549-1 assume !(0 == ~E_3~0); 3877#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3550#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3551#L250 assume 1 == ~m_pc~0; 3769#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3880#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3693#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3694#L637 assume !(0 != activate_threads_~tmp~1#1); 3557#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3558#L269 assume !(1 == ~t1_pc~0); 3495#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3494#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3545#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3546#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3738#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3739#L288 assume 1 == ~t2_pc~0; 3832#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3735#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3816#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3817#L653 assume !(0 != activate_threads_~tmp___1~0#1); 3852#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3759#L307 assume !(1 == ~t3_pc~0); 3696#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3697#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3498#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3499#L661 assume !(0 != activate_threads_~tmp___2~0#1); 3709#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3710#L326 assume 1 == ~t4_pc~0; 3901#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3511#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3599#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3600#L669 assume !(0 != activate_threads_~tmp___3~0#1); 3853#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3854#L572 assume !(1 == ~M_E~0); 3881#L572-2 assume !(1 == ~T1_E~0); 3563#L577-1 assume !(1 == ~T2_E~0); 3564#L582-1 assume !(1 == ~T3_E~0); 3836#L587-1 assume !(1 == ~T4_E~0); 3845#L592-1 assume !(1 == ~E_M~0); 3502#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3503#L602-1 assume !(1 == ~E_2~0); 3731#L607-1 assume !(1 == ~E_3~0); 3732#L612-1 assume !(1 == ~E_4~0); 3678#L617-1 assume { :end_inline_reset_delta_events } true; 3679#L803-2 [2024-11-09 16:07:40,108 INFO L747 eck$LassoCheckResult]: Loop: 3679#L803-2 assume !false; 3823#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3789#L489-1 assume !false; 3790#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3760#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3609#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3675#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3825#L428 assume !(0 != eval_~tmp~0#1); 3604#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3605#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3794#L514-3 assume !(0 == ~M_E~0); 3744#L514-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3745#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3835#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3649#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3650#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3491#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3492#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3894#L549-3 assume !(0 == ~E_3~0); 3700#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3701#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3793#L250-18 assume 1 == ~m_pc~0; 3830#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3803#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3727#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3728#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3659#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3534#L269-18 assume !(1 == ~t1_pc~0); 3536#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3611#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3612#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3782#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3783#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3686#L288-18 assume 1 == ~t2_pc~0; 3670#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3500#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3501#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3768#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3665#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3666#L307-18 assume !(1 == ~t3_pc~0); 3632#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 3633#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3703#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3646#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3647#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3863#L326-18 assume !(1 == ~t4_pc~0); 3864#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3871#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3746#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3487#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3488#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3906#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3662#L572-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3663#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3548#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3549#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3791#L592-3 assume !(1 == ~E_M~0); 3792#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3718#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3719#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3673#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3674#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3725#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3690#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3707#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 3757#L822 assume !(0 == start_simulation_~tmp~3#1); 3758#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3860#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3798#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3544#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 3519#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3520#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3796#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3888#L835 assume !(0 != start_simulation_~tmp___0~1#1); 3679#L803-2 [2024-11-09 16:07:40,109 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:40,109 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2024-11-09 16:07:40,110 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:40,110 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883270426] [2024-11-09 16:07:40,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:40,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:40,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:40,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:40,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:40,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883270426] [2024-11-09 16:07:40,161 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1883270426] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:40,161 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:40,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:40,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2124898542] [2024-11-09 16:07:40,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:40,162 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:40,162 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:40,163 INFO L85 PathProgramCache]: Analyzing trace with hash 738349124, now seen corresponding path program 1 times [2024-11-09 16:07:40,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:40,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310353196] [2024-11-09 16:07:40,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:40,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:40,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:40,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:40,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:40,202 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310353196] [2024-11-09 16:07:40,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [310353196] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:40,202 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:40,202 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:40,203 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34831894] [2024-11-09 16:07:40,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:40,203 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:40,203 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:40,204 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:40,204 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:40,204 INFO L87 Difference]: Start difference. First operand 430 states and 639 transitions. cyclomatic complexity: 210 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:40,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:40,224 INFO L93 Difference]: Finished difference Result 430 states and 634 transitions. [2024-11-09 16:07:40,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 634 transitions. [2024-11-09 16:07:40,226 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2024-11-09 16:07:40,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 634 transitions. [2024-11-09 16:07:40,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 430 [2024-11-09 16:07:40,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 430 [2024-11-09 16:07:40,230 INFO L73 IsDeterministic]: Start isDeterministic. Operand 430 states and 634 transitions. [2024-11-09 16:07:40,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:40,230 INFO L218 hiAutomatonCegarLoop]: Abstraction has 430 states and 634 transitions. [2024-11-09 16:07:40,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states and 634 transitions. [2024-11-09 16:07:40,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 430. [2024-11-09 16:07:40,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430 states, 430 states have (on average 1.4744186046511627) internal successors, (634), 429 states have internal predecessors, (634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:40,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430 states to 430 states and 634 transitions. [2024-11-09 16:07:40,236 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430 states and 634 transitions. [2024-11-09 16:07:40,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:40,239 INFO L425 stractBuchiCegarLoop]: Abstraction has 430 states and 634 transitions. [2024-11-09 16:07:40,239 INFO L332 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2024-11-09 16:07:40,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 430 states and 634 transitions. [2024-11-09 16:07:40,241 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 363 [2024-11-09 16:07:40,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:40,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:40,243 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:40,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:40,247 INFO L745 eck$LassoCheckResult]: Stem: 4578#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4579#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4678#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4679#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4490#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 4491#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4745#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4434#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4435#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4571#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4462#L514 assume !(0 == ~M_E~0); 4463#L514-2 assume !(0 == ~T1_E~0); 4759#L519-1 assume !(0 == ~T2_E~0); 4422#L524-1 assume !(0 == ~T3_E~0); 4423#L529-1 assume !(0 == ~T4_E~0); 4547#L534-1 assume !(0 == ~E_M~0); 4723#L539-1 assume !(0 == ~E_1~0); 4724#L544-1 assume !(0 == ~E_2~0); 4743#L549-1 assume !(0 == ~E_3~0); 4744#L554-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4417#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4418#L250 assume 1 == ~m_pc~0; 4639#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4747#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4560#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4561#L637 assume !(0 != activate_threads_~tmp~1#1); 4424#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4425#L269 assume !(1 == ~t1_pc~0); 4362#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4361#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4412#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4413#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4605#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4606#L288 assume 1 == ~t2_pc~0; 4699#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4602#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4683#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4684#L653 assume !(0 != activate_threads_~tmp___1~0#1); 4719#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4626#L307 assume !(1 == ~t3_pc~0); 4563#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4564#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4365#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4366#L661 assume !(0 != activate_threads_~tmp___2~0#1); 4576#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4577#L326 assume 1 == ~t4_pc~0; 4768#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4378#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4466#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4467#L669 assume !(0 != activate_threads_~tmp___3~0#1); 4720#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4721#L572 assume !(1 == ~M_E~0); 4748#L572-2 assume !(1 == ~T1_E~0); 4430#L577-1 assume !(1 == ~T2_E~0); 4431#L582-1 assume !(1 == ~T3_E~0); 4704#L587-1 assume !(1 == ~T4_E~0); 4713#L592-1 assume !(1 == ~E_M~0); 4369#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4370#L602-1 assume !(1 == ~E_2~0); 4598#L607-1 assume !(1 == ~E_3~0); 4599#L612-1 assume !(1 == ~E_4~0); 4545#L617-1 assume { :end_inline_reset_delta_events } true; 4546#L803-2 [2024-11-09 16:07:40,247 INFO L747 eck$LassoCheckResult]: Loop: 4546#L803-2 assume !false; 4691#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4656#L489-1 assume !false; 4657#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4627#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4476#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4542#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4692#L428 assume !(0 != eval_~tmp~0#1); 4471#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4472#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4661#L514-3 assume !(0 == ~M_E~0); 4612#L514-5 assume !(0 == ~T1_E~0); 4613#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4702#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4518#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4519#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4358#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4359#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4761#L549-3 assume !(0 == ~E_3~0); 4567#L554-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4568#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4660#L250-18 assume 1 == ~m_pc~0; 4697#L251-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4670#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4594#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4595#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4526#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4401#L269-18 assume 1 == ~t1_pc~0; 4402#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4478#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4479#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4649#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4650#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4553#L288-18 assume 1 == ~t2_pc~0; 4534#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4367#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4368#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4635#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4532#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4533#L307-18 assume !(1 == ~t3_pc~0); 4497#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4498#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4570#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4510#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4511#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4730#L326-18 assume !(1 == ~t4_pc~0); 4731#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 4738#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4611#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4354#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4355#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4773#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4529#L572-5 assume !(1 == ~T1_E~0); 4530#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4415#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4416#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4658#L592-3 assume !(1 == ~E_M~0); 4659#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4585#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4586#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4540#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4541#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4592#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4557#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4573#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 4624#L822 assume !(0 == start_simulation_~tmp~3#1); 4625#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4726#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4665#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4411#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 4386#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4387#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4663#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4755#L835 assume !(0 != start_simulation_~tmp___0~1#1); 4546#L803-2 [2024-11-09 16:07:40,248 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:40,248 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2024-11-09 16:07:40,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:40,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071520397] [2024-11-09 16:07:40,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:40,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:40,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:40,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:40,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:40,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1071520397] [2024-11-09 16:07:40,323 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1071520397] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:40,323 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:40,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:40,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778528131] [2024-11-09 16:07:40,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:40,324 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:40,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:40,325 INFO L85 PathProgramCache]: Analyzing trace with hash -1861717885, now seen corresponding path program 1 times [2024-11-09 16:07:40,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:40,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920041666] [2024-11-09 16:07:40,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:40,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:40,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:40,383 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:40,384 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:40,384 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920041666] [2024-11-09 16:07:40,384 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920041666] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:40,384 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:40,384 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:40,384 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498323519] [2024-11-09 16:07:40,385 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:40,385 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:40,385 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:40,386 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:07:40,386 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:07:40,386 INFO L87 Difference]: Start difference. First operand 430 states and 634 transitions. cyclomatic complexity: 205 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:40,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:40,511 INFO L93 Difference]: Finished difference Result 720 states and 1058 transitions. [2024-11-09 16:07:40,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 720 states and 1058 transitions. [2024-11-09 16:07:40,516 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2024-11-09 16:07:40,519 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 720 states to 720 states and 1058 transitions. [2024-11-09 16:07:40,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 720 [2024-11-09 16:07:40,520 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 720 [2024-11-09 16:07:40,520 INFO L73 IsDeterministic]: Start isDeterministic. Operand 720 states and 1058 transitions. [2024-11-09 16:07:40,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:40,521 INFO L218 hiAutomatonCegarLoop]: Abstraction has 720 states and 1058 transitions. [2024-11-09 16:07:40,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 720 states and 1058 transitions. [2024-11-09 16:07:40,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 720 to 719. [2024-11-09 16:07:40,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 719 states, 719 states have (on average 1.4700973574408902) internal successors, (1057), 718 states have internal predecessors, (1057), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:40,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 719 states to 719 states and 1057 transitions. [2024-11-09 16:07:40,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 719 states and 1057 transitions. [2024-11-09 16:07:40,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:07:40,538 INFO L425 stractBuchiCegarLoop]: Abstraction has 719 states and 1057 transitions. [2024-11-09 16:07:40,538 INFO L332 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2024-11-09 16:07:40,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 719 states and 1057 transitions. [2024-11-09 16:07:40,542 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 642 [2024-11-09 16:07:40,542 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:40,542 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:40,543 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:40,543 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:40,544 INFO L745 eck$LassoCheckResult]: Stem: 5741#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5742#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5848#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5849#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5650#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 5651#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5926#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5594#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5595#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5734#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5622#L514 assume !(0 == ~M_E~0); 5623#L514-2 assume !(0 == ~T1_E~0); 5946#L519-1 assume !(0 == ~T2_E~0); 5582#L524-1 assume !(0 == ~T3_E~0); 5583#L529-1 assume !(0 == ~T4_E~0); 5709#L534-1 assume !(0 == ~E_M~0); 5901#L539-1 assume !(0 == ~E_1~0); 5902#L544-1 assume !(0 == ~E_2~0); 5924#L549-1 assume !(0 == ~E_3~0); 5925#L554-1 assume !(0 == ~E_4~0); 5577#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5578#L250 assume 1 == ~m_pc~0; 5805#L251 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5928#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5723#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5724#L637 assume !(0 != activate_threads_~tmp~1#1); 5584#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5585#L269 assume !(1 == ~t1_pc~0); 5522#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5521#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5573#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5768#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5769#L288 assume 1 == ~t2_pc~0; 5874#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5765#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5853#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5854#L653 assume !(0 != activate_threads_~tmp___1~0#1); 5897#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5791#L307 assume !(1 == ~t3_pc~0); 5726#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5727#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5525#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5526#L661 assume !(0 != activate_threads_~tmp___2~0#1); 5739#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5740#L326 assume 1 == ~t4_pc~0; 5955#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5538#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5626#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5627#L669 assume !(0 != activate_threads_~tmp___3~0#1); 5898#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5899#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 5929#L572-2 assume !(1 == ~T1_E~0); 5590#L577-1 assume !(1 == ~T2_E~0); 5591#L582-1 assume !(1 == ~T3_E~0); 5880#L587-1 assume !(1 == ~T4_E~0); 5890#L592-1 assume !(1 == ~E_M~0); 5962#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6079#L602-1 assume !(1 == ~E_2~0); 5998#L607-1 assume !(1 == ~E_3~0); 5997#L612-1 assume !(1 == ~E_4~0); 5707#L617-1 assume { :end_inline_reset_delta_events } true; 5708#L803-2 [2024-11-09 16:07:40,545 INFO L747 eck$LassoCheckResult]: Loop: 5708#L803-2 assume !false; 5861#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5862#L489-1 assume !false; 5985#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5984#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5703#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5704#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5978#L428 assume !(0 != eval_~tmp~0#1); 5977#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5938#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5939#L514-3 assume !(0 == ~M_E~0); 5777#L514-5 assume !(0 == ~T1_E~0); 5778#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5878#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5676#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5677#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5518#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5519#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5948#L549-3 assume !(0 == ~E_3~0); 5730#L554-3 assume !(0 == ~E_4~0); 5731#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5826#L250-18 assume !(1 == ~m_pc~0); 5872#L250-20 is_master_triggered_~__retres1~0#1 := 0; 5840#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5757#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5758#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5686#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5561#L269-18 assume 1 == ~t1_pc~0; 5562#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5638#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5639#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5815#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5816#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5716#L288-18 assume 1 == ~t2_pc~0; 5694#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5527#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5528#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5800#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5692#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5693#L307-18 assume 1 == ~t3_pc~0; 5763#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5658#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5733#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5670#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5671#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5909#L326-18 assume !(1 == ~t4_pc~0); 5910#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 5917#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5776#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5514#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5515#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5961#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5689#L572-5 assume !(1 == ~T1_E~0); 5690#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5715#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6135#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6134#L592-3 assume !(1 == ~E_M~0); 6133#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6132#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6131#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6130#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5701#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5755#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5720#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5736#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 5789#L822 assume !(0 == start_simulation_~tmp~3#1); 5790#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5968#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5833#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5571#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 5546#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5547#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5831#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5941#L835 assume !(0 != start_simulation_~tmp___0~1#1); 5708#L803-2 [2024-11-09 16:07:40,546 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:40,549 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2024-11-09 16:07:40,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:40,550 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692301442] [2024-11-09 16:07:40,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:40,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:40,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:40,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:40,594 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:40,594 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [692301442] [2024-11-09 16:07:40,594 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [692301442] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:40,594 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:40,594 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:40,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [419283080] [2024-11-09 16:07:40,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:40,595 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:40,595 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:40,595 INFO L85 PathProgramCache]: Analyzing trace with hash -1800160059, now seen corresponding path program 1 times [2024-11-09 16:07:40,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:40,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792011603] [2024-11-09 16:07:40,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:40,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:40,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:40,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:40,629 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:40,629 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [792011603] [2024-11-09 16:07:40,629 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [792011603] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:40,630 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:40,630 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:40,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040956899] [2024-11-09 16:07:40,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:40,630 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:40,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:40,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:40,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:40,631 INFO L87 Difference]: Start difference. First operand 719 states and 1057 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:40,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:40,691 INFO L93 Difference]: Finished difference Result 1344 states and 1952 transitions. [2024-11-09 16:07:40,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1344 states and 1952 transitions. [2024-11-09 16:07:40,697 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1264 [2024-11-09 16:07:40,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1344 states to 1344 states and 1952 transitions. [2024-11-09 16:07:40,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1344 [2024-11-09 16:07:40,704 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1344 [2024-11-09 16:07:40,704 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1344 states and 1952 transitions. [2024-11-09 16:07:40,705 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:40,705 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1344 states and 1952 transitions. [2024-11-09 16:07:40,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1344 states and 1952 transitions. [2024-11-09 16:07:40,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1344 to 1276. [2024-11-09 16:07:40,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1276 states, 1276 states have (on average 1.4561128526645768) internal successors, (1858), 1275 states have internal predecessors, (1858), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:40,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1276 states to 1276 states and 1858 transitions. [2024-11-09 16:07:40,727 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1276 states and 1858 transitions. [2024-11-09 16:07:40,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:40,730 INFO L425 stractBuchiCegarLoop]: Abstraction has 1276 states and 1858 transitions. [2024-11-09 16:07:40,730 INFO L332 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2024-11-09 16:07:40,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1276 states and 1858 transitions. [2024-11-09 16:07:40,735 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1196 [2024-11-09 16:07:40,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:40,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:40,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:40,737 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:40,739 INFO L745 eck$LassoCheckResult]: Stem: 7820#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7821#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7945#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7946#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7720#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 7721#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8043#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7664#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7665#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7812#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7692#L514 assume !(0 == ~M_E~0); 7693#L514-2 assume !(0 == ~T1_E~0); 8073#L519-1 assume !(0 == ~T2_E~0); 7652#L524-1 assume !(0 == ~T3_E~0); 7653#L529-1 assume !(0 == ~T4_E~0); 7783#L534-1 assume !(0 == ~E_M~0); 8005#L539-1 assume !(0 == ~E_1~0); 8006#L544-1 assume !(0 == ~E_2~0); 8041#L549-1 assume !(0 == ~E_3~0); 8042#L554-1 assume !(0 == ~E_4~0); 7647#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7648#L250 assume !(1 == ~m_pc~0); 7894#L250-2 is_master_triggered_~__retres1~0#1 := 0; 8045#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7797#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7798#L637 assume !(0 != activate_threads_~tmp~1#1); 7654#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7655#L269 assume !(1 == ~t1_pc~0); 7592#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7591#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7643#L645 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7857#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7858#L288 assume 1 == ~t2_pc~0; 7975#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7847#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7952#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7953#L653 assume !(0 != activate_threads_~tmp___1~0#1); 8000#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7882#L307 assume !(1 == ~t3_pc~0); 7800#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7801#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7595#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7596#L661 assume !(0 != activate_threads_~tmp___2~0#1); 7818#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7819#L326 assume 1 == ~t4_pc~0; 8084#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7608#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7696#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7697#L669 assume !(0 != activate_threads_~tmp___3~0#1); 8002#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8003#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 8046#L572-2 assume !(1 == ~T1_E~0); 7660#L577-1 assume !(1 == ~T2_E~0); 7661#L582-1 assume !(1 == ~T3_E~0); 7983#L587-1 assume !(1 == ~T4_E~0); 7993#L592-1 assume !(1 == ~E_M~0); 7599#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7600#L602-1 assume !(1 == ~E_2~0); 7843#L607-1 assume !(1 == ~E_3~0); 7844#L612-1 assume !(1 == ~E_4~0); 8127#L617-1 assume { :end_inline_reset_delta_events } true; 8466#L803-2 [2024-11-09 16:07:40,739 INFO L747 eck$LassoCheckResult]: Loop: 8466#L803-2 assume !false; 8187#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8188#L489-1 assume !false; 8444#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 7883#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7706#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7962#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7963#L428 assume !(0 != eval_~tmp~0#1); 8434#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8819#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8817#L514-3 assume !(0 == ~M_E~0); 8815#L514-5 assume !(0 == ~T1_E~0); 8813#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8811#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8809#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8807#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8804#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8802#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8800#L549-3 assume !(0 == ~E_3~0); 8798#L554-3 assume !(0 == ~E_4~0); 8748#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8016#L250-18 assume !(1 == ~m_pc~0); 8017#L250-20 is_master_triggered_~__retres1~0#1 := 0; 8766#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8763#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 8762#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8761#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8760#L269-18 assume 1 == ~t1_pc~0; 8758#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8757#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8756#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8755#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8754#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8753#L288-18 assume 1 == ~t2_pc~0; 8752#L289-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8750#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8749#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7891#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7764#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7765#L307-18 assume !(1 == ~t3_pc~0); 7729#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 7730#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7811#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7744#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7745#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8018#L326-18 assume !(1 == ~t4_pc~0); 8019#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 8425#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8424#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8423#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8422#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8421#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8420#L572-5 assume !(1 == ~T1_E~0); 8416#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7645#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7646#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7918#L592-3 assume !(1 == ~E_M~0); 7919#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8410#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8409#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8407#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8408#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8204#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8192#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8186#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 7880#L822 assume !(0 == start_simulation_~tmp~3#1); 7881#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8337#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 8331#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8328#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 8326#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8325#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8322#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 8323#L835 assume !(0 != start_simulation_~tmp___0~1#1); 8466#L803-2 [2024-11-09 16:07:40,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:40,739 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2024-11-09 16:07:40,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:40,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [192135614] [2024-11-09 16:07:40,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:40,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:40,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:40,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:40,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:40,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [192135614] [2024-11-09 16:07:40,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [192135614] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:40,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:40,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:07:40,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1191887932] [2024-11-09 16:07:40,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:40,794 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:40,794 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:40,794 INFO L85 PathProgramCache]: Analyzing trace with hash -748710970, now seen corresponding path program 1 times [2024-11-09 16:07:40,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:40,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640581391] [2024-11-09 16:07:40,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:40,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:40,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:40,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:40,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:40,831 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640581391] [2024-11-09 16:07:40,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640581391] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:40,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:40,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:40,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [733478067] [2024-11-09 16:07:40,833 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:40,833 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:40,834 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:40,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:07:40,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:07:40,834 INFO L87 Difference]: Start difference. First operand 1276 states and 1858 transitions. cyclomatic complexity: 586 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:40,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:40,987 INFO L93 Difference]: Finished difference Result 1345 states and 1927 transitions. [2024-11-09 16:07:40,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1345 states and 1927 transitions. [2024-11-09 16:07:40,994 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1262 [2024-11-09 16:07:41,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1345 states to 1345 states and 1927 transitions. [2024-11-09 16:07:41,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1345 [2024-11-09 16:07:41,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1345 [2024-11-09 16:07:41,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1345 states and 1927 transitions. [2024-11-09 16:07:41,002 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:41,003 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1345 states and 1927 transitions. [2024-11-09 16:07:41,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1345 states and 1927 transitions. [2024-11-09 16:07:41,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1345 to 1345. [2024-11-09 16:07:41,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1345 states, 1345 states have (on average 1.4327137546468403) internal successors, (1927), 1344 states have internal predecessors, (1927), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:41,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1345 states to 1345 states and 1927 transitions. [2024-11-09 16:07:41,023 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1345 states and 1927 transitions. [2024-11-09 16:07:41,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:07:41,024 INFO L425 stractBuchiCegarLoop]: Abstraction has 1345 states and 1927 transitions. [2024-11-09 16:07:41,024 INFO L332 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2024-11-09 16:07:41,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1345 states and 1927 transitions. [2024-11-09 16:07:41,043 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1262 [2024-11-09 16:07:41,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:41,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:41,045 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:41,045 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:41,045 INFO L745 eck$LassoCheckResult]: Stem: 10441#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 10442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 10555#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10556#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10350#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 10351#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10646#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10294#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10295#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10433#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10322#L514 assume !(0 == ~M_E~0); 10323#L514-2 assume !(0 == ~T1_E~0); 10672#L519-1 assume !(0 == ~T2_E~0); 10282#L524-1 assume !(0 == ~T3_E~0); 10283#L529-1 assume !(0 == ~T4_E~0); 10409#L534-1 assume !(0 == ~E_M~0); 10611#L539-1 assume !(0 == ~E_1~0); 10612#L544-1 assume !(0 == ~E_2~0); 10644#L549-1 assume !(0 == ~E_3~0); 10645#L554-1 assume !(0 == ~E_4~0); 10277#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10278#L250 assume !(1 == ~m_pc~0); 10508#L250-2 is_master_triggered_~__retres1~0#1 := 0; 10648#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10422#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10423#L637 assume !(0 != activate_threads_~tmp~1#1); 10284#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10285#L269 assume !(1 == ~t1_pc~0); 10222#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10404#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10718#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10673#L645 assume !(0 != activate_threads_~tmp___0~0#1); 10474#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10475#L288 assume 1 == ~t2_pc~0; 10584#L289 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10468#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10562#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10563#L653 assume !(0 != activate_threads_~tmp___1~0#1); 10606#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10498#L307 assume !(1 == ~t3_pc~0); 10425#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10426#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10225#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10226#L661 assume !(0 != activate_threads_~tmp___2~0#1); 10439#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10440#L326 assume 1 == ~t4_pc~0; 10686#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10238#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10326#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10327#L669 assume !(0 != activate_threads_~tmp___3~0#1); 10608#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10609#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 10649#L572-2 assume !(1 == ~T1_E~0); 11380#L577-1 assume !(1 == ~T2_E~0); 11379#L582-1 assume !(1 == ~T3_E~0); 11378#L587-1 assume !(1 == ~T4_E~0); 11377#L592-1 assume !(1 == ~E_M~0); 11376#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11375#L602-1 assume !(1 == ~E_2~0); 11374#L607-1 assume !(1 == ~E_3~0); 11373#L612-1 assume !(1 == ~E_4~0); 10708#L617-1 assume { :end_inline_reset_delta_events } true; 11298#L803-2 [2024-11-09 16:07:41,045 INFO L747 eck$LassoCheckResult]: Loop: 11298#L803-2 assume !false; 11152#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11151#L489-1 assume !false; 11150#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11149#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11144#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11143#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11142#L428 assume !(0 != eval_~tmp~0#1); 11040#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11039#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11036#L514-3 assume !(0 == ~M_E~0); 11037#L514-5 assume !(0 == ~T1_E~0); 11372#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11371#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11370#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11369#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11368#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11367#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11366#L549-3 assume !(0 == ~E_3~0); 11365#L554-3 assume !(0 == ~E_4~0); 11364#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11363#L250-18 assume !(1 == ~m_pc~0); 11362#L250-20 is_master_triggered_~__retres1~0#1 := 0; 11361#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11360#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 11359#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11358#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11357#L269-18 assume !(1 == ~t1_pc~0); 11355#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 11353#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11351#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 11350#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 11348#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11347#L288-18 assume !(1 == ~t2_pc~0); 11345#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 11344#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11343#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11342#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11341#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11340#L307-18 assume 1 == ~t3_pc~0; 11338#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11337#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11336#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11335#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11334#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11333#L326-18 assume !(1 == ~t4_pc~0); 11331#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 11330#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11329#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11328#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11327#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11326#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10711#L572-5 assume !(1 == ~T1_E~0); 11325#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11324#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11323#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11322#L592-3 assume !(1 == ~E_M~0); 11321#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11320#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11319#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11318#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10401#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11317#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11312#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11311#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 11310#L822 assume !(0 == start_simulation_~tmp~3#1); 10912#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 11308#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 11304#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 11303#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 11302#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11301#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11300#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 11299#L835 assume !(0 != start_simulation_~tmp___0~1#1); 11298#L803-2 [2024-11-09 16:07:41,046 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:41,046 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2024-11-09 16:07:41,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:41,047 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820160384] [2024-11-09 16:07:41,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:41,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:41,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:41,082 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:41,082 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:41,083 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [820160384] [2024-11-09 16:07:41,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [820160384] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:41,083 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:41,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:41,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [118328854] [2024-11-09 16:07:41,083 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:41,084 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:41,084 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:41,084 INFO L85 PathProgramCache]: Analyzing trace with hash -781202935, now seen corresponding path program 1 times [2024-11-09 16:07:41,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:41,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539476205] [2024-11-09 16:07:41,084 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:41,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:41,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:41,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:41,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:41,119 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1539476205] [2024-11-09 16:07:41,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1539476205] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:41,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:41,120 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:41,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1817952900] [2024-11-09 16:07:41,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:41,120 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:41,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:41,121 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:41,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:41,121 INFO L87 Difference]: Start difference. First operand 1345 states and 1927 transitions. cyclomatic complexity: 586 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:41,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:41,173 INFO L93 Difference]: Finished difference Result 2430 states and 3458 transitions. [2024-11-09 16:07:41,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2430 states and 3458 transitions. [2024-11-09 16:07:41,184 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2336 [2024-11-09 16:07:41,194 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2430 states to 2430 states and 3458 transitions. [2024-11-09 16:07:41,194 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2430 [2024-11-09 16:07:41,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2430 [2024-11-09 16:07:41,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2430 states and 3458 transitions. [2024-11-09 16:07:41,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:41,198 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2430 states and 3458 transitions. [2024-11-09 16:07:41,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2430 states and 3458 transitions. [2024-11-09 16:07:41,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2430 to 2422. [2024-11-09 16:07:41,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2422 states, 2422 states have (on average 1.4244426094137077) internal successors, (3450), 2421 states have internal predecessors, (3450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:41,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2422 states to 2422 states and 3450 transitions. [2024-11-09 16:07:41,234 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2422 states and 3450 transitions. [2024-11-09 16:07:41,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:41,235 INFO L425 stractBuchiCegarLoop]: Abstraction has 2422 states and 3450 transitions. [2024-11-09 16:07:41,236 INFO L332 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2024-11-09 16:07:41,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2422 states and 3450 transitions. [2024-11-09 16:07:41,244 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2328 [2024-11-09 16:07:41,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:41,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:41,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:41,245 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:41,245 INFO L745 eck$LassoCheckResult]: Stem: 14226#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 14227#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 14345#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14346#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14133#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 14134#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14445#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14076#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14077#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14219#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14106#L514 assume !(0 == ~M_E~0); 14107#L514-2 assume !(0 == ~T1_E~0); 14470#L519-1 assume !(0 == ~T2_E~0); 14064#L524-1 assume !(0 == ~T3_E~0); 14065#L529-1 assume !(0 == ~T4_E~0); 14192#L534-1 assume !(0 == ~E_M~0); 14405#L539-1 assume !(0 == ~E_1~0); 14406#L544-1 assume !(0 == ~E_2~0); 14442#L549-1 assume !(0 == ~E_3~0); 14443#L554-1 assume !(0 == ~E_4~0); 14059#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14060#L250 assume !(1 == ~m_pc~0); 14295#L250-2 is_master_triggered_~__retres1~0#1 := 0; 14446#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14207#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14208#L637 assume !(0 != activate_threads_~tmp~1#1); 14066#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14067#L269 assume !(1 == ~t1_pc~0); 14004#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14187#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14547#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 14471#L645 assume !(0 != activate_threads_~tmp___0~0#1); 14260#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14261#L288 assume !(1 == ~t2_pc~0); 14251#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14252#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14351#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14352#L653 assume !(0 != activate_threads_~tmp___1~0#1); 14399#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14284#L307 assume !(1 == ~t3_pc~0); 14210#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14211#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14007#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14008#L661 assume !(0 != activate_threads_~tmp___2~0#1); 14224#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14225#L326 assume 1 == ~t4_pc~0; 14488#L327 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14020#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14108#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14109#L669 assume !(0 != activate_threads_~tmp___3~0#1); 14401#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14402#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 14447#L572-2 assume !(1 == ~T1_E~0); 15315#L577-1 assume !(1 == ~T2_E~0); 15183#L582-1 assume !(1 == ~T3_E~0); 15180#L587-1 assume !(1 == ~T4_E~0); 15178#L592-1 assume !(1 == ~E_M~0); 14013#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14014#L602-1 assume !(1 == ~E_2~0); 15170#L607-1 assume !(1 == ~E_3~0); 15168#L612-1 assume !(1 == ~E_4~0); 14533#L617-1 assume { :end_inline_reset_delta_events } true; 15142#L803-2 [2024-11-09 16:07:41,245 INFO L747 eck$LassoCheckResult]: Loop: 15142#L803-2 assume !false; 15137#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15135#L489-1 assume !false; 15134#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15133#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15123#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15121#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15118#L428 assume !(0 != eval_~tmp~0#1); 15115#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15113#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15110#L514-3 assume !(0 == ~M_E~0); 15106#L514-5 assume !(0 == ~T1_E~0); 15103#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15101#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15099#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15097#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15095#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15092#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15090#L549-3 assume !(0 == ~E_3~0); 15088#L554-3 assume !(0 == ~E_4~0); 15087#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15084#L250-18 assume !(1 == ~m_pc~0); 15080#L250-20 is_master_triggered_~__retres1~0#1 := 0; 15076#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15073#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 15070#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15066#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15067#L269-18 assume !(1 == ~t1_pc~0); 15387#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 15386#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15385#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 15384#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 15383#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15382#L288-18 assume !(1 == ~t2_pc~0); 15381#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 15380#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15379#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 15378#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15028#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15029#L307-18 assume 1 == ~t3_pc~0; 15368#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15367#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15366#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15365#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15364#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15011#L326-18 assume !(1 == ~t4_pc~0); 15008#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 15005#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15003#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15001#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14998#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14999#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14996#L572-5 assume !(1 == ~T1_E~0); 14987#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14988#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15349#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14783#L592-3 assume !(1 == ~E_M~0); 14780#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14781#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14774#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14775#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14766#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 14767#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 14757#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 14758#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 14751#L822 assume !(0 == start_simulation_~tmp~3#1); 14752#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 15291#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 15286#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 15284#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 15172#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15171#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15169#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 15152#L835 assume !(0 != start_simulation_~tmp___0~1#1); 15142#L803-2 [2024-11-09 16:07:41,246 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:41,246 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2024-11-09 16:07:41,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:41,246 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099171917] [2024-11-09 16:07:41,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:41,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:41,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:41,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:41,276 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:41,277 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099171917] [2024-11-09 16:07:41,277 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099171917] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:41,277 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:41,277 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:41,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1545277847] [2024-11-09 16:07:41,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:41,277 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:41,278 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:41,278 INFO L85 PathProgramCache]: Analyzing trace with hash -781202935, now seen corresponding path program 2 times [2024-11-09 16:07:41,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:41,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715917918] [2024-11-09 16:07:41,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:41,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:41,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:41,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:41,305 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:41,305 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715917918] [2024-11-09 16:07:41,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [715917918] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:41,306 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:41,306 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:41,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2106248038] [2024-11-09 16:07:41,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:41,306 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:41,307 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:41,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:41,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:41,307 INFO L87 Difference]: Start difference. First operand 2422 states and 3450 transitions. cyclomatic complexity: 1036 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:41,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:41,369 INFO L93 Difference]: Finished difference Result 4413 states and 6255 transitions. [2024-11-09 16:07:41,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4413 states and 6255 transitions. [2024-11-09 16:07:41,390 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4288 [2024-11-09 16:07:41,409 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4413 states to 4413 states and 6255 transitions. [2024-11-09 16:07:41,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4413 [2024-11-09 16:07:41,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4413 [2024-11-09 16:07:41,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4413 states and 6255 transitions. [2024-11-09 16:07:41,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:41,418 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4413 states and 6255 transitions. [2024-11-09 16:07:41,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4413 states and 6255 transitions. [2024-11-09 16:07:41,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4413 to 4397. [2024-11-09 16:07:41,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4397 states, 4397 states have (on average 1.4189219922674552) internal successors, (6239), 4396 states have internal predecessors, (6239), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:41,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4397 states to 4397 states and 6239 transitions. [2024-11-09 16:07:41,529 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4397 states and 6239 transitions. [2024-11-09 16:07:41,530 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:41,531 INFO L425 stractBuchiCegarLoop]: Abstraction has 4397 states and 6239 transitions. [2024-11-09 16:07:41,531 INFO L332 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2024-11-09 16:07:41,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4397 states and 6239 transitions. [2024-11-09 16:07:41,547 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4272 [2024-11-09 16:07:41,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:41,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:41,549 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:41,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:41,549 INFO L745 eck$LassoCheckResult]: Stem: 21071#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 21072#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 21180#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21181#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20976#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 20977#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21270#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20921#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20922#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21063#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20947#L514 assume !(0 == ~M_E~0); 20948#L514-2 assume !(0 == ~T1_E~0); 21291#L519-1 assume !(0 == ~T2_E~0); 20907#L524-1 assume !(0 == ~T3_E~0); 20908#L529-1 assume !(0 == ~T4_E~0); 21035#L534-1 assume !(0 == ~E_M~0); 21241#L539-1 assume !(0 == ~E_1~0); 21242#L544-1 assume !(0 == ~E_2~0); 21268#L549-1 assume !(0 == ~E_3~0); 21269#L554-1 assume !(0 == ~E_4~0); 20902#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20903#L250 assume !(1 == ~m_pc~0); 21132#L250-2 is_master_triggered_~__retres1~0#1 := 0; 21272#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21050#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21051#L637 assume !(0 != activate_threads_~tmp~1#1); 20909#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20910#L269 assume !(1 == ~t1_pc~0); 20846#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21030#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21351#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21292#L645 assume !(0 != activate_threads_~tmp___0~0#1); 21100#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21101#L288 assume !(1 == ~t2_pc~0); 21095#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21096#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21188#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21189#L653 assume !(0 != activate_threads_~tmp___1~0#1); 21236#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21122#L307 assume !(1 == ~t3_pc~0); 21053#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21054#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20849#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20850#L661 assume !(0 != activate_threads_~tmp___2~0#1); 21069#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21070#L326 assume !(1 == ~t4_pc~0); 20861#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20862#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20951#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20952#L669 assume !(0 != activate_threads_~tmp___3~0#1); 21238#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21239#L572 assume 1 == ~M_E~0;~M_E~0 := 2; 21273#L572-2 assume !(1 == ~T1_E~0); 20917#L577-1 assume !(1 == ~T2_E~0); 20918#L582-1 assume !(1 == ~T3_E~0); 21228#L587-1 assume !(1 == ~T4_E~0); 21229#L592-1 assume !(1 == ~E_M~0); 20853#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20854#L602-1 assume !(1 == ~E_2~0); 21092#L607-1 assume !(1 == ~E_3~0); 21093#L612-1 assume !(1 == ~E_4~0); 21033#L617-1 assume { :end_inline_reset_delta_events } true; 21034#L803-2 [2024-11-09 16:07:41,550 INFO L747 eck$LassoCheckResult]: Loop: 21034#L803-2 assume !false; 21198#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21150#L489-1 assume !false; 21151#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 21123#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 20962#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 21029#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 21200#L428 assume !(0 != eval_~tmp~0#1); 21342#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24049#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24047#L514-3 assume !(0 == ~M_E~0); 24045#L514-5 assume !(0 == ~T1_E~0); 24043#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24041#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24039#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24037#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24035#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24033#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24031#L549-3 assume !(0 == ~E_3~0); 24029#L554-3 assume !(0 == ~E_4~0); 24027#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24025#L250-18 assume !(1 == ~m_pc~0); 24023#L250-20 is_master_triggered_~__retres1~0#1 := 0; 24021#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24019#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24017#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24015#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24013#L269-18 assume 1 == ~t1_pc~0; 24009#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24005#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24001#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23997#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23995#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23993#L288-18 assume !(1 == ~t2_pc~0); 23991#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 23989#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23987#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23985#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23983#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23981#L307-18 assume 1 == ~t3_pc~0; 23977#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23975#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23973#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23971#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23969#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23967#L326-18 assume !(1 == ~t4_pc~0); 23965#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 23963#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23961#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23959#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23957#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23956#L572-3 assume 1 == ~M_E~0;~M_E~0 := 2; 23953#L572-5 assume !(1 == ~T1_E~0); 23951#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23949#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23947#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23945#L592-3 assume !(1 == ~E_M~0); 23943#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23941#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23939#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23938#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23935#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23934#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23929#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23928#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 23927#L822 assume !(0 == start_simulation_~tmp~3#1); 21237#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 23925#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 23921#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 23920#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 23919#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21162#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21163#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 21286#L835 assume !(0 != start_simulation_~tmp___0~1#1); 21034#L803-2 [2024-11-09 16:07:41,550 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:41,550 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2024-11-09 16:07:41,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:41,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463804191] [2024-11-09 16:07:41,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:41,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:41,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:41,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:41,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:41,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [463804191] [2024-11-09 16:07:41,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [463804191] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:41,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:41,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:41,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549264456] [2024-11-09 16:07:41,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:41,601 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:41,601 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:41,601 INFO L85 PathProgramCache]: Analyzing trace with hash 2009632518, now seen corresponding path program 1 times [2024-11-09 16:07:41,601 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:41,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26811929] [2024-11-09 16:07:41,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:41,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:41,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:41,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:41,640 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:41,640 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [26811929] [2024-11-09 16:07:41,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [26811929] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:41,641 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:41,641 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:41,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1236289706] [2024-11-09 16:07:41,641 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:41,641 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:41,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:41,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:41,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:41,643 INFO L87 Difference]: Start difference. First operand 4397 states and 6239 transitions. cyclomatic complexity: 1858 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:41,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:41,691 INFO L93 Difference]: Finished difference Result 6588 states and 9333 transitions. [2024-11-09 16:07:41,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6588 states and 9333 transitions. [2024-11-09 16:07:41,723 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6448 [2024-11-09 16:07:41,758 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6588 states to 6588 states and 9333 transitions. [2024-11-09 16:07:41,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6588 [2024-11-09 16:07:41,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6588 [2024-11-09 16:07:41,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6588 states and 9333 transitions. [2024-11-09 16:07:41,774 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:41,775 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6588 states and 9333 transitions. [2024-11-09 16:07:41,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6588 states and 9333 transitions. [2024-11-09 16:07:41,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6588 to 4775. [2024-11-09 16:07:41,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4775 states, 4775 states have (on average 1.4157068062827225) internal successors, (6760), 4774 states have internal predecessors, (6760), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:41,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4775 states to 4775 states and 6760 transitions. [2024-11-09 16:07:41,855 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4775 states and 6760 transitions. [2024-11-09 16:07:41,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:41,856 INFO L425 stractBuchiCegarLoop]: Abstraction has 4775 states and 6760 transitions. [2024-11-09 16:07:41,856 INFO L332 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2024-11-09 16:07:41,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4775 states and 6760 transitions. [2024-11-09 16:07:41,868 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4660 [2024-11-09 16:07:41,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:41,869 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:41,869 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:41,869 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:41,870 INFO L745 eck$LassoCheckResult]: Stem: 32058#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 32059#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 32166#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32167#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31968#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 31969#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32245#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31911#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 31912#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32050#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31938#L514 assume !(0 == ~M_E~0); 31939#L514-2 assume !(0 == ~T1_E~0); 32266#L519-1 assume !(0 == ~T2_E~0); 31899#L524-1 assume !(0 == ~T3_E~0); 31900#L529-1 assume !(0 == ~T4_E~0); 32026#L534-1 assume !(0 == ~E_M~0); 32219#L539-1 assume !(0 == ~E_1~0); 32220#L544-1 assume !(0 == ~E_2~0); 32243#L549-1 assume !(0 == ~E_3~0); 32244#L554-1 assume !(0 == ~E_4~0); 31894#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31895#L250 assume !(1 == ~m_pc~0); 32122#L250-2 is_master_triggered_~__retres1~0#1 := 0; 32247#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32039#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 32040#L637 assume !(0 != activate_threads_~tmp~1#1); 31901#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31902#L269 assume !(1 == ~t1_pc~0); 31838#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 32021#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32312#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 32267#L645 assume !(0 != activate_threads_~tmp___0~0#1); 32087#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32088#L288 assume !(1 == ~t2_pc~0); 32082#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 32083#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32174#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 32175#L653 assume !(0 != activate_threads_~tmp___1~0#1); 32214#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32112#L307 assume !(1 == ~t3_pc~0); 32042#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32043#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31841#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31842#L661 assume !(0 != activate_threads_~tmp___2~0#1); 32056#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32057#L326 assume !(1 == ~t4_pc~0); 31853#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 31854#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31942#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31943#L669 assume !(0 != activate_threads_~tmp___3~0#1); 32216#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32217#L572 assume !(1 == ~M_E~0); 32248#L572-2 assume !(1 == ~T1_E~0); 31907#L577-1 assume !(1 == ~T2_E~0); 31908#L582-1 assume !(1 == ~T3_E~0); 32198#L587-1 assume !(1 == ~T4_E~0); 32207#L592-1 assume !(1 == ~E_M~0); 31845#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 31846#L602-1 assume !(1 == ~E_2~0); 32079#L607-1 assume !(1 == ~E_3~0); 32080#L612-1 assume !(1 == ~E_4~0); 32024#L617-1 assume { :end_inline_reset_delta_events } true; 32025#L803-2 [2024-11-09 16:07:41,870 INFO L747 eck$LassoCheckResult]: Loop: 32025#L803-2 assume !false; 35202#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35198#L489-1 assume !false; 35194#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 35175#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 35166#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 35161#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 35156#L428 assume !(0 != eval_~tmp~0#1); 35151#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35147#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35143#L514-3 assume !(0 == ~M_E~0); 35138#L514-5 assume !(0 == ~T1_E~0); 35133#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35117#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35107#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35101#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35096#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35091#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35048#L549-3 assume !(0 == ~E_3~0); 35039#L554-3 assume !(0 == ~E_4~0); 35031#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35023#L250-18 assume !(1 == ~m_pc~0); 35016#L250-20 is_master_triggered_~__retres1~0#1 := 0; 35011#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35009#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 35007#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 35001#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34999#L269-18 assume 1 == ~t1_pc~0; 34996#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34992#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34989#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34986#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34984#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34982#L288-18 assume !(1 == ~t2_pc~0); 34980#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 34978#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34976#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34974#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34972#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34970#L307-18 assume 1 == ~t3_pc~0; 34967#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34965#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34963#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34961#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34958#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34956#L326-18 assume !(1 == ~t4_pc~0); 34954#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 34952#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34950#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34948#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34945#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34942#L572-3 assume !(1 == ~M_E~0); 33534#L572-5 assume !(1 == ~T1_E~0); 34937#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34935#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34933#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34931#L592-3 assume !(1 == ~E_M~0); 34929#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 34927#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34925#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34923#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34921#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 34918#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 34912#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34840#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 34829#L822 assume !(0 == start_simulation_~tmp~3#1); 34830#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 35256#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 35251#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 35249#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 35246#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35244#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35236#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 35235#L835 assume !(0 != start_simulation_~tmp___0~1#1); 32025#L803-2 [2024-11-09 16:07:41,870 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:41,870 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2024-11-09 16:07:41,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:41,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1577823520] [2024-11-09 16:07:41,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:41,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:41,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:41,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:41,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:41,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1577823520] [2024-11-09 16:07:41,927 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1577823520] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:41,927 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:41,927 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:41,927 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634948303] [2024-11-09 16:07:41,927 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:41,928 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:41,929 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:41,929 INFO L85 PathProgramCache]: Analyzing trace with hash 204194184, now seen corresponding path program 1 times [2024-11-09 16:07:41,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:41,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086956117] [2024-11-09 16:07:41,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:41,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:41,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:42,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:42,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:42,003 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086956117] [2024-11-09 16:07:42,003 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086956117] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:42,003 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:42,003 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:42,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775284325] [2024-11-09 16:07:42,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:42,004 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:42,004 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:42,004 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:07:42,004 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:07:42,005 INFO L87 Difference]: Start difference. First operand 4775 states and 6760 transitions. cyclomatic complexity: 1993 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:42,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:42,116 INFO L93 Difference]: Finished difference Result 6527 states and 9077 transitions. [2024-11-09 16:07:42,116 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6527 states and 9077 transitions. [2024-11-09 16:07:42,139 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6310 [2024-11-09 16:07:42,160 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6527 states to 6527 states and 9077 transitions. [2024-11-09 16:07:42,160 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6527 [2024-11-09 16:07:42,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6527 [2024-11-09 16:07:42,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6527 states and 9077 transitions. [2024-11-09 16:07:42,171 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:42,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6527 states and 9077 transitions. [2024-11-09 16:07:42,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6527 states and 9077 transitions. [2024-11-09 16:07:42,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6527 to 5362. [2024-11-09 16:07:42,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5362 states, 5362 states have (on average 1.3979858261842597) internal successors, (7496), 5361 states have internal predecessors, (7496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:42,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5362 states to 5362 states and 7496 transitions. [2024-11-09 16:07:42,246 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5362 states and 7496 transitions. [2024-11-09 16:07:42,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:07:42,247 INFO L425 stractBuchiCegarLoop]: Abstraction has 5362 states and 7496 transitions. [2024-11-09 16:07:42,247 INFO L332 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2024-11-09 16:07:42,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5362 states and 7496 transitions. [2024-11-09 16:07:42,258 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5204 [2024-11-09 16:07:42,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:42,259 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:42,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:42,259 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:42,260 INFO L745 eck$LassoCheckResult]: Stem: 43369#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 43370#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 43477#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43478#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 43280#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 43281#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43555#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43221#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43222#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43361#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 43251#L514 assume !(0 == ~M_E~0); 43252#L514-2 assume !(0 == ~T1_E~0); 43575#L519-1 assume !(0 == ~T2_E~0); 43209#L524-1 assume !(0 == ~T3_E~0); 43210#L529-1 assume !(0 == ~T4_E~0); 43336#L534-1 assume !(0 == ~E_M~0); 43529#L539-1 assume 0 == ~E_1~0;~E_1~0 := 1; 43530#L544-1 assume !(0 == ~E_2~0); 43553#L549-1 assume !(0 == ~E_3~0); 43554#L554-1 assume !(0 == ~E_4~0); 43204#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43205#L250 assume !(1 == ~m_pc~0); 43557#L250-2 is_master_triggered_~__retres1~0#1 := 0; 43558#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43658#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43657#L637 assume !(0 != activate_threads_~tmp~1#1); 43656#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43233#L269 assume !(1 == ~t1_pc~0); 43234#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 43660#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43659#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43652#L645 assume !(0 != activate_threads_~tmp___0~0#1); 43651#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43650#L288 assume !(1 == ~t2_pc~0); 43649#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 43648#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43647#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43646#L653 assume !(0 != activate_threads_~tmp___1~0#1); 43645#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43644#L307 assume !(1 == ~t3_pc~0); 43642#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 43641#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43640#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43639#L661 assume !(0 != activate_threads_~tmp___2~0#1); 43638#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43637#L326 assume !(1 == ~t4_pc~0); 43636#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 43635#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43634#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 43633#L669 assume !(0 != activate_threads_~tmp___3~0#1); 43632#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 43631#L572 assume !(1 == ~M_E~0); 43630#L572-2 assume !(1 == ~T1_E~0); 43629#L577-1 assume !(1 == ~T2_E~0); 43628#L582-1 assume !(1 == ~T3_E~0); 43627#L587-1 assume !(1 == ~T4_E~0); 43626#L592-1 assume !(1 == ~E_M~0); 43625#L597-1 assume 1 == ~E_1~0;~E_1~0 := 2; 43158#L602-1 assume !(1 == ~E_2~0); 43389#L607-1 assume !(1 == ~E_3~0); 43390#L612-1 assume !(1 == ~E_4~0); 43334#L617-1 assume { :end_inline_reset_delta_events } true; 43335#L803-2 [2024-11-09 16:07:42,260 INFO L747 eck$LassoCheckResult]: Loop: 43335#L803-2 assume !false; 46128#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45501#L489-1 assume !false; 45494#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45388#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45382#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45380#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 45377#L428 assume !(0 != eval_~tmp~0#1); 45375#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45373#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45371#L514-3 assume !(0 == ~M_E~0); 45369#L514-5 assume !(0 == ~T1_E~0); 45368#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45366#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45355#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45345#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45335#L539-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45334#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45333#L549-3 assume !(0 == ~E_3~0); 45332#L554-3 assume !(0 == ~E_4~0); 45331#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45330#L250-18 assume !(1 == ~m_pc~0); 45329#L250-20 is_master_triggered_~__retres1~0#1 := 0; 45328#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45327#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 45326#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45325#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45324#L269-18 assume 1 == ~t1_pc~0; 45321#L270-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45319#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45317#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45315#L645-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45314#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45313#L288-18 assume !(1 == ~t2_pc~0); 45312#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 45311#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45310#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 45309#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 45308#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45307#L307-18 assume 1 == ~t3_pc~0; 45305#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 45304#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45303#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 45302#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 45301#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45300#L326-18 assume !(1 == ~t4_pc~0); 45299#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 45298#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45297#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 45296#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 45295#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 45294#L572-3 assume !(1 == ~M_E~0); 45157#L572-5 assume !(1 == ~T1_E~0); 45293#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45292#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45291#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 45290#L592-3 assume !(1 == ~E_M~0); 45288#L597-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45283#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45280#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45273#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45270#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 45267#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45257#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45251#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 45117#L822 assume !(0 == start_simulation_~tmp~3#1); 45118#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 46160#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 46155#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 46153#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 46151#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46149#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46147#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 46145#L835 assume !(0 != start_simulation_~tmp___0~1#1); 43335#L803-2 [2024-11-09 16:07:42,260 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:42,260 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2024-11-09 16:07:42,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:42,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760464540] [2024-11-09 16:07:42,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:42,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:42,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:42,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:42,293 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:42,293 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [760464540] [2024-11-09 16:07:42,293 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [760464540] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:42,293 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:42,293 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:42,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1234814236] [2024-11-09 16:07:42,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:42,294 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:42,294 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:42,294 INFO L85 PathProgramCache]: Analyzing trace with hash 204194184, now seen corresponding path program 2 times [2024-11-09 16:07:42,294 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:42,294 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590398977] [2024-11-09 16:07:42,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:42,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:42,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:42,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:42,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:42,319 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [590398977] [2024-11-09 16:07:42,319 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [590398977] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:42,319 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:42,319 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:42,319 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1914067557] [2024-11-09 16:07:42,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:42,320 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:42,320 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:42,320 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:07:42,320 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:07:42,320 INFO L87 Difference]: Start difference. First operand 5362 states and 7496 transitions. cyclomatic complexity: 2142 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:42,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:42,390 INFO L93 Difference]: Finished difference Result 5478 states and 7611 transitions. [2024-11-09 16:07:42,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5478 states and 7611 transitions. [2024-11-09 16:07:42,409 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5342 [2024-11-09 16:07:42,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5478 states to 5478 states and 7611 transitions. [2024-11-09 16:07:42,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5478 [2024-11-09 16:07:42,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5478 [2024-11-09 16:07:42,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5478 states and 7611 transitions. [2024-11-09 16:07:42,435 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:42,435 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5478 states and 7611 transitions. [2024-11-09 16:07:42,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5478 states and 7611 transitions. [2024-11-09 16:07:42,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5478 to 4556. [2024-11-09 16:07:42,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4556 states, 4556 states have (on average 1.3926690079016681) internal successors, (6345), 4555 states have internal predecessors, (6345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:42,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4556 states to 4556 states and 6345 transitions. [2024-11-09 16:07:42,564 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4556 states and 6345 transitions. [2024-11-09 16:07:42,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:07:42,565 INFO L425 stractBuchiCegarLoop]: Abstraction has 4556 states and 6345 transitions. [2024-11-09 16:07:42,565 INFO L332 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2024-11-09 16:07:42,565 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4556 states and 6345 transitions. [2024-11-09 16:07:42,578 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4444 [2024-11-09 16:07:42,578 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:42,578 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:42,579 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:42,579 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:42,579 INFO L745 eck$LassoCheckResult]: Stem: 54217#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 54218#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 54326#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54327#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54126#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 54127#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54411#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54072#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 54073#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54209#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 54100#L514 assume !(0 == ~M_E~0); 54101#L514-2 assume !(0 == ~T1_E~0); 54430#L519-1 assume !(0 == ~T2_E~0); 54058#L524-1 assume !(0 == ~T3_E~0); 54059#L529-1 assume !(0 == ~T4_E~0); 54184#L534-1 assume !(0 == ~E_M~0); 54381#L539-1 assume !(0 == ~E_1~0); 54382#L544-1 assume !(0 == ~E_2~0); 54408#L549-1 assume !(0 == ~E_3~0); 54409#L554-1 assume !(0 == ~E_4~0); 54053#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54054#L250 assume !(1 == ~m_pc~0); 54285#L250-2 is_master_triggered_~__retres1~0#1 := 0; 54412#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54198#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 54199#L637 assume !(0 != activate_threads_~tmp~1#1); 54062#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54063#L269 assume !(1 == ~t1_pc~0); 53999#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54179#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54049#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54050#L645 assume !(0 != activate_threads_~tmp___0~0#1); 54247#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54248#L288 assume !(1 == ~t2_pc~0); 54240#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 54241#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54332#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54333#L653 assume !(0 != activate_threads_~tmp___1~0#1); 54375#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54273#L307 assume !(1 == ~t3_pc~0); 54201#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54202#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54002#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 54003#L661 assume !(0 != activate_threads_~tmp___2~0#1); 54215#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54216#L326 assume !(1 == ~t4_pc~0); 54014#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 54015#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54102#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 54103#L669 assume !(0 != activate_threads_~tmp___3~0#1); 54377#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54378#L572 assume !(1 == ~M_E~0); 54413#L572-2 assume !(1 == ~T1_E~0); 54068#L577-1 assume !(1 == ~T2_E~0); 54069#L582-1 assume !(1 == ~T3_E~0); 54360#L587-1 assume !(1 == ~T4_E~0); 54369#L592-1 assume !(1 == ~E_M~0); 54012#L597-1 assume !(1 == ~E_1~0); 54013#L602-1 assume !(1 == ~E_2~0); 54237#L607-1 assume !(1 == ~E_3~0); 54238#L612-1 assume !(1 == ~E_4~0); 54182#L617-1 assume { :end_inline_reset_delta_events } true; 54183#L803-2 [2024-11-09 16:07:42,580 INFO L747 eck$LassoCheckResult]: Loop: 54183#L803-2 assume !false; 55811#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55809#L489-1 assume !false; 55807#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 55805#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 55799#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 55797#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 55795#L428 assume !(0 != eval_~tmp~0#1); 55796#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57188#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57187#L514-3 assume !(0 == ~M_E~0); 57185#L514-5 assume !(0 == ~T1_E~0); 57183#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57181#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57179#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57177#L534-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57175#L539-3 assume !(0 == ~E_1~0); 57173#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57171#L549-3 assume !(0 == ~E_3~0); 57169#L554-3 assume !(0 == ~E_4~0); 57167#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57165#L250-18 assume !(1 == ~m_pc~0); 57163#L250-20 is_master_triggered_~__retres1~0#1 := 0; 57161#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57159#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 57157#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57155#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57153#L269-18 assume !(1 == ~t1_pc~0); 57150#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 57147#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57145#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 57143#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 57141#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57139#L288-18 assume !(1 == ~t2_pc~0); 57137#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 57135#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57132#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57130#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57128#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57126#L307-18 assume 1 == ~t3_pc~0; 57123#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57121#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57118#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57116#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57114#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57112#L326-18 assume !(1 == ~t4_pc~0); 57110#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 57108#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57106#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57104#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57102#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57100#L572-3 assume !(1 == ~M_E~0); 56247#L572-5 assume !(1 == ~T1_E~0); 57050#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57048#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57046#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57044#L592-3 assume !(1 == ~E_M~0); 57042#L597-3 assume !(1 == ~E_1~0); 57040#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57036#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57032#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57029#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 56976#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 56970#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 56968#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 56163#L822 assume !(0 == start_simulation_~tmp~3#1); 56160#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 56155#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 56150#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 56148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 56145#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 56143#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 56141#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 56139#L835 assume !(0 != start_simulation_~tmp___0~1#1); 54183#L803-2 [2024-11-09 16:07:42,580 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:42,580 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2024-11-09 16:07:42,580 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:42,580 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543696435] [2024-11-09 16:07:42,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:42,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:42,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:42,589 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:42,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:42,626 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:42,626 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:42,628 INFO L85 PathProgramCache]: Analyzing trace with hash 553707211, now seen corresponding path program 1 times [2024-11-09 16:07:42,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:42,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442669974] [2024-11-09 16:07:42,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:42,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:42,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:42,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:42,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:42,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1442669974] [2024-11-09 16:07:42,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1442669974] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:42,654 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:42,654 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:42,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1908980621] [2024-11-09 16:07:42,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:42,655 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:42,655 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:42,656 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:42,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:42,656 INFO L87 Difference]: Start difference. First operand 4556 states and 6345 transitions. cyclomatic complexity: 1797 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:42,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:42,726 INFO L93 Difference]: Finished difference Result 6981 states and 9610 transitions. [2024-11-09 16:07:42,726 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6981 states and 9610 transitions. [2024-11-09 16:07:42,750 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6810 [2024-11-09 16:07:42,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6981 states to 6981 states and 9610 transitions. [2024-11-09 16:07:42,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6981 [2024-11-09 16:07:42,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6981 [2024-11-09 16:07:42,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6981 states and 9610 transitions. [2024-11-09 16:07:42,783 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:42,783 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6981 states and 9610 transitions. [2024-11-09 16:07:42,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6981 states and 9610 transitions. [2024-11-09 16:07:42,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6981 to 6977. [2024-11-09 16:07:42,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6977 states, 6977 states have (on average 1.3768095169843773) internal successors, (9606), 6976 states have internal predecessors, (9606), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:42,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6977 states to 6977 states and 9606 transitions. [2024-11-09 16:07:42,959 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6977 states and 9606 transitions. [2024-11-09 16:07:42,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:42,960 INFO L425 stractBuchiCegarLoop]: Abstraction has 6977 states and 9606 transitions. [2024-11-09 16:07:42,964 INFO L332 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2024-11-09 16:07:42,964 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6977 states and 9606 transitions. [2024-11-09 16:07:42,988 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6806 [2024-11-09 16:07:42,988 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:42,988 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:42,989 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:42,989 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:42,990 INFO L745 eck$LassoCheckResult]: Stem: 65761#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 65762#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 65870#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 65871#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 65670#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 65671#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 65954#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 65615#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 65616#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65753#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 65643#L514 assume !(0 == ~M_E~0); 65644#L514-2 assume !(0 == ~T1_E~0); 65973#L519-1 assume !(0 == ~T2_E~0); 65601#L524-1 assume !(0 == ~T3_E~0); 65602#L529-1 assume !(0 == ~T4_E~0); 65728#L534-1 assume 0 == ~E_M~0;~E_M~0 := 1; 65977#L539-1 assume !(0 == ~E_1~0); 65950#L544-1 assume !(0 == ~E_2~0); 65951#L549-1 assume !(0 == ~E_3~0); 65981#L554-1 assume !(0 == ~E_4~0); 65982#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65824#L250 assume !(1 == ~m_pc~0); 65825#L250-2 is_master_triggered_~__retres1~0#1 := 0; 65974#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65741#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 65742#L637 assume !(0 != activate_threads_~tmp~1#1); 65603#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65604#L269 assume !(1 == ~t1_pc~0); 66052#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 65833#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65590#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 65591#L645 assume !(0 != activate_threads_~tmp___0~0#1); 65789#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65790#L288 assume !(1 == ~t2_pc~0); 65894#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 66049#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65876#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65877#L653 assume !(0 != activate_threads_~tmp___1~0#1); 65920#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65813#L307 assume !(1 == ~t3_pc~0); 65744#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 65745#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66045#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66044#L661 assume !(0 != activate_threads_~tmp___2~0#1); 66043#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66042#L326 assume !(1 == ~t4_pc~0); 66041#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 66040#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66039#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66038#L669 assume !(0 != activate_threads_~tmp___3~0#1); 66037#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66036#L572 assume !(1 == ~M_E~0); 66035#L572-2 assume !(1 == ~T1_E~0); 66034#L577-1 assume !(1 == ~T2_E~0); 66033#L582-1 assume !(1 == ~T3_E~0); 66032#L587-1 assume !(1 == ~T4_E~0); 66007#L592-1 assume 1 == ~E_M~0;~E_M~0 := 2; 65549#L597-1 assume !(1 == ~E_1~0); 65550#L602-1 assume !(1 == ~E_2~0); 65782#L607-1 assume !(1 == ~E_3~0); 65783#L612-1 assume !(1 == ~E_4~0); 65726#L617-1 assume { :end_inline_reset_delta_events } true; 65727#L803-2 [2024-11-09 16:07:42,990 INFO L747 eck$LassoCheckResult]: Loop: 65727#L803-2 assume !false; 66706#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 66685#L489-1 assume !false; 66705#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66704#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66699#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66698#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 66696#L428 assume !(0 != eval_~tmp~0#1); 66697#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 66925#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 66924#L514-3 assume !(0 == ~M_E~0); 66923#L514-5 assume !(0 == ~T1_E~0); 66922#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 66921#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 66920#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 66917#L534-3 assume !(0 == ~E_M~0); 66915#L539-3 assume !(0 == ~E_1~0); 66913#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 66911#L549-3 assume !(0 == ~E_3~0); 66909#L554-3 assume !(0 == ~E_4~0); 66907#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 66904#L250-18 assume !(1 == ~m_pc~0); 66902#L250-20 is_master_triggered_~__retres1~0#1 := 0; 66900#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 66898#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 66896#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 66894#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 66892#L269-18 assume !(1 == ~t1_pc~0); 66889#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 66887#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66885#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 66883#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 66881#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 66878#L288-18 assume !(1 == ~t2_pc~0); 66876#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 66874#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 66872#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 66870#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 66868#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 66866#L307-18 assume !(1 == ~t3_pc~0); 66864#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 66861#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 66859#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 66857#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 66855#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 66853#L326-18 assume !(1 == ~t4_pc~0); 66850#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 66848#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66846#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 66844#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 66842#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66840#L572-3 assume !(1 == ~M_E~0); 66836#L572-5 assume !(1 == ~T1_E~0); 66834#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 66832#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 66830#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 66742#L592-3 assume !(1 == ~E_M~0); 66740#L597-3 assume !(1 == ~E_1~0); 66738#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 66736#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 66734#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 66732#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66730#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66724#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66722#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 66720#L822 assume !(0 == start_simulation_~tmp~3#1); 66718#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 66716#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 66712#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 66711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 66710#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 66709#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 66708#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 66707#L835 assume !(0 != start_simulation_~tmp___0~1#1); 65727#L803-2 [2024-11-09 16:07:42,990 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:42,990 INFO L85 PathProgramCache]: Analyzing trace with hash 1842238409, now seen corresponding path program 1 times [2024-11-09 16:07:42,991 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:42,991 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460552115] [2024-11-09 16:07:42,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:42,991 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:42,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:43,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:43,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:43,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460552115] [2024-11-09 16:07:43,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [460552115] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:43,030 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:43,030 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:43,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [279046218] [2024-11-09 16:07:43,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:43,031 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:43,031 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:43,031 INFO L85 PathProgramCache]: Analyzing trace with hash -2129111218, now seen corresponding path program 1 times [2024-11-09 16:07:43,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:43,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046335695] [2024-11-09 16:07:43,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:43,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:43,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:43,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:43,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:43,080 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1046335695] [2024-11-09 16:07:43,080 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1046335695] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:43,081 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:43,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:07:43,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306313531] [2024-11-09 16:07:43,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:43,081 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:43,081 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:43,082 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2024-11-09 16:07:43,082 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2024-11-09 16:07:43,082 INFO L87 Difference]: Start difference. First operand 6977 states and 9606 transitions. cyclomatic complexity: 2637 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:43,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:43,182 INFO L93 Difference]: Finished difference Result 9400 states and 12933 transitions. [2024-11-09 16:07:43,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9400 states and 12933 transitions. [2024-11-09 16:07:43,219 INFO L131 ngComponentsAnalysis]: Automaton has 20 accepting balls. 9019 [2024-11-09 16:07:43,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9400 states to 9400 states and 12933 transitions. [2024-11-09 16:07:43,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9400 [2024-11-09 16:07:43,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9400 [2024-11-09 16:07:43,323 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9400 states and 12933 transitions. [2024-11-09 16:07:43,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:43,338 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9400 states and 12933 transitions. [2024-11-09 16:07:43,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9400 states and 12933 transitions. [2024-11-09 16:07:43,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9400 to 6582. [2024-11-09 16:07:43,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6582 states, 6582 states have (on average 1.3773928896991796) internal successors, (9066), 6581 states have internal predecessors, (9066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:43,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6582 states to 6582 states and 9066 transitions. [2024-11-09 16:07:43,489 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6582 states and 9066 transitions. [2024-11-09 16:07:43,489 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2024-11-09 16:07:43,489 INFO L425 stractBuchiCegarLoop]: Abstraction has 6582 states and 9066 transitions. [2024-11-09 16:07:43,489 INFO L332 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2024-11-09 16:07:43,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6582 states and 9066 transitions. [2024-11-09 16:07:43,513 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6454 [2024-11-09 16:07:43,513 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:43,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:43,515 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:43,516 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:43,517 INFO L745 eck$LassoCheckResult]: Stem: 82149#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 82150#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 82260#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 82261#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 82059#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 82060#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 82352#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 82003#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 82004#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 82141#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 82031#L514 assume !(0 == ~M_E~0); 82032#L514-2 assume !(0 == ~T1_E~0); 82374#L519-1 assume !(0 == ~T2_E~0); 81989#L524-1 assume !(0 == ~T3_E~0); 81990#L529-1 assume !(0 == ~T4_E~0); 82116#L534-1 assume !(0 == ~E_M~0); 82321#L539-1 assume !(0 == ~E_1~0); 82322#L544-1 assume !(0 == ~E_2~0); 82350#L549-1 assume !(0 == ~E_3~0); 82351#L554-1 assume !(0 == ~E_4~0); 81984#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81985#L250 assume !(1 == ~m_pc~0); 82214#L250-2 is_master_triggered_~__retres1~0#1 := 0; 82355#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82129#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 82130#L637 assume !(0 != activate_threads_~tmp~1#1); 81991#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81992#L269 assume !(1 == ~t1_pc~0); 81931#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 82111#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81979#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81980#L645 assume !(0 != activate_threads_~tmp___0~0#1); 82179#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82180#L288 assume !(1 == ~t2_pc~0); 82175#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 82176#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82266#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 82267#L653 assume !(0 != activate_threads_~tmp___1~0#1); 82315#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82203#L307 assume !(1 == ~t3_pc~0); 82132#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 82133#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81934#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81935#L661 assume !(0 != activate_threads_~tmp___2~0#1); 82147#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82148#L326 assume !(1 == ~t4_pc~0); 81946#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81947#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82035#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82036#L669 assume !(0 != activate_threads_~tmp___3~0#1); 82318#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82319#L572 assume !(1 == ~M_E~0); 82356#L572-2 assume !(1 == ~T1_E~0); 81999#L577-1 assume !(1 == ~T2_E~0); 82000#L582-1 assume !(1 == ~T3_E~0); 82297#L587-1 assume !(1 == ~T4_E~0); 82306#L592-1 assume !(1 == ~E_M~0); 81938#L597-1 assume !(1 == ~E_1~0); 81939#L602-1 assume !(1 == ~E_2~0); 82172#L607-1 assume !(1 == ~E_3~0); 82173#L612-1 assume !(1 == ~E_4~0); 82114#L617-1 assume { :end_inline_reset_delta_events } true; 82115#L803-2 [2024-11-09 16:07:43,517 INFO L747 eck$LassoCheckResult]: Loop: 82115#L803-2 assume !false; 82799#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82645#L489-1 assume !false; 82789#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 82768#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 82762#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 82741#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 82734#L428 assume !(0 != eval_~tmp~0#1); 82735#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83441#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83440#L514-3 assume !(0 == ~M_E~0); 83439#L514-5 assume !(0 == ~T1_E~0); 83438#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 83437#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 83436#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83434#L534-3 assume !(0 == ~E_M~0); 83432#L539-3 assume !(0 == ~E_1~0); 83430#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 83428#L549-3 assume !(0 == ~E_3~0); 83426#L554-3 assume !(0 == ~E_4~0); 83424#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 83422#L250-18 assume !(1 == ~m_pc~0); 83420#L250-20 is_master_triggered_~__retres1~0#1 := 0; 83418#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 83416#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 83414#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 83412#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 83410#L269-18 assume !(1 == ~t1_pc~0); 83407#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 83405#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 83403#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 83401#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 83399#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83396#L288-18 assume !(1 == ~t2_pc~0); 83394#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 83392#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 83390#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 83388#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 83386#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 83384#L307-18 assume 1 == ~t3_pc~0; 83381#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 83379#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 83377#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 83375#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 83373#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 83371#L326-18 assume !(1 == ~t4_pc~0); 83368#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 83366#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 83364#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 83362#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 83360#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83358#L572-3 assume !(1 == ~M_E~0); 83201#L572-5 assume !(1 == ~T1_E~0); 83354#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83352#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 83333#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 83296#L592-3 assume !(1 == ~E_M~0); 83295#L597-3 assume !(1 == ~E_1~0); 83294#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 83293#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 83292#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 83291#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 83290#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 83285#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 83284#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 83267#L822 assume !(0 == start_simulation_~tmp~3#1); 83268#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 83302#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 83298#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 83297#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 82823#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82818#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82813#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 82808#L835 assume !(0 != start_simulation_~tmp___0~1#1); 82115#L803-2 [2024-11-09 16:07:43,517 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:43,518 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2024-11-09 16:07:43,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:43,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461671563] [2024-11-09 16:07:43,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:43,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:43,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:43,529 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:43,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:43,548 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:43,549 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:43,549 INFO L85 PathProgramCache]: Analyzing trace with hash 1114406989, now seen corresponding path program 1 times [2024-11-09 16:07:43,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:43,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088963470] [2024-11-09 16:07:43,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:43,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:43,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:43,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:43,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:43,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2088963470] [2024-11-09 16:07:43,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2088963470] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:43,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:43,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:07:43,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1756549826] [2024-11-09 16:07:43,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:43,629 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:43,629 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:43,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:07:43,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:07:43,630 INFO L87 Difference]: Start difference. First operand 6582 states and 9066 transitions. cyclomatic complexity: 2492 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:43,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:43,714 INFO L93 Difference]: Finished difference Result 6718 states and 9202 transitions. [2024-11-09 16:07:43,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6718 states and 9202 transitions. [2024-11-09 16:07:43,745 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6590 [2024-11-09 16:07:43,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6718 states to 6718 states and 9202 transitions. [2024-11-09 16:07:43,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6718 [2024-11-09 16:07:43,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6718 [2024-11-09 16:07:43,774 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6718 states and 9202 transitions. [2024-11-09 16:07:43,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:43,784 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6718 states and 9202 transitions. [2024-11-09 16:07:43,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6718 states and 9202 transitions. [2024-11-09 16:07:43,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6718 to 6654. [2024-11-09 16:07:44,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6654 states, 6654 states have (on average 1.3733092876465285) internal successors, (9138), 6653 states have internal predecessors, (9138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:44,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6654 states to 6654 states and 9138 transitions. [2024-11-09 16:07:44,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6654 states and 9138 transitions. [2024-11-09 16:07:44,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:07:44,027 INFO L425 stractBuchiCegarLoop]: Abstraction has 6654 states and 9138 transitions. [2024-11-09 16:07:44,027 INFO L332 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2024-11-09 16:07:44,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6654 states and 9138 transitions. [2024-11-09 16:07:44,048 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6526 [2024-11-09 16:07:44,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:44,049 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:44,050 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:44,050 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:44,050 INFO L745 eck$LassoCheckResult]: Stem: 95462#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 95463#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 95568#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 95569#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 95367#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 95368#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 95654#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 95311#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 95312#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 95452#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 95338#L514 assume !(0 == ~M_E~0); 95339#L514-2 assume !(0 == ~T1_E~0); 95673#L519-1 assume !(0 == ~T2_E~0); 95297#L524-1 assume !(0 == ~T3_E~0); 95298#L529-1 assume !(0 == ~T4_E~0); 95426#L534-1 assume !(0 == ~E_M~0); 95624#L539-1 assume !(0 == ~E_1~0); 95625#L544-1 assume !(0 == ~E_2~0); 95652#L549-1 assume !(0 == ~E_3~0); 95653#L554-1 assume !(0 == ~E_4~0); 95292#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95293#L250 assume !(1 == ~m_pc~0); 95525#L250-2 is_master_triggered_~__retres1~0#1 := 0; 95657#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95440#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 95441#L637 assume !(0 != activate_threads_~tmp~1#1); 95299#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95300#L269 assume !(1 == ~t1_pc~0); 95239#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 95421#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95287#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 95288#L645 assume !(0 != activate_threads_~tmp___0~0#1); 95491#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95492#L288 assume !(1 == ~t2_pc~0); 95486#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 95487#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95576#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 95577#L653 assume !(0 != activate_threads_~tmp___1~0#1); 95619#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95514#L307 assume !(1 == ~t3_pc~0); 95443#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 95444#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95242#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 95243#L661 assume !(0 != activate_threads_~tmp___2~0#1); 95460#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95461#L326 assume !(1 == ~t4_pc~0); 95254#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 95255#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95342#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95343#L669 assume !(0 != activate_threads_~tmp___3~0#1); 95621#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95622#L572 assume !(1 == ~M_E~0); 95658#L572-2 assume !(1 == ~T1_E~0); 95307#L577-1 assume !(1 == ~T2_E~0); 95308#L582-1 assume !(1 == ~T3_E~0); 95602#L587-1 assume !(1 == ~T4_E~0); 95612#L592-1 assume !(1 == ~E_M~0); 95246#L597-1 assume !(1 == ~E_1~0); 95247#L602-1 assume !(1 == ~E_2~0); 95483#L607-1 assume !(1 == ~E_3~0); 95484#L612-1 assume !(1 == ~E_4~0); 95424#L617-1 assume { :end_inline_reset_delta_events } true; 95425#L803-2 [2024-11-09 16:07:44,050 INFO L747 eck$LassoCheckResult]: Loop: 95425#L803-2 assume !false; 97140#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97139#L489-1 assume !false; 97138#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 97137#L386 assume !(0 == ~m_st~0); 97134#L390 assume !(0 == ~t1_st~0); 97135#L394 assume !(0 == ~t2_st~0); 97136#L398 assume !(0 == ~t3_st~0); 97132#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 97133#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 97125#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 97126#L428 assume !(0 != eval_~tmp~0#1); 97694#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 97693#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 97692#L514-3 assume !(0 == ~M_E~0); 97691#L514-5 assume !(0 == ~T1_E~0); 97690#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 97689#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 97688#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 97687#L534-3 assume !(0 == ~E_M~0); 97686#L539-3 assume !(0 == ~E_1~0); 97685#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 97684#L549-3 assume !(0 == ~E_3~0); 97683#L554-3 assume !(0 == ~E_4~0); 97682#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97681#L250-18 assume !(1 == ~m_pc~0); 97680#L250-20 is_master_triggered_~__retres1~0#1 := 0; 97679#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97678#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 97677#L637-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 97676#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97675#L269-18 assume !(1 == ~t1_pc~0); 97673#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 97672#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97671#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 97670#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 97669#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97668#L288-18 assume !(1 == ~t2_pc~0); 97667#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 97666#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 97665#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 97664#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 97663#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97662#L307-18 assume !(1 == ~t3_pc~0); 97661#L307-20 is_transmit3_triggered_~__retres1~3#1 := 0; 97659#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97658#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 97657#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97656#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 97655#L326-18 assume !(1 == ~t4_pc~0); 97654#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 97653#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97652#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 97651#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 97650#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97649#L572-3 assume !(1 == ~M_E~0); 97381#L572-5 assume !(1 == ~T1_E~0); 97648#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 97647#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97646#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 97645#L592-3 assume !(1 == ~E_M~0); 97644#L597-3 assume !(1 == ~E_1~0); 97643#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 97642#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 97641#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97640#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 97639#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 97506#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 97226#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 97221#L822 assume !(0 == start_simulation_~tmp~3#1); 97217#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 97211#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 97198#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 97148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 97146#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 97145#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 97144#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 97143#L835 assume !(0 != start_simulation_~tmp___0~1#1); 95425#L803-2 [2024-11-09 16:07:44,051 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:44,051 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2024-11-09 16:07:44,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:44,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194910136] [2024-11-09 16:07:44,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:44,052 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:44,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:44,060 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:44,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:44,075 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:44,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:44,076 INFO L85 PathProgramCache]: Analyzing trace with hash 1054020418, now seen corresponding path program 1 times [2024-11-09 16:07:44,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:44,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775249816] [2024-11-09 16:07:44,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:44,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:44,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:44,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:44,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:44,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775249816] [2024-11-09 16:07:44,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775249816] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:44,141 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:44,141 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2024-11-09 16:07:44,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [631761007] [2024-11-09 16:07:44,142 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:44,142 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:44,142 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:44,142 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2024-11-09 16:07:44,143 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2024-11-09 16:07:44,143 INFO L87 Difference]: Start difference. First operand 6654 states and 9138 transitions. cyclomatic complexity: 2492 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:44,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:44,300 INFO L93 Difference]: Finished difference Result 6774 states and 9181 transitions. [2024-11-09 16:07:44,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6774 states and 9181 transitions. [2024-11-09 16:07:44,326 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6646 [2024-11-09 16:07:44,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6774 states to 6774 states and 9181 transitions. [2024-11-09 16:07:44,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6774 [2024-11-09 16:07:44,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6774 [2024-11-09 16:07:44,352 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6774 states and 9181 transitions. [2024-11-09 16:07:44,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:44,359 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6774 states and 9181 transitions. [2024-11-09 16:07:44,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6774 states and 9181 transitions. [2024-11-09 16:07:44,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6774 to 6774. [2024-11-09 16:07:44,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6774 states, 6774 states have (on average 1.3553291998819015) internal successors, (9181), 6773 states have internal predecessors, (9181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:44,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6774 states to 6774 states and 9181 transitions. [2024-11-09 16:07:44,452 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6774 states and 9181 transitions. [2024-11-09 16:07:44,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2024-11-09 16:07:44,453 INFO L425 stractBuchiCegarLoop]: Abstraction has 6774 states and 9181 transitions. [2024-11-09 16:07:44,453 INFO L332 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2024-11-09 16:07:44,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6774 states and 9181 transitions. [2024-11-09 16:07:44,513 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6646 [2024-11-09 16:07:44,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:44,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:44,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:44,519 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:44,519 INFO L745 eck$LassoCheckResult]: Stem: 108902#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 108903#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 109011#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 109012#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 108806#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 108807#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109094#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 108750#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 108751#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 108892#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 108777#L514 assume !(0 == ~M_E~0); 108778#L514-2 assume !(0 == ~T1_E~0); 109116#L519-1 assume !(0 == ~T2_E~0); 108736#L524-1 assume !(0 == ~T3_E~0); 108737#L529-1 assume !(0 == ~T4_E~0); 108867#L534-1 assume !(0 == ~E_M~0); 109066#L539-1 assume !(0 == ~E_1~0); 109067#L544-1 assume !(0 == ~E_2~0); 109092#L549-1 assume !(0 == ~E_3~0); 109093#L554-1 assume !(0 == ~E_4~0); 108731#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 108732#L250 assume !(1 == ~m_pc~0); 108967#L250-2 is_master_triggered_~__retres1~0#1 := 0; 109096#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 108880#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 108881#L637 assume !(0 != activate_threads_~tmp~1#1); 108738#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 108739#L269 assume !(1 == ~t1_pc~0); 108675#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 108862#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 108725#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 108726#L645 assume !(0 != activate_threads_~tmp___0~0#1); 108931#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 108932#L288 assume !(1 == ~t2_pc~0); 108926#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 108927#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109017#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 109018#L653 assume !(0 != activate_threads_~tmp___1~0#1); 109062#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 108958#L307 assume !(1 == ~t3_pc~0); 108883#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 108884#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 108678#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 108679#L661 assume !(0 != activate_threads_~tmp___2~0#1); 108900#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 108901#L326 assume !(1 == ~t4_pc~0); 108692#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 108693#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 108781#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 108782#L669 assume !(0 != activate_threads_~tmp___3~0#1); 109063#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109064#L572 assume !(1 == ~M_E~0); 109097#L572-2 assume !(1 == ~T1_E~0); 108746#L577-1 assume !(1 == ~T2_E~0); 108747#L582-1 assume !(1 == ~T3_E~0); 109045#L587-1 assume !(1 == ~T4_E~0); 109055#L592-1 assume !(1 == ~E_M~0); 108682#L597-1 assume !(1 == ~E_1~0); 108683#L602-1 assume !(1 == ~E_2~0); 108923#L607-1 assume !(1 == ~E_3~0); 108924#L612-1 assume !(1 == ~E_4~0); 108865#L617-1 assume { :end_inline_reset_delta_events } true; 108866#L803-2 [2024-11-09 16:07:44,519 INFO L747 eck$LassoCheckResult]: Loop: 108866#L803-2 assume !false; 112369#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 110944#L489-1 assume !false; 112365#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 112362#L386 assume !(0 == ~m_st~0); 112359#L390 assume !(0 == ~t1_st~0); 112360#L394 assume !(0 == ~t2_st~0); 112361#L398 assume !(0 == ~t3_st~0); 112357#L402 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 112358#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 112348#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 112349#L428 assume !(0 != eval_~tmp~0#1); 112460#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112459#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 112458#L514-3 assume !(0 == ~M_E~0); 112457#L514-5 assume !(0 == ~T1_E~0); 112456#L519-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 112455#L524-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 112454#L529-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 112453#L534-3 assume !(0 == ~E_M~0); 112452#L539-3 assume !(0 == ~E_1~0); 112451#L544-3 assume 0 == ~E_2~0;~E_2~0 := 1; 112450#L549-3 assume !(0 == ~E_3~0); 112449#L554-3 assume !(0 == ~E_4~0); 112448#L559-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112447#L250-18 assume !(1 == ~m_pc~0); 112446#L250-20 is_master_triggered_~__retres1~0#1 := 0; 112445#L261-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112444#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 112443#L637-18 assume !(0 != activate_threads_~tmp~1#1); 112442#L637-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112441#L269-18 assume !(1 == ~t1_pc~0); 112439#L269-20 is_transmit1_triggered_~__retres1~1#1 := 0; 112438#L280-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112437#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 112436#L645-18 assume !(0 != activate_threads_~tmp___0~0#1); 112434#L645-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112432#L288-18 assume !(1 == ~t2_pc~0); 112430#L288-20 is_transmit2_triggered_~__retres1~2#1 := 0; 112428#L299-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112426#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 112423#L653-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 112420#L653-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112417#L307-18 assume 1 == ~t3_pc~0; 112413#L308-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 112410#L318-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112407#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 112404#L661-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112401#L661-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112398#L326-18 assume !(1 == ~t4_pc~0); 112396#L326-20 is_transmit4_triggered_~__retres1~4#1 := 0; 112389#L337-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112386#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 112383#L669-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 112380#L669-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112376#L572-3 assume !(1 == ~M_E~0); 112301#L572-5 assume !(1 == ~T1_E~0); 112371#L577-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112354#L582-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112350#L587-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 109600#L592-3 assume !(1 == ~E_M~0); 109597#L597-3 assume !(1 == ~E_1~0); 109595#L602-3 assume 1 == ~E_2~0;~E_2~0 := 2; 109592#L607-3 assume 1 == ~E_3~0;~E_3~0 := 2; 109593#L612-3 assume 1 == ~E_4~0;~E_4~0 := 2; 109587#L617-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 109585#L386-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 109572#L413-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 109565#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret17#1;havoc start_simulation_#t~ret17#1; 109292#L822 assume !(0 == start_simulation_~tmp~3#1); 109293#L822-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 112393#L386-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 112387#L413-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 112384#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret16#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret16#1;havoc stop_simulation_#t~ret16#1; 112381#L777 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 112377#L784 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 112374#stop_simulation_returnLabel#1 start_simulation_#t~ret18#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret16#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 112372#L835 assume !(0 != start_simulation_~tmp___0~1#1); 108866#L803-2 [2024-11-09 16:07:44,520 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:44,520 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2024-11-09 16:07:44,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:44,521 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012370607] [2024-11-09 16:07:44,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:44,521 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:44,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:44,535 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:44,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:44,560 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:44,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:44,560 INFO L85 PathProgramCache]: Analyzing trace with hash -12947389, now seen corresponding path program 1 times [2024-11-09 16:07:44,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:44,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336141946] [2024-11-09 16:07:44,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:44,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:44,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:44,595 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:44,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:44,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336141946] [2024-11-09 16:07:44,596 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [336141946] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:44,596 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:44,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:44,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1693492003] [2024-11-09 16:07:44,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:44,597 INFO L762 eck$LassoCheckResult]: loop already infeasible [2024-11-09 16:07:44,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:44,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:44,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:44,598 INFO L87 Difference]: Start difference. First operand 6774 states and 9181 transitions. cyclomatic complexity: 2415 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:44,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:44,662 INFO L93 Difference]: Finished difference Result 10652 states and 14255 transitions. [2024-11-09 16:07:44,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10652 states and 14255 transitions. [2024-11-09 16:07:44,706 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10490 [2024-11-09 16:07:44,736 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10652 states to 10652 states and 14255 transitions. [2024-11-09 16:07:44,737 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10652 [2024-11-09 16:07:44,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10652 [2024-11-09 16:07:44,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10652 states and 14255 transitions. [2024-11-09 16:07:44,757 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:44,757 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10652 states and 14255 transitions. [2024-11-09 16:07:44,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10652 states and 14255 transitions. [2024-11-09 16:07:44,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10652 to 10396. [2024-11-09 16:07:44,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10396 states, 10396 states have (on average 1.338880338591766) internal successors, (13919), 10395 states have internal predecessors, (13919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:44,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10396 states to 10396 states and 13919 transitions. [2024-11-09 16:07:44,883 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10396 states and 13919 transitions. [2024-11-09 16:07:44,884 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:44,884 INFO L425 stractBuchiCegarLoop]: Abstraction has 10396 states and 13919 transitions. [2024-11-09 16:07:44,884 INFO L332 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2024-11-09 16:07:44,884 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10396 states and 13919 transitions. [2024-11-09 16:07:44,952 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10234 [2024-11-09 16:07:44,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:44,953 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:44,953 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:44,953 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:44,954 INFO L745 eck$LassoCheckResult]: Stem: 126334#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 126335#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 126445#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 126446#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 126236#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 126237#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126533#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126180#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 126181#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 126324#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 126206#L514 assume !(0 == ~M_E~0); 126207#L514-2 assume !(0 == ~T1_E~0); 126555#L519-1 assume !(0 == ~T2_E~0); 126166#L524-1 assume !(0 == ~T3_E~0); 126167#L529-1 assume !(0 == ~T4_E~0); 126296#L534-1 assume !(0 == ~E_M~0); 126502#L539-1 assume !(0 == ~E_1~0); 126503#L544-1 assume !(0 == ~E_2~0); 126531#L549-1 assume !(0 == ~E_3~0); 126532#L554-1 assume !(0 == ~E_4~0); 126161#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 126162#L250 assume !(1 == ~m_pc~0); 126397#L250-2 is_master_triggered_~__retres1~0#1 := 0; 126535#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 126311#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 126312#L637 assume !(0 != activate_threads_~tmp~1#1); 126168#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 126169#L269 assume !(1 == ~t1_pc~0); 126107#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 126291#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126155#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 126156#L645 assume !(0 != activate_threads_~tmp___0~0#1); 126365#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126366#L288 assume !(1 == ~t2_pc~0); 126358#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 126359#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126453#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 126454#L653 assume !(0 != activate_threads_~tmp___1~0#1); 126497#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126386#L307 assume !(1 == ~t3_pc~0); 126314#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 126315#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126110#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 126111#L661 assume !(0 != activate_threads_~tmp___2~0#1); 126332#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126333#L326 assume !(1 == ~t4_pc~0); 126122#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 126123#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126210#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 126211#L669 assume !(0 != activate_threads_~tmp___3~0#1); 126499#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 126500#L572 assume !(1 == ~M_E~0); 126536#L572-2 assume !(1 == ~T1_E~0); 126176#L577-1 assume !(1 == ~T2_E~0); 126177#L582-1 assume !(1 == ~T3_E~0); 126480#L587-1 assume !(1 == ~T4_E~0); 126489#L592-1 assume !(1 == ~E_M~0); 126114#L597-1 assume !(1 == ~E_1~0); 126115#L602-1 assume !(1 == ~E_2~0); 126355#L607-1 assume !(1 == ~E_3~0); 126356#L612-1 assume !(1 == ~E_4~0); 126294#L617-1 assume { :end_inline_reset_delta_events } true; 126295#L803-2 assume !false; 127096#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 127094#L489-1 [2024-11-09 16:07:44,954 INFO L747 eck$LassoCheckResult]: Loop: 127094#L489-1 assume !false; 127091#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 127088#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 127086#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 127084#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 127075#L428 assume 0 != eval_~tmp~0#1; 127067#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 127063#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 127035#L436-2 havoc eval_~tmp_ndt_1~0#1; 127026#L433-1 assume !(0 == ~t1_st~0); 127018#L447-1 assume !(0 == ~t2_st~0); 127019#L461-1 assume !(0 == ~t3_st~0); 127098#L475-1 assume !(0 == ~t4_st~0); 127094#L489-1 [2024-11-09 16:07:44,956 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:44,957 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2024-11-09 16:07:44,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:44,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462796051] [2024-11-09 16:07:44,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:44,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:44,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:44,967 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:44,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:44,985 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:44,986 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:44,986 INFO L85 PathProgramCache]: Analyzing trace with hash 1561748980, now seen corresponding path program 1 times [2024-11-09 16:07:44,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:44,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992156719] [2024-11-09 16:07:44,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:44,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:44,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:44,990 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:44,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:44,993 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:44,994 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:44,994 INFO L85 PathProgramCache]: Analyzing trace with hash 1479320330, now seen corresponding path program 1 times [2024-11-09 16:07:44,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:44,994 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574294967] [2024-11-09 16:07:44,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:44,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:45,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:45,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:45,029 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:45,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574294967] [2024-11-09 16:07:45,029 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1574294967] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:45,029 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:45,029 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:45,030 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1423970576] [2024-11-09 16:07:45,030 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:45,109 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:45,110 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:45,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:45,113 INFO L87 Difference]: Start difference. First operand 10396 states and 13919 transitions. cyclomatic complexity: 3535 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:45,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:45,208 INFO L93 Difference]: Finished difference Result 16722 states and 22211 transitions. [2024-11-09 16:07:45,208 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16722 states and 22211 transitions. [2024-11-09 16:07:45,276 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16404 [2024-11-09 16:07:45,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16722 states to 16722 states and 22211 transitions. [2024-11-09 16:07:45,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16722 [2024-11-09 16:07:45,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16722 [2024-11-09 16:07:45,344 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16722 states and 22211 transitions. [2024-11-09 16:07:45,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:45,359 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16722 states and 22211 transitions. [2024-11-09 16:07:45,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16722 states and 22211 transitions. [2024-11-09 16:07:45,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16722 to 16722. [2024-11-09 16:07:45,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16722 states, 16722 states have (on average 1.328250209305107) internal successors, (22211), 16721 states have internal predecessors, (22211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:45,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16722 states to 16722 states and 22211 transitions. [2024-11-09 16:07:45,646 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16722 states and 22211 transitions. [2024-11-09 16:07:45,646 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:45,647 INFO L425 stractBuchiCegarLoop]: Abstraction has 16722 states and 22211 transitions. [2024-11-09 16:07:45,647 INFO L332 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2024-11-09 16:07:45,647 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16722 states and 22211 transitions. [2024-11-09 16:07:45,708 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16404 [2024-11-09 16:07:45,708 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:45,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:45,709 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:45,709 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:45,710 INFO L745 eck$LassoCheckResult]: Stem: 153457#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 153458#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 153564#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 153565#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 153360#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 153361#L353-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 153646#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 153304#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 153305#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 153446#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 153330#L514 assume !(0 == ~M_E~0); 153331#L514-2 assume !(0 == ~T1_E~0); 153670#L519-1 assume !(0 == ~T2_E~0); 153292#L524-1 assume !(0 == ~T3_E~0); 153293#L529-1 assume !(0 == ~T4_E~0); 153420#L534-1 assume !(0 == ~E_M~0); 153621#L539-1 assume !(0 == ~E_1~0); 153622#L544-1 assume !(0 == ~E_2~0); 153644#L549-1 assume !(0 == ~E_3~0); 153645#L554-1 assume !(0 == ~E_4~0); 153287#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 153288#L250 assume !(1 == ~m_pc~0); 153522#L250-2 is_master_triggered_~__retres1~0#1 := 0; 153649#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153435#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 153436#L637 assume !(0 != activate_threads_~tmp~1#1); 153294#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 153295#L269 assume !(1 == ~t1_pc~0); 153233#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 153415#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 153281#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 153282#L645 assume !(0 != activate_threads_~tmp___0~0#1); 153487#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 153488#L288 assume !(1 == ~t2_pc~0); 153480#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 153481#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 153572#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 153573#L653 assume !(0 != activate_threads_~tmp___1~0#1); 153616#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 153510#L307 assume !(1 == ~t3_pc~0); 153438#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 153439#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 153236#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 153237#L661 assume !(0 != activate_threads_~tmp___2~0#1); 153455#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 153456#L326 assume !(1 == ~t4_pc~0); 153248#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 153249#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 153334#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 153335#L669 assume !(0 != activate_threads_~tmp___3~0#1); 153618#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153619#L572 assume !(1 == ~M_E~0); 153650#L572-2 assume !(1 == ~T1_E~0); 153300#L577-1 assume !(1 == ~T2_E~0); 153301#L582-1 assume !(1 == ~T3_E~0); 153599#L587-1 assume !(1 == ~T4_E~0); 153609#L592-1 assume !(1 == ~E_M~0); 153240#L597-1 assume !(1 == ~E_1~0); 153241#L602-1 assume !(1 == ~E_2~0); 153723#L607-1 assume !(1 == ~E_3~0); 154506#L612-1 assume !(1 == ~E_4~0); 154503#L617-1 assume { :end_inline_reset_delta_events } true; 154501#L803-2 assume !false; 154438#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 154436#L489-1 [2024-11-09 16:07:45,710 INFO L747 eck$LassoCheckResult]: Loop: 154436#L489-1 assume !false; 154434#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 154431#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 154429#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 154427#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 154426#L428 assume 0 != eval_~tmp~0#1; 154424#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 154420#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 154418#L436-2 havoc eval_~tmp_ndt_1~0#1; 154415#L433-1 assume !(0 == ~t1_st~0); 154410#L447-1 assume !(0 == ~t2_st~0); 154411#L461-1 assume !(0 == ~t3_st~0); 154440#L475-1 assume !(0 == ~t4_st~0); 154436#L489-1 [2024-11-09 16:07:45,710 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:45,711 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2024-11-09 16:07:45,711 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:45,711 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959754360] [2024-11-09 16:07:45,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:45,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:45,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:45,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:45,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:45,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [959754360] [2024-11-09 16:07:45,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [959754360] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:45,736 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:45,736 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:45,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [889257341] [2024-11-09 16:07:45,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:45,737 INFO L750 eck$LassoCheckResult]: stem already infeasible [2024-11-09 16:07:45,737 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:45,737 INFO L85 PathProgramCache]: Analyzing trace with hash 1561748980, now seen corresponding path program 2 times [2024-11-09 16:07:45,737 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:45,737 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [932409152] [2024-11-09 16:07:45,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:45,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:45,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:45,741 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:45,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:45,744 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:45,802 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:45,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:45,803 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:45,803 INFO L87 Difference]: Start difference. First operand 16722 states and 22211 transitions. cyclomatic complexity: 5501 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:45,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:45,860 INFO L93 Difference]: Finished difference Result 16662 states and 22132 transitions. [2024-11-09 16:07:45,860 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16662 states and 22132 transitions. [2024-11-09 16:07:45,938 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16404 [2024-11-09 16:07:45,997 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16662 states to 16662 states and 22132 transitions. [2024-11-09 16:07:45,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16662 [2024-11-09 16:07:46,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16662 [2024-11-09 16:07:46,012 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16662 states and 22132 transitions. [2024-11-09 16:07:46,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:46,177 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16662 states and 22132 transitions. [2024-11-09 16:07:46,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16662 states and 22132 transitions. [2024-11-09 16:07:46,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16662 to 16662. [2024-11-09 16:07:46,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16662 states, 16662 states have (on average 1.3282919217380866) internal successors, (22132), 16661 states have internal predecessors, (22132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:46,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16662 states to 16662 states and 22132 transitions. [2024-11-09 16:07:46,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16662 states and 22132 transitions. [2024-11-09 16:07:46,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:46,371 INFO L425 stractBuchiCegarLoop]: Abstraction has 16662 states and 22132 transitions. [2024-11-09 16:07:46,371 INFO L332 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2024-11-09 16:07:46,372 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16662 states and 22132 transitions. [2024-11-09 16:07:46,416 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16404 [2024-11-09 16:07:46,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:46,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:46,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:46,417 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:46,418 INFO L745 eck$LassoCheckResult]: Stem: 186847#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 186848#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 186956#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 186957#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 186751#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 186752#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 187040#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 186694#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 186695#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 186837#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 186721#L514 assume !(0 == ~M_E~0); 186722#L514-2 assume !(0 == ~T1_E~0); 187061#L519-1 assume !(0 == ~T2_E~0); 186682#L524-1 assume !(0 == ~T3_E~0); 186683#L529-1 assume !(0 == ~T4_E~0); 186811#L534-1 assume !(0 == ~E_M~0); 187007#L539-1 assume !(0 == ~E_1~0); 187008#L544-1 assume !(0 == ~E_2~0); 187038#L549-1 assume !(0 == ~E_3~0); 187039#L554-1 assume !(0 == ~E_4~0); 186677#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186678#L250 assume !(1 == ~m_pc~0); 186910#L250-2 is_master_triggered_~__retres1~0#1 := 0; 187042#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 186826#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 186827#L637 assume !(0 != activate_threads_~tmp~1#1); 186684#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186685#L269 assume !(1 == ~t1_pc~0); 186623#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 186806#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 186671#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 186672#L645 assume !(0 != activate_threads_~tmp___0~0#1); 186876#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186877#L288 assume !(1 == ~t2_pc~0); 186870#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 186871#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 186962#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 186963#L653 assume !(0 != activate_threads_~tmp___1~0#1); 187002#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 186900#L307 assume !(1 == ~t3_pc~0); 186829#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 186830#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 186626#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 186627#L661 assume !(0 != activate_threads_~tmp___2~0#1); 186845#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 186846#L326 assume !(1 == ~t4_pc~0); 186638#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 186639#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 186725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 186726#L669 assume !(0 != activate_threads_~tmp___3~0#1); 187004#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 187005#L572 assume !(1 == ~M_E~0); 187043#L572-2 assume !(1 == ~T1_E~0); 186690#L577-1 assume !(1 == ~T2_E~0); 186691#L582-1 assume !(1 == ~T3_E~0); 186986#L587-1 assume !(1 == ~T4_E~0); 186995#L592-1 assume !(1 == ~E_M~0); 186630#L597-1 assume !(1 == ~E_1~0); 186631#L602-1 assume !(1 == ~E_2~0); 186867#L607-1 assume !(1 == ~E_3~0); 186868#L612-1 assume !(1 == ~E_4~0); 186809#L617-1 assume { :end_inline_reset_delta_events } true; 186810#L803-2 assume !false; 188070#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 188064#L489-1 [2024-11-09 16:07:46,418 INFO L747 eck$LassoCheckResult]: Loop: 188064#L489-1 assume !false; 188057#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 188050#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 188043#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 188036#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 188032#L428 assume 0 != eval_~tmp~0#1; 188024#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 187994#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 187993#L436-2 havoc eval_~tmp_ndt_1~0#1; 187992#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 187976#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 187973#L450-2 havoc eval_~tmp_ndt_2~0#1; 187964#L447-1 assume !(0 == ~t2_st~0); 187965#L461-1 assume !(0 == ~t3_st~0); 188072#L475-1 assume !(0 == ~t4_st~0); 188064#L489-1 [2024-11-09 16:07:46,419 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:46,419 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2024-11-09 16:07:46,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:46,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047429866] [2024-11-09 16:07:46,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:46,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:46,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:46,428 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:46,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:46,441 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:46,442 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:46,442 INFO L85 PathProgramCache]: Analyzing trace with hash 1594291277, now seen corresponding path program 1 times [2024-11-09 16:07:46,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:46,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43375166] [2024-11-09 16:07:46,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:46,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:46,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:46,446 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:46,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:46,450 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:46,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:46,450 INFO L85 PathProgramCache]: Analyzing trace with hash -310230045, now seen corresponding path program 1 times [2024-11-09 16:07:46,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:46,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995212345] [2024-11-09 16:07:46,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:46,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:46,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:46,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:46,484 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:46,484 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995212345] [2024-11-09 16:07:46,484 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995212345] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:46,485 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:46,485 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:46,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [172392151] [2024-11-09 16:07:46,485 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:46,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:46,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:46,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:46,547 INFO L87 Difference]: Start difference. First operand 16662 states and 22132 transitions. cyclomatic complexity: 5482 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:46,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:46,778 INFO L93 Difference]: Finished difference Result 19491 states and 25805 transitions. [2024-11-09 16:07:46,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19491 states and 25805 transitions. [2024-11-09 16:07:46,867 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 19169 [2024-11-09 16:07:46,931 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19491 states to 19491 states and 25805 transitions. [2024-11-09 16:07:46,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19491 [2024-11-09 16:07:46,948 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19491 [2024-11-09 16:07:46,948 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19491 states and 25805 transitions. [2024-11-09 16:07:46,964 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:46,964 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19491 states and 25805 transitions. [2024-11-09 16:07:46,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19491 states and 25805 transitions. [2024-11-09 16:07:47,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19491 to 18721. [2024-11-09 16:07:47,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18721 states, 18721 states have (on average 1.3255167993162758) internal successors, (24815), 18720 states have internal predecessors, (24815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:47,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18721 states to 18721 states and 24815 transitions. [2024-11-09 16:07:47,411 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18721 states and 24815 transitions. [2024-11-09 16:07:47,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:47,412 INFO L425 stractBuchiCegarLoop]: Abstraction has 18721 states and 24815 transitions. [2024-11-09 16:07:47,412 INFO L332 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2024-11-09 16:07:47,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18721 states and 24815 transitions. [2024-11-09 16:07:47,463 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 18399 [2024-11-09 16:07:47,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:47,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:47,465 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:47,465 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:47,465 INFO L745 eck$LassoCheckResult]: Stem: 223013#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 223014#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 223128#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 223129#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 222914#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 222915#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 223230#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 222856#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 222857#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 223001#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222884#L514 assume !(0 == ~M_E~0); 222885#L514-2 assume !(0 == ~T1_E~0); 223250#L519-1 assume !(0 == ~T2_E~0); 222842#L524-1 assume !(0 == ~T3_E~0); 222843#L529-1 assume !(0 == ~T4_E~0); 222976#L534-1 assume !(0 == ~E_M~0); 223196#L539-1 assume !(0 == ~E_1~0); 223197#L544-1 assume !(0 == ~E_2~0); 223228#L549-1 assume !(0 == ~E_3~0); 223229#L554-1 assume !(0 == ~E_4~0); 222837#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 222838#L250 assume !(1 == ~m_pc~0); 223082#L250-2 is_master_triggered_~__retres1~0#1 := 0; 223233#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 222990#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 222991#L637 assume !(0 != activate_threads_~tmp~1#1); 222844#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 222845#L269 assume !(1 == ~t1_pc~0); 222784#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 222971#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 222832#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 222833#L645 assume !(0 != activate_threads_~tmp___0~0#1); 223044#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223045#L288 assume !(1 == ~t2_pc~0); 223036#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 223037#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223137#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 223138#L653 assume !(0 != activate_threads_~tmp___1~0#1); 223190#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223069#L307 assume !(1 == ~t3_pc~0); 222993#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 222994#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 222787#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 222788#L661 assume !(0 != activate_threads_~tmp___2~0#1); 223011#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223012#L326 assume !(1 == ~t4_pc~0); 222799#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 222800#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 222888#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 222889#L669 assume !(0 != activate_threads_~tmp___3~0#1); 223193#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 223194#L572 assume !(1 == ~M_E~0); 223234#L572-2 assume !(1 == ~T1_E~0); 222852#L577-1 assume !(1 == ~T2_E~0); 222853#L582-1 assume !(1 == ~T3_E~0); 223170#L587-1 assume !(1 == ~T4_E~0); 223180#L592-1 assume !(1 == ~E_M~0); 222791#L597-1 assume !(1 == ~E_1~0); 222792#L602-1 assume !(1 == ~E_2~0); 223033#L607-1 assume !(1 == ~E_3~0); 223034#L612-1 assume !(1 == ~E_4~0); 222974#L617-1 assume { :end_inline_reset_delta_events } true; 222975#L803-2 assume !false; 227317#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 227312#L489-1 [2024-11-09 16:07:47,466 INFO L747 eck$LassoCheckResult]: Loop: 227312#L489-1 assume !false; 227308#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 227303#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 227298#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 227294#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 227289#L428 assume 0 != eval_~tmp~0#1; 227285#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 227280#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 227276#L436-2 havoc eval_~tmp_ndt_1~0#1; 227272#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 227245#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 227268#L450-2 havoc eval_~tmp_ndt_2~0#1; 227344#L447-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 227338#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 227333#L464-2 havoc eval_~tmp_ndt_3~0#1; 227326#L461-1 assume !(0 == ~t3_st~0); 227319#L475-1 assume !(0 == ~t4_st~0); 227312#L489-1 [2024-11-09 16:07:47,466 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:47,466 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2024-11-09 16:07:47,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:47,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591009911] [2024-11-09 16:07:47,467 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:47,467 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:47,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:47,478 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:47,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:47,490 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:47,491 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:47,491 INFO L85 PathProgramCache]: Analyzing trace with hash -1337685132, now seen corresponding path program 1 times [2024-11-09 16:07:47,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:47,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870999698] [2024-11-09 16:07:47,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:47,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:47,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:47,495 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:47,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:47,498 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:47,498 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:47,498 INFO L85 PathProgramCache]: Analyzing trace with hash -1926607478, now seen corresponding path program 1 times [2024-11-09 16:07:47,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:47,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2048390742] [2024-11-09 16:07:47,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:47,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:47,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:47,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:47,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:47,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2048390742] [2024-11-09 16:07:47,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2048390742] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:47,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:47,531 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2024-11-09 16:07:47,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891669708] [2024-11-09 16:07:47,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:47,592 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:47,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:47,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:47,593 INFO L87 Difference]: Start difference. First operand 18721 states and 24815 transitions. cyclomatic complexity: 6107 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:47,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:47,830 INFO L93 Difference]: Finished difference Result 33042 states and 43580 transitions. [2024-11-09 16:07:47,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33042 states and 43580 transitions. [2024-11-09 16:07:47,998 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 32464 [2024-11-09 16:07:48,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33042 states to 33042 states and 43580 transitions. [2024-11-09 16:07:48,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33042 [2024-11-09 16:07:48,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33042 [2024-11-09 16:07:48,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33042 states and 43580 transitions. [2024-11-09 16:07:48,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:48,153 INFO L218 hiAutomatonCegarLoop]: Abstraction has 33042 states and 43580 transitions. [2024-11-09 16:07:48,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33042 states and 43580 transitions. [2024-11-09 16:07:48,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33042 to 31886. [2024-11-09 16:07:48,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31886 states, 31886 states have (on average 1.3235275669572852) internal successors, (42202), 31885 states have internal predecessors, (42202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:48,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31886 states to 31886 states and 42202 transitions. [2024-11-09 16:07:48,632 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31886 states and 42202 transitions. [2024-11-09 16:07:48,633 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:48,633 INFO L425 stractBuchiCegarLoop]: Abstraction has 31886 states and 42202 transitions. [2024-11-09 16:07:48,633 INFO L332 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2024-11-09 16:07:48,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31886 states and 42202 transitions. [2024-11-09 16:07:48,876 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 31308 [2024-11-09 16:07:48,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:48,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:48,878 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:48,878 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:48,878 INFO L745 eck$LassoCheckResult]: Stem: 274776#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 274777#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 274894#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 274895#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 274680#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 274681#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 274987#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 274625#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 274626#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 274765#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 274654#L514 assume !(0 == ~M_E~0); 274655#L514-2 assume !(0 == ~T1_E~0); 275009#L519-1 assume !(0 == ~T2_E~0); 274613#L524-1 assume !(0 == ~T3_E~0); 274614#L529-1 assume !(0 == ~T4_E~0); 274739#L534-1 assume !(0 == ~E_M~0); 274955#L539-1 assume !(0 == ~E_1~0); 274956#L544-1 assume !(0 == ~E_2~0); 274984#L549-1 assume !(0 == ~E_3~0); 274985#L554-1 assume !(0 == ~E_4~0); 274608#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274609#L250 assume !(1 == ~m_pc~0); 274845#L250-2 is_master_triggered_~__retres1~0#1 := 0; 274988#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 274753#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 274754#L637 assume !(0 != activate_threads_~tmp~1#1); 274615#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 274616#L269 assume !(1 == ~t1_pc~0); 274555#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 274734#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 274604#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 274605#L645 assume !(0 != activate_threads_~tmp___0~0#1); 274809#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 274810#L288 assume !(1 == ~t2_pc~0); 274802#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 274803#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 274901#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 274902#L653 assume !(0 != activate_threads_~tmp___1~0#1); 274950#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 274833#L307 assume !(1 == ~t3_pc~0); 274756#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 274757#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 274558#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 274559#L661 assume !(0 != activate_threads_~tmp___2~0#1); 274774#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 274775#L326 assume !(1 == ~t4_pc~0); 274570#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 274571#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 274656#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 274657#L669 assume !(0 != activate_threads_~tmp___3~0#1); 274952#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 274953#L572 assume !(1 == ~M_E~0); 274989#L572-2 assume !(1 == ~T1_E~0); 274621#L577-1 assume !(1 == ~T2_E~0); 274622#L582-1 assume !(1 == ~T3_E~0); 274934#L587-1 assume !(1 == ~T4_E~0); 274944#L592-1 assume !(1 == ~E_M~0); 274568#L597-1 assume !(1 == ~E_1~0); 274569#L602-1 assume !(1 == ~E_2~0); 274799#L607-1 assume !(1 == ~E_3~0); 274800#L612-1 assume !(1 == ~E_4~0); 274737#L617-1 assume { :end_inline_reset_delta_events } true; 274738#L803-2 assume !false; 279220#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 279219#L489-1 [2024-11-09 16:07:48,878 INFO L747 eck$LassoCheckResult]: Loop: 279219#L489-1 assume !false; 279218#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 279217#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 279206#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 279207#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 279165#L428 assume 0 != eval_~tmp~0#1; 279166#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 279225#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 279226#L436-2 havoc eval_~tmp_ndt_1~0#1; 279203#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 279201#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 279200#L450-2 havoc eval_~tmp_ndt_2~0#1; 279199#L447-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 279196#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 279193#L464-2 havoc eval_~tmp_ndt_3~0#1; 279190#L461-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 278926#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 279186#L478-2 havoc eval_~tmp_ndt_4~0#1; 279222#L475-1 assume !(0 == ~t4_st~0); 279219#L489-1 [2024-11-09 16:07:48,878 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:48,879 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2024-11-09 16:07:48,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:48,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89215037] [2024-11-09 16:07:48,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:48,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:48,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:48,889 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:48,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:48,903 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:48,903 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:48,904 INFO L85 PathProgramCache]: Analyzing trace with hash -1324933107, now seen corresponding path program 1 times [2024-11-09 16:07:48,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:48,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580774618] [2024-11-09 16:07:48,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:48,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:48,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:48,907 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:48,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:48,910 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:48,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:48,911 INFO L85 PathProgramCache]: Analyzing trace with hash -343624541, now seen corresponding path program 1 times [2024-11-09 16:07:48,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:48,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290987825] [2024-11-09 16:07:48,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:48,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:48,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2024-11-09 16:07:48,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2024-11-09 16:07:48,949 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2024-11-09 16:07:48,949 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290987825] [2024-11-09 16:07:48,949 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290987825] provided 1 perfect and 0 imperfect interpolant sequences [2024-11-09 16:07:48,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2024-11-09 16:07:48,950 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2024-11-09 16:07:48,950 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1695509721] [2024-11-09 16:07:48,950 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2024-11-09 16:07:49,020 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2024-11-09 16:07:49,021 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2024-11-09 16:07:49,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2024-11-09 16:07:49,022 INFO L87 Difference]: Start difference. First operand 31886 states and 42202 transitions. cyclomatic complexity: 10329 Second operand has 3 states, 2 states have (on average 41.5) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:49,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2024-11-09 16:07:49,281 INFO L93 Difference]: Finished difference Result 37559 states and 49485 transitions. [2024-11-09 16:07:49,281 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37559 states and 49485 transitions. [2024-11-09 16:07:49,385 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 36677 [2024-11-09 16:07:49,489 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37559 states to 37559 states and 49485 transitions. [2024-11-09 16:07:49,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37559 [2024-11-09 16:07:49,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37559 [2024-11-09 16:07:49,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37559 states and 49485 transitions. [2024-11-09 16:07:49,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2024-11-09 16:07:49,545 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37559 states and 49485 transitions. [2024-11-09 16:07:49,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37559 states and 49485 transitions. [2024-11-09 16:07:50,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37559 to 37271. [2024-11-09 16:07:50,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37271 states, 37271 states have (on average 1.3199806820316062) internal successors, (49197), 37270 states have internal predecessors, (49197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2024-11-09 16:07:50,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37271 states to 37271 states and 49197 transitions. [2024-11-09 16:07:50,095 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37271 states and 49197 transitions. [2024-11-09 16:07:50,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2024-11-09 16:07:50,096 INFO L425 stractBuchiCegarLoop]: Abstraction has 37271 states and 49197 transitions. [2024-11-09 16:07:50,096 INFO L332 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2024-11-09 16:07:50,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37271 states and 49197 transitions. [2024-11-09 16:07:50,213 INFO L131 ngComponentsAnalysis]: Automaton has 14 accepting balls. 36389 [2024-11-09 16:07:50,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2024-11-09 16:07:50,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2024-11-09 16:07:50,214 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,214 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2024-11-09 16:07:50,214 INFO L745 eck$LassoCheckResult]: Stem: 344242#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 344243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 344364#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret17#1, start_simulation_#t~ret18#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 344365#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 344138#L353 assume 1 == ~m_i~0;~m_st~0 := 0; 344139#L353-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 344458#L358-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 344080#L363-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 344081#L368-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 344231#L373-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 344110#L514 assume !(0 == ~M_E~0); 344111#L514-2 assume !(0 == ~T1_E~0); 344483#L519-1 assume !(0 == ~T2_E~0); 344068#L524-1 assume !(0 == ~T3_E~0); 344069#L529-1 assume !(0 == ~T4_E~0); 344201#L534-1 assume !(0 == ~E_M~0); 344426#L539-1 assume !(0 == ~E_1~0); 344427#L544-1 assume !(0 == ~E_2~0); 344454#L549-1 assume !(0 == ~E_3~0); 344455#L554-1 assume !(0 == ~E_4~0); 344063#L559-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 344064#L250 assume !(1 == ~m_pc~0); 344318#L250-2 is_master_triggered_~__retres1~0#1 := 0; 344459#L261 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 344217#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 344218#L637 assume !(0 != activate_threads_~tmp~1#1); 344070#L637-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 344071#L269 assume !(1 == ~t1_pc~0); 344009#L269-2 is_transmit1_triggered_~__retres1~1#1 := 0; 344196#L280 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 344059#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 344060#L645 assume !(0 != activate_threads_~tmp___0~0#1); 344274#L645-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 344275#L288 assume !(1 == ~t2_pc~0); 344266#L288-2 is_transmit2_triggered_~__retres1~2#1 := 0; 344267#L299 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 344372#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 344373#L653 assume !(0 != activate_threads_~tmp___1~0#1); 344421#L653-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 344301#L307 assume !(1 == ~t3_pc~0); 344220#L307-2 is_transmit3_triggered_~__retres1~3#1 := 0; 344221#L318 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 344012#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 344013#L661 assume !(0 != activate_threads_~tmp___2~0#1); 344240#L661-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 344241#L326 assume !(1 == ~t4_pc~0); 344024#L326-2 is_transmit4_triggered_~__retres1~4#1 := 0; 344025#L337 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 344112#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 344113#L669 assume !(0 != activate_threads_~tmp___3~0#1); 344423#L669-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 344424#L572 assume !(1 == ~M_E~0); 344460#L572-2 assume !(1 == ~T1_E~0); 344076#L577-1 assume !(1 == ~T2_E~0); 344077#L582-1 assume !(1 == ~T3_E~0); 344404#L587-1 assume !(1 == ~T4_E~0); 344415#L592-1 assume !(1 == ~E_M~0); 344022#L597-1 assume !(1 == ~E_1~0); 344023#L602-1 assume !(1 == ~E_2~0); 344263#L607-1 assume !(1 == ~E_3~0); 344264#L612-1 assume !(1 == ~E_4~0); 344199#L617-1 assume { :end_inline_reset_delta_events } true; 344200#L803-2 assume !false; 352843#L804 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 352840#L489-1 [2024-11-09 16:07:50,214 INFO L747 eck$LassoCheckResult]: Loop: 352840#L489-1 assume !false; 352838#L424 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 352836#L386 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 352833#L413 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 352831#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 352829#L428 assume 0 != eval_~tmp~0#1; 352830#L428-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 353641#L436 assume !(0 != eval_~tmp_ndt_1~0#1); 353621#L436-2 havoc eval_~tmp_ndt_1~0#1; 349807#L433-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 349804#L450 assume !(0 != eval_~tmp_ndt_2~0#1); 349802#L450-2 havoc eval_~tmp_ndt_2~0#1; 349800#L447-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 349797#L464 assume !(0 != eval_~tmp_ndt_3~0#1); 349795#L464-2 havoc eval_~tmp_ndt_3~0#1; 349792#L461-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 349653#L478 assume !(0 != eval_~tmp_ndt_4~0#1); 349790#L478-2 havoc eval_~tmp_ndt_4~0#1; 353143#L475-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 352846#L492 assume !(0 != eval_~tmp_ndt_5~0#1); 352844#L492-2 havoc eval_~tmp_ndt_5~0#1; 352840#L489-1 [2024-11-09 16:07:50,216 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,216 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2024-11-09 16:07:50,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531686173] [2024-11-09 16:07:50,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:50,228 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:50,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:50,248 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:50,248 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,248 INFO L85 PathProgramCache]: Analyzing trace with hash -1950508812, now seen corresponding path program 1 times [2024-11-09 16:07:50,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,249 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530976931] [2024-11-09 16:07:50,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,249 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:50,254 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:50,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:50,259 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:50,259 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2024-11-09 16:07:50,259 INFO L85 PathProgramCache]: Analyzing trace with hash 489185290, now seen corresponding path program 1 times [2024-11-09 16:07:50,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2024-11-09 16:07:50,260 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457257334] [2024-11-09 16:07:50,260 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2024-11-09 16:07:50,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2024-11-09 16:07:50,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:50,273 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:50,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:50,290 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2024-11-09 16:07:51,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:51,678 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2024-11-09 16:07:51,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2024-11-09 16:07:51,881 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 09.11 04:07:51 BoogieIcfgContainer [2024-11-09 16:07:51,882 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2024-11-09 16:07:51,883 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2024-11-09 16:07:51,883 INFO L270 PluginConnector]: Initializing Witness Printer... [2024-11-09 16:07:51,883 INFO L274 PluginConnector]: Witness Printer initialized [2024-11-09 16:07:51,884 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 04:07:38" (3/4) ... [2024-11-09 16:07:51,886 INFO L139 WitnessPrinter]: Generating witness for non-termination counterexample [2024-11-09 16:07:51,972 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2024-11-09 16:07:51,972 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2024-11-09 16:07:51,973 INFO L158 Benchmark]: Toolchain (without parser) took 14908.94ms. Allocated memory was 136.3MB in the beginning and 6.5GB in the end (delta: 6.4GB). Free memory was 83.7MB in the beginning and 5.8GB in the end (delta: -5.7GB). Peak memory consumption was 661.2MB. Max. memory is 16.1GB. [2024-11-09 16:07:51,973 INFO L158 Benchmark]: CDTParser took 0.21ms. Allocated memory is still 136.3MB. Free memory is still 97.9MB. There was no memory consumed. Max. memory is 16.1GB. [2024-11-09 16:07:51,973 INFO L158 Benchmark]: CACSL2BoogieTranslator took 353.98ms. Allocated memory is still 136.3MB. Free memory was 83.7MB in the beginning and 66.2MB in the end (delta: 17.5MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2024-11-09 16:07:51,973 INFO L158 Benchmark]: Boogie Procedure Inliner took 81.87ms. Allocated memory is still 136.3MB. Free memory was 65.8MB in the beginning and 61.7MB in the end (delta: 4.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-09 16:07:51,974 INFO L158 Benchmark]: Boogie Preprocessor took 100.62ms. Allocated memory is still 136.3MB. Free memory was 61.7MB in the beginning and 56.2MB in the end (delta: 5.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2024-11-09 16:07:51,974 INFO L158 Benchmark]: RCFGBuilder took 1180.96ms. Allocated memory was 136.3MB in the beginning and 203.4MB in the end (delta: 67.1MB). Free memory was 56.2MB in the beginning and 117.2MB in the end (delta: -61.0MB). Peak memory consumption was 15.5MB. Max. memory is 16.1GB. [2024-11-09 16:07:51,974 INFO L158 Benchmark]: BuchiAutomizer took 13095.80ms. Allocated memory was 203.4MB in the beginning and 6.5GB in the end (delta: 6.3GB). Free memory was 117.2MB in the beginning and 5.8GB in the end (delta: -5.7GB). Peak memory consumption was 614.2MB. Max. memory is 16.1GB. [2024-11-09 16:07:51,974 INFO L158 Benchmark]: Witness Printer took 89.36ms. Allocated memory is still 6.5GB. Free memory was 5.8GB in the beginning and 5.8GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2024-11-09 16:07:51,976 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21ms. Allocated memory is still 136.3MB. Free memory is still 97.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 353.98ms. Allocated memory is still 136.3MB. Free memory was 83.7MB in the beginning and 66.2MB in the end (delta: 17.5MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 81.87ms. Allocated memory is still 136.3MB. Free memory was 65.8MB in the beginning and 61.7MB in the end (delta: 4.1MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 100.62ms. Allocated memory is still 136.3MB. Free memory was 61.7MB in the beginning and 56.2MB in the end (delta: 5.6MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1180.96ms. Allocated memory was 136.3MB in the beginning and 203.4MB in the end (delta: 67.1MB). Free memory was 56.2MB in the beginning and 117.2MB in the end (delta: -61.0MB). Peak memory consumption was 15.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 13095.80ms. Allocated memory was 203.4MB in the beginning and 6.5GB in the end (delta: 6.3GB). Free memory was 117.2MB in the beginning and 5.8GB in the end (delta: -5.7GB). Peak memory consumption was 614.2MB. Max. memory is 16.1GB. * Witness Printer took 89.36ms. Allocated memory is still 6.5GB. Free memory was 5.8GB in the beginning and 5.8GB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 37271 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 12.9s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 4.2s. Construction of modules took 0.8s. Büchi inclusion checks took 6.8s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 3.3s AutomataMinimizationTime, 23 MinimizatonAttempts, 9349 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 1.5s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 12948 SdHoareTripleChecker+Valid, 1.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 12948 mSDsluCounter, 28712 SdHoareTripleChecker+Invalid, 0.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 12733 mSDsCounter, 242 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 798 IncrementalHoareTripleChecker+Invalid, 1040 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 242 mSolverCounterUnsat, 15979 mSDtfsCounter, 798 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 423]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE !(\read(tmp_ndt_1)) [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE !(\read(tmp_ndt_2)) [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE !(\read(tmp_ndt_3)) [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE !(\read(tmp_ndt_4)) [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 423]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L848] int __retres1 ; [L852] CALL init_model() [L760] m_i = 1 [L761] t1_i = 1 [L762] t2_i = 1 [L763] t3_i = 1 [L764] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L852] RET init_model() [L853] CALL start_simulation() [L789] int kernel_st ; [L790] int tmp ; [L791] int tmp___0 ; [L795] kernel_st = 0 [L796] FCALL update_channels() [L797] CALL init_threads() [L353] COND TRUE m_i == 1 [L354] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L358] COND TRUE t1_i == 1 [L359] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L363] COND TRUE t2_i == 1 [L364] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L368] COND TRUE t3_i == 1 [L369] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L373] COND TRUE t4_i == 1 [L374] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L797] RET init_threads() [L798] CALL fire_delta_events() [L514] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L519] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L524] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L529] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L534] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L539] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L544] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L549] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L554] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L559] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L798] RET fire_delta_events() [L799] CALL activate_threads() [L627] int tmp ; [L628] int tmp___0 ; [L629] int tmp___1 ; [L630] int tmp___2 ; [L631] int tmp___3 ; [L635] CALL, EXPR is_master_triggered() [L247] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L250] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L260] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L635] RET, EXPR is_master_triggered() [L635] tmp = is_master_triggered() [L637] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] CALL, EXPR is_transmit1_triggered() [L266] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L269] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L279] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L643] RET, EXPR is_transmit1_triggered() [L643] tmp___0 = is_transmit1_triggered() [L645] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] CALL, EXPR is_transmit2_triggered() [L285] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L288] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L298] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L651] RET, EXPR is_transmit2_triggered() [L651] tmp___1 = is_transmit2_triggered() [L653] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] CALL, EXPR is_transmit3_triggered() [L304] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L307] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L317] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L659] RET, EXPR is_transmit3_triggered() [L659] tmp___2 = is_transmit3_triggered() [L661] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] CALL, EXPR is_transmit4_triggered() [L323] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L326] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L336] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L667] RET, EXPR is_transmit4_triggered() [L667] tmp___3 = is_transmit4_triggered() [L669] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L799] RET activate_threads() [L800] CALL reset_delta_events() [L572] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L577] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L582] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L587] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L592] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L597] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L602] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L607] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L612] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L617] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L800] RET reset_delta_events() [L803] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L806] kernel_st = 1 [L807] CALL eval() [L419] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L423] COND TRUE 1 [L426] CALL, EXPR exists_runnable_thread() [L383] int __retres1 ; [L386] COND TRUE m_st == 0 [L387] __retres1 = 1 [L414] return (__retres1); [L426] RET, EXPR exists_runnable_thread() [L426] tmp = exists_runnable_thread() [L428] COND TRUE \read(tmp) [L433] COND TRUE m_st == 0 [L434] int tmp_ndt_1; [L435] tmp_ndt_1 = __VERIFIER_nondet_int() [L436] COND FALSE !(\read(tmp_ndt_1)) [L447] COND TRUE t1_st == 0 [L448] int tmp_ndt_2; [L449] tmp_ndt_2 = __VERIFIER_nondet_int() [L450] COND FALSE !(\read(tmp_ndt_2)) [L461] COND TRUE t2_st == 0 [L462] int tmp_ndt_3; [L463] tmp_ndt_3 = __VERIFIER_nondet_int() [L464] COND FALSE !(\read(tmp_ndt_3)) [L475] COND TRUE t3_st == 0 [L476] int tmp_ndt_4; [L477] tmp_ndt_4 = __VERIFIER_nondet_int() [L478] COND FALSE !(\read(tmp_ndt_4)) [L489] COND TRUE t4_st == 0 [L490] int tmp_ndt_5; [L491] tmp_ndt_5 = __VERIFIER_nondet_int() [L492] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2024-11-09 16:07:52,011 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)